A simulation method of a system in package product

Abstract

The embodiment of the application discloses a simulation method of a system-level package product, and the method comprises the following steps: obtaining a package substrate model and a bonding wire model of the system-level package product; performing cascade interconnection on S parameter models of the package substrate model and the bonding wire model to obtain a package interconnection model of the system-level package product; combining the package interconnection model with a controller model, a controlled device model and a PCB line model of the system-level package product to obtain a system-level simulation model of the controlled device; and performing time domain simulation on the system-level simulation model to obtain signal integrity and power integrity simulation results of the controlled device on a PCB board. The embodiment of the application solves the technical problems of low simulation efficiency, poor flexibility and inability to modularly reuse in the prior art of overall modeling simulation of the system-level package product, improves the simulation efficiency and accuracy, and improves the flexibility of model use.

Description

Technical Field

[0001] This invention relates to the field of chip simulation technology, and more particularly to a simulation method for system-in-package products. Background Technology

[0002] Currently, the closest existing technical solution for simulating system-in-package (SiP) DDR (Double Data Rate SDRAM) devices mainly adopts a method of overall modeling and one-time simulation. The technical measures and steps are as follows: a three-dimensional model of the complete package structure, including the SiP substrate, bonding wires, controller, and DDR chip, is created in one go; then, a full-wave electromagnetic field simulation is performed on this overall model to extract S-parameters; finally, the extracted S-parameters are combined with the chip behavior model to perform system-level time-domain simulation.

[0003] However, the overall modeling involves complex substrate traces, bonding wires, chip pads, and other intricate structures, resulting in a massive number of meshes and long computation times. If any part of the package structure undergoes a design change, the entire model needs to be modified and a full-wave simulation performed again, making modular reuse impossible and leading to a large amount of repetitive work. Summary of the Invention

[0004] This invention provides a simulation method for system-in-package (SiP) products, which solves the technical problems of low simulation efficiency, poor flexibility, and inability to perform modular reuse in the existing technology for overall modeling and simulation of SiP products.

[0005] This invention provides a simulation method for a system-in-package (SIPP) product, the method comprising: Obtain the packaging substrate model and bonding wire model of the system-in-package product; The S-parameter models of the packaging substrate model and the bonding wire model are cascaded and interconnected to obtain the packaging interconnection model of the system-in-package product. The package interconnect model is combined with the controller model, controlled device model, and PCB line model of the system-in-package product to obtain the system-level simulation model of the controlled device; Time-domain simulation was performed on the system-level simulation model to obtain the signal integrity and power integrity simulation results of the controlled device on the PCB board.

[0006] Furthermore, obtaining the packaging substrate model and bonding wire model of the system-in-package product includes: Extract the packaging substrate model of the system-in-package product, wherein the packaging substrate model is a model built based on the traces, vias, and pads of the packaging substrate; Perform board-level simulation on the packaging substrate model and extract the S-parameters of the packaging substrate model; A three-dimensional model of the bonding wire of the system-in-package product is performed to obtain the bonding wire model; Electromagnetic simulation was performed on the bonding wire model to extract the S-parameter model of the bonding wire model.

[0007] Furthermore, before cascading and interconnecting the S-parameter models of the packaging substrate model and the bonding wire model to obtain the packaging interconnect model of the system-in-package product, the method further includes: Based on the S-parameters of the packaging substrate model and the S-parameter model of the bonding wire model, the reference impedance of different trace areas of the packaging substrate is set using preset impedance compensation requirements.

[0008] Furthermore, based on the S-parameters of the packaging substrate model and the S-parameter model of the bonding wire model, and using preset impedance compensation requirements, the reference impedance of different trace regions of the packaging substrate is set, including: Based on the S-parameters of the packaging substrate model and the S-parameter model of the bonding wire model, the characteristic parameters of the substrate and the bonding wire are determined, wherein the characteristic parameters include at least the characteristic impedance, insertion loss, return loss and crosstalk of the substrate and the bonding wire. The impedance compensation requirements are set based on the determined characteristic parameters; The reference impedance of different trace areas on the packaging substrate is set based on the impedance compensation requirements.

[0009] Furthermore, by combining the package interconnect model with the controller model, controlled device model, and PCB line model of the system-in-package product, a system-level simulation model of the controlled device is obtained, including: The packaged interconnect model is combined with the controller model and controlled device model of the system-in-package product to obtain a combined simulation model; The PCB line model is added between the controller model and the packaging substrate model to obtain the system-level simulation model of the controlled device.

[0010] Furthermore, the controlled device includes one of the following: DDR, SRAM, EEPROM, Flash, LPDDR4x, DDR3, HyperRAM.

[0011] This invention discloses a simulation method for system-in-package (SiP) products. The method includes: acquiring a substrate model and a bonding wire model of the SiP product; cascading and interconnecting the S-parameter models of the substrate model and the bonding wire model to obtain a SiP interconnect model; combining the interconnect model with a controller model, a controlled device model, and a PCB line model of the SiP product to obtain a SiP simulation model of the controlled device; and performing time-domain simulation on the SiP simulation model to obtain the signal integrity and power integrity simulation results of the controlled device on the PCB board. This invention solves the technical problems of low simulation efficiency, poor flexibility, and inability to modularly reuse existing SiP products modeling and simulation methods, thereby improving simulation efficiency and accuracy, and enhancing the flexibility of model use. Attached Figure Description

[0012] Figure 1 This is a flowchart of a simulation method for a system-level packaged product provided in an embodiment of the present invention. Detailed Implementation

[0013] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0014] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish different objects, not to limit a specific order. The various embodiments of this invention described below can be performed individually or in combination with each other; the embodiments of this invention do not impose specific limitations in this regard.

[0015] Figure 1 This is a flowchart of a simulation method for a system-level packaged product provided in an embodiment of the present invention.

[0016] like Figure 1 As shown, the simulation method for this system-level packaged product includes the following steps: S101, Obtain the packaging substrate model and bonding wire model of the system-in-package product.

[0017] Optionally, S101 specifically includes: extracting the packaging substrate model of the system-in-package product, wherein the packaging substrate model is a model established based on the traces, vias, and pads of the packaging substrate; performing board-level simulation on the packaging substrate model to extract the S-parameters of the packaging substrate model; performing three-dimensional modeling on the bonding wires of the system-in-package product to obtain the bonding wire model; and performing electromagnetic simulation on the bonding wire model to extract the S-parameter model of the bonding wire model.

[0018] Specifically, bonding wires are the core connection materials in semiconductor packaging, crucial micro-wires that enable electrical conduction between the chip and external circuits. Their diameter is typically only about 1 / 5 the thickness of a human hair. S-parameters, or scattering parameters, are core network parameters describing the signal reflection and transmission characteristics in RF / microwave networks. They characterize device performance based on the ratio of incident to scattered waves, and are easier to implement in high-frequency scenarios than directly measuring voltage and current. S-parameters include S... ij i is the output port and j is the input port. Specifically, S ij It includes S11, S21, S12 and S22, where S11 is the input reflection coefficient, i.e. return loss; S21 is the forward transmission coefficient, i.e. insertion loss / gain; S12 is the reverse transmission coefficient, i.e. isolation; and S22 is the output reflection coefficient.

[0019] In this embodiment of the invention, board-level simulation is performed on the SiP packaging substrate with bonding wires removed to extract the S-parameters of the packaging substrate. The substrate model is imported using only a pure substrate structure model including substrate traces, vias, and pads, and full-wave electromagnetic simulation is performed to extract the multi-port S-parameter matrix for all ports of the packaging substrate, effectively eliminating interference from the bonding wire structure. Furthermore, according to actual process parameters such as the diameter, length, arch height, and spacing between adjacent bonding wires, a three-dimensional model of the bonding wires is established, and electromagnetic simulation is performed separately to obtain an independent S-parameter model of the bonding wires, accurately capturing their high-frequency parasitic effects.

[0020] By modeling and simulating the packaging substrate and bonding wire separately, the models of each part can be modularized. When a certain packaging part of the system-in-package product undergoes a design iteration, it is only necessary to re-simulate the updated part and replace the corresponding model, without having to remodel the overall 3D model and perform full-wave simulation.

[0021] S102, cascade the S-parameter models of the packaging substrate model and the bonding wire model to obtain the packaging interconnect model of the system-in-package product.

[0022] Specifically, the S-parameter models of the packaging substrate model and the bonding wire model are cascaded and interconnected using circuit simulation tools to obtain a complete SiP package interconnect S-parameter model, namely the above-mentioned package interconnect model. When design changes occur in the future, only the modified parts need to be re-simulated and the corresponding models replaced, without the need for a complete re-simulation.

[0023] S103 combines the package interconnect model with the controller model, controlled device model, and PCB line model of the system-in-package product to obtain the system-level simulation model of the controlled device.

[0024] Optionally, S103 specifically includes: The package interconnect model is combined with the controller model and controlled device model of the system-in-package product to obtain the combined simulation model; a PCB line model is added between the controller model and the package substrate model to obtain the system-level simulation model of the controlled device.

[0025] Specifically, in traditional system-level co-simulation, the package S-parameters and chip behavior model are directly interfacing, completely omitting the PCB interconnect signal line model between the controller and the package substrate model, thus lacking the ability to reproduce the distributed parameter characteristics of this trace. This results in the simulation model missing the actual impedance fluctuations, crosstalk, transmission delays, and other real effects of this trace on the actual development board. Consequently, the eye diagrams, timing margins, and other results obtained from the simulation deviate significantly from the actual signal performance at the board level, failing to accurately reflect the true operating state.

[0026] Optionally, the controlled device includes, but is not limited to, one of the following: DDR, SRAM (Static Random Access Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), Flash (Flash Memory), LPDDR4x (LowPower Double Data Rate 4X SDRAM), DDR3 (Double Data Rate 3 SDRAM), and HyperRAM (HyperBus Random Access Memory).

[0027] In this embodiment of the invention, taking DDR as the controlled device as an example, the complete package interconnect model is first docked with the DDR controller model and the DDR controlled device model to obtain a combined simulation model. Then, a distributed PCB routing model that conforms to the actual development board parameters is inserted between the DDR controller model and the package substrate model, i.e., the above-mentioned PCB model, to form a system-level simulation model covering the entire "PCB-package-chip" link. The actual development board parameters include at least signal line parameters such as impedance, line width, and spacing.

[0028] S104 performs time-domain simulation on the system-level simulation model to obtain the simulation results of signal integrity and power integrity of the controlled device on the PCB board.

[0029] Specifically, after obtaining the system-level simulation model, time-domain transient simulation is performed on the complete system-level simulation model to extract key indicators such as eye diagram, timing margin, power ripple, and synchronous switching noise. The signal and power integrity performance of SiP packaged DDR devices (taking DDR as the controlled device as an example) on the actual development board (i.e. the PCB board mentioned above) is evaluated, and potential problems such as impedance discontinuity and PDN resonance are located.

[0030] Optionally, before S102, the method further includes: S1021, based on the S-parameters of the packaging substrate model and the S-parameter model of the bonding wire model, sets the reference impedance for different trace areas of the packaging substrate using preset impedance compensation requirements.

[0031] Optionally, S1021 specifically includes: Based on the S-parameter model of the packaging substrate model and the S-parameter model of the bonding wire model, the characteristic parameters of the substrate and the bonding wire are determined. The characteristic parameters include at least the characteristic impedance, insertion loss, return loss and crosstalk of the substrate and the bonding wire. Impedance compensation requirements are set based on the determined characteristic parameters. The reference impedance of different trace areas of the packaging substrate is set based on the impedance compensation requirements.

[0032] Specifically, traditional methods typically use a uniform port reference impedance, such as 50Ω, when extracting substrate S-parameters, without considering the impedance compensation requirements of different trace areas in the design of the packaging substrate. This leads to a mismatch between the simulation model and the actual impedance continuity, resulting in a large deviation between the simulation results and the actual measurements.

[0033] In this embodiment of the invention, based on the impedance compensation requirements established by considering the S-parameters of the packaging substrate model and the S-parameters of the bonding wire model, the target characteristic impedance of different trace areas of the packaging substrate is set as the reference impedance of the corresponding port, such as 45Ω in the compensation area and 50Ω in the non-compensation area, to replace the traditional default setting of 50Ω, so as to match the actual impedance design.

[0034] By setting segmented port reference impedances, the impedance continuity between the simulation model and the actual package substrate is made consistent, eliminating the mismatch error caused by uniform impedance. Simultaneously, the introduced PCB line model recreates the actual interconnect environment of the development board. Theoretical derivation and experimental comparison show that the deviation between the simulated eye diagram, jitter, and other signal integrity indicators and the measured results can be reduced by 15% to 25%.

[0035] In summary, the embodiments of the present invention establish three-dimensional models of the packaging substrate, bonding wire, controller, controlled device, and PCB line respectively, and then modularly combine the models of each part to obtain a complete system-level simulation model. (1) By adopting modular combination simulation, when a certain part of the system-level simulation model is iterated, it is only necessary to remodel that part and replace the model, without having to re-perform full-wave simulation of the entire model. (1) The simulation cycle of multi-pin controlled devices can be shortened from several weeks to several days, which greatly speeds up the simulation work pace; (2) The simulation results can more realistically reflect the signal and power performance of SiP packaged controlled devices on the actual development board, which helps to discover and solve potential problems in the early stage of design, reduce the number of repeated hardware debugging in the later stage, and reduce debugging costs and risks; (3) The segmented port reference impedance setting makes the simulation model consistent with the impedance of the actual substrate, eliminates the mismatch error caused by the unified impedance, and greatly improves the simulation accuracy. At the same time, the modular method and scientific port setting also reduce the consumption of computing resources, such as memory and CPU (Central Processing Unit) computing power, and also reduce the requirements of simulation personnel for overall modeling experience, enabling more designers to perform high-quality simulations efficiently.

[0036] In the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0037] Finally, it should be noted that the above are merely preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A simulation method for a system-in-package product, characterized in that, The method includes: Obtain the packaging substrate model and bonding wire model of the system-in-package product; The S-parameter models of the packaging substrate model and the bonding wire model are cascaded and interconnected to obtain the packaging interconnection model of the system-in-package product. The package interconnect model is combined with the controller model, controlled device model, and PCB line model of the system-in-package product to obtain the system-level simulation model of the controlled device; Time-domain simulation was performed on the system-level simulation model to obtain the signal integrity and power integrity simulation results of the controlled device on the PCB board.

2. The simulation method for system-in-package products according to claim 1, characterized in that, Obtaining the packaging substrate model and bonding wire model of the system-in-package product includes: Extract the packaging substrate model of the system-in-package product, wherein the packaging substrate model is a model built based on the traces, vias, and pads of the packaging substrate; Perform board-level simulation on the packaging substrate model and extract the S-parameters of the packaging substrate model; A three-dimensional model of the bonding wire of the system-in-package product is performed to obtain the bonding wire model; Electromagnetic simulation was performed on the bonding wire model to extract the S-parameter model of the bonding wire model.

3. The simulation method for system-in-package products according to claim 2, characterized in that, Before cascading and interconnecting the S-parameter models of the packaging substrate model and the bonding wire model to obtain the packaging interconnect model of the system-in-package product, the method further includes: Based on the S-parameters of the packaging substrate model and the S-parameter model of the bonding wire model, the reference impedance of different trace areas of the packaging substrate is set using preset impedance compensation requirements.

4. The simulation method for system-in-package products according to claim 3, characterized in that, Based on the S-parameters of the package substrate model and the S-parameter model of the bonding wire model, the reference impedance of different trace regions of the package substrate is set using preset impedance compensation requirements, including: Based on the S-parameters of the packaging substrate model and the S-parameter model of the bonding wire model, the characteristic parameters of the substrate and the bonding wire are determined, wherein the characteristic parameters include at least the characteristic impedance, insertion loss, return loss and crosstalk of the substrate and the bonding wire. The impedance compensation requirements are set based on the determined characteristic parameters; The reference impedance of different trace areas on the packaging substrate is set based on the impedance compensation requirements.

5. The simulation method for system-in-package products according to claim 1, characterized in that, Combining the package interconnect model with the controller model, controlled device model, and PCB line model of the system-in-package product yields the system-level simulation model of the controlled device, including: The packaged interconnect model is combined with the controller model and controlled device model of the system-in-package product to obtain a combined simulation model; The PCB line model is added between the controller model and the packaging substrate model to obtain the system-level simulation model of the controlled device.

6. The simulation method for a system-in-package product according to any one of claims 1-5, characterized in that, The controlled device includes one of the following: DDR, SRAM, EEPROM, Flash, LPDDR4x, DDR3, HyperRAM.

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