Multi-board circuit simulation method and system, computer device and storage medium

Abstract

The application provides a multi-board circuit simulation method and system, computer equipment and a storage medium. The method comprises the following steps: obtaining device pin information and network topology information of each circuit board in a multi-board circuit; marking each device pin on each circuit board as a starting point or an ending point of a cross-board signal; constructing a connector model, wherein the connector model comprises a 0-ohm resistance model and an S parameter model; establishing a cross-board pin mapping relationship of the device pins on each circuit board to the device pins on other circuit boards through the connector model; selecting the 0-ohm resistance model and / or the S parameter model based on the type of the cross-board signal, and performing multi-board circuit system-level simulation in combination with the cross-board pin mapping relationship. The scheme can accurately perform pin and connector modeling in multi-board circuit simulation, ensure parasitic effects and real topology information, and accurately reflect the insertion loss, reflection and mode conversion characteristics under high-speed signals, so that the simulation of the multi-board circuit is more accurate.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and more particularly to a multi-board circuit simulation method, system, computer equipment, and storage medium. Background Technology

[0002] With the increasing complexity of computer, communication, and storage devices, multi-board systems (such as motherboard + daughter card + backplane) are becoming increasingly widespread. Different PCBs are interconnected via connectors or cables to achieve high-speed data transmission, using interfaces such as PCIe, DDR, USB, and SerDes. However, existing EDA simulation tools suffer from the following problems in multi-board simulation: inconsistent connector modeling: some tools only support ideal conduction (0 ohm resistance), failing to accurately reflect characteristics such as insertion loss, reflection, and mode conversion under high-speed signals; simplistic pin handling: some methods ignore or replace device pins during cross-board modeling, leading to the loss of parasitic effects and accurate signal characteristics. Therefore, a method is needed to accurately model pins and connectors in multi-board circuit simulation to achieve efficient, accurate, and repeatable multi-board system-level simulation. Summary of the Invention

[0003] The purpose of this invention is to provide a multi-board circuit simulation method, system, computer device, and storage medium that can accurately model pins and connectors in multi-board circuit simulation, ensure parasitic effects and real topology information, and accurately reflect characteristics such as insertion loss, reflection, and mode conversion under high-speed signals, making multi-board circuit simulation more accurate and more verifiable.

[0004] The technical solution provided by this invention is as follows:

[0005] Firstly, this application provides a multi-board circuit simulation method, including the following steps:

[0006] Obtain the device pin information and network topology information of each circuit board in the multi-board circuit to be simulated;

[0007] Based on the device pin information, each device pin on each circuit board is marked as the start or end point of the cross-board signal;

[0008] Construct a connector model with a unified interface, which includes a 0-ohm resistance model and an S-parameter model;

[0009] Based on the network topology information and the start or end point of the cross-board signal, establish a cross-board pin mapping relationship where device pins on each board are mapped to device pins on other boards through the connector model;

[0010] Based on the type of the cross-board signal, select the 0-ohm resistor model and / or S-parameter model, and perform multi-board circuit system-level simulation in conjunction with the cross-board pin mapping relationship.

[0011] In some implementations, after establishing the cross-board pin mapping relationship, the following steps are also included:

[0012] The integrity of the cross-board pin mapping relationship is checked to determine whether there are unmapped device pins or duplicated device pins, as well as whether there are differential pairs or positive and negative polarity mapping errors. If the determination is yes, the erroneous pins are marked and an error message is given to correct the cross-board pin mapping relationship.

[0013] In some implementations, the construction of a connector model with a unified interface includes:

[0014] Define a unified interface class;

[0015] Obtain the first port parameter file under ideal conduction state, and construct the 0-ohm resistance model. The 0-ohm resistance model is adapted to the cross-board signal being a low-frequency signal.

[0016] Obtain the second port parameter file that configures the high-frequency signal transmission characteristics, and construct the S-parameter model, which is adapted to the cross-board signal being a high-frequency signal.

[0017] In some implementations, the 0-ohm resistor model is selected when the cross-board signal between the circuit boards of a multi-board circuit is a low-frequency signal.

[0018] When the cross-board signal between the circuit boards of a multi-board circuit is a high-frequency signal, the S-parameter model is selected.

[0019] When the cross-board signal between the circuit boards of a multi-board circuit includes both low-frequency and high-frequency signals, the 0-ohm resistor model and the S-parameter model are used in combination according to the corresponding cross-board signal.

[0020] In some implementations, establishing cross-board pin mapping relationships from device pins on each circuit board to device pins on other circuit boards via the connector model includes:

[0021] Preset pin mapping rules, including one-to-one sequential mapping, differential pair mapping, and cross mapping;

[0022] Select the target pin mapping rule according to the mapping instruction, and after obtaining the network topology information and the start or end point of the cross-board signal, establish the cross-board pin mapping relationship of the device pins on each board to the device pins on other boards through the connector model according to the target pin mapping rule.

[0023] In some implementations, establishing cross-board pin mapping relationships from device pins on each circuit board to device pins on other circuit boards via the connector model includes:

[0024] Build a graphical interface and display each circuit board and the pins of the devices on each circuit board in real time;

[0025] Establish image interaction rules, and based on the interaction instructions, establish cross-board pin mapping relationships between device pins on each circuit board and device pins on other circuit boards through the connector model.

[0026] In some implementations, marking each device pin on each circuit board as the start or end point of a cross-board signal based on the device pin information includes:

[0027] Based on the device pin information and the network topology information, each device pin on each circuit board is divided into a first device pin with cross-board connection relationship and a second device pin without cross-board connection relationship.

[0028] Mark the pins of each first device on each circuit board as the start or end point of the cross-board signal.

[0029] Secondly, this application provides a multi-board circuit simulation system, comprising:

[0030] The acquisition module is used to acquire the device pin information and network topology information of each circuit board in the multi-board circuit to be simulated;

[0031] The marking module is used to mark each device pin on each circuit board as the start or end point of the cross-board signal according to the device pin information;

[0032] The module constructs a connector model with a unified interface, which includes a 0-ohm resistance model and an S-parameter model.

[0033] The mapping module is used to establish a cross-board pin mapping relationship between device pins on each board and device pins on other boards through the connector model, based on the network topology information and the start or end point of the cross-board signal.

[0034] The simulation module is used to select the 0-ohm resistor model and / or S-parameter model based on the type of the cross-board signal, and to perform system-level simulation in conjunction with the cross-board pin mapping relationship.

[0035] Thirdly, this application provides a computer device including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the multi-board circuit simulation method described in the first aspect.

[0036] Fourthly, this application provides a computer storage medium storing a computer program or instructions thereon, wherein the computer program or instructions, when executed by a processor, implement the steps of the multi-board circuit simulation method described in the first aspect.

[0037] The multi-board circuit simulation method, system, computer equipment, and storage medium provided by this invention have at least the following technical effects:

[0038] 1) High precision: This solution retains device pins and is used for multi-board circuit simulation, which can ensure parasitic effects and real topology information;

[0039] 2) Flexible modeling: The connector models in this solution include 0-ohm resistance models and S-parameter models. The two types of models can be selected and used according to the actual scenario, so as to adapt to low-speed and high-speed interfaces respectively, and avoid ignoring characteristics such as insertion loss, reflection and mode conversion under high-speed signals.

[0040] 3) High degree of automation: This solution can automatically check the accuracy of pin mapping when performing cross-board pin mapping, thereby reducing human error;

[0041] 4) Wide applicability: This solution is applicable to various multi-board systems such as motherboard + daughter card, motherboard + backplane, and DDR SO-DIMM, making it more widely applicable;

[0042] 5) Strong verifiability: The system-level simulation of this solution can output analysis results such as link eye diagram, BER, and impedance curve to perform signal integrity, timing margin and power integrity analysis, providing a basis for design optimization. Attached Figure Description

[0043] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of this solution.

[0044] Figure 1 This is a schematic diagram of the overall process of one embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the system architecture of one embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of a connector model according to an embodiment of the present invention;

[0047] Figure 4This is a schematic diagram of cross-board pin mapping according to an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of the topology of a cross-board simulation example according to an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of a multi-board circuit simulation system according to an embodiment of the present invention.

[0050] The numbers in the diagram are: 10 - Acquisition module; 20 - Marking module; 30 - Construction module; 40 - Mapping module; 50 - Simulation module. Detailed Implementation

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0052] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of components with the same structure or function is shown schematically, or only one is labeled. In this document, "one" can mean not only "only one" but also "more than one".

[0053] With the increasing complexity of computer, communication, and storage devices, multi-board systems (such as motherboard + daughter card + backplane) are becoming increasingly widespread. Different PCBs are interconnected via connectors or cables to achieve high-speed data transmission, using interfaces such as PCIe, DDR, USB, and SerDes. However, existing EDA simulation tools have the following problems in multi-board simulation:

[0054] 1) Inconsistent connector modeling: Some tools only support ideal conduction (0 ohm resistance), which cannot accurately reflect the characteristics such as insertion loss, reflection and mode conversion under high-speed signals;

[0055] 2) Simplified Pin Handling: Some methods ignore or replace device pins when modeling across boards, resulting in the loss of parasitic effects and accurate signal characteristics. Therefore, a method is needed that can accurately model pins and connectors in multi-board circuit simulation to achieve efficient, accurate, and repeatable multi-board system-level simulation;

[0056] 3) Complex pin mapping: Cross-board signal mapping requires manual configuration, which is prone to errors and lacks automated checking.

[0057] Therefore, a method is needed to accurately model pins and connectors in multi-board circuit simulation to achieve efficient, accurate, and repeatable multi-board system-level simulation. This solution retains device pin information during simulation as the start and end points of cross-board signals, ensuring parasitic effects and accurate topology information. Simultaneously, two cross-board connector models are defined, suitable for low-speed or connectivity verification and high-frequency signal verification respectively, thus adapting to different application scenarios and avoiding neglecting insertion loss, reflection, and mode conversion characteristics under high-speed signals, resulting in higher simulation accuracy for multi-board circuits. The following is a detailed description of this solution with reference to the accompanying drawings:

[0058] In one embodiment, refer to the appendix to the specification. Figure 1 This application provides a multi-board circuit simulation method, including the following steps:

[0059] S100: Obtain the device pin information and network topology information of each circuit board in the multi-board circuit to be simulated.

[0060] Multi-board circuits are not simply a matter of placing several PCBs together. Instead, they intentionally distribute system functionality across two or more interconnecting PCBs (including rigid boards, FPCs, RF modules, daughter cards, backplanes, connectors, cables, and packaging substrates). Through various interconnection methods such as high-speed differential, single-ended, power, RF, and optical interconnects, they achieve an optimal balance between performance, cost, manufacturability, maintainability, and upgradeability. Common multi-board circuit systems include PCIe and DDR SO-DIMM. These systems employ different signal connection methods. For example, in a PCIe cross-board system, the motherboard FPGA and daughter card NIC are interconnected via high-speed connectors; similarly, in a DDR SO-DIMM system, the motherboard memory controller and daughter card DRAM are interconnected via slots. Using a uniform connector model during simulation for different connection methods can lead to reduced simulation accuracy. For instance, some existing tools only support ideal conduction (0 ohms resistance), failing to accurately reflect insertion loss, reflection, and mode conversion characteristics under high-speed signals. Therefore, this application imports the device information, pin information and network topology information of each circuit board in the multi-board circuit to be simulated, and retains the device pin information as the start and end points of cross-board signals, thereby ensuring parasitic effects and real topology information.

[0061] S200: Mark each device pin on each circuit board as the start or end point of the cross-board signal according to the device pin information.

[0062] Furthermore, due to the large number and variety of device pins on the circuit board, and the fact that some device pins are not used for cross-board connections, this solution, in addition to marking each device pin on each circuit board as the start or end point of the cross-board signal based on the device pin information, also includes:

[0063] Based on the device pin information and network topology information, each device pin on each circuit board is divided into first device pins with cross-board connection relationship and second device pins without cross-board connection relationship; each first device pin on each circuit board is marked as the start or end point of the cross-board signal.

[0064] S300. Construct a connector model with a unified interface. The connector model includes a 0-ohm resistor model and an S-parameter model.

[0065] The 0-ohm resistance model corresponds to an ideal conduction state. In connector simulation, the 0-ohm resistance model does not actually treat the contact resistance as an ideal 0 ohm, but rather uses an equivalent resistance (typically 1~5 mΩ) that can be artificially scaled to near 0 ohms to represent the DC loss of the entire conductive path of the "male-female terminal" for SI / PI simulation. The 0-ohm resistance model is used for low-speed signals or to verify connectivity, equivalent to ideal conduction. The S-parameter (scattering parameter) model corresponds to the high-frequency (or high-speed) signal connection state. The S-parameter model is based on the Touchstone file to build the port model and can reflect the high-frequency signal transmission characteristics. When building the connector model in this solution, refer to the appendix of the instruction manual. Figure 3 Simultaneously, a 0-ohm resistance model and an S-parameter model are constructed, and both models have a unified interface, allowing for easy switching between them. In one example, refer to the attached manual. Figure 2 PCB A is connected to PCB B through a connector model that includes a 0-ohm resistor model and an S-parameter model. Signals are transmitted from the device pins of PCB A to the device pins of PCB B through the connector model.

[0066] In one specific implementation, a connector model with a unified interface is constructed, including:

[0067] Define a unified interface class, obtain the first port parameter file under ideal conduction conditions, and construct a 0-ohm resistance model. The 0-ohm resistance model is suitable for cross-board signals that are low-frequency signals. Obtain the second port parameter file that configures the transmission characteristics of high-frequency signals, and construct an S-parameter model. The S-parameter model is suitable for cross-board signals that are high-frequency signals.

[0068] A unified interface class refers to abstracting a set of functions with different underlying implementations but the same usage at the upper level into a simplified contract, which is then implemented by various specific models. In this solution, to improve its versatility and adaptability to different multi-board systems, a unified interface is set for the 0-ohm resistor model and the S-parameter model, allowing for model selection based on usage requirements. When selecting a model, the type of cross-board signal is first determined. If the cross-board signal between the boards in a multi-board circuit is a low-frequency signal, the 0-ohm resistor model is selected; if it is a high-frequency signal, the S-parameter model is selected; and if the cross-board signal includes both low-frequency and high-frequency signals, a mixture of the 0-ohm resistor model and the S-parameter model can be used depending on the specific cross-board signal.

[0069] The second-port parameter file, also known as the Touchstone file, is a plain text data file used to store and exchange linear network parameters of RF / microwave devices measured (or simulated) at different frequencies. The most common parameters are S-parameters (scattering parameters). Touchstone files are considered a "universal language" in the RF field, storing the device's S / Y / Z parameters in a standardized text format, enabling seamless exchange between measurement, simulation, and modeling. This application constructs an S-parameter model based on Touchstone files to reflect the characteristics of high-frequency signal transmission.

[0070] S400. Based on the network topology information and the start or end point of cross-board signals, establish cross-board pin mapping relationships where device pins on each board are mapped to device pins on other boards through a connector model.

[0071] Reference manual attached Figure 4 This solution, after constructing the connector model and determining the start or end point of cross-board signals, can establish cross-board pin mapping relationships based on network topology information. For example, it can map the device pins of PCB A to the device pins of PCB B through connectors. Various methods can be used for pin mapping. For instance, in one specific implementation, a cross-board pin mapping relationship can be established, mapping device pins on each board to device pins on other boards through the connector model. This includes:

[0072] Preset pin mapping rules, including one-to-one sequential mapping, differential pair mapping, and cross mapping; select the target pin mapping rule according to the mapping instruction, and after obtaining the network topology information and the start or end point of the cross-board signal, establish the cross-board pin mapping relationship of the device pins on each board to the device pins on other boards through the connector model according to the target pin mapping rule.

[0073] One-to-one sequential mapping refers to pins on two circuit boards corresponding sequentially in a 1:1 ratio according to their numbering, without any jumps or swaps. This method is suitable for chips with a small number of pins, ample routing layers, and low requirements for differential impedance / length matching. Its advantages are that it is intuitive and can be automatically generated by scripts. Its disadvantage is that it may split the differential pairs to the two sides, resulting in excessively long traces.

[0074] Differential pair mapping refers to first binding differential signals (such as LVDS, SSTL) in pairs according to "+ / -", and then mapping each pair to two adjacent and symmetrical physical pins (in the same row or the same differential pair pin group). The advantage of this method is that it maintains the minimum spacing and length difference within the pair, and is close to the internal differential buffer, reducing common-mode noise.

[0075] Cross mapping is an additional "+ / - interchange" or "channel cross" on the basis of differential pair mapping. It deliberately misaligns the P / N of adjacent pairs, allowing "cross routing" on the PCB layer without the need for vias under the components, thereby shortening the difference in differential line length; placing high-speed pairs on the same layer reduces via parasitics; and reduces crosstalk between adjacent pairs (the routing is "cross-finger" and the electric field cancels out).

[0076] This solution first presets pin mapping rules for one-to-one sequential mapping, differential pair mapping, and cross mapping. During simulation, the target pin mapping rule is selected according to the mapping instructions given by the user (such as clicking, selecting, inputting, etc.). Then, according to the target pin mapping rule, the cross-board pin mapping relationship is established by mapping the device pins on each board to the device pins on other boards through the connector model.

[0077] For example, in one specific implementation, a cross-board pin mapping relationship is established, mapping device pins on each circuit board to device pins on other circuit boards through a connector model, including:

[0078] Build a graphical interface and display each circuit board and the pins of the devices on each circuit board in real time; establish image interaction rules and establish cross-board pin mapping relationships based on interaction commands, mapping the pins of devices on each circuit board to the pins of devices on other circuit boards through the connector model.

[0079] This method provides a graphical interface, allowing users to create cross-board mappings by dragging or selecting device pins, making the operation more convenient. However, errors may occur due to human error, requiring inspection.

[0080] In one specific implementation, after establishing the cross-board pin mapping relationship, it also includes:

[0081] Perform an integrity check on the cross-board pin mapping relationship to determine if there are any unmapped or duplicated device pins, as well as if there are any differential pairs or positive / negative polarity mapping errors. If the determination is correct, mark the erroneous pins and provide an error message to correct the cross-board pin mapping relationship.

[0082] S500, based on the type of cross-board signal, selects a 0-ohm resistor model and / or an S-parameter model, and combines the cross-board pin mapping relationship to perform multi-board circuit system-level simulation.

[0083] This solution constructs two connector models and selects a 0-ohm resistor model and / or an S-parameter model based on the type of cross-board signal. It can also perform multi-board circuit system-level simulations by combining cross-board pin mapping relationships, including signal integrity, timing margin, and power integrity analysis. The system can output link eye diagrams, BER curves, and power impedance curves for verifying system-level signal integrity and power integrity.

[0084] The multi-board circuit simulation method provided by this invention has at least the following technical effects:

[0085] 1) High precision: This solution retains device pins and is used for multi-board circuit simulation, which can ensure parasitic effects and real topology information;

[0086] 2) Flexible modeling: The connector models in this solution include 0-ohm resistance models and S-parameter models. The two types of models can be selected and used according to the actual scenario, so as to adapt to low-speed and high-speed interfaces respectively, and avoid ignoring characteristics such as insertion loss, reflection and mode conversion under high-speed signals.

[0087] 3) High degree of automation: This solution can automatically check the accuracy of pin mapping when performing cross-board pin mapping, thereby reducing human error;

[0088] 4) Wide applicability: This solution is applicable to various multi-board systems such as motherboard + daughter card, motherboard + backplane, and DDR SO-DIMM, making it more widely applicable;

[0089] 5) Strong verifiability: The system-level simulation of this solution can output analysis results such as link eye diagram, BER, and impedance curve to perform signal integrity, timing margin and power integrity analysis, providing a basis for design optimization.

[0090] In one example, the multi-board circuit is PCIe. When performing PCIe cross-board simulation, the system includes the motherboard FPGA and the daughter card NIC, which are interconnected through a high-speed connector. The FPGA TX pin is mapped to the connector port, and the connector port is mapped to the NIC RX pin. The connector model is selected as an S-parameter model to ensure high-speed signal characteristics. The system simulation outputs the link eye diagram and BER to verify the PCIe Gen4 signal integrity and timing margin.

[0091] In another example, refer to the attached instruction manual. Figure 5 The multi-board circuit is a DDR SO-DIMM. When performing DDR SO-DIMM simulation, the system includes the motherboard memory controller and the daughter card DRAM, which are interconnected through slots. The slots are modeled as 0-ohm resistor connectors. Pin mapping relationships are established to ensure that command, address and data signals correspond correctly. The simulation results can verify timing margin and signal integrity.

[0092] In one embodiment, refer to the appendix to the specification. Figure 6 This application provides a multi-board circuit simulation system, including an acquisition module 10, a marking module 20, a construction module 30, a mapping module 40, and a simulation module 50.

[0093] The acquisition module 10 is used to acquire the device pin information and network topology information of each circuit board in the multi-board circuit to be simulated; the marking module 20 is used to mark each device pin on each circuit board as the start or end point of cross-board signals according to the device pin information; the construction module 30 is used to construct a connector model with a unified interface, which includes a 0-ohm resistor model and an S-parameter model; the mapping module 40 is used to establish the cross-board pin mapping relationship of the device pins on each circuit board to the device pins on other circuit boards through the connector model according to the network topology information and the start or end point of the cross-board signals; the simulation module 50 is used to select the 0-ohm resistor model and / or the S-parameter model based on the type of cross-board signals, and perform system-level simulation in combination with the cross-board pin mapping relationship.

[0094] The technical concept of this multi-board circuit simulation system is the same as that of the multi-board circuit simulation method in the previous embodiment, and will not be described again in this embodiment.

[0095] In one embodiment, based on the foregoing embodiments, this application provides a computer device including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the multi-board circuit simulation method of the foregoing embodiments.

[0096] In one embodiment, based on the foregoing embodiments, this application provides a computer storage medium storing a computer program or instructions thereon, wherein the computer program or instructions, when executed by a processor, implement the steps of the multi-board circuit simulation method of the foregoing embodiments.

[0097] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-board circuit simulation method, characterized in that, Including the following steps: Obtain the device pin information and network topology information of each circuit board in the multi-board circuit to be simulated; Based on the device pin information, each device pin on each circuit board is marked as the start or end point of the cross-board signal; Construct a connector model with a unified interface, the connector model including a 0-ohm resistance model and an S-parameter model; the construction of the connector model with a unified interface includes: defining a unified interface class; Obtain the first port parameter file under ideal conduction state, construct the 0-ohm resistance model, the 0-ohm resistance model is adapted to the cross-board signal being a low-frequency signal; obtain the second port parameter file configuring high-frequency signal transmission characteristics, construct the S-parameter model, the S-parameter model is adapted to the cross-board signal being a high-frequency signal; Based on the network topology information and the start or end point of the cross-board signal, establish a cross-board pin mapping relationship where device pins on each board are mapped to device pins on other boards through the connector model; The 0-ohm resistor model and / or S-parameter model are selected based on the type of the cross-board signal, and multi-board circuit system-level simulation is performed in conjunction with the cross-board pin mapping relationship; when the cross-board signal between the circuit boards of the multi-board circuit is a low-frequency signal, the 0-ohm resistor model is selected; when the cross-board signal between the circuit boards of the multi-board circuit is a high-frequency signal, the S-parameter model is selected; when the cross-board signal between the circuit boards of the multi-board circuit includes both low-frequency and high-frequency signals, the 0-ohm resistor model and the S-parameter model are used in combination according to the corresponding cross-board signal.

2. The multi-board circuit simulation method according to claim 1, characterized in that, After establishing the cross-board pin mapping relationship, the following is also included: The integrity of the cross-board pin mapping relationship is checked to determine whether there are unmapped device pins or duplicated device pins, as well as whether there are differential pairs or positive and negative polarity mapping errors. If the determination is yes, the erroneous pins are marked and an error message is given to correct the cross-board pin mapping relationship.

3. The multi-board circuit simulation method according to claim 1, characterized in that, The establishment of cross-board pin mapping relationships, whereby device pins on each circuit board are mapped to device pins on other circuit boards via the connector model, includes: Preset pin mapping rules, including one-to-one sequential mapping, differential pair mapping, and cross mapping; Select the target pin mapping rule according to the mapping instruction, and after obtaining the network topology information and the start or end point of the cross-board signal, establish the cross-board pin mapping relationship of the device pins on each board to the device pins on other boards through the connector model according to the target pin mapping rule.

4. The multi-board circuit simulation method according to claim 1, characterized in that, The establishment of cross-board pin mapping relationships, whereby device pins on each circuit board are mapped to device pins on other circuit boards via the connector model, includes: Build a graphical interface and display each circuit board and the pins of the devices on each circuit board in real time; Establish image interaction rules, and based on the interaction instructions, establish cross-board pin mapping relationships between device pins on each circuit board and device pins on other circuit boards through the connector model.

5. The multi-board circuit simulation method according to claim 1, characterized in that, The method of marking each device pin on each circuit board as the start or end point of a cross-board signal based on the device pin information includes: Based on the device pin information and the network topology information, each device pin on each circuit board is divided into a first device pin with cross-board connection relationship and a second device pin without cross-board connection relationship. Mark the pins of each first device on each circuit board as the start or end point of the cross-board signal.

6. A multi-board circuit simulation system, characterized in that, include: The acquisition module is used to acquire the device pin information and network topology information of each circuit board in the multi-board circuit to be simulated; The marking module is used to mark each device pin on each circuit board as the start or end point of the cross-board signal according to the device pin information; The module constructs a connector model with a unified interface, which includes a 0-ohm resistance model and an S-parameter model. This includes: defining a unified interface class; obtaining a first port parameter file under ideal conduction conditions and constructing the 0-ohm resistance model, which is adapted to the cross-board signal being a low-frequency signal; obtaining a second port parameter file configuring high-frequency signal transmission characteristics and constructing the S-parameter model, which is adapted to the cross-board signal being a high-frequency signal. The mapping module is used to establish a cross-board pin mapping relationship between device pins on each board and device pins on other boards through the connector model, based on the network topology information and the start or end point of the cross-board signal. The simulation module is used to select the 0-ohm resistor model and / or S-parameter model based on the type of the cross-board signal, and to perform system-level simulation in conjunction with the cross-board pin mapping relationship; when the cross-board signal between the circuit boards of a multi-board circuit is a low-frequency signal, the 0-ohm resistor model is selected; when the cross-board signal between the circuit boards of a multi-board circuit is a high-frequency signal, the S-parameter model is selected; when the cross-board signal between the circuit boards of a multi-board circuit includes both low-frequency and high-frequency signals, the 0-ohm resistor model and the S-parameter model are used in combination according to the corresponding cross-board signal.

7. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the multi-board circuit simulation method according to any one of claims 1-5.

8. A computer storage medium storing computer programs or instructions thereon, characterized in that, When the computer program or instructions are executed by the processor, they implement the steps of the multi-board circuit simulation method according to any one of claims 1-5.

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