Display module, driving method and display device

Abstract

The application discloses a display module, a driving method and a display device. The display module comprises a photosensitive unit, the photosensitive unit comprising a plurality of sensing transistors; the gate of the sensing transistor is electrically connected with a control signal end or a ground end, the first pole of the sensing transistor is electrically connected with a driving signal line, and the second pole of the sensing transistor is electrically connected with a current output end; a light valve unit is arranged on the light entering side of the photosensitive unit, the orthographic projection of the light valve unit on a substrate and the orthographic projection of at least one sensing transistor on the substrate overlap, the light valve unit is configured to provide a signal on a data signal line to a pixel electrode in the light valve unit in response to a signal on a scanning signal line, so as to control the light valve unit to be in a first state or a second state; wherein the photosensitive unit is configured to provide a first current to the current output end when the light valve unit is in the first state, and provide a second current to the current output end when the light valve unit is in the second state, the first current being different from the second current.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to display modules, driving methods, and display devices. Background Technology

[0002] With the development of display technology, more and more display products integrate light sensors to detect ambient light levels in real time, enabling adaptive adjustment of screen brightness. However, the long-term reliability of light sensors integrated in large-size liquid crystal displays (LCDs) is currently insufficient. After prolonged reliability tests under high light, high temperature, and high humidity conditions, the current output by the light sensor changes significantly compared to its initial state. The sensed value obtained after analog-to-digital conversion of the current output by the light sensor deviates considerably, making it difficult to accurately reflect actual ambient light data and severely affecting detection accuracy. Summary of the Invention

[0003] The display module provided in this embodiment of the invention includes: a display panel, comprising a display area and a non-display area located on a substrate; The non-display area includes: A photosensitive unit includes multiple sensing transistors; the gate of each sensing transistor is electrically connected to a control signal terminal or a ground terminal, the first terminal of each sensing transistor is electrically connected to a drive signal line, and the second terminal of each sensing transistor is electrically connected to a current output terminal. A light valve unit is disposed on the light-incident side of the photosensitive unit. The orthographic projection of the light valve unit on the substrate overlaps with the orthographic projection of at least one of the sensing transistors on the substrate. The light valve unit is configured to provide a signal on the data signal line to the pixel electrode in the light valve unit in response to a signal on the scan signal line, so as to control the light valve unit to be in a first state or a second state. The photosensitive unit is configured to provide a first current to the current output terminal when the light valve unit is in the first state, and to provide a second current to the current output terminal when the light valve unit is in the second state, wherein the first current and the second current are different.

[0004] In some possible implementations, the first state is a light-transmitting state and the second state is a light-blocking state; or, the first state is a light-blocking state and the second state is a light-transmitting state.

[0005] In some possible implementations, the light valve unit includes an array of sub-pixel units; Each of the sub-pixel units includes: a pixel electrode, a pixel capacitor, and a transistor; The gate of the conducting transistor is electrically connected to the scan signal line, the first electrode of the conducting transistor is electrically connected to the data signal line, and the second electrode of the conducting transistor is electrically connected to the pixel electrode. The first electrode of the pixel capacitor is electrically connected to the pixel electrode, and the second electrode of the pixel capacitor is electrically connected to the scan signal line.

[0006] In some possible implementations, the orthographic projection of the light valve unit onto the substrate covers the orthographic projection of the entire sensing transistor onto the substrate.

[0007] In some possible implementations, the light valve unit includes: a first light valve unit and a second light valve unit; the plurality of sensing transistors includes: a plurality of first sensing transistors and a plurality of second sensing transistors; The orthographic projection of the first light valve unit onto the substrate covers the orthographic projection of the plurality of first sensing transistors onto the substrate. The orthographic projection of the second light valve unit onto the substrate covers the orthographic projection of the plurality of second sensing transistors onto the substrate.

[0008] In some possible implementations, the first optical valve unit and the second optical valve unit are electrically connected to the same scan signal line; the first optical valve unit and the second optical valve unit are electrically connected to different data signal lines, respectively. The gates of the first sensing transistor and the second sensing transistor are electrically connected to the ground terminal, the first terminals of the first sensing transistor and the second sensing transistor are electrically connected to the same drive signal line, and the second terminals of the first sensing transistor and the second sensing transistor are electrically connected to different current output terminals.

[0009] In some possible implementations, the scan signal line includes a first scan signal line and a second scan signal line; the data signal line includes a first data signal line and a second data signal line; the drive signal line includes a first drive signal line and a second drive signal line; and the current output terminal includes a first current output terminal and a second current output terminal. The first optical valve unit is electrically connected to the first scan signal line and the first data signal line; the second optical valve unit is electrically connected to the second scan signal line and the second data signal line. The gate of the first sensing transistor is electrically connected to the ground terminal, the first electrode of the first sensing transistor is electrically connected to the first drive signal line, and the second electrode of the first sensing transistor is electrically connected to the first current output terminal. The gate of the second sensing transistor is electrically connected to the ground terminal, the first terminal of the second sensing transistor is electrically connected to the second drive signal line, and the second terminal of the second sensing transistor is electrically connected to the second current output terminal.

[0010] In some possible implementations, the non-display area further includes a first switching transistor, a second switching transistor, and a third switching transistor; The gates of the first switching transistor, the second switching transistor, and the third switching transistor are all electrically connected to the switching control signal terminal; The first terminal of the first switching transistor is electrically connected to the first scan signal line, and the second terminal of the first switching transistor is electrically connected to the second scan signal line; The first terminal of the second switching transistor is electrically connected to the first data signal line, and the second terminal of the second switching transistor is electrically connected to the second data signal line; The first terminal of the third switching transistor is electrically connected to the first drive signal line, and the second terminal of the third switching transistor is electrically connected to the second drive signal line.

[0011] In some possible implementations, the orthogonal projection of the light valve unit onto the substrate covers a portion of the orthogonal projection of the sensing transistor onto the substrate.

[0012] In some possible implementations, the plurality of sensing transistors includes: a plurality of first sensing transistors and a plurality of second sensing transistors; The orthographic projection of the light valve unit onto the substrate covers the orthographic projection of the plurality of first sensing transistors onto the substrate.

[0013] In some possible implementations, the drive signal line includes a first drive signal line and a second drive signal line; the current output terminal includes a first current output terminal and a second current output terminal. The gate of the first sensing transistor is electrically connected to the ground terminal, the first electrode of the first sensing transistor is electrically connected to the first drive signal line, and the second electrode of the first sensing transistor is electrically connected to the first current output terminal. The gate of the second sensing transistor is electrically connected to the ground terminal, the first terminal of the second sensing transistor is electrically connected to the second drive signal line, and the second terminal of the second sensing transistor is electrically connected to the second current output terminal.

[0014] In some possible implementations, the non-display area further includes a fourth switching transistor; The gate of the fourth switching transistor is electrically connected to the switch control signal terminal, the first terminal of the fourth switching transistor is electrically connected to the first drive signal line, and the second terminal of the fourth switching transistor is electrically connected to the second drive signal line.

[0015] In some possible implementations, it also includes: a current mirror circuit and a sampling resistor; The input terminal of the current mirror circuit is electrically connected to the current output terminal, and the output terminal of the current mirror circuit is electrically connected to the first terminal of the sampling resistor. The current mirror circuit is configured to provide a mirror current to the first terminal of the sampling resistor according to the current output terminal. The second end of the sampling resistor is electrically connected to the ground terminal, and the sampling resistor is configured to convert the mirror current output by the current mirror circuit into a voltage signal.

[0016] In some possible implementations, a rectifier circuit is also included, electrically connected to a first terminal of the sampling resistor, configured to convert the voltage signal across the sampling resistor into the absolute value of the voltage signal as an output.

[0017] The display device provided in this embodiment of the invention includes the display module described above.

[0018] The driving method for the display module provided in this embodiment of the invention includes: In the working mode, the light valve unit responds to the signal on the scanning signal line and provides the signal on the data signal line to the pixel electrode in the light valve unit to control the light valve unit to be in the first state, load the first driving signal to the driving signal line, and obtain the first current provided by the photosensitive detection unit to the current output terminal. In calibration mode, the light valve unit responds to the signal on the scan signal line by providing the signal on the data signal line to the pixel electrode in the light valve unit, thereby controlling the light valve unit to be in the second state, loading the second drive signal to the drive signal line, and acquiring the second current provided by the photosensitive detection unit to the current output terminal. The first current is different from the second current. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a display module provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a display module provided in an embodiment of the present invention; Figure 3 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 4This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 5 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 6 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 7 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 8 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 9 A flowchart of a driving method for a display module provided in an embodiment of the present invention; Figure 10 A signal timing diagram is provided for an embodiment of the present invention; Figure 11 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 12 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 13 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 14 Another signal timing diagram is provided for embodiments of the present invention; Figure 15 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 16 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 17 This invention provides yet another signal timing diagram for embodiments of the invention; Figure 18 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 19 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 20 This provides yet another signal timing diagram for embodiments of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0022] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0023] Currently, to address the issue of detection accuracy drift caused by the aging of optical sensors, algorithms are typically used to compensate for the aging of the sensing values ​​obtained after analog-to-digital conversion of the current output by the optical sensor. However, this method requires determining the degree of aging of the optical sensor. Due to the fluctuation of the optical sensor's own characteristic parameters, the degree of aging of the optical sensor itself is uncertain, making it difficult to achieve accurate calibration. Therefore, the method of using algorithms for aging compensation is also difficult to guarantee the detection accuracy of the optical sensor after long-term failure.

[0024] To address the aforementioned issues, the display module provided in this embodiment of the invention can detect the lifespan of the optical sensor, thereby eliminating or accurately compensating for the drift in detection accuracy caused by the attenuation and aging of the optical sensor.

[0025] Figure 1 This is a schematic diagram of a display module provided in an embodiment of the present invention; Figure 2 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0026] In some embodiments of the present invention, such as Figure 1As shown, the display module includes: a display panel 100, comprising a display area AA and a non-display area BB located on a substrate; wherein, as Figure 2 As shown, the display area AA may include multiple pixel units arranged in an array, multiple scan control signal lines GA (e.g., GA1, GA2, GA3, GA4), and multiple data signal lines DA (e.g., DA1, DA2, DA3).

[0027] For example, each pixel unit may include multiple sub-pixels of different colors (spx). For instance, a pixel unit may include three sub-pixels of different colors: these three sub-pixels can be red, green, and blue, respectively. Alternatively, a pixel unit may also include four sub-pixels of different colors: red, green, blue, and white, respectively. It should be noted that in practical applications, the emission color and specific number of sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and this invention does not limit this.

[0028] In some embodiments of the present invention, such as Figure 2 As shown, each sub-pixel spx may include a switch control transistor 01 and a pixel electrode 02. In some embodiments, a row of sub-pixels spx is coupled to a scan control signal line GA, and a column of sub-pixels spx is coupled to a data signal line DA. Specifically, the gate of the switch control transistor 01 is coupled to the corresponding scan control signal line GA, the source of the switch control transistor 01 is coupled to the corresponding data signal line DA, and the drain of the switch control transistor 01 is coupled to the pixel electrode 02 in the same sub-pixel spx. In a specific implementation, when the scan drive signal loaded on the scan control signal line GA is at an active level, the switch control transistor 01 can be turned on. This allows the data voltage loaded on the data signal line DA to be input to the pixel electrode 02 through the turned-on switch control transistor 01, thereby charging the pixel electrode 02, i.e., charging the sub-pixel. Conversely, when the scan control signal loaded on the scan control signal line GA is at an inactive level, the switch control transistor 01 can be turned off. This allows the pixel electrode 02 to maintain the input data voltage through the turned-off switch control transistor 01.

[0029] In some embodiments of the present invention, the pixel array structure can also be a dual-gate structure, that is, two scan signal lines are arranged between two adjacent rows of sub-pixels. This arrangement can reduce the number of data signal lines by half; that is, some adjacent columns of sub-pixels include data signal lines, while others do not. It should be noted that in practical applications, the specific pixel arrangement structure and the arrangement of data signal lines and scan signal lines can be designed and determined according to the actual application environment, and the present invention does not limit this.

[0030] In some embodiments of the present invention, the display panel may be a liquid crystal display (LCD) panel. Exemplarily, a liquid crystal display panel generally includes an array substrate and a counter substrate, and a liquid crystal molecule layer encapsulated between the array substrate and the counter substrate. Exemplarily, when displaying an image, a voltage difference exists between the data voltage applied to the pixel electrode of each sub-pixel and the common electrode voltage on the common electrode. This voltage difference can form an electric field, causing the liquid crystal molecules in the liquid crystal molecule layer to deflect under the action of this electric field. Because different intensities of electric fields cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixels differs, enabling the sub-pixels to achieve different grayscale brightness levels, thereby realizing image display.

[0031] In some embodiments of the present invention, to prevent liquid crystal polarization, liquid crystal display panels often employ a polarity-inverting driving method, which requires switching the positive and negative polarities of the voltage of the data signal input to the sub-pixels. Polarity-inverting driving methods include frame inversion, row inversion, column inversion, and dot inversion. For example, for two adjacent image frames, the voltage polarity of the data signal input to the pixel electrode in one frame is positive (i.e., positive frame driving), while the voltage polarity of the data signal input to the same pixel electrode in the other frame is negative (i.e., negative frame driving); or, for two adjacent rows of sub-pixels, the voltage polarity of the data signal input to the pixel electrode of one row of sub-pixels is positive, while the voltage polarity of the data signal input to the pixel electrode of the other row of sub-pixels is negative.

[0032] For example, grayscale typically divides the brightness variation between the darkest and brightest points into several parts to facilitate brightness control of the display panel. For instance, if a displayed image consists of red, green, and blue colors, each color can be displayed at different brightness levels, and different brightness levels of red, green, and blue can be combined to form different colors. For example, if a liquid crystal display panel has a grayscale bit depth of 6 bits, then red, green, and blue each have 64 (i.e., 2^34) grayscale values. 6 There are 64 gray levels, with gray values ​​ranging from 0 to 63. If the LCD panel has an 8-bit grayscale bit depth, then red, green, and blue each have 256 (i.e., 2^64) gray levels. 8There are 256 gray levels, with gray values ​​ranging from 0 to 255. If the LCD panel has a 10-bit grayscale, then red, green, and blue each have 1024 (i.e., 2^35) grayscale values. 10 There are 1024 gray levels, with gray values ​​ranging from 0 to 1023. If the LCD panel has a 12-bit grayscale bit depth, then red, green, and blue each have 4096 (i.e., 2^32) gray levels. 12 There are 4096 gray levels, with gray values ​​ranging from 0 to 4093.

[0033] For example, taking a sub-pixel spx as an example, when the data voltage Vda1 input to the pixel electrode of the sub-pixel spx is greater than the common electrode voltage Vcom, the liquid crystal molecules at the sub-pixel spx can be made positive, and the polarity corresponding to the data voltage Vda1 in the sub-pixel spx is positive. When the data voltage Vda2 input to the pixel electrode of the sub-pixel spx is less than the common electrode voltage Vcom, the liquid crystal molecules at the sub-pixel spx can be made negative, and the polarity corresponding to the data voltage Vda2 in the sub-pixel spx is negative. For example, the common electrode voltage can be 8.3V. If a data voltage of 8.8V to 16V is input to the pixel electrode of the sub-pixel spx, the liquid crystal molecules at the sub-pixel spx can be made positive, and the data voltage of 8.8V to 16V is the data voltage corresponding to the positive polarity. If a data voltage of 0.6V to 7.8V is input to the pixel electrode of a sub-pixel sx, the liquid crystal molecules at that sub-pixel sx will be negatively polarized. Therefore, the 0.6V to 7.8V data voltage corresponds to the negative polarity. For example, taking an 8-bit grayscale of 0 to 255 as an example, if a data voltage of 16V is input to the pixel electrode of a sub-pixel sx, the sub-pixel sx can achieve the maximum grayscale value (i.e., grayscale value 255) brightness using a positive polarity data voltage. If a data voltage of 0.6V is input to the pixel electrode of a sub-pixel sx, the sub-pixel sx can achieve the maximum grayscale value (i.e., grayscale value 255) brightness using a negative polarity data voltage. It should be noted that there may be a voltage difference between the data voltage for grayscale value 0 and the common electrode voltage. For example, if the common electrode voltage is 8.3V, the positive polarity data voltage corresponding to grayscale value 0 can be 8.8V, and the negative polarity data voltage corresponding to grayscale value 0 can be 7.8V. Of course, the data voltage for 0 grayscale value and the common electrode voltage can also be the same. In practical applications, this can be determined according to the needs of the application, and is not limited here.

[0034] Figure 3 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0035] In some embodiments of the present invention, such as Figure 3 As shown, the non-display area BB includes: The photosensitive unit 10 includes multiple sensing transistors MT; the gate of the sensing transistor MT is electrically connected to the control signal terminal CS, the first terminal of the sensing transistor MT is electrically connected to the drive signal line DL, and the second terminal of the sensing transistor MT is electrically connected to the current output terminal Isen. A light valve unit 20 is disposed on the light-incident side of the photosensitive unit 10. The orthographic projection of the light valve unit 20 on the substrate overlaps with the orthographic projection of at least one sensing transistor MT on the substrate. The light valve unit 20 is configured to provide a signal on the data signal line DA to the pixel electrode in the light valve unit 20 in response to a signal on the scan signal line SS, so as to control the light valve unit 20 to be in a first state or a second state. The photosensitive unit 10 is configured to provide a first current to the current output terminal Isen when the light valve unit 20 is in a first state, and to provide a second current to the current output terminal Isen when the light valve unit 20 is in a second state, wherein the first current and the second current are different.

[0036] The display module provided in this invention provides a light valve unit that can switch between a first state and a second state on the light-incident side of the photosensitive unit. The photosensitive unit provides different first and second currents to the current output terminal when the light valve unit is in different states. These first and second currents reflect the electrical characteristics of the photosensitive unit under different lighting conditions, providing a data basis for determining the aging degree of the photosensitive unit and compensating for detection accuracy drift caused by the decay and aging of the sensing transistor. Accordingly, by comparing and analyzing the first and second currents, characteristic parameters reflecting the aging degree of the photosensitive unit can be extracted, enabling precise calibration and compensation, thereby improving the detection accuracy drift problem caused by the decay and aging of the sensing transistor. Furthermore, since both the photosensitive unit and the light valve unit are integrated into the non-display area of ​​the display panel, they do not occupy additional display area, which helps to improve the screen-to-body ratio.

[0037] For example, the light sensor can be understood as the photosensitive unit in this invention, wherein the sensing transistor in the photosensitive unit is generally a phototransistor, which is a photoelectric conversion device that converts light signals into electrical signals, and is usually a thin-film transistor or a bipolar transistor with photosensitive characteristics.

[0038] When a phototransistor operates in the cutoff region (i.e., the gate voltage is below the threshold voltage), the channel is off, and the current between the source and drain is primarily leakage current. Under illumination, the channel region absorbs incident photons and generates electron-hole pairs, forming photogenerated carriers. These carriers are collected under the source-drain bias voltage, thus generating photocurrent. Therefore, the leakage current output by a phototransistor operating in the cutoff region includes both photogenerated current and the device's inherent dark current component. The dark current originates from factors such as the intrinsic thermal excitation of carriers in the semiconductor material, interface states, and process defects, and its magnitude is significantly affected by temperature and the degree of device aging. When a phototransistor operates in the linear region (i.e., the gate voltage is higher than the sum of the threshold voltage and the drain-source voltage), the channel is fully conducting, and the source-drain connection is equivalent to a voltage-controlled resistor. At this time, the channel current is much larger than the photocurrent, and the proportion of the photocurrent component in the total conduction current is negligible. The magnitude of the conduction current mainly depends on parameters such as the gate voltage, drain-source voltage, and channel carrier mobility. The channel carrier mobility drifts with device aging and temperature changes; therefore, measuring the conduction current and calculating the equivalent resistance in the linear region can reflect the degree of aging of the phototransistor itself.

[0039] In some embodiments of the present invention, the first state is a light-transmitting state and the second state is a light-blocking state.

[0040] In some embodiments of the present invention, such as Figure 3 As shown, the orthographic projection of the light valve unit onto the substrate covers the orthographic projection of all the sensing transistors onto the substrate.

[0041] Figure 4 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0042] In some embodiments of the present invention, such as Figure 4 As shown, the light valve unit 20 includes sub-pixel units PX arranged in an array; Each sub-pixel unit PX includes: a pixel electrode d0, a pixel capacitor C0, and a turn-on transistor T0; wherein, the gate of the turn-on transistor T0 is electrically connected to the scan signal line SS, the first electrode of the turn-on transistor T0 is electrically connected to the data signal line DA, and the second electrode of the turn-on transistor T0 is electrically connected to the pixel electrode d0; the first electrode of the pixel capacitor C0 is electrically connected to the pixel electrode d0, and the second electrode of the pixel capacitor C0 is electrically connected to the scan signal line SS.

[0043] For example, if the turn-on transistor T0 is an N-type transistor, then the turn-on transistor T0 is turned on under the control of a high-level signal on the scan signal line SS, and the turn-on transistor T0 is turned off under the control of a low-level signal on the scan signal line SS; of course, the turn-on transistor T0 can also be a P-type transistor, then the turn-on transistor T0 is turned on under the control of a low-level signal on the scan signal line SS, and the turn-on transistor T0 is turned off under the control of a low-level signal on the scan signal line SS.

[0044] For example, the light valve unit 20 may further include: a first polarizer, a first substrate, a liquid crystal layer, a second substrate, and a second polarizer sequentially stacked on a substrate; the pixel electrode of the sub-pixel unit PX is disposed on the first substrate, and a common electrode is disposed on the second substrate; the liquid crystal layer is encapsulated between the pixel electrode and the common electrode.

[0045] For example, taking an N-type transistor as the conducting transistor, in the light-transmitting state, when a high-level signal is applied to the scanning signal line, the conducting transistor is turned on; a first gray-level data voltage (e.g., the voltage corresponding to L255) is applied to the data signal line, and the conducting transistor transmits the first gray-level data voltage to the pixel electrode, and the pixel capacitor stores the first gray-level data voltage; when a low-level signal is applied to the scanning signal line, the conducting transistor is turned off, and the pixel capacitor maintains the first gray-level data voltage on the pixel electrode; then a first electric field is formed between the first gray-level data voltage on the pixel electrode and the common voltage on the common electrode. Under the action of the first electric field, the liquid crystal molecules in the liquid crystal layer are deflected from the initial orientation to a light-transmitting orientation that matches the polarization direction of the incident light. The ambient light incident from the first polarizer is polarized by the first polarizer and becomes linearly polarized light; when the linearly polarized light passes through the liquid crystal layer in the light-transmitting orientation, its polarization direction is modulated, and it can be emitted through the second polarizer; at this time, the sub-pixel unit is in the light-transmitting state, and the incident light can pass through the light valve unit to reach the photosensitive unit below.

[0046] For example, taking an N-type transistor as the conducting transistor, in the light-shielding state, a high-level signal is applied to the scan signal line, and the conducting transistor is turned on; the data signal line provides a second gray-level data voltage (e.g., the voltage corresponding to L0), and the conducting transistor transmits the second gray-level data voltage to the pixel electrode, and the pixel capacitor stores the second gray-level data voltage; when a low-level signal is applied to the scan signal line, the conducting transistor is turned off, and the pixel capacitor maintains the second gray-level data voltage on the pixel electrode; a second electric field is formed between the second gray-level data voltage on the pixel electrode and the common voltage on the common electrode; under the action of the second electric field, the liquid crystal molecules in the liquid crystal layer maintain their initial orientation or deflect to a light-shielding orientation orthogonal to the polarization direction of the incident light; when the ambient light incident from the first polarizer is polarized and forms linearly polarized light, its polarization direction does not change or undergoes orthogonal rotation when passing through the liquid crystal layer in the light-shielding orientation, and it cannot pass through the second polarizer; at this time, the sub-pixel unit is in a light-shielding state, and the incident light is blocked by the light valve unit and cannot reach the photosensitive unit below.

[0047] Figure 5 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0048] In some embodiments of the present invention, such as Figure 5 As shown, the display module also includes: a current mirror circuit 30 and a sampling resistor R0; The input terminal of the current mirror circuit 30 is electrically connected to the current output terminal Isen, and the output terminal of the current mirror circuit 30 is electrically connected to the first terminal of the sampling resistor R0. The current mirror circuit 30 is configured to provide a mirror current to the first terminal of the sampling resistor R0 according to the current output terminal Isen. The second end of the sampling resistor R0 is electrically connected to the ground terminal GND. The sampling resistor R0 is configured to convert the mirror current output by the current mirror circuit 30 into a voltage signal.

[0049] Figure 6 This is another structural schematic diagram of the display module provided in an embodiment of the present invention. Figure 7 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0050] In some embodiments of the present invention, such as Figure 6 and Figure 7 As shown, the display module also includes: a microcontroller 40; The microcontroller unit (MCU) 40 is electrically connected to the first terminal of the sampling resistor R0, the drive signal line DL, and the control signal terminal CS via the control signal line CSL. The microcontroller unit 40 is configured to provide a first drive signal or a second drive signal to the drive signal line DL, provide a control signal to the control signal terminal CS, receive the voltage signal generated by the sampling resistor R0 based on the current output by the current mirror circuit 30, and convert the voltage signal into a digital signal through a built-in analog-to-digital converter. Based on the digital signal acquired when the light valve unit 20 is in the second state, it determines the characteristic parameters reflecting the aging degree of the photosensitive unit 10, and adjusts the conversion method of the output data based on the characteristic parameters and the digital signal acquired when the light valve unit 20 is in the first state. The output data is a digital quantity reflecting the ambient light intensity, and the conversion method is an algorithm or correspondence that converts the original digital quantity output by the analog-to-digital converter into an ambient light intensity digital quantity.

[0051] In some embodiments of the present invention, such as Figure 6 and Figure 7 As shown, the display module also includes: a timing controller 50 and a level converter 60; The timing controller 50 (TCON) is electrically connected to the microcontroller 40, the level converter 60, and the data signal line DA. The timing controller 50 is configured to receive mode control commands issued by the microcontroller 40. When the mode control command indicates the working mode, it generates a scan signal and a data signal that puts the light valve unit 20 in the first state. When the mode control command indicates the calibration mode, it generates a scan signal and a data signal that puts the light valve unit 20 in the second state.

[0052] Level shifter 60 (LS) is electrically connected between timing controller 50 and scan signal line SS. Level shifter 60 is configured to perform level shifting on the scan signal output by timing controller 50 and output the level-shifted scan signal to scan signal line SS.

[0053] In some embodiments of the present invention, such as Figure 7 As shown, the display module also includes a first circuit board, a second circuit board, a chip-on-film (COF) film, and a flexible flat cable (FFC). A timing controller 50 and a level converter 60 are mounted on the first circuit board. A microcontroller 40, a current mirror circuit 30, and a sampling resistor R0 are all mounted on the second circuit board. The first circuit board is electrically connected to the second circuit board via the flexible flat cable (FFC). The second circuit board is electrically connected to the non-display area BB of the display panel via the COF film.

[0054] Figure 8 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0055] In some embodiments of the present invention, such as Figure 8 As shown, the current mirror circuit 30 includes: a first transistor 30-M1, a second transistor 30-M2, a third transistor 30-M3, a fourth transistor 30-M4, and a reference current source I1; wherein, the input terminal of the reference current source I1 is electrically connected to the current output terminal Isen, and the output terminal of the reference current source I1 is electrically connected to the gates of the third transistor 30-M3 and the fourth transistor 30-M4; the bias signal terminal is electrically connected to the gates of the first transistor 30-M1 and the second transistor 30-M2; the first terminal of the first transistor 30-M1 is electrically connected to the output terminal of the reference current source I1, and the second terminal of the first transistor 30-M1 is electrically connected to the first terminal of the third transistor 30-M3; the second terminal of the third transistor 30-M3 is electrically connected to the ground terminal GND; the first terminal of the second transistor 30-M2 is electrically connected to the power supply signal terminal VDD, and the second terminal of the second transistor 30-M2 is electrically connected to the first terminal of the fourth transistor 30-M4; the second terminal of the fourth transistor 30-M4 is electrically connected to the first terminal of the sampling resistor R0.

[0056] Figure 9 A flowchart of a driving method for a display module provided in an embodiment of the present invention; The driving method for the display module provided in the embodiments of the present invention, such as Figure 9 As shown, it includes: S100. In the working mode, the light valve unit responds to the signal on the scanning signal line and provides the signal on the data signal line to the pixel electrode in the light valve unit to control the light valve unit to be in the first state, load the first driving signal to the driving signal line, and obtain the first current provided by the photosensitive detection unit to the current output terminal. S200. In calibration mode, the light valve unit responds to the signal on the scan signal line and provides the signal on the data signal line to the pixel electrode in the light valve unit to control the light valve unit to be in the second state, load the second drive signal to the drive signal line, and obtain the second current provided by the photosensitive detection unit to the current output terminal; wherein, the first current is different from the second current.

[0057] Figure 10 A signal timing diagram is provided for an embodiment of the present invention; For example, such as Figure 10As shown, dl1 is the first drive signal loaded on the drive signal line, dl2 is the second drive signal loaded on the drive signal line, ss is the scan signal loaded on the scan signal line SS, da1 is the first grayscale data voltage signal loaded on the data signal line DA, da2 is the second grayscale data voltage signal loaded on the data signal line DA, and cs is the control signal loaded on the control signal terminal CS.

[0058] under Figure 4 and Figure 6 Taking the structure of the display module shown as an example, combined with Figure 10 The signal timing diagram shown describes the working process of the display module provided in the embodiments of this disclosure.

[0059] In operating mode S1, the duty cycle of the scan signal ss is 50%, and the period is two frames, where 1H represents one frame; the voltage value when the scan signal ss is high is V. GH The voltage value when the scan signal ss is low is V. GL The first grayscale data voltage signal da1 flips every two frames, and its voltage is the first grayscale data voltage, which is V. L255+ or V L255- This ensures that the light valve unit is in a transparent state; the first driving signal dl1 is high for two consecutive frames out of every four frames, and there is a time interval t1 between the rising edge of the first driving signal dl1 and the rising edge of the first grayscale data voltage signal da1, to ensure that when the current of the photosensitive unit is collected during the high level of the first driving signal dl1, each sub-pixel unit in the light valve unit is fully in a transparent state; the control signal cs is a low level signal, and the voltage of the control signal cs is less than the threshold voltage V of the sensing transistor MT. th This ensures that the sensing transistor MT operates in the cutoff region; When the transistor T0 in each sub-pixel unit PX is turned on under the control of the high level of the scanning signal ss, the turned-on transistor T0 provides the first grayscale data voltage signal da1 to the pixel electrode. The first grayscale data voltage on the pixel electrode and the common voltage Vcom on the common electrode form a first electric field. The liquid crystal molecules in the liquid crystal layer are in a light-transmitting state, that is, the light valve unit 20 is in a light-transmitting state. Then the ambient light can pass through the light valve unit 20 to reach the photosensitive unit 10 below. The sensing transistor MT in the photosensitive unit 10 works in the cutoff region. The sensing transistor MT generates a first current I1 according to the first driving signal dl1 and provides it to the current output terminal Isen. Then the current mirror circuit 30 provides a first mirror current If1 to the first terminal of the sampling resistor R0 according to the first current I1. The sampling resistor R0 converts the first mirror current If1 into a first voltage signal. The microcontroller 40 collects the first voltage signal and converts the first voltage signal into a first digital signal through the built-in analog-to-digital converter. The first digital signal is the original sensing data output by the photosensitive unit under light-transmitting conditions, which includes the ambient light signal component and the dark current component of the sensing transistor.

[0060] In calibration mode S2, the scan signal ss is a low-level signal with a voltage value of V. GL The second grayscale data voltage signal da2 flips once per frame, and its voltage is the second grayscale data voltage, which is V. L0+ or V L0- This keeps the light valve unit in a light-blocking state; the control signal cs is a high-level signal with a voltage value greater than the threshold voltage V of the sensing transistor. th The voltage value V of the second drive signal dl2 DS The sum (i.e., V) th +V DS This ensures that the sensing transistor MT operates in the linear region; the second drive signal dl2 is a high-level signal with a voltage value of V. DS .

[0061] When the transistor T0 in each sub-pixel unit PX is turned on under the control of the high level of the scan signal ss (this stage is not shown in the figure), the turned-on transistor T0 provides the second grayscale data voltage signal da2 to the pixel electrode. A second electric field is formed between the second grayscale data voltage on the pixel electrode and the common voltage Vcom on the common electrode. The liquid crystal molecules in the liquid crystal layer are in a light-transmitting state, that is, the light valve unit 20 is in a light-blocking state. Therefore, ambient light is blocked and cannot reach the photosensitive unit 10 below the light valve unit. Then, the transistor T0 is turned off under the control of the low level of the scan signal ss. The pixel capacitor maintains the second grayscale data voltage written on the pixel electrode in the previous writing stage. The light valve unit is kept in a light-blocking state; the sensing transistor MT in the photosensitive unit 10 operates in the linear region. Under the bias of the second driving signal dl2, the sensing transistor MT generates a second current I2 and provides the second current I2 to the current mirror circuit 30 through the current output terminal Isen; then the current mirror circuit 30 provides a second mirror current If2 to the first terminal of the sampling resistor R0 according to the second current I2; the sampling resistor R0 converts the second mirror current If2 into a second voltage signal; the microcontroller 40 acquires the second voltage signal and converts the second voltage signal into a second digital signal through the built-in analog-to-digital converter; the microcontroller 40 calculates the voltage value V of the second digital signal and the second driving signal dl2. DS The equivalent resistance of the sensing transistor MT is calculated, and the characteristic parameters reflecting the aging degree of the photosensitive unit 10 are determined based on the equivalent resistance, so as to adjust the conversion method of determining the ambient light output value based on the first digital signal.

[0062] The sensing transistor MT in the photosensitive unit operates in the linear region. Under the bias of the second driving signal dl2, the sensing transistor MT generates a second current I2 and provides the second current I2 to the current mirror circuit via the current output terminal Isen. The current mirror circuit provides a second mirror current If2 to the first terminal of the sampling resistor R0 based on the second current I2. The sampling resistor R0 converts the second mirror current If2 into a second voltage signal. The microcontroller acquires the second voltage signal and converts it into a second digital signal through the built-in analog-to-digital converter. The microcontroller then calculates the voltage value V between the second digital signal and the second driving signal dl2. DSThe equivalent resistance of the sensing transistor MT is calculated, and characteristic parameters reflecting the aging degree of the sensing transistor are determined based on the equivalent resistance. This allows the microcontroller to adjust the conversion method for determining the ambient light output value based on the first digital signal. In other words, the microcontroller uses characteristic parameters reflecting the aging degree (such as equivalent resistance) obtained in calibration mode to correct the algorithm or correspondence for converting the first digital signal into an ambient light output value in operating mode. For example, the dark current reference value and / or gain coefficient in the calculation formula are adjusted based on the characteristic parameters, so that even after the sensing transistor has aged, the component purely contributed by ambient light can still be accurately extracted from the first digital signal, thereby obtaining an accurate ambient light output value.

[0063] This invention provides other embodiments of the display module, which are modifications of the embodiments described above. The differences between this embodiment and the above embodiments are described below; similarities are not repeated here.

[0064] Figure 11 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 12 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0065] In some embodiments of the present invention, such as Figure 11 As shown, the light valve unit includes: a first light valve unit 20-1 and a second light valve unit 20-2; the multiple sensing transistors include: multiple first sensing transistors MT1 and multiple second sensing transistors MT2; The orthographic projection of the first light valve unit 20-1 onto the substrate covers the orthographic projection of the plurality of first sensing transistors MT1 onto the substrate. The orthographic projection of the second light valve unit 20-2 onto the substrate covers the orthographic projection of the multiple second sensing transistors MT2 onto the substrate.

[0066] In some embodiments of the present invention, such as Figure 11 As shown, the scan signal line SS includes a first scan signal line SS1 and a second scan signal line SS2; the data signal line DA includes a first data signal line DA1 and a second data signal line DA2; the drive signal line DL includes a first drive signal line DL1 and a second drive signal line DL2; and the current output terminal Isen includes a first current output terminal Isen1 and a second current output terminal Isen2. The first optical valve unit 20-1 is electrically connected to the first scan signal line SS1 and the first data signal line DA1; the second optical valve unit 20-2 is electrically connected to the second scan signal line SS1 and the second data signal line SS2. The gate of the first sensing transistor MT1 is electrically connected to the ground terminal GND, the first terminal of the first sensing transistor MT1 is electrically connected to the first drive signal line DL1, and the second terminal of the first sensing transistor MT1 is electrically connected to the first current output terminal Isen1. The gate of the second sensing transistor MT2 is electrically connected to the ground terminal GND, the first terminal of the second sensing transistor MT2 is electrically connected to the second drive signal line DL2, and the second terminal of the second sensing transistor MT2 is electrically connected to the second current output terminal Isen2.

[0067] In some embodiments of the present invention, such as Figure 11 As shown, the non-display area BB also includes a first switching transistor MK1, a second switching transistor MK2, and a third switching transistor MK3; The gates of the first switching transistor MK1, the second switching transistor MK2, and the third switching transistor MK3 are all electrically connected to the switch control signal terminal EN. The first terminal of the first switching transistor MK1 is electrically connected to the first scan signal line SS1, and the second terminal of the first switching transistor MK1 is electrically connected to the second scan signal line SS2. The first terminal of the second switching transistor MK2 is electrically connected to the first data signal line DA1, and the second terminal of the second switching transistor MK2 is electrically connected to the second data signal line DA2. The first terminal of the third switching transistor MK3 is electrically connected to the first drive signal line DL1, and the second terminal of the third switching transistor MK3 is electrically connected to the second drive signal line DL2.

[0068] For example, when the first switching transistor MK1, the second switching transistor MK2, and the third switching transistor MK3 are N-type transistors, they can be turned on under the control of a high level of the signal on the switching control signal terminal EN, and turned off under the control of a low level of the signal on the switching control signal terminal EN; when the first switching transistor MK1, the second switching transistor MK2, and the third switching transistor MK3 are P-type transistors, they can be turned on under the control of a low level of the signal on the switching control signal terminal EN, and turned off under the control of a high level of the signal on the switching control signal terminal EN.

[0069] In some embodiments of the present invention, such as Figure 11 As shown, the current mirror circuit 20-1 is electrically connected between the first current output terminal Isen1 and the first terminal of the sampling resistor R0; the current mirror circuit 20-2 is electrically connected between the second current output terminal Isen2 and the first terminal of the sampling resistor R0.

[0070] In some embodiments of the present invention, such as Figure 11 and Figure 12As shown, the microcontroller 40 is electrically connected to the switch control signal terminal EN via the switch control signal line ENL.

[0071] In some embodiments of the present invention, such as Figure 11 and Figure 13 As shown, the display module also includes a rectifier circuit 70, electrically connected to the first terminal of the sampling resistor R0, configured to convert the voltage signal across the sampling resistor R0 into the absolute value of the voltage signal output; the rectified input signal terminal VIN is electrically connected to the first terminal of the sampling resistor R0, and the rectified output signal terminal VOUT is electrically connected to the microcontroller 40.

[0072] Figure 13 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0073] In some embodiments of the present invention, such as Figure 13 As shown, the rectifier circuit 70 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a feedback resistor Rf, a diode E1, a diode E2, an operational amplifier A1, and an operational amplifier A2; wherein, the first end of the first resistor R1 is electrically connected to the rectified input signal terminal VIN, and the second end of the first resistor R1 is electrically connected to the inverting input terminal of the first operational amplifier A1; the first end of the second resistor R2 is electrically connected to the inverting input terminal of the first operational amplifier A1, and the second end of the second resistor R2 is electrically connected to the output terminal of the first operational amplifier A1; the first end of the third resistor R3 is electrically connected to the rectified input signal terminal VIN, and the second end of the third resistor R3 is electrically connected to the inverting input terminal of the second operational amplifier A2; the first end of the fourth resistor R4 is electrically connected to the cathode of the diode E2, and the fourth resistor... The second terminal of resistor R4 is electrically connected to the inverting input terminal of the second operational amplifier A2; the first terminal of the fifth resistor R5 is electrically connected to the non-inverting input terminal of the first operational amplifier A1, and the second terminal of the fifth resistor R5 is electrically connected to the ground terminal GND; the first terminal of the sixth resistor R6 is electrically connected to the non-inverting input terminal of the second operational amplifier A2, and the second terminal of the sixth resistor R6 is electrically connected to the ground terminal GND; the first terminal of the feedback resistor Rf is electrically connected to the inverting input terminal of the second operational amplifier A2, and the second terminal of the feedback resistor Rf is electrically connected to the output terminal of the second operational amplifier A2; the cathode of diode E1 is electrically connected to the inverting input terminal of the first operational amplifier A1, and the anode of diode E1 is electrically connected to the output terminal of the first operational amplifier A1; the anode of diode E2 is electrically connected to the output terminal of the first operational amplifier A1, and the cathode of diode E2 is electrically connected to the first terminal of the fourth resistor R4.

[0074] In some embodiments of the present invention, such as Figure 13As shown, the first resistor R1, the second resistor R2, the third resistor R3 and the feedback resistor Rf have the same resistance value, and the resistance value of the feedback resistor Rf is twice the resistance value of the fourth resistor R4.

[0075] Figure 14 Another signal timing diagram is provided for embodiments of the present invention; For example, such as Figure 14 As shown, dl1 is the first drive signal loaded on the drive signal line, dl2 is the second drive signal loaded on the drive signal line, ss is the scan signal loaded on the scan signal line SS, da1 is the first grayscale data voltage signal loaded on the data signal line DA, da2 is the second grayscale data voltage signal loaded on the data signal line DA, and en is the switch control signal loaded on the switch control signal terminal EN.

[0076] under Figure 4 and Figure 11 Taking the structure of the display module shown as an example, combined with Figure 14 The signal timing diagram shown describes the working process of the display module provided in the embodiments of this disclosure.

[0077] In operating mode S1, the duty cycle of the scan signal ss is 50%, and the period is two frames, where 1H represents one frame; the voltage value when the scan signal ss is high is V. GH The voltage value when the scan signal ss is low is V. GL The first grayscale data voltage signal da1 flips every two frames, and its voltage is the first grayscale data voltage, which is V. L255+ or V L255- This ensures that the light valve unit is in a light-transmitting state; the first driving signal dl1 is high for two consecutive frames out of every four frames, and there is a time interval t1 between the rising edge of the first driving signal dl1 and the rising edge of the first grayscale data voltage signal da1, so as to ensure that when the current of the photosensitive unit is collected during the period when the first driving signal dl1 is high, each sub-pixel unit in the light valve unit is fully in a light-transmitting state; the switch control signal en is a low-level signal. The conducting transistor T0 in the first light valve unit 20-1 is turned on under the control of the high level of the scanning signal ss. The turned-on transistor T0 provides the first gray-level data voltage signal da1 to the pixel electrode. The first gray-level data voltage on the pixel electrode and the common voltage Vcom on the common electrode form a first electric field. The liquid crystal molecules in the liquid crystal layer are in a light-transmitting state, that is, the first light valve unit 20-1 is in a light-transmitting state. Then, ambient light can pass through the first light valve unit 20-1 and reach the first sensing transistor MT1 in the photosensitive unit 10 below. The first sensing transistor MT1 generates a first current I1 according to the first driving signal dl1 and provides it to the first sensor. A current output terminal Isen1 is provided; then the current mirror circuit 30-1 provides a first mirror current If1 to the first terminal of the sampling resistor R0 according to the first current I1; the sampling resistor R0 converts the first mirror current If1 into a first voltage signal; the microcontroller 40 acquires the first voltage signal, and the microcontroller 40 converts the first voltage signal into a first digital signal through the built-in analog-to-digital converter, wherein the first digital signal is the original sensing data output by the photosensitive unit under light transmission conditions, which includes the ambient light signal component and the dark current component of the sensing transistor; at this time, the second light valve unit is in the light-blocking state, and the second sensing transistor MT2 is in the non-working state; In calibration mode S2, the scan signal ss is a low-level signal with a voltage value of V. GL The second grayscale data voltage signal da2 flips once per frame, and its voltage is the second grayscale data voltage, which is V. L0+ or V L0- This keeps the light valve unit in a light-blocking state; the second drive signal dl2 is high for two consecutive frames out of every four frames; the switch control signal en is a high-level signal. The first switching transistor MK1, the second switching transistor MK2, and the third switching transistor MK3 are turned on under the control of the high level of the switching control signal en; the turned-on first switching transistor MK1 turns on the first scan signal line SS1 and the second scan signal line SS2; the turned-on second switching transistor MK2 turns on the first data signal line DA1 and the second data signal line DA2; the turned-on third switching transistor MK3 turns on the first drive signal line DL1 and the second drive signal line DL2. When the transistor T0 in each sub-pixel unit PX is turned on under the control of the high level of the scanning signal ss (this stage is not shown in the figure), the turned-on transistor T0 provides the second grayscale data voltage signal da2 to the pixel electrode. A second electric field is formed between the second grayscale data voltage on the pixel electrode and the common voltage Vcom on the common electrode. The liquid crystal molecules in the liquid crystal layer are in a light-transmitting state, that is, the light valve unit 20 is in a light-blocking state. Then, the ambient light is blocked and cannot reach the photosensitive unit 10 below the first light valve unit 20-1 and the second light valve unit 20-2. Then, the transistor T0 is turned off under the control of the low level of the scanning signal ss, and the pixel capacitance maintains the image. The second grayscale data voltage written on the base electrode during the previous writing stage keeps the first light valve unit 20-1 and the second light valve unit 20-2 in a light-blocking state; the first sensing transistor MT1 in the photosensitive unit 10 generates a second current I2-1 under the bias of the second driving signal dl2, and provides the second current I2-1 to the current mirror circuit 30-1 through the first current output terminal Isen1; the first current mirror circuit 30-1 provides a second mirror current If2-1 to the first terminal of the sampling resistor R0 according to the second current I2-1; the second sensing transistor MT2 in the photosensitive unit 10 generates a second current I2-2 under the bias of the second driving signal dl2, and provides the second current I... 2-2 is supplied to the current mirror circuit 30-2 via the second current output terminal Isen2; the current mirror circuit 30-2 provides a second mirror current If2-2 to the first terminal of the sampling resistor R0 according to the second current I2-2; since the second sensing transistor MT2 is permanently shielded from light and its aging degree is close to the ideal use condition, while the first sensing transistor MT1 has undergone aging in the actual use environment, there is a difference between the second current I2-1 and the third current I2-2. This difference reflects the aging degree of the first sensing transistor MT1 compared to the ideal state; then the sampling resistor R0 converts the difference current between the second mirror current If2-1 and the third mirror current If2-2 into a differential current. The voltage signal; the rectifier circuit 70 receives the differential voltage signal and converts it into its absolute value before outputting it; the microcontroller 40 acquires the absolute value of the differential voltage signal and converts it into a differential digital signal through a built-in analog-to-digital converter; the microcontroller 40 determines characteristic parameters reflecting the aging degree of the first sensing transistor MT1 based on the differential digital signal, so as to adjust the conversion method for determining the ambient light illuminance output value based on the first digital signal; that is, the microcontroller uses the characteristic parameters reflecting the aging degree (such as the differential digital signal) obtained in calibration mode to correct the algorithm or correspondence for converting the first digital signal into the ambient light illuminance output value in the working mode. For example, the dark current reference value and / or gain coefficient in the calculation formula are adjusted according to the characteristic parameters so that even after the sensing transistor ages, the component purely contributed by ambient light can still be accurately extracted from the first digital signal, thereby obtaining an accurate ambient light illuminance output value.

[0078] This invention provides further embodiments of the display module, which are modifications of the embodiments described above. The differences between this embodiment and the above embodiments are described below; similarities are not repeated here.

[0079] Figure 15 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 16 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0080] In some embodiments of the present invention, such as Figure 15 As shown, the light valve unit includes: a first light valve unit 20-1 and a second light valve unit 20-2; the multiple sensing transistors include: multiple first sensing transistors MT1 and multiple second sensing transistors MT2; The orthographic projection of the first light valve unit 20-1 onto the substrate covers the orthographic projection of the plurality of first sensing transistors MT1 onto the substrate. The orthographic projection of the second light valve unit 20-2 onto the substrate covers the orthographic projection of the multiple second sensing transistors MT2 onto the substrate.

[0081] In some embodiments of the present invention, such as Figure 15 As shown, the first optical valve unit 20-1 and the second optical valve unit 20-2 are electrically connected to the same scanning signal line SS; the first optical valve unit 20-1 and the second optical valve unit 20-2 are electrically connected to different data signal lines DA-1 and DA-2, respectively. The gates of the first sensing transistor MT1 and the second sensing transistor MT2 are electrically connected to the ground terminal. The first terminals of the first sensing transistor MT1 and the second sensing transistor MT2 are electrically connected to the same drive signal line DL. The second terminals of the first sensing transistor MT1 and the second sensing transistor MT2 are electrically connected to different current output terminals Isen-1 and Isen-2, respectively.

[0082] In some embodiments of the present invention, such as Figure 15 As shown, the current mirror circuit 20-1 is electrically connected between the current output terminal Isen-1 and the first terminal of the sampling resistor R0; the current mirror circuit 20-2 is electrically connected between the current output terminal Isen-2 and the first terminal of the sampling resistor R0.

[0083] Figure 17 Another signal timing diagram is provided for embodiments of the present invention; For example, such as Figure 17As shown, dl1 is the first drive signal loaded on the drive signal line, dl2 is the second drive signal loaded on the drive signal line, ss is the scan signal loaded on the scan signal line SS, da-11 is the first grayscale data voltage signal loaded on the data signal line DA-1, da-12 is the second grayscale data voltage signal loaded on the data signal line DA-1, da-21 is the first grayscale data voltage signal loaded on the data signal line DA-2, and da-22 is the second grayscale data voltage signal loaded on the data signal line DA-2.

[0084] under Figure 4 and Figure 15 Taking the structure of the display module shown as an example, combined with Figure 17 The signal timing diagram shown describes the working process of the display module provided in the embodiments of this disclosure.

[0085] In operating mode S1 and calibration mode S2, the duty cycle of the scan signal ss is 50%, and the period is two frames, where 1H represents one frame; the voltage value when the scan signal ss is high is V. GH The voltage value when the scan signal ss is low is V. GL The first grayscale data voltage signal da-21 flips every two frames, and its voltage is the first grayscale data voltage, which is V. L255+ or V L255- This puts the second light valve unit 30-2 in a light-transmitting state; the second grayscale data voltage signal da-11 flips every two frames, and its voltage is the second grayscale data voltage, which is V. L0+ or V L0- This causes the first light valve unit 30-1 to be in a light-blocking state; that is, the first grayscale data voltage and the second grayscale data voltage are alternately applied on the data signal line DA-1 and the data signal line DA-2, so the first light valve unit 30-1 and the second light valve unit 30-2 are alternately in a light-transmitting state or a light-blocking state; the first driving signal dl1 is high for two consecutive frames in every four frames, and there is a time interval t1 between the rising edge of the first driving signal dl1 or the second driving signal dl2 and the rising edge of the first grayscale data voltage signal da-11, da-21, so as to ensure that when the current of the photosensitive unit is collected during the period when the first driving signal dl1 or the second driving signal dl2 is high, each sub-pixel unit in the first light valve unit 30-1 or the second light valve unit 30-2 is completely in a light-transmitting state; The conducting transistor T0 in the first light valve unit 20-1 is turned on under the control of the high level of the scanning signal ss. The turned-on transistor T0 provides the second gray level data voltage signal da-12 to the pixel electrode. The second gray level data voltage signal da-12 on the pixel electrode and the common voltage Vcom on the common electrode form a second electric field. The liquid crystal molecules in the liquid crystal layer are in a light-blocking state, that is, the first light valve unit 20-1 is in a light-blocking state. Then the ambient light is blocked and cannot reach the first sensing transistor MT1 in the photosensitive unit 10 below the first light valve unit 20-1. The conducting transistor T0 in the second light valve unit 20-2 is turned on under the control of the high level of the scanning signal ss. The turned-on transistor T0 provides the first gray level data voltage signal da-21 to the pixel electrode. The first gray level data voltage signal da-21 on the pixel electrode and the common voltage Vcom on the common electrode form a first electric field. The liquid crystal molecules in the liquid crystal layer are in a light-transmitting state, that is, the second light valve unit 20-2 is in a light-transmitting state. Then the ambient light can pass through the second light valve unit 20-2 to reach the second sensing transistor MT2 in the photosensitive unit 10 below. The second sensing transistor MT2 in the photosensitive unit 10 generates a first current I1 under the bias of the first driving signal dl1, and provides the first current I1 to the current mirror circuit 30-2 through the current output terminal Isen-2; the current mirror circuit 30-2 provides a first mirror current If1 to the first terminal of the sampling resistor R0 according to the first current I1. The first sensing transistor MT1 in the photosensitive unit 10 generates a second current I2-1 under the bias of the second driving signal dl2, and provides the second current I2 to the current mirror circuit 30-1 through the current output terminal Isen-1; the current mirror circuit 30-1 provides a second mirror current If2 to the first terminal of the sampling resistor R0 according to the second current I2. Since the first sensing transistor MT1 and the second sensing transistor MT2 receive light for the same amount of time, they have the same degree of aging. Therefore, the dark current component in the first current I1 is equal to the dark current component in the second current I2. The sampling resistor R0 converts the difference between the first mirror current If1 and the second mirror current If2 into a differential voltage signal. This differential voltage signal cancels out the common-mode drift of the dark current component and reflects the pure ambient light signal component.

[0086] The rectifier circuit 70 receives the differential voltage signal and outputs it after converting it into its absolute value. The microcontroller 40 acquires the absolute value of the differential voltage signal and converts it into a differential digital signal through its built-in analog-to-digital converter. The microcontroller 40 determines the ambient light intensity output value based on the differential digital signal. The microcontroller 40 uses the differential digital signal as photosensitive data after differential compensation. Since the common-mode drift has been canceled by hardware differential processing, the drift amplitude of the differential digital signal is small and can directly reflect the ambient light intensity without the need for additional aging compensation algorithm switching.

[0087] This invention provides further embodiments of the display module, which are modifications of the embodiments described above. The differences between this embodiment and the above embodiments are described below; similarities are not repeated here.

[0088] Figure 18 This is another structural schematic diagram of the display module provided in an embodiment of the present invention; Figure 19 This is another structural schematic diagram of the display module provided in an embodiment of the present invention.

[0089] In some embodiments of the present invention, the first state is a light-blocking state and the second state is a light-transmitting state.

[0090] In some embodiments of the present invention, the light valve unit senses the orthogonal projection of the transistor onto the substrate in the orthogonal projection of the substrate.

[0091] In some embodiments of the present invention, such as Figure 18 As shown, the plurality of sensing transistors include: a plurality of first sensing transistors MT1 and a plurality of second sensing transistors MT2; The orthographic projection of the light valve unit 20 onto the substrate covers the orthographic projection of the plurality of first sensing transistors MT1 onto the substrate.

[0092] In some embodiments of the present invention, such as Figure 18 As shown, the drive signal line DL includes a first drive signal line DL1 and a second drive signal line DL2; the current output terminal Isen includes a first current output terminal Isen1 and a second current output terminal Isen2. The gate of the first sensing transistor MT1 is electrically connected to the ground terminal GND, the first terminal of the first sensing transistor MT1 is electrically connected to the first drive signal line DL1, and the second terminal of the first sensing transistor MT1 is electrically connected to the first current output terminal Isen1. The gate of the second sensing transistor MT2 is electrically connected to the ground terminal, the first terminal of the second sensing transistor MT2 is electrically connected to the second drive signal line DL2, and the second terminal of the second sensing transistor MT2 is electrically connected to the second current output terminal Isen2.

[0093] In some embodiments of the present invention, such as Figure 18 As shown, the non-display area also includes a fourth switching transistor MK4; The gate of the fourth switching transistor MK4 is electrically connected to the switch control signal terminal EN, the first terminal of the fourth switching transistor MK4 is electrically connected to the first drive signal line DL1, and the second terminal of the fourth switching transistor MK4 is electrically connected to the second drive signal line DL2.

[0094] In some embodiments of the present invention, such as Figure 18 and Figure 19 As shown, the microcontroller 40 is electrically connected to the switch control signal terminal EN via the switch control signal line ENL.

[0095] Figure 20 Another signal timing diagram is provided for embodiments of the present invention; For example, such as Figure 20 As shown, dl1 is the first drive signal loaded on the drive signal line, dl2 is the second drive signal loaded on the drive signal line, ss is the scan signal loaded on the scan signal line SS, da1 is the first grayscale data voltage signal loaded on the data signal line DA, da2 is the second grayscale data voltage signal loaded on the data signal line DA, and en is the switch control signal loaded on the switch control signal terminal EN.

[0096] under Figure 4 and Figure 18 Taking the structure of the display module shown as an example, combined with Figure 20 The signal timing diagram shown describes the working process of the display module provided in the embodiments of this disclosure.

[0097] In operating mode S1, the scan signal ss is a low-level signal with a voltage value of V. GL The second grayscale data voltage signal da2 flips once per frame, and its voltage is the second grayscale data voltage, which is V. L0+ or V L0- This keeps the light valve unit in a light-blocking state; the second drive signal dl2 is high for two consecutive frames out of every four frames; the switch control signal en is low. When the transistor T0 in each sub-pixel unit PX is turned on under the control of the high level of the scan signal ss (this stage is not shown in the figure), the turned-on transistor T0 provides the second grayscale data voltage signal da2 to the pixel electrode. A second electric field is formed between the second grayscale data voltage on the pixel electrode and the common voltage Vcom on the common electrode. The liquid crystal molecules in the liquid crystal layer are in a light-transmitting state, that is, the light valve unit 20 is in a light-blocking state. Ambient light is blocked and cannot reach the first sensing transistor MT1 in the photosensitive unit 10 below the light valve unit 20. Then, the transistor T0 is turned off under the control of the low level of the scan signal ss. The pixel capacitor maintains the second grayscale data voltage written on the pixel electrode in the previous writing stage, so that the light valve unit... 20. Maintain the light-blocking state; the second sensing transistor MT2 generates a first current I1 according to the first driving signal dl1 and provides it to the second current output terminal Isen2; then the current mirror circuit 30-1 provides a first mirror current If1 to the first terminal of the sampling resistor R0 according to the first current I1; the sampling resistor R0 converts the first mirror current If1 into a first voltage signal; the microcontroller 40 acquires the first voltage signal, and the microcontroller 40 converts the first voltage signal into a first digital signal through the built-in analog-to-digital converter, wherein the first digital signal is the original sensing data output by the photosensitive unit under light transmission conditions, which includes the ambient light signal component and the dark current component of the sensing transistor; at this time, the light valve unit is in the light-blocking state, and the second sensing transistor MT1 is in the non-working state; In calibration mode S2, the duty cycle of the scan signal ss is 50%, and the period is two frames, where 1H represents one frame; the voltage value when the scan signal ss is high is V. GH The voltage value when the scan signal ss is low is V. GL The first grayscale data voltage signal da1 flips every two frames, and its voltage is the first grayscale data voltage, which is V. L255+ or V L255- This ensures that the light valve unit is in a light-transmitting state; the second driving signal dl2 is high for two consecutive frames out of every four frames, and there is a time interval t1 between the rising edge of the second driving signal dl2 and the rising edge of the first grayscale data voltage signal da1, so as to ensure that when the current of the photosensitive unit is collected during the period when the second driving signal dl2 is high, each sub-pixel unit in the light valve unit is completely in a light-transmitting state; the switch control signal en is a high-level signal. When the switch control signal en is high, the fourth switch transistor MK4 is turned on, and the second drive signal dl2 on the first drive signal line DL1 is transmitted to the second drive signal line DL2 through the turned-on fourth switch transistor MK4, so that the first sensing transistor MT1 and the second sensing transistor MT2 in the photosensitive unit 10 both receive the second drive signal dl2.

[0098] The conducting transistor T0 in the light valve unit 20 is turned on under the control of the high level of the scanning signal ss. The turned-on transistor T0 provides the first gray level data voltage signal da1 to the pixel electrode. The first gray level data voltage on the pixel electrode and the common voltage Vcom on the common electrode form a first electric field. The liquid crystal molecules in the liquid crystal layer are in a light-transmitting state, that is, the light valve unit 20 is in a light-transmitting state. Then the ambient light can pass through the light valve unit 20 to reach the first sensing transistor MT1 in the photosensitive unit 10 below. The first sensing transistor MT1 in the photosensitive unit 10 generates a second current I2-1 under the bias of the second driving signal dl2, and provides the second current I2-1 to the current mirror circuit 30-1 through the first current output terminal Isen1; the first current mirror circuit 30-1 provides a second mirror current If2-1 to the first terminal of the sampling resistor R0 according to the second current I2-1; the second current I2-1 includes the photocurrent component and the dark current component of the first sensing transistor MT1.

[0099] The second sensing transistor MT2 in the photosensitive unit 10 generates a second current I2-2 under the bias of the second driving signal dl2, and provides the second current I2-2 to the current mirror circuit 30-2 through the second current output terminal Isen2; the second current mirror circuit 30-2 provides a second mirror current If2-2 to the first terminal of the sampling resistor R0 according to the second current I2-2; the second mirror current If2-1 and the third mirror current If2-2 flow into the first terminal of the sampling resistor R0 at the same time; the second current I2-2 includes the photocurrent component and the dark current component of the second sensing transistor MT2.

[0100] The sampling resistor R0 converts the difference between the second mirror current If2-1 and the second mirror current If2-2 into a differential voltage signal, which reflects the difference between the two currents. The rectifier circuit 70 receives this differential voltage signal, converts it into its absolute value, and outputs it. The microcontroller 40 acquires the absolute value of the differential voltage signal and converts it into a differential digital signal using its built-in analog-to-digital converter. Since the first sensing transistor MT1 is only occasionally activated to receive light in calibration mode, its aging is relatively slight, while the second sensing transistor MT2 is always in operation and its aging is relatively obvious. Therefore, the difference between the second current I2-1 and the third current I2-2 reflects the amount of output drift of the second sensing transistor MT2 due to aging under the same ambient light. The microcontroller 40 calibrates the converted value of the first digital signal acquired in operating mode S1 based on the difference digital signal. That is, the microcontroller 40 uses the difference digital signal acquired in calibration mode S2 as a calibration reference to update the correspondence between the first digital signal and the ambient light output value in operating mode S1, thereby compensating for the output drift of the second sensing transistor MT2 caused by aging, ensuring that an accurate ambient light output value can still be obtained after the second sensing transistor MT2 ages. Specifically, the microcontroller 40 uses the characteristic parameters reflecting the degree of aging acquired in calibration mode S2 to correct the algorithm or correspondence for converting the first digital signal into the ambient light output value in operating mode S1. For example, it adjusts the dark current reference value and / or gain coefficient in the calculation formula according to the characteristic parameters, so that even after the first sensing transistor MT1 ages, the component purely contributed by ambient light can still be accurately extracted from the first digital signal, thereby obtaining an accurate ambient light output value and effectively compensating for the detection accuracy drift caused by device aging.

[0101] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel described above in the embodiments of the present invention. The principle by which this display device solves the problem is similar to that of the aforementioned display panel; therefore, the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be described again here.

[0102] In specific implementations, in the embodiments of the present invention, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present invention.

[0103] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0104] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0105] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0106] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0107] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0108] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A display module, characterized in that, include: A display panel, including a display area and a non-display area located on a substrate; The non-display area includes: A photosensitive unit includes multiple sensing transistors; the gate of each sensing transistor is electrically connected to a control signal terminal or a ground terminal, the first terminal of each sensing transistor is electrically connected to a drive signal line, and the second terminal of each sensing transistor is electrically connected to a current output terminal. A light valve unit is disposed on the light-incident side of the photosensitive unit. The orthographic projection of the light valve unit on the substrate overlaps with the orthographic projection of at least one of the sensing transistors on the substrate. The light valve unit is configured to provide a signal on the data signal line to the pixel electrode in the light valve unit in response to a signal on the scan signal line, so as to control the light valve unit to be in a first state or a second state. The photosensitive unit is configured to provide a first current to the current output terminal when the light valve unit is in the first state, and to provide a second current to the current output terminal when the light valve unit is in the second state, wherein the first current and the second current are different.

2. The display module as described in claim 1, characterized in that, The first state is a light-transmitting state, and the second state is a light-blocking state; or, the first state is a light-blocking state, and the second state is a light-transmitting state.

3. The display module as described in claim 1, characterized in that, The light valve unit includes sub-pixel units arranged in an array; Each of the sub-pixel units includes: a pixel electrode, a pixel capacitor, and a transistor; The gate of the conducting transistor is electrically connected to the scan signal line, the first electrode of the conducting transistor is electrically connected to the data signal line, and the second electrode of the conducting transistor is electrically connected to the pixel electrode. The first electrode of the pixel capacitor is electrically connected to the pixel electrode, and the second electrode of the pixel capacitor is electrically connected to the scan signal line.

4. The display module as described in any one of claims 1-3, characterized in that, The orthographic projection of the light valve unit onto the substrate covers the orthographic projection of all the sensing transistors onto the substrate.

5. The display module as described in claim 4, characterized in that, The optical valve unit includes: a first optical valve unit and a second optical valve unit; the plurality of sensing transistors includes: a plurality of first sensing transistors and a plurality of second sensing transistors; The orthographic projection of the first light valve unit onto the substrate covers the orthographic projection of the plurality of first sensing transistors onto the substrate. The orthographic projection of the second light valve unit onto the substrate covers the orthographic projection of the plurality of second sensing transistors onto the substrate.

6. The display module as described in claim 5, characterized in that, The first optical valve unit and the second optical valve unit are electrically connected to the same scanning signal line; the first optical valve unit and the second optical valve unit are respectively electrically connected to different data signal lines. The gates of the first sensing transistor and the second sensing transistor are electrically connected to the ground terminal, the first terminals of the first sensing transistor and the second sensing transistor are electrically connected to the same drive signal line, and the second terminals of the first sensing transistor and the second sensing transistor are electrically connected to different current output terminals.

7. The display module as described in claim 5, characterized in that, The scan signal line includes a first scan signal line and a second scan signal line; the data signal line includes a first data signal line and a second data signal line; the drive signal line includes a first drive signal line and a second drive signal line; the current output terminal includes a first current output terminal and a second current output terminal. The first optical valve unit is electrically connected to the first scan signal line and the first data signal line; the second optical valve unit is electrically connected to the second scan signal line and the second data signal line. The gate of the first sensing transistor is electrically connected to the ground terminal, the first electrode of the first sensing transistor is electrically connected to the first drive signal line, and the second electrode of the first sensing transistor is electrically connected to the first current output terminal. The gate of the second sensing transistor is electrically connected to the ground terminal, the first terminal of the second sensing transistor is electrically connected to the second drive signal line, and the second terminal of the second sensing transistor is electrically connected to the second current output terminal.

8. The display module as described in claim 7, characterized in that, The non-display area also includes a first switching transistor, a second switching transistor, and a third switching transistor; The gates of the first switching transistor, the second switching transistor, and the third switching transistor are all electrically connected to the switching control signal terminal; The first terminal of the first switching transistor is electrically connected to the first scan signal line, and the second terminal of the first switching transistor is electrically connected to the second scan signal line; The first terminal of the second switching transistor is electrically connected to the first data signal line, and the second terminal of the second switching transistor is electrically connected to the second data signal line; The first terminal of the third switching transistor is electrically connected to the first drive signal line, and the second terminal of the third switching transistor is electrically connected to the second drive signal line.

9. The display module as described in any one of claims 1-3, characterized in that, The optical valve unit covers the orthogonal projection of the sensing transistor onto the substrate.

10. The display module as described in claim 9, characterized in that, The plurality of sensing transistors includes: a plurality of first sensing transistors and a plurality of second sensing transistors; The orthographic projection of the light valve unit onto the substrate covers the orthographic projection of the plurality of first sensing transistors onto the substrate.

11. The display module as described in claim 10, characterized in that, The drive signal line includes a first drive signal line and a second drive signal line; the current output terminal includes a first current output terminal and a second current output terminal. The gate of the first sensing transistor is electrically connected to the ground terminal, the first electrode of the first sensing transistor is electrically connected to the first drive signal line, and the second electrode of the first sensing transistor is electrically connected to the first current output terminal. The gate of the second sensing transistor is electrically connected to the ground terminal, the first terminal of the second sensing transistor is electrically connected to the second drive signal line, and the second terminal of the second sensing transistor is electrically connected to the second current output terminal.

12. The display module as described in claim 11, characterized in that, The non-display area also includes a fourth switching transistor; The gate of the fourth switching transistor is electrically connected to the switch control signal terminal, the first terminal of the fourth switching transistor is electrically connected to the first drive signal line, and the second terminal of the fourth switching transistor is electrically connected to the second drive signal line.

13. The display module as described in any one of claims 1-3, characterized in that, Also includes: Current mirror circuit and sampling resistor; The input terminal of the current mirror circuit is electrically connected to the current output terminal, and the output terminal of the current mirror circuit is electrically connected to the first terminal of the sampling resistor. The current mirror circuit is configured to provide a mirror current to the first terminal of the sampling resistor according to the current output terminal. The second end of the sampling resistor is electrically connected to the ground terminal, and the sampling resistor is configured to convert the mirror current output by the current mirror circuit into a voltage signal.

14. The display module as described in claim 13, characterized in that, Also includes: A rectifier circuit, electrically connected to the first terminal of the sampling resistor, is configured to convert the voltage signal across the sampling resistor into the absolute value of the voltage signal and output it.

15. A display device, characterized in that, Includes the display module as described in any one of claims 1-14.

16. A driving method for a display module as described in any one of claims 1-14, characterized in that, include: In the working mode, the light valve unit responds to the signal on the scanning signal line and provides the signal on the data signal line to the pixel electrode in the light valve unit to control the light valve unit to be in the first state, load the first driving signal to the driving signal line, and obtain the first current provided by the photosensitive detection unit to the current output terminal. In calibration mode, the light valve unit responds to the signal on the scan signal line by providing the signal on the data signal line to the pixel electrode in the light valve unit, thereby controlling the light valve unit to be in the second state, loading the second drive signal to the drive signal line, and acquiring the second current provided by the photosensitive detection unit to the current output terminal. The first current is different from the second current.

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