Write operation techniques for memory systems

Abstract

This application relates to write operation techniques for memory systems. In some memory systems, a write operation performed on a target memory cell of a memory device can disturb the logical state stored by one or more neighboring memory cells. Such disturbance can result in a decrease in read margin when accessing the one or more memory cells, or can result in data loss in the one or more memory cells. The described techniques can reduce aspects of logical state degradation by supporting an operational mode in which a host device, a memory device, or both, suppresses writing information to a region of a memory array or disables a write command associated with a write operation to a region of a memory array.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the invention patent application filed on October 13, 2020, with application number "202080083254.8" and invention title "Write Operation Technology for Memory Systems".

[0003] Cross-reference

[0004] This patent application is the national phase application of International Patent Application No. PCT / US2020 / 055344, filed by Lu et al. on October 13, 2020, entitled “WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS”, which claims priority to U.S. Patent Application No. 16 / 700,948, filed by Lu et al. on December 2, 2019, entitled “WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS”, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field relates to write operation techniques for memory systems. Background Technology

[0006] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of those states. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program states into the memory device.

[0007] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Summary of the Invention

[0008] Describe a method. The method may include: identifying at a memory device that the number of write operations performed on a region of a memory array meets a threshold; suppressing the writing of information to the region of the memory array for a first duration based at least in part on the fact that the number of write operations meets the threshold; and performing one or more write operations on the region based at least in part on the suppression of the writing of information to the region of the memory array for the first duration.

[0009] Describe an apparatus. The apparatus may include: a memory array comprising a plurality of memory cells; and a controller operable to: identify that the number of write operations performed on a region of the memory array satisfies a threshold; suppress writing information to the region of the memory array for a first duration based at least in part on the fact that the number of write operations satisfies the threshold; and perform one or more write operations on the region of the memory array based at least in part on the suppression of writing information to the region of the memory array for the first duration.

[0010] A method is described, the method comprising: identifying at a host device that the number of write operations performed on a region of a memory array of a memory device meets a threshold; at the host device, prohibiting information from being written to the region of the memory array for a first duration based at least in part on the number of write operations meeting the threshold; and performing one or more write operations based at least in part on the prohibition of writing information to the region of the memory array for the first duration.

[0011] Describe an apparatus. The apparatus may include: a host device operable to couple with a memory device; and a controller operable to: identify that the number of write operations performed on a region of a memory array of the memory device meets a threshold; prohibit writing information to the region of the memory array for a first duration based at least in part on the fact that the number of write operations meets the threshold; and perform one or more write operations based at least in part on the prohibition of writing information to the region of the memory array for the first duration.

[0012] A system is described. The system may include: a host device; and a memory device including at least one memory array having a plurality of memory cells. The system is operable to: identify at the memory device that the number of write operations performed on a region of the memory array of the memory device meets a threshold; signal from the memory device to the host device, at least in part based on the identification that the number of write operations performed on the region of the memory array meets the threshold, that the region of the memory array is unavailable for write operations for a first duration; and at the host device, prohibit write operations on the region of the memory array at least in part based on receiving the signaling that the region of the memory array is unavailable for write operations for the first duration. Attached Figure Description

[0013] Figure 1 This describes an example of a system that supports write operation techniques for memory systems, as illustrated in the examples disclosed herein.

[0014] Figure 2 This describes an example of a memory die that supports write operation techniques for memory systems, as illustrated in the examples disclosed herein.

[0015] Figure 3 This describes an example of a memory array that supports write operation techniques for memory systems, as illustrated in the examples disclosed herein.

[0016] Figure 4 This document describes an example of a plot of characteristic voltage distribution in a memory device that supports write operation techniques for memory systems, based on examples disclosed herein.

[0017] Figure 5 A block diagram of a memory device supporting write operation techniques for a memory system, based on examples disclosed herein.

[0018] Figure 6 A block diagram of a host device supporting write operation techniques for memory systems, based on examples disclosed herein.

[0019] Figure 7 and 8 The flowchart illustrates one or more methods that support write operation techniques for memory systems, based on examples disclosed herein. Detailed Implementation

[0020] Memory systems according to the examples disclosed herein may include memory devices and host devices coupled to said memory devices. In some memory systems, write operations performed on target memory cells of the memory device may interfere with the logic state stored by one or more neighboring memory cells. For example, if the number of write operations performed on a region of the memory array meets (e.g., exceeds) a threshold, or if the rate of write operations performed on a region of the memory array (e.g., the number of write operations over a duration) meets a threshold, then memory cells not targeted by write operations may become susceptible to degradation of their stored logic state. This degradation may result in reduced read margin when accessing one or more memory cells, or may result in data loss in one or more memory cells. Although the logic state may be periodically refreshed to overcome some degradation, refresh operations may be associated with unwanted power consumption, adverse memory cell stress or durability loss, or other disadvantages.

[0021] The techniques described herein can reduce aspects of logic state degradation by supporting an operational mode in which a host device, memory device, or both suppress information writing to a region of a memory array for a duration or prohibit write commands associated with write operations to a region of the memory array for a duration. In some instances, this suppression or prohibition for a duration can support a region of the memory array returning to a nominal state or condition where memory cells are less likely to have their logic state degraded by write operations to adjacent memory cells. Such conditions can be identified by one or both of the memory device or host device, and in some instances, this suppression or prohibition can be accompanied by storing write commands in a buffer, determining access to a different region of the memory array, or determining complete access to a different memory array or memory device. During or after the duration of this suppression, write operations to a region of the memory array can continue, or the region of the memory array can be used for write operations in other ways.

[0022] First, as referenced Figures 1 to 3 Features of this disclosure are described in the context of the memory system, die, and array described herein. Features of this disclosure are further described in the context of the corresponding distribution of logic state characteristics, as referenced in [reference needed]. Figure 4 Description. These and other features of this disclosure are further illustrated and described with reference to device diagrams and flowcharts relating to write operation techniques for memory systems, as well as to device diagrams and flowcharts, such as reference. Figures 5 to 8 describe.

[0023] Figure 1This describes an example of a system 100 utilizing one or more memory devices, as disclosed herein. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices, but aspects of one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0024] System 100 may include portions of electronic devices, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data for use by one or more other components of system 100.

[0025] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes (e.g., a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or other fixed or portable electronic device, and other instances). In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0026] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals; various pin configurations for transmitting signals; various physical package dimensions for host device 105 and memory device 110; clock signaling and synchronization between host device 105 and memory device 110; timing conventions; or other factors.

[0027] Memory device 110 is operable to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0028] The host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (such as one or more peripheral components or one or more input / output controllers). The components of the host device may be coupled to each other using bus 135.

[0029] Processor 125 is operable to provide control or other functionality to at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), and other instances. In some instances, external memory controller 120 may be implemented by or be part of processor 125.

[0030] BIOS component 130 may be a software component containing a BIOS configured as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0031] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) for supporting a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more dies, one or more segments), wherein each memory cell is operable to store at least one data bit. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory or multi-die package or multi-chip memory or multi-chip package.

[0032] Memory die 160 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may contain a single memory array 170. A 3D memory die 160 may contain two or more memory arrays 170 that can be stacked on top of each other or positioned adjacent to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in a 3D memory die 160 may be referred to as layers, layers, stacks, or dies. A 3D memory die 160 may contain any number of stacked memory arrays 170 (e.g., two heights, three heights, four heights, five heights, six heights, seven heights, eight heights). In some 3D memory dies 160, different layers may share at least one common access line such that some layers may share one or more row lines or column lines.

[0033] Device memory controller 155 may include circuitry, logic, or components operable to control the operation of memory device 110. Device memory controller 155 may include hardware, firmware, or instructions enabling memory device 110 to perform various operations and is operable to receive, transmit, or execute commands, data, or control information relating to components of memory device 110. Device memory controller 155 is operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, device memory controller 155 may control the operation of memory device 110 as described herein in conjunction with local memory controller 165 of memory die 160.

[0034] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to the host device.

[0035] A local memory controller 165 (e.g., local to memory die 160) is operable to control the operation of memory die 160. In some instances, the local memory controller 165 is operable to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, to communicate with other local memory controllers 165, or to communicate directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0036] External memory controller 120 is operable to enable the transfer of one or more of the information, data, or commands between a component of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functions described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functions described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165) or vice versa.

[0037] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 are operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path operable to carry a signal. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins are operable to act as part of a channel.

[0038] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or dual data rate (DDR) signaling may be transmitted via channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be entered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be entered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0039] In some instances, write operations performed on regions of memory array 170 may interfere with the logic state stored by one or more adjacent memory cells of the memory array. For example, if the number of write operations performed on regions of memory array 170 meets a threshold, or if the rate of write operations performed on regions of memory array 170 (e.g., the number of write operations over a duration) meets a threshold, then memory cells not targeted by write operations may become susceptible to degradation of their stored logic state (e.g., by write operations). This degradation may result in reduced read margin when accessing memory cells of memory array 170, or may result in data loss in one or more memory cells of memory array 170. Although the logic state stored in memory array 170 may be periodically refreshed to overcome some degradation, refresh operations may be associated with unwanted power consumption, adverse memory cell stress or durability loss, or other disadvantages.

[0040] Logical state degradation can be reduced by supporting an operating mode in which host device 105, memory device 110, or both can suppress writing information to areas of memory array 170 for a duration or prohibit writing commands associated with write operations to areas of memory array 170 for a duration. In some instances, this suppression or prohibition can support areas of memory array 170 returning to a nominal state or condition where memory cells are less likely to have their logical state degraded by write operations to adjacent memory cells. Such conditions can be identified by one or both of memory device 110 or host device 105, and in some instances, this suppression or prohibition can be accompanied by storing write commands in a buffer (e.g., at memory device 110, host device 105) to determine access to different areas of memory array 170, or to determine access to different memory array 170 or memory device 110. Furthermore, in various instances, this suppression or prohibition can be supported or otherwise enhanced by signaling between host device 105 and memory device 110.

[0041] Figure 2 This describes an example of a memory die 200 as disclosed herein. The memory die 200 may be used as a reference. Figure 1 Examples of memory die 160 described herein. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each of which may be programmed to store different logic states (e.g., a set of two or more possible programmed states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., multilevel memory cell 205) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, such as referenced in [reference needed]. Figure 1 The memory array 170 is described.

[0042] Memory cell 205 may use configurable materials (which may be referred to as memory elements, memory storage elements, material elements, material memory elements, material portions, or polarity write material portions, etc.) to store logical states. The configurable materials of memory cell 205 may refer to chalcogenide-based storage components, as referenced in [reference needed]. Figure 3 To describe in more detail. For example, chalcogenide memory elements can be used in phase change memory (PCM) cells, limit memory cells, or selectable memory cells.

[0043] The memory die 200 may include access lines (e.g., row lines 210, column lines 215) arranged in a pattern (e.g., a grid pattern). The access lines may be formed of one or more conductive materials. In some instances, row lines 210 may be referred to as word lines. In some instances, column lines 215 may be referred to as digital lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, are interchangeable without loss of understanding or operability. Memory cells 205 may be located at the intersections of row lines 210 and column lines 215.

[0044] Memory cell 205 can be accessed, for example, by activating or selecting access lines (e.g., one or more of row lines 210 or column lines 215). A single memory cell 205 can be accessed at its intersection by applying a bias voltage to the row lines 210 and column lines 215 (e.g., applying a voltage to the row lines 210 or column lines 215). The intersection of the row lines 210 and column lines 215, arranged in a two-dimensional or three-dimensional configuration, can be referred to as the address of the memory cell 205. Access lines can be conductive lines coupled to the memory cell 205 and can be used to perform access operations on the memory cell 205.

[0045] The access memory unit 205 can be controlled via either row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 245 and activate row line 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 245 and activate column line 215 based on the received column addresses.

[0046] Sensing component 230 is operable to detect the state of memory cell 205 (e.g., material state, resistance, threshold state) and determine the logic state of memory cell 205 based on the stored state. Sensing component 230 may include one or more sensing amplifiers for amplifying or otherwise converting the signal caused by accessing memory cell 205. Sensing component 230 may compare the signal detected from memory cell 205 with reference 235 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 230 (e.g., to input / output 240) and may indicate the detected logic state to another component of the memory device including memory die 200.

[0047] The local memory controller 245 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 230). The local memory controller 245 may be a reference. Figure 1Examples of local memory controller 165 described herein. In some instances, one or more of row decoder 220, column decoder 225, and sensing component 230 may be co-located with local memory controller 245. Local memory controller 245 is operable to receive one or more commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of one or more operations. Local memory controller 245 may generate row signals and column address signals to activate target row line 210 and target column line 215. Local memory controller 245 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed in the operational memory die 200.

[0048] The local memory controller 245 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. The local memory controller 245 is operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0049] Local memory controller 245 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of memory die 200. During a write operation, the memory cells 205 of memory die 200 can be programmed to store a desired logical state. Local memory controller 245 can identify the target memory cell 205 to which a write operation is performed. Local memory controller 245 can identify target row lines 210 and target column lines 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). Local memory controller 245 can activate the target row lines 210 and target column lines 215 (e.g., apply voltage to row lines 210 or column lines 215) to access the target memory cell 205. Local memory controller 245 can apply a specific signal (e.g., a write pulse) to column line 215 during a write operation to store a specific state in the memory element of memory cell 205. The pulse used as part of the write operation may include one or more voltage levels over a duration.

[0050] The local memory controller 245 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 245 can identify the target memory cell 205 to which the read operation is performed. The local memory controller 245 can identify target row lines 210 and target column lines 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 245 can activate the target row lines 210 and target column lines 215 (e.g., apply a voltage to the row lines 210 or column lines 215) to access the target memory cell 205. The sensing component 230 can detect signals received from the memory cell 205 based on pulses applied to the row lines 210, pulses applied to the column lines, and / or the resistance or threshold characteristics of the memory cell 205. The sensing component 230 can amplify the signals. The local memory controller 245 can activate the sensing component 230 (e.g., a latching sensing component) and thereby compare the signal received from the memory cell 205 with a reference 235. Based on the comparison, the sensing component 230 can determine the logic state stored in the memory cell 205. The pulse used for the read operation may include one or more voltage levels over a duration.

[0051] In some instances, a write operation performed on target memory cell 205 may interfere with the logical state stored by one or more adjacent memory cells 205. For example, for illustrative purposes, memory cells 205 may be arranged or otherwise grouped into regions 250, wherein region 250 contains memory cells a to i. When a write operation is performed on memory cell 205 in region 250, it may interfere with one or more other memory cells 205 in region 250. For example, when a write operation is performed on memory cell a, the write operation may interfere with one or more of memory cells b to i. Similarly, when a write operation is performed on memory cell b, the write operation may interfere with one or more of memory cells a and c to i, and so on. In some instances, the interference may be stronger for relatively close cells, such that a write operation performed on memory cell a may interfere with memory cell e more strongly than the interference interfered with memory cell i. Although the memory die 200 is described as having a single region 250, the memory cells 205 of the memory die 200 may be arranged into any number of regions 250, and the memory cells 205 may be components of one or more of the regions 250.

[0052] In some cases, disturbances in zone 250 may not be strong enough to cause degradation of the logic state stored by memory cells 205 in the zone. However, if the number of write operations performed on a set of memory cells 205 meets a threshold, or if the rate of write operations performed on a set of memory cells 205 (e.g., the number of write operations within a time window) meets a threshold, then memory cells 205 not targeted by write operations may become susceptible to degradation of their stored logic state. In other words, in some instances, when the number of write operations within a time window is relatively high, the degradation of the logic state stored by memory cells 205 can be more severe. This degradation can lead to reduced read margin when accessing memory cells 205, or it can lead to data loss in memory cells 205.

[0053] In one instance, the target memory cell 205 may be written at least in part by thermal cycling or quantitative curves of the material element applied to the corresponding memory cell 205. For example, the memory cell 205 may be written by heating the corresponding material element to achieve an unstable amorphous atomic arrangement (e.g., melting the material element, causing it to transform into a relatively amorphous phase), followed by relatively rapid cooling (e.g., causing the material to reach a stable, relatively amorphous phase) or relatively slow cooling (e.g., causing the material to reach a stable, relatively crystalline phase). In some instances, this heating and cooling may be supported by applying one or more current pulses via the corresponding row lines 210 and column lines 215.

[0054] In some instances, heating and cooling associated with a target memory cell 205 in write zone 250 can cause unintended or unintended heating of adjacent (e.g., non-target) memory cells 205 in zone 250. For example, heating associated with the number or rate of write operations to a set of memory cells 205 can exceed a threshold rate of heat dissipation, which can cause an increase in the temperature of the set of memory cells 205 (e.g., the bulk temperature of zone 250, the average temperature of zone 250, the area temperature). This heating of adjacent memory cells 205 can, for example, cause a change in the material state or properties of the adjacent memory cells 205.

[0055] In one example, adjacent memory cells 205 of region 250 may have material elements written in a relatively amorphous material state, and heating associated with a write operation to adjacent memory cells 205 of region 250 can mobilize the atoms of the material elements to shift toward a more crystalline arrangement. In other words, heating of the material memory elements written in a relatively amorphous atomic arrangement can lead to an unintended shift toward a more crystalline atomic arrangement. This shift toward a more crystalline atomic arrangement or away from a more amorphous atomic arrangement can reduce the ability to distinguish memory cells 205 as originally written in a more amorphous atomic arrangement. Therefore, according to this and other examples, adverse heating of adjacent memory cells 205 during a write operation can reduce the ability to correctly read the logic state initially written to memory cells 205.

[0056] Although described in the context of an unexpected or degraded change in the atomic arrangement caused by a write operation to an adjacent memory cell 205, the degradation of the stored state in memory cell 205 can be caused by other phenomena. For example, for memory cell 205 that distinguishes logic states based on material memory elements storing different threshold characteristics, the stored logic state may be degraded when heating from a write operation to an adjacent memory cell 205 causes a change in threshold characteristics (e.g., causing the threshold voltage of memory cell 205 to rise or fall compared to the initial write threshold voltage). In another example, for memory cell 205 that distinguishes logic states based on maintaining charge or polarization, the stored logic state may be degraded when heating from a write operation to an adjacent memory cell 205 changes the capacity used to store charge or polarization (e.g., due to temperature-dependent charge capacity, due to temperature-dependent saturation polarization, due to temperature-dependent dielectric properties). Furthermore, although described in the context of unexpected or unintended heating from a write operation, this heating can also be caused by other access operations (e.g., read or refresh operations) that could lead to thermal degradation of the logical state stored in zone 250 of the memory array.

[0057] In some instances, to accommodate correct read operations in the presence of this degradation, the memory die 200 may be configured to perform periodic refresh operations to mitigate, reduce, or eliminate the effects of this degradation (e.g., to restore the written state). However, such refresh operations may be associated with unwanted power consumption, adverse memory cell stress or durability loss, or other disadvantages. Alternatively, the memory die 200 may be configured with a relatively wide protection band between the characteristics of different logic states, but this configuration may be associated with a relatively narrow read window budget, relatively high power consumption, relatively low array density, or other unwanted characteristics.

[0058] According to examples disclosed herein, logic state degradation can be reduced by supporting an operating mode in which memory die 200 suppresses or disables writing information to a group of memory cells 205 (e.g., region 250 of a memory array). In some instances, suppressing or disabling write operations can support a group of memory cells 205 returning to a nominal state or condition where memory cells 205 are less susceptible to logic state degradation due to write operations to adjacent memory cells 205. For example, this suppression or disabling for a period of time can allow the temperature of the bulk or region of the group of memory cells 205 to decrease (e.g., through heat dissipation from regions of the memory array), which may include reducing the temperature to normal, nominal, or other preferred operating conditions for the group of memory cells 205. During or after the duration of this suppression or disabling, write operations to regions of the memory array may continue, or regions of the memory array may be otherwise made available for write operations (e.g., because the reduction or stabilization of the temperature of the group of memory cells 205 reduces the sensitivity of the group of memory cells 205 to logic state degradation).

[0059] Figure 3 This describes an example of a memory array 300 as disclosed herein. The memory array 300 may be used as a reference. Figure 1 and 2 Examples of portions of a memory array or memory die described. Memory array 300 may include a first layer 305 of memory cells positioned above a substrate and a second layer 310 of memory cells on top of the first array or layer 305. Although an example of memory array 300 includes two layers 305, 310, memory array 300 may include any number of layers (e.g., one, two, three, four, five, six, seven, eight).

[0060] The memory array 300 may also include row lines 210-a, 210-b, 210-c, 210-d, column lines 215-a and 215-b, which may be examples of row lines 210 and column lines 215, as shown in the reference. Figure 2 Description. One or more memory cells in the first layer 305 and the second layer 310 may include one or more chalcogenide materials in the struts between access lines. For example, a single stack between access lines may include one or more of a first electrode, a first chalcogenide material (e.g., a selector assembly), a second electrode, a second chalcogenide material (e.g., a memory element), or a third electrode. Although the numerical indicators indicate that the contents are included in Figure 3 Some elements in the text, even if they are not labeled with other corresponding elements, are identical or will be understood as similar, in an attempt to increase the visibility and clarity of the depicted features.

[0061] One or more memory cells in the first layer 305 may include one or more of electrodes 325-a, memory elements 320-a, or electrodes 325-b. One or more memory cells in the second layer 310 may include electrodes 325-c, memory elements 320-b, and electrodes 325-d. The memory element 320 may be an example of a chalcogenide material, such as a phase-change memory element, a limited memory element, or a self-selection memory element. In some embodiments, the memory cells of the first layer 305 and the second layer 310 may have a common conductive line such that corresponding memory cells in one or more layers 305 and one or more layers 310 can share column line 215 or row line 210. For example, the first electrode 325-c of the second layer 310 and the second electrode 325-b of the first layer 305 may be coupled to column line 215-a such that column line 215-a can be shared by vertically adjacent memory cells.

[0062] In some instances, the material of the memory element 320 may comprise a chalcogenide material or other alloy, comprising selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (IN), sulfur (S), gallium (Ga), tin (Sn), or lead (Pb), or various combinations thereof. In some instances, the chalcogenide may contain additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0063] In some instances, storage element 320 may be an example of a phase-change memory cell. In such instances, the material used in storage element 320 may be based on an alloy (e.g., the alloys listed above) and may be operable to undergo a phase transition or change to a different physical state during normal operation of the memory cell. For example, a phase-change memory cell may have an amorphous state (e.g., a relatively disordered atomic configuration) and a crystalline state (e.g., a relatively ordered atomic configuration).

[0064] Phase change memory cells can exhibit a significant difference in resistance between the crystalline and amorphous states of a phase change material (which can be a chalcogenide material). Materials in the crystalline state can have atoms arranged in a periodic structure, which can result in relatively low resistance. In contrast, materials in the amorphous state may not have a periodic atomic structure or have a relatively small periodic atomic structure, which can result in relatively high resistance.

[0065] The difference in resistance between the amorphous and crystalline states of a material can be significant. For example, a material in an amorphous state may have a resistance one or more orders of magnitude greater than that in a crystalline state. In some instances, the material may be partially amorphous and partially crystalline, and the resistance may be somewhere between that of a fully crystalline or fully amorphous material. In such instances, the material can be used to store more than two logic states (e.g., three or more logic states).

[0066] During programming (writing) operations of phase-change memory cells (e.g., electrode 325-a, memory element 320-a, electrode 325-b), various parameters of the programming pulse can affect (e.g., determine, set, program) specific behaviors or properties of the material of memory element 320, such as the threshold voltage or resistance of the material. To program a low-resistance state (e.g., a relatively crystalline state) in the phase-change memory cell, a programming pulse that heats or melts the material of memory element 320 can be applied, which may be associated with at least temporarily forming a relatively disordered (e.g., amorphous) atomic arrangement. The amplitude of the programming pulse can be reduced (e.g., relatively slowly) over a duration to allow the material to form a crystalline structure as it cools, thereby forming a stable crystalline material state. To program a high-resistance state (e.g., a relatively amorphous state) in the phase-change memory cell, a programming pulse that heats and / or melts the material of memory element 320 can be applied. The amplitude of the programming pulse can be reduced more rapidly than that used for a low-resistance state. In such cases, the material can be cooled along with atoms arranged in a more disordered manner because the atoms cannot form a crystalline structure before the material reaches a stable state, thereby forming a stable amorphous material state. The difference in the threshold voltage or resistance of the material of storage element 320, depending on the logic state stored by the material of storage element 320, can correspond to the read window of storage element 320. In some cases, portions of the storage element may undergo material changes associated with the logic state.

[0067] In some instances, such as for limited or selectable memory cells, some or all of a set of logic states supported by the memory cell may be associated with an amorphous state of the chalcogenide material (e.g., a material in a single state can be operated to store different logic states). In some instances, memory element 320 may be an example of a selectable memory cell. In such instances, the material used in memory element 320 may be an alloy (e.g., alloys listed above) and may be operable so as not to undergo a phase transition during normal operation of the memory cell (e.g., not to undergo a change between a relatively crystalline state and a relatively amorphous state). For example, the material of memory element 320 may contain a chemical element, such as arsenic, that prevents the chalcogenide material from changing its state and thus can remain in a single state (e.g., an amorphous state or a crystalline state). In some instances, such as for selectable memory cells, some or all of a set of logic states supported by the memory cell may be associated with an amorphous state of the chalcogenide material (e.g., a material in a single state can be operated to store different logic states). For example, logic state '0' and logic state '1' can both be associated with the amorphous state of chalcogenide materials.

[0068] During a programming (write) operation of a self-selecting memory cell (e.g., including electrode 325-a, memory element 320-a, and electrode 325-b), the polarity of the write operation can affect (determine, set, program) specific behavior or characteristics of the material of memory element 320, such as the threshold voltage of the material. The difference in the threshold voltage of the material of memory element 320 depending on the logic state stored by the material of memory element 320 (e.g., the difference between the threshold voltage when the material stores logic state '0' and the threshold voltage when it stores logic state '1') can correspond to the read window of memory element 320.

[0069] In some instances, the architecture of memory array 300 may be referred to as a crosspoint architecture, where memory cells are formed at topological intersections between row lines 210 and column lines 215. Compared to other memory architectures, this crosspoint architecture can provide relatively high-density data storage at a lower manufacturing cost. For example, the crosspoint architecture can have a smaller area and therefore a higher density of memory cells compared to other architectures. For example, compared to other architectures with a 6F² memory cell area (e.g., an architecture with three-terminal selector elements), the architecture can have a 4F² memory cell area, where F is the minimum feature size. For example, DRAM can use transistors (which are three-terminal devices) as selector elements for each memory cell and can have a larger memory cell area compared to the crosspoint architecture.

[0070] Although Figure 3The examples demonstrate two memory layers, but other configurations are possible. In some instances, a single memory layer of a memory cell (which may be referred to as a two-dimensional memory) can be constructed above the substrate. In some instances, two or more layers of a memory cell can be configured in a manner similar to that in a three-dimensional intersection architecture. Furthermore, in some cases, in Figure 3 Displayed or referenced in Figure 3 The components described may be electrically coupled to each other as shown or described but physically rearranged (e.g., storage element 320 and possibly select element or electrode 325 may be electrically connected in series between row line 210 and column line 215 but need not be in a pillar or stack configuration).

[0071] In some instances, write operations performed on a region of memory array 300 may interfere with the logical state stored by one or more adjacent memory cells of memory array 300. For example, if the number of write operations performed on a region of memory array 300 meets a threshold, or if the rate of write operations performed on a region of memory array 300 meets a threshold, then a memory cell not targeted by a write operation may become susceptible to degradation of its stored logical state. This degradation may result in reduced read margin when accessing memory cells of memory array 300, or may result in the loss of data in one or more memory cells of memory array 300.

[0072] In one instance, heat transfer from a write operation performed on a memory cell of memory array 300 can cause unintended or unintended heating of adjacent (e.g., non-target) memory cells of memory array 300. For example, heating associated with the number or rate of write operations on a region of memory array 300 can exceed a threshold rate of heat dissipation, which can cause an increase in the temperature (e.g., body temperature, region temperature) of a group of memory cells in memory array 300. This heating of adjacent memory cells 205 can, for example, cause a change in the material state or other physical properties of adjacent memory cells 205.

[0073] In some cases, heat can be transferred along one or both of row lines 210 or column lines 215, which can lead to localized heating of non-target memory cells of the memory array 300. For example, heat can be transferred to memory element 320 via electrode 325, which can lead to localized migration of atoms in memory element 320 near electrode 325. In some cases, this atomic migration can lead to localized nucleation of crystalline regions of memory element 320 near electrode 325. Therefore, one or more regions of memory element 320 near electrode 325 can become partially crystalline due to write interference caused by write operations to adjacent memory cells. In some instances, the heat transfer or bulk heating between the first layer 305 and the second layer 310 or for other arrangements that may have thermal asymmetries (e.g., asymmetries with respect to heat transfer paths or thermal conductivity, asymmetries with respect to thermal capacity) can be different, making memory element 320 in one layer more or less susceptible to this crystallization from thermal interference. A shift toward a more crystalline atomic arrangement or away from a more amorphous atomic arrangement of the storage element 320 can reduce the ability to distinguish the corresponding memory cell as one that was initially written with a more amorphous atomic arrangement.

[0074] Therefore, according to this and other examples, adverse heating of memory cells attributable to write operations to adjacent memory cells of memory array 300 can reduce the ability to correctly read the logic state of memory cells initially written to the memory array. According to examples disclosed herein, this logic state degradation can be reduced by supporting an operating mode in which host device 105, memory device 110, or both can suppress writing information to areas of memory array 300 for a duration or can disable write commands associated with write operations to areas of memory array 300 for a duration. In some instances, this suppression or disabling for a period of time can support a relative reduction or stabilization of the body or region temperature of a group of memory cells 205 (e.g., through heat dissipation from areas of the memory array), which may include reducing the temperature (e.g., during the duration of suppression or disabling) to normal, nominal, or other preferred operating conditions for the group of memory cells.

[0075] As used herein, a “zone” in a memory array can refer to various divisions or organization of memory cells, and in the context of the described technology, a memory array can contain any number of one or more zones. For example, a first layer 305 can be referred to as a first zone, and a second layer 310 can be referred to as a second zone. Therefore, when the number or rate of write operations to the first layer 305 meets a threshold, write operations can be paused or disabled on the first layer 305. In other instances, a zone can span more than one layer, and a layer can contain multiple zones or combinations thereof. In some instances, write operations can continue on the second layer 310 while write operations are paused or disabled on the first layer 305. In some instances, read operations can continue on the first layer 305 while write operations are paused or disabled on the first layer 305.

[0076] In another example, a region of a memory array may refer to a group of memory cells sharing a row line 210 or a set of row lines 210. Alternatively, a region of a memory array may refer to a group of memory cells sharing a column line 215 or a set of column lines 215. In another example, one region of a memory array may refer to a first independently addressable segment of the memory array associated with the first set of row lines 210 and the first set of column lines 215, and another region of the memory array may refer to a second independently addressable segment of the memory array associated with the second set of row lines 210 and the second set of column lines 215. In another example, a region of a memory array may refer to all memory cells associated with the memory array (e.g., for a memory array with a single region). These examples for defining regions of a memory array are for illustrative purposes only, and the described techniques for pausing or disabling write operations may be applied to other definitions of regions of a memory array.

[0077] In some instances, suppressing or disabling write operations for a period of time can allow regions of memory array 300 to return to a nominal state or condition where memory cells are less susceptible to logical state degradation due to write operations to adjacent memory cells. For example, this suppression or disabling can allow the body or region temperature of a region of memory array 300 to decrease (e.g., through heat dissipation from the region of the memory array), which may involve reducing the temperature (e.g., during the duration of the disabling or suppression) to normal, nominal, or other preferred operating conditions for the regions of the memory array. Under these operating conditions, or as a result of them, memory cells may become less susceptible to logical state degradation, such as becoming less prone to forming or nucleating crystalline or partially crystalline regions (e.g., in memory cells written with amorphous or relatively amorphous atomic arrangements).

[0078] Figure 4A plot 400 illustrating the characteristic voltage distribution in a memory device 110 supporting write operation techniques for a memory system, as disclosed herein. Plot 400 illustrates the characteristic voltage distribution of a representative group of memory cells 205 of a memory array (e.g., a representative group of configurable material memory elements, a representative group of memory elements 320, or a group of memory cells 205 of region 250) relative to a standard deviation σ or some other probability measurement. For illustrative purposes, the σ-axis may be a non-linear axis such that a normal distribution of the characteristic voltage can be illustrated as a linear distribution in plot 400. In some instances, the distribution in plot 400 may be referred to as a Gaussian distribution.

[0079] The characteristic voltages depicted in plot 400 can illustrate various voltages that can be associated with the logic states stored by the represented memory cells. In a first example, the characteristic voltages depicted in plot 400 can refer to the voltage across memory cell 205 when a read pulse or read signal with a configured current amplitude is applied. This interpretation can represent PCM memory cells, where different logic states can be associated with different resistance levels of storage element 320. In other words, a memory cell 205 with relatively low characteristic resistance (e.g., a memory cell with storage element 320 having a more crystalline atomic arrangement) can be associated with a relatively low characteristic voltage (e.g., a read voltage) in plot 400, and a memory cell 205 with relatively high characteristic resistance (e.g., a memory cell 205 with storage element 320 having a more amorphous atomic arrangement) can be associated with a relatively high characteristic voltage in plot 400.

[0080] In the second example, the characteristic voltage depicted in plot 400 can refer to the threshold voltage of the represented memory cell 205, such as a voltage boundary, above which the memory cell 205 will allow current to flow, and below which the memory cell 205 will not allow current to flow. This interpretation can represent a finite-limit memory cell, where different logic states can be associated with different threshold voltage levels of the memory element 320. In other words, a memory cell 205 with a relatively low threshold voltage can be associated with a relatively low characteristic voltage in plot 400, and a memory cell 205 with a relatively high threshold voltage can be associated with a relatively high characteristic voltage in plot 400.

[0081] Distribution 410 may describe the nominal distribution of characteristic voltages for a representative group of memory cells 205 when storing a first logical state or material state (e.g., a "set" state). Distribution 410 may be associated with a lower boundary or edge (e.g., edge 411) (which may be referred to as "E1") and an upper boundary or edge (e.g., edge 412) (which may be referred to as "E2"). Distribution 410 may describe various interpretations of a statistical distribution, such as a span of six standard deviations (e.g., 6σ), a span of twelve standard deviations (e.g., 12σ), or the span between the minimum and maximum characteristic voltages of a representative group of memory cells 205 when storing a set state.

[0082] Distribution 420 may describe the nominal distribution of characteristic voltages for a representative group of memory cells 205 when storing a second logic state or material state (e.g., a "reset" state). Distribution 420 may be associated with a lower boundary or edge (e.g., edge 421) (which may be referred to as "E3") and an upper boundary or edge (e.g., edge 422) (which may be referred to as "E4"). Distribution 420 may describe various interpretations of a statistical distribution, such as a span of six standard deviations (e.g., 6σ), a span of twelve standard deviations (e.g., 12σ), or the span between the minimum and maximum characteristic voltages of a representative group of memory cells 205 when storing a reset state.

[0083] Plot 400 also illustrates a reference voltage 430 (e.g., read voltage, boundary voltage, cutoff voltage) that can be used to detect or distinguish corresponding logic states stored by a representative group of memory cells 205. In some instances, the reference voltage 430 may be referred to as a voltage cutoff (V). DM Or otherwise associated with a voltage threshold, which may refer to a threshold or other reference voltage or bias configured between the set and reset states of a representative group of memory cells 205, and may be fixed or variable in the memory device 110.

[0084] Referring to instances where characteristic voltages are associated with the voltage across memory cell 205 (e.g., read voltage) or the voltage used to drive the configured read pulse when a read pulse with a configured current amplitude is applied, the logic state of memory cell 205 can be evaluated based on whether the voltage is higher or lower than reference voltage 430. Referring to distributions 410 and 420, memory cells 205 storing a representative group of set states may have read voltages associated with read pulses lower than reference voltage 430, and memory cells 205 storing a representative group of reset states may have read voltages associated with read pulses higher than reference voltage 430.

[0085] Referring to an example where characteristic voltages are associated with threshold voltages of memory cell 205 (e.g., the voltage used to drive current through memory cell 205, the voltage used to break down a resistor in memory cell 205), the logic state of memory cell 205 can be evaluated based on whether the voltage across memory cell 205 that causes a threshold event is higher or lower than reference voltage 430. For example, referring to distributions 410 and 420, memory cells 205 storing a representative group of set states may allow current flow (e.g., current flow exceeding a threshold current amount) when reference voltage 430 is applied because reference voltage 430 is higher than the threshold voltage of each of the memory cells 205 (e.g., because distribution 410 is lower than reference voltage 430). In other words, memory cells 205 in a set state will be “limited” in response to the application of reference voltage 430. On the other hand, memory cells 205 representing a representative group of memory cells in a reset state may not allow current flow when a reference voltage 430 is applied, or may allow a current flow below a threshold (e.g., leakage current), because the reference voltage 430 is below the threshold voltage of each of the memory cells 205 (e.g., because distribution 420 is above the reference voltage 430). In other words, memory cells 205 in a reset state may not be constrained in response to the application of the reference voltage 430. Therefore, detecting whether memory cells 205 are constrained in response to the application of the reference voltage 430 can be used to assess whether writing to memory cells 205 is in a set state or a reset state.

[0086] Plot 400 may also illustrate various margins applicable to access operations of a representative group of memory cells 205. For example, “E3 margin” may refer to the difference between the edge 421 of distribution 420 (e.g., the lower edge of a distribution associated with a logic state or material state having a relatively high threshold voltage) and the reference voltage 430. Typically, E3 margin may refer to the margin for a relatively low resistance to a memory cell 205 unexpectedly detected in a reset state given the reference voltage 430, or for unexpectedly limiting a memory cell 205 in a reset state (e.g., unexpectedly detecting or interpreting a set state when reading a memory cell 205 that should store a reset state or write to it in a reset state). Therefore, improving E3 margin may be associated with widening the margin between distribution 420 and the reference voltage 430 (e.g., by shifting the reference voltage 430 to a lower voltage, by shifting the edge 421 to a higher voltage, and by shifting distribution 420 to a higher voltage).

[0087] In another instance, "E2 margin" may refer to the difference between the edge 412 of distribution 410 (e.g., the upper edge of the distribution associated with a logic state or material state having a relatively low threshold voltage) and the reference voltage 430. Typically, E2 margin may refer to the margin for unexpectedly detecting a relatively high resistance in a memory cell 205 in a set state given the reference voltage 430, or failing to limit a memory cell 205 in a set state (e.g., unexpectedly detecting or interpreting a reset state while reading a memory cell 205 that should store a set state or write to it in a set state). Therefore, improving E2 margin may be associated with widening the margin between distribution 410 and the reference voltage 430 (e.g., by shifting the reference voltage 430 to a higher voltage, by shifting the edge 412 to a lower voltage, and by shifting distribution 410 to a lower voltage).

[0088] In some memory devices 110, the distribution of characteristic voltages of a representative group of memory cells 205 (e.g., distribution 410, distribution 420, or both) may change or shift during the operation of the memory device 110. For example, diagram 400 illustrates an instance where the characteristic voltages for the reset state shift from distribution 420 to distribution 420-a. In some instances, this shift may be caused by heat transfer to non-target memory cells 205 driven by write operations to the target memory cell 205 (e.g., the rate of write operations, the number of write operations in a period of time). For example, as described herein, this heat transfer or associated temperature rise in the region may cause changes in atomic configuration, resistance, threshold voltage, or other characteristics that directionally cause memory cells 205 written in the reset state to behave more like memory cells 205 written in the set state. In other words, as a result of a write operation performed on the target memory cell 205, the characteristic voltages of a representative group of memory cells 205 for the reset state may be shifted downward. In some instances, the reduction in characteristic voltage corresponding to edge 421 to edge 421-a can be described as E3 migration.

[0089] While the offset from distribution 420 to distribution 420-a illustrates a relatively uniform migration of the characteristic voltages of the population of memory cells 205 (e.g., an average offset with no standard deviation), the disturbances described herein can lead to other types of migration. In one instance, certain memory cells 205 (e.g., memory cells 205 relatively close to the lower edge of the distribution (e.g., memory cells 205 closer to edge 421 or E3)) may be more susceptible to logic state degradation. For example, memory cells 205 near the lower edge of the distribution may be more prone to nucleation of crystallization regions in the presence of thermal disturbances, causing the lower edge of distribution 420 to migrate further along the voltage axis than the upper edge of distribution 420 (e.g., where the E3 migration is greater than the E4 migration). In various instances, this migration can cause a change in the slope of distribution 420 in plot 400 (e.g., a change in the standard deviation of distribution 420) or a deformation into a non-linear shape in plot 400 (e.g., a deformation into a non-uniform distribution 420). In some instances, migration can be relatively uniform in some areas of the memory array, and more varied in other areas of the memory array.

[0090] The migration of characteristic voltages of a representative group of memory cells 205 in a reset state can be accompanied by a reduction in the voltage margin of the associated memory device 110. For example, as the voltage of edge 421 decreases (e.g., due to E3 migration) to edge 421-a, the lower edge of distribution 420 may become closer to or fall below the reference voltage 430, thus illustrating a reduction, folding, or elimination of the E3 margin. The voltage of edge 422 may similarly decrease to edge 422-a, which may be closer to the reference voltage 430.

[0091] According to the examples disclosed herein, logical state degradation (e.g., degradation described by a migration from distribution 420 to distribution 420-a) can be reduced or eliminated by supporting an operating mode in which the memory device suppresses or disables writing information to a group of representative memory cells 205 (e.g., a region of a memory array). In some instances, this suspension or disabling of write operations can support a group of memory cells 205 returning to a nominal state or condition where memory cells 205 are less likely to migrate from distribution 420 to distribution 420-a. In other words, the described techniques for disabling or suspending write operations can prevent or mitigate this migration, enabling the corresponding memory device to maintain read margin (e.g., maintain E3 margin) without periodic refresh operations, or to support a reduced frequency of such refresh operations or other configuration changes.

[0092] Return to Reference Figure 1In an illustrative example of the described system 100, host device 105, memory device 110, or both, may be configured to support the described techniques to reduce logical state degradation in memory array 170. For example, in various embodiments or designs, memory device 110 (e.g., device memory controller 155, local memory controller 165) may be configured to implement certain techniques without communication with host device 105, or memory device 110 may be configured to implement certain techniques at least in part based on communication or signaling from host device 105 (e.g., based on operations performed at external memory controller 120), or host device 105 and memory device 110 may be jointly configured to implement certain techniques in a coordinated or supportive manner.

[0093] In various instances, techniques for identifying conditions that guarantee the suppression, prohibition, or otherwise suspension of write operations or other access operations may be performed by one or both of the host device 105 and the memory device 110. For example, the memory device 110 may be configured to identify that: the number of write operations performed on a region of memory array 170 meets (e.g., exceeds, satisfies, is greater than, or equal to) a threshold; the number of write operations performed on a region of memory array 170 during a given period meets a threshold; or the rate of write operations performed on a region of memory array 170 meets a threshold. In some instances, the memory device 110 may signal to the host device 105 that such conditions have been identified by the memory device 110, which may or may not include indication of a specific memory array 170 or a region of memory array 170.

[0094] Alternatively, host device 105 may be configured to identify that: the number of write operations performed on a region of memory array 170 by command or otherwise meets (e.g., exceeds, meets, is greater than, or equal to) a threshold; the number of write operations performed on a region of memory array 170 by command or otherwise meets a threshold during a certain duration; or the rate of write operations performed on a region of memory array 170 by command or otherwise meets a threshold. In some instances, host device 105 may signal to memory device 110 that such conditions have been identified by host device 105, which may or may not include indication of a specific memory array 170 or a region of memory array 170.

[0095] Although discussed in the context of write operations, some techniques may perform this identification based on other types of access operations or more generally on the total number or rate of access operations (e.g., at host device 105, at memory device 110). In some instances, specific types of access operations (e.g., write operations, read operations, refresh operations) may or may not be weighted differently as part of the identification, based on the fact that such types of access operations tend to cause interference to adjacent memory cells. In some instances, the identification may include directly or indirectly identifying that the rate of heating or heat transfer in areas of memory array 170 meets a threshold, regardless of the body or ambient temperature measured at host device 105 or memory device 110 (e.g., to estimate local heat transfer or temperature rise in areas of memory array 170).

[0096] Furthermore, techniques for prohibiting, suppressing, or otherwise suspending write operations can be performed by one or both of the host device 105 and the memory device 110. For example, the memory device 110 can be configured to suppress the writing of information to areas of the memory array 170 based on various techniques for identifying conditions that guarantee the suppression, prohibition, or otherwise suspension of write operations. For example, the memory device 110 can be configured for this suppression based on identification performed by the memory device 110 itself or based on identification performed by the host device 105 and signaled to the memory device 110. In some instances, this suppression can be performed for a duration that may be a pre-configured duration, a duration determined based on conditions identified by the memory device 110 or the host device 105 (e.g., at the host device 105 or the memory device 110), or a combination thereof (e.g., selection from a set of pre-configured durations based on the identified conditions)).

[0097] During this suppression period, memory device 110 may process incoming access commands from host device 105 according to various techniques. In one example, memory device 110 may store a write command in a buffer (e.g., of memory device 110) and execute a write operation corresponding to the command stored in the buffer after the suppression period is completed. In another example, based on suppressing write operations on areas of memory array 170, memory device 110 may determine whether to execute the received write command on a different area of ​​the same memory array 170 or on a completely different memory array 170. In other examples, memory device 110 may ignore such access commands (e.g., write commands, refresh commands) received from host device 105, or may explicitly signal to memory device 110 that the received access command has not been or cannot be executed. This may allow host device 105 to save such commands for later publication to memory device 110, or may allow host device 105 to reconfigure such commands (e.g., publish them to a different area of ​​memory array 170, a different memory array 170, or a different memory device 110).

[0098] In some instances, while suppressing write operations, memory device 110 may allow other access operations, such as read operations, to regions of memory array 170. For example, other access operations, such as read operations, may be associated with lower levels of heating or other disturbances compared to write operations, and are therefore less likely to make adjacent memory cells susceptible to logic state degradation. In other instances, while suppressing write operations, memory device 110 may suppress read operations, read and refresh operations, or access operations entirely on memory array 170 or regions of memory array 170. In some instances, during this suppression period, memory device 110 may signal to host device 105 that it is suppressing one or more of the write, read, or refresh operations, or that memory device 110 is otherwise unavailable for access operations (e.g., write operations, for a duration).

[0099] Alternatively, host device 105 may be configured to prohibit writing information to memory array 170 or a region of memory array 170 based on various techniques for identifying conditions that guarantee suppression, prohibition, or otherwise suspend of write operations. For example, host device 105 may be configured to prohibit this based on identification performed by host device 105 itself, or based on identification performed by memory device 110 and signaled to host device 105. In some instances, this prohibition may be performed for a duration that may be a pre-configured duration, a duration determined based on conditions identified by host device 105 or memory device 110 (e.g., at host device 105 or memory device 110), or a combination thereof (e.g., selection from a set of pre-configured durations based on the identified conditions)).

[0100] During this prohibition period, host device 105 may process or issue write commands according to various techniques. In one example, host device 105 may store a write command in a buffer (e.g., a buffer of host device 105) and transmit a write operation corresponding to the command stored in the buffer after the write operation prohibition period is completed. In another example, based on suppressing write operations on regions of memory array 170, host device 105 may determine to perform write operations on different regions of memory array 170 at least in part based on this prohibition (e.g., during the duration of this prohibition). In another example, based on suppressing write operations on regions of memory array 170, host device 105 may determine to perform write operations on different memory arrays 170 at least in part based on this prohibition (e.g., during the duration of this prohibition). In yet another example, based on suppressing write operations on regions of memory array 170, host device 105 may determine to perform write operations on different memory devices 110.

[0101] In some instances, while write operations are disabled, host device 105 may continue to issue or transmit other types of access commands (e.g., read commands) to areas of memory array 170. For example, other access commands, such as read commands, may be associated with lower levels of heat or other disturbances compared to write operations, and are therefore less likely to make adjacent memory cells susceptible to logic state degradation. In other instances, while write operations are disabled, host device 105 may also disable read operations, read operations and refresh operations, or access operations on memory array 170 or areas of memory array 170. In some instances, during this disabling period, host device 105 may signal memory device 110 to suppress the execution of one or more of the write, read, or refresh operations, which may be to suppress access operations commanded by the same or different host device 105.

[0102] By using various techniques according to the examples disclosed herein, memory device 110, host device 105, or a system including host device 105 and memory device 110 can be configured to reduce aspects of logic state degradation by supporting operating modes in which host device 105, memory device 110, or both suppress or disable access operations to regions of the memory array. Such techniques enable memory device 110 to maintain adequate read margin while also reducing the rate of refresh operations, which can provide advantageous performance, such as reduced access errors, reduced power consumption, reduced memory cell fatigue, and other benefits.

[0103] Figure 5 A block diagram 500 illustrates a memory device 505 supporting write operation techniques for a memory system, according to examples disclosed herein. The memory device 505 may be as described in the references... Figures 1 to 7 Examples of aspects of the described memory device. Memory device 505 may include an access operation identifier 510, an access operation controller 515, a write operation component 520, a write operation command receiver 525, a write operation buffer 530, and a write mode indicator 535. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0104] Access operation identifier 510 can identify that the number of write operations performed on a region of the memory array meets a threshold. In some instances, access operation identifier 510 can identify that the number of write operations performed during a second duration meets a threshold. In some instances, access operation identifier 510 can identify that the rate at which the number of write operations is performed meets a threshold. In some instances, access operation identifier 510 can identify that the heating rate associated with the number of write operations meets a threshold.

[0105] The access operation controller 515 may suppress the writing of information to a region of the memory array for a first duration based on the number of write operations meeting a threshold. In some instances, the access operation controller 515 may determine the first duration based on a second duration in which the number of write operations are performed or the rate at which the number of write operations are performed.

[0106] In some instances, the access operation controller 515 may allow read operations on a region of the memory array during at least a portion of a first duration for suppressing the writing of information to a region of the memory array. In some instances, the access operation controller 515 may suppress read operations on a region of the memory array while suppressing write operations (e.g., during at least a portion of the first duration for suppressing the writing of information to a region of the memory array).

[0107] The write operation component 520 may perform one or more write operations on a region of the memory array based on suppressing the writing of information to the region during a first duration. In some instances, performing one or more write operations on a region of the memory array includes retrieving one or more write commands from a buffer and performing one or more write operations after the first duration. In some instances, the write operation component 520 may determine to perform a write operation corresponding to one or more write commands on a second region of the memory array based on suppressing the writing of information to the region during the first duration. In some instances, the write operation component 520 may direct a write operation to a second region of the memory array during the first duration.

[0108] The write operation command receiver 525 can receive one or more write commands corresponding to one or more write operations from the host device. In some instances, the write operation command receiver 525 can receive one or more write commands from the host device during a first duration.

[0109] The write operation buffer 530 can store one or more write commands in the buffer based on suppressing the writing of information to a region of the memory array for a first duration.

[0110] The write mode indicator 535 may signal to the host device, based on the recognition that the number of write operations meets a threshold, an indication of the write mode for a first duration. In some instances, the write mode indicator 535 may instruct the host device to suppress write operations. In some instances, the write mode indicator 535 may indicate a region of the memory array to the host device.

[0111] Figure 6 A block diagram 600 illustrates a host device 605 supporting write operation techniques for a memory system, according to examples disclosed herein. The host device 605 may be as described in the references... Figures 1 to 7 Examples of aspects of the described host device. Host device 605 may include an access operation identifier 610, an access operation controller 615, a write operation component 620, a write mode signaling component 625, a write operation buffer 630, a write command transmitter 635, and a read command transmitter 640. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0112] Access operation identifier 610 can identify that the number of write operations performed on a region of the memory array of the memory device meets a threshold. In some instances, access operation identifier 610 can identify that the number of write operations performed during a second duration meets a threshold. In some instances, access operation identifier 610 can identify that the rate at which the number of write operations is performed meets a threshold. In some instances, access operation identifier 610 can identify that the heating rate associated with the number of write operations meets a threshold.

[0113] Access control controller 615 may prohibit writing information to a region of the memory array for a first duration based on the number of write operations meeting a threshold. In some instances, access control controller 615 may determine to perform one or more write operations to a second region of the memory array based on prohibiting writing information during the first duration. In some instances, access control controller 615 may determine to perform one or more write operations to a second memory device based on prohibiting writing information during the first duration. In some instances, access control controller 615 may determine the first duration based on a second duration in which the number of write operations are performed or the rate at which the number of write operations are performed. In some instances, access control controller 615 may prohibit read operations to a region of the memory array while write operations are prohibited.

[0114] The write operation component 620 can perform one or more write operations based on areas of the memory array that prohibit writing information to the memory array during a first duration.

[0115] The write mode signaling component 625 can transmit an indication to the memory device to suppress writing information to a region of the memory array during a first duration. In some instances, the write mode signaling component 625 can signal the memory device to indicate the write mode indication during the first duration based on the recognition that the number of write operations meets a threshold. In some instances, the write mode signaling component 625 can instruct the memory device to prohibit write operations by the host device. In some instances, the write mode signaling component 625 can indicate a region of the memory array to the memory device.

[0116] The write operation buffer 630 can store one or more write commands in the write buffer.

[0117] The write command transmitter 635 may transmit one or more write commands to the memory device after a first duration. In some instances, the write command transmitter 635 may transmit one or more write commands for a second region of the memory array based on determining that one or more write operations will be performed on a second region of the memory array. In some instances, the write command transmitter 635 may transmit one or more write commands to a second memory device based on determining that one or more write operations will be performed on a second memory device.

[0118] The read command transmitter 640 can transmit one or more read commands for one or more read operations to be performed on the area of ​​the memory array during at least a portion of a first duration used to prohibit writing information to the area of ​​the memory array.

[0119] Figure 7 The illustration depicts a flowchart of one or more methods 700 supporting write operation techniques for memory systems, based on examples disclosed herein. The operation of method 700 can be implemented by a memory device or its components as described herein. For example, it can be implemented by... (refer to...) Figure 5 The described memory device performs the operation of method 700. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0120] At 705, the memory device can identify that the number of write operations performed on a region of the memory array meets a threshold. The operation at 705 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described access operation recognizer performs the 705 operation aspect.

[0121] In 710, the memory device may suppress the writing of information to a region of the memory array for a first duration based on the number of write operations meeting a threshold. The operation of 710 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described aspects of the access control controller performing the operations of 710.

[0122] At 715, the memory device may perform one or more write operations on a region based on suppressing the writing of information to a region of the memory array during a first duration. The operation of 715 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 5 The described write operation component performs the 715 operation aspect.

[0123] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for recognizing at a memory device that the number of write operations performed on a region of a memory array meets a threshold, suppressing the writing of information to a region of the memory array for a first duration based on the number of write operations meeting the threshold, and performing one or more write operations on a region based on the suppression of the writing of information to a region of the memory array for the first duration.

[0124] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, components, or instructions for receiving one or more write commands corresponding to one or more write operations from a host device and storing one or more write commands in a buffer based on suppressing the writing of information to a region of a memory array during a first duration. In some examples, performing one or more write operations on a region of the memory array includes retrieving one or more write commands from the buffer and performing one or more write operations after the first duration. Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, components, or instructions for receiving one or more write commands from a host device during the first duration and determining to perform write operations corresponding to one or more write commands on said region based on suppressing the writing of information to a second region of the memory array during the first duration.

[0125] In some instances of the method 700 and apparatus described herein, identifying that the number of write operations meets a threshold may include operations, features, circuitry, components, or instructions for identifying that the number of write operations performed during a second duration meets the threshold. Some instances of the method 700 and apparatus described herein may further include operations, features, circuitry, components, or instructions for determining a first duration based on a second duration in which the number of write operations are performed or the rate at which the number of write operations are performed.

[0126] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, components, or instructions for allowing read operations on a region of the memory array during at least a portion of a first duration for suppressing the writing of information to a region of the memory array. Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, components, or instructions for signaling an indication of a write mode during the first duration based on a threshold value for identifying that the number of write operations meets that threshold value.

[0127] In some examples of the method 700 and apparatus described herein, signaling may include operations, features, circuitry, components, or instructions for instructing a host device to suppress the execution of write operations by a memory device. In some examples of the method 700 and apparatus described herein, signaling may include operations, features, circuitry, components, or instructions for instructing a region of a memory array to a host device. In some examples of the method 700 and apparatus described herein, suppression may include operations, features, circuitry, components, or instructions for directing write operations to a second region of the memory array during a first duration. In some examples of the method 700 and apparatus described herein, identification may include operations, features, circuitry, components, or instructions for identifying that the rate at which the number of write operations is performed meets a threshold.

[0128] In some instances of the method 700 and apparatus described herein, identification may include operations, features, circuitry, components, or instructions for identifying heating rates associated with the number of write operations that meet a threshold. Some instances of the method 700 and apparatus described herein may further include operations, features, circuitry, components, or instructions for suppressing read operations on regions of the memory array while suppressing write operations.

[0129] Figure 8 The illustration describes one or more methods 800 supporting write operation techniques for memory systems, based on examples disclosed herein. Method 800 can be operated by a host device or its components as described herein. For example, it can be implemented by... (See references...) Figure 6 The described host device performs the operation of method 800. In some instances, the host device may execute an instruction set to control the functional elements of the host device to perform the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0130] In 805, the host device can identify if the number of write operations performed on a region of the memory array of the memory device meets a threshold. The operation of 805 can be performed according to the methods described herein. In some instances, it can be performed by, as referenced... Figure 6 The described access operation recognizer performs the 805 operation.

[0131] In 810, the host device can prevent information from being written to a region of the memory array for a first duration based on the number of write operations meeting a threshold. The operation of 810 can be performed according to the method described herein. In some instances, it can be performed as described in the reference... Figure 6 The described access control controller performs the operations of 810.

[0132] In 815, the host device can perform one or more write operations based on a region of the memory array where writing to information is prohibited for a first duration. The operation of 815 can be performed according to the methods described herein. In some instances, it can be performed as described in the references... Figure 6 The described write operation component performs the 815 operation aspect.

[0133] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for identifying at a host device that the number of write operations performed on a region of a memory array of the memory device meets a threshold, forbidding information from being written to a region of the memory array at the host device for a first duration based on the number of write operations meeting the threshold, and for performing one or more write operations based on the prohibition of information being written to a region of the memory array for the first duration.

[0134] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, components, or instructions for suppressing the transmission of instructions to the memory device to a region of the memory array for a first duration of time.

[0135] In some instances of the method 800 and apparatus described herein, performing one or more write operations may include operations, features, circuitry, components, or instructions for storing one or more write commands in a write buffer and transmitting one or more write commands to a memory device after a first duration. Some instances of the method 800 and apparatus described herein may further include operations, features, circuitry, components, or instructions for determining to perform one or more write operations on a second region of the memory array based on write-prohibited information during the first duration and for transmitting one or more write commands for the second region of the memory array based on the determination to perform one or more write operations on the second region of the memory array.

[0136] In some instances of the method 800 and apparatus described herein, the prohibition of write operations may include operations, features, circuitry, components, or instructions for determining, based on write prohibition information during a first duration, that one or more write operations will be performed on the second memory device, and for transmitting one or more write commands to the second memory device based on the determination that one or more write operations will be performed on the second memory device. In some instances of the method 800 and apparatus described herein, identifying that the number of write operations performed on a region of the memory array meets a threshold may include operations, features, circuitry, components, or instructions for identifying that the number of write operations performed during a second duration meets a threshold.

[0137] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, components, or instructions for determining a first duration based on a second duration in which the number of write operations are performed or the rate at which the number of write operations are performed. Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, components, or instructions for transmitting one or more read commands for one or more read operations to be performed on the area of ​​the memory array during at least a portion of a first duration for prohibiting the writing of information to a region of the memory array.

[0138] In some examples of the method 800 and apparatus described herein, identification may include operations, features, circuitry, components, or instructions for identifying the rate at which the number of write operations is performed meets a threshold. In some examples of the method 800 and apparatus described herein, identification may include operations, features, circuitry, components, or instructions for identifying the heating rate associated with the number of write operations as meeting a threshold. Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, components, or instructions for disabling read operations on regions of the memory array when write operations are disabled.

[0139] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, components, or instructions for signaling an indication of a write mode within a first duration based on the number of identified write operations meeting a threshold. In some examples of the method 800 and apparatus described herein, signaling may include operations, features, circuitry, components, or instructions for instructing the memory device that the host device prohibits write operations. In some examples of the method 800 and apparatus described herein, signaling may include operations, features, circuitry, components, or instructions for instructing the memory device of a region of the memory array.

[0140] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods can be combined.

[0141] Describe an apparatus. The apparatus may include a memory array comprising a set of memory cells and a controller. The controller is operable to identify that the number of write operations performed on a region of the memory array meets a threshold, suppress writing information to a region of the memory array for a first duration based on the number of write operations meeting the threshold, and perform one or more write operations on a region of the memory array based on suppressing writing information to a region of the memory array for the first duration.

[0142] In some instances, the controller is operable to receive one or more write commands corresponding to one or more write operations from a host device, and stores one or more write commands in a buffer based on suppressing the writing of information to a region of the memory array during a first duration. In some instances, to perform one or more write operations on a region of the memory array, the controller is operable to retrieve one or more write commands from the buffer and perform one or more write operations after the first duration. In some instances, the controller is operable to receive one or more write commands from a host device during a first duration, and determines to perform a write operation corresponding to one or more write commands on a second region of the memory array based on suppressing the writing of information to a region of the memory array during the first duration.

[0143] In some instances, the controller is operable to determine the first duration based on a second duration in which the number of write operations are performed or the rate at which the number of write operations are performed. In some instances, the controller is operable to allow read operations on the region during at least a portion of the first duration used to suppress writing information to the region of the memory array.

[0144] In some instances, the controller is operable to signal an indication of a write pattern within a first duration based on the recognition that the number of write operations meets a threshold. In some instances, each of the memory cells contains a corresponding chalcogenide material element. In some instances, the controller is operable to direct write operations to a second region of the memory array within the first duration. In some instances, the controller is operable to recognize that the duration for which the number of write operations are performed therein meets a threshold. In some instances, the controller is operable to recognize that the rate at which the number of write operations are performed meets a threshold.

[0145] In some instances, the controller is operable to identify that the heating rate associated with the number of write operations meets a threshold. In some instances, the controller is operable to determine a first duration based on the duration of the number of write operations performed therein or the rate at which the number of write operations are performed. In some instances, the controller is operable to suppress read operations on regions of the memory array while suppressing write operations. In some instances, each of the memory cells contains a memory element of a corresponding material. In some instances, each of the memory cells is operable to store a logical state based on the atomic configuration of the corresponding material of the memory cell. In some instances, each of the memory cells is operable to store a logical state based on a threshold voltage of the corresponding material of the memory cell.

[0146] Describe an apparatus. The apparatus may include a host device operable to couple with a memory device and a controller. The controller is operable to identify that the number of write operations performed on a region of a memory array of the memory device meets a threshold, to prohibit writing information to a region of the memory array for a first duration based on the number of write operations meeting the threshold, and to perform one or more write operations based on the prohibition of writing information to a region of the memory array for the first duration.

[0147] In some instances, the controller is operable to suppress the transmission of instructions to the memory device to write information to a region of the memory array during a first duration. In some instances, the controller is operable to store one or more write commands in a write buffer and transmit the one or more write commands to the memory device after the first duration.

[0148] In some instances, the controller is operable to determine, based on write-prohibited information during a first duration, that one or more write operations will be performed on a second region of the memory array, and to transmit one or more write commands for the second region of the memory array based on the determination that one or more write operations will be performed on the second region of the memory array. In some instances, the controller is operable to determine, based on write-prohibited information during a first duration, that one or more write operations will be performed on a second memory device, and to transmit one or more write commands to the second memory device based on the determination that one or more write operations will be performed on the second memory device.

[0149] In some instances, the controller is operable to identify that the number of write operations performed during a second duration meets a threshold. In some instances, the controller is operable to determine a first duration based on a second duration in which the number of write operations are performed or the rate at which the number of write operations are performed. In some instances, the controller is operable to disable read operations on a region of the memory array when write operations are disabled. In some instances, the controller is operable to allow read operations on a region of the memory array when write operations are disabled.

[0150] In some instances, the controller is operable to identify that the rate at which the number of write operations is performed meets a threshold. In some instances, the controller is operable to identify that the heating rate associated with the number of write operations meets a threshold. In some instances, the controller is operable to signal an indication of a write pattern within a first duration to the memory device based on the identification that the number of write operations meets a threshold.

[0151] In some instances, the controller is operable to instruct the memory device that the host device may disable write operations. In some instances, the controller is operable to instruct the memory device of a region of the memory array. In some instances, the controller is operable to identify that the rate at which the number of write operations is performed meets a threshold.

[0152] A system is described. The system may include a host device and a memory device including at least one memory array having a plurality of memory cells. The system is operable to identify at the memory device that the number of write operations performed on a region of the memory array of the memory device meets a threshold, at least in part based on the identification that the number of write operations performed on a region of the memory array meets the threshold, to signal from the memory device to the host device that a region of the memory array is unavailable for write operations for a first duration, and at the host device, to prohibit write operations on a region of the memory array at least in part based on receiving signaling that a region of the memory array is unavailable for write operations for the first duration.

[0153] In some instances of the system, the system is operable to store one or more write commands in a write buffer of a host device based at least in part on prohibiting write operations on a region of the memory array, and to transfer one or more write commands from the host device to the memory device after a first duration. In some instances of the system, the system is operable to determine, at the host device, to perform a write operation on a second region of the memory array based at least in part on prohibiting write operations on a region of the memory array, and to transfer one or more write commands for the second region of the memory array from the host device to the memory device based at least in part on the determination that a write operation will be performed on the second region of the memory array.

[0154] In some instances of the system, the system is operable to determine, at the host device, that a write operation will be performed on the second memory device based at least in part on prohibiting write operations on regions of the memory array, and to transmit one or more write commands from the host device to the second memory device based at least in part on the determination that a write operation will be performed on the second memory device. In some instances of the system, the system is operable to determine a first duration based at least in part on a second duration during which the number of write operations are performed or at a rate during which the number of write operations are performed.

[0155] In some instances of the system, to identify that the number of write operations meets a threshold, the memory device may be operable to identify that the duration of performing said number of write operations within it meets a threshold. In some instances of the system, to identify that the number of write operations meets a threshold, the memory device may be operable to identify that the rate at which said number of write operations are performed meets a threshold. In some instances of the system, to identify that the number of write operations meets a threshold, the memory device may be operable to identify that the heating rate associated with said number of write operations meets a threshold.

[0156] In some instances of the system, each of the plurality of memory cells includes a corresponding material memory element. In some instances of the system, each of the plurality of memory cells includes a corresponding chalcogenide material element. In some instances of the system, each of the memory cells is operable to store a logical state at least partially based on the atomic configuration of the corresponding material of the memory cell. In some instances of the system, each of the memory cells is operable to store a logical state at least partially based on a threshold voltage of the corresponding material of the memory cell.

[0157] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, where the bus can have multiple bit widths.

[0158] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) if there is any conductive path between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between the components, or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0159] The term "coupling" refers to a shift from an open-circuit relationship between components (where signals cannot currently travel between components through conductive paths) to a closed-circuit relationship between components (where signals can travel between components through conductive paths). When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between the other components through conductive paths that were previously not permitted.

[0160] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if an open circuit exists between them. For example, when a switch is open, two components separated by a switch positioned between them are isolated from each other. When a controller isolates two components, the controller introduces a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0161] As used herein, the term "layer" or "layer step" refers to a layer or sheet-like structure of geometry (e.g., relative to a substrate). Each layer or layer step may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or layer step may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a thin film. A layer or layer step may contain different elements, components, and / or materials. In some instances, a layer or layer step may consist of two or more sublayers or sub-layer steps.

[0162] As used herein, the term "electrode" may refer to an electrical conductor and, in some instances, may serve as an electrical contact with other components of a memory cell or memory array. Electrodes may be included as traces, wires, conductive lines, conductive layers, or the like that providing a conductive path between elements or components of the memory array.

[0163] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0164] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0165] The descriptions set forth herein, together with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and not "preferred" or "superior to other instances." The detailed description includes specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0166] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a hyphen after the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0167] The information and signals described herein can be represented by any of a variety of technologies and techniques. For example, they can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, as well as the data, instructions, commands, information, signals, bits, symbols, and chips referenced herein.

[0168] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in alternative examples, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0169] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located in various locations, including portions distributed such that the functions are implemented in different physical locations. Moreover, as used herein, the word "or" in the list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") includes the contents of the claims, indicating a list of inclusions, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as a reference to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0170] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for a write operation in a memory system, comprising: The number of write operations performed on the first region of the memory array at the memory device meets a threshold. The host device is signaled with an indication of the write mode during a first duration, at least in part based on the number of identified write operations meeting the threshold. An operating mode is set at the memory device for at least a period of time to suppress the application of write signals for refresh and write operations to the first region of the memory array, based at least in part on the number of write operations satisfying the threshold. and At least in part, one or more write operations are performed on the first region based on setting the operating mode at the memory device during the first duration to suppress the application of the write signal to the first region of the memory array.

2. The method according to claim 1, further comprising: Receive one or more write commands corresponding to the one or more write operations from the host device; and The one or more write commands are stored in a buffer, at least in part, based on setting the operating mode at the memory device during the first duration to suppress the application of the write signal to the first region of the memory array. Performing one or more write operations on the first region of the memory array includes retrieving one or more write commands from the buffer and performing one or more write operations after the first duration.

3. The method according to claim 1, further comprising: During the first duration, one or more write commands are received from the host device; and The decision to perform a write operation corresponding to the one or more write commands on the second region of the memory array is based at least in part on setting the operating mode at the memory device during the first duration to suppress the application of the write signal to the first region of the memory array.

4. The method of claim 1, wherein identifying the number of write operations that satisfies the threshold comprises: The number of write operations performed during the second duration is identified as satisfying the threshold.

5. The method of claim 1, further comprising: The first duration is determined at least in part based on a second duration during which the number of write operations are performed or the rate at which the number of write operations are performed.

6. The method of claim 1, further comprising: Read operations on the first region of the memory array are permitted during at least a portion of the first duration for suppressing the application of the write signal to the first region of the memory array.

7. A device for write operations in a memory system, comprising: A memory array, which comprises multiple memory cells; and The controller is operable to: The number of write operations performed on the first region of the memory array meets a threshold. The host device is signaled with an indication of the write mode during a first duration, at least in part based on the number of identified write operations meeting the threshold. An operation mode is set at the device for at least a period of time to suppress the application of write signals for refresh and write operations to the first region of the memory array, based at least in part on the number of write operations satisfying the threshold; and At least in part, one or more write operations are performed on the first region of the memory array by setting the operating mode at the device during the first duration to suppress the application of the write signal to the first region of the memory array.

8. The device of claim 7, wherein the controller is operable to: Receive one or more write commands corresponding to the one or more write operations from the host device; and The one or more write commands are stored in a buffer, at least in part, based on setting the operating mode during the first duration to suppress the application of the write signal to the first region of the memory array. In order to perform the one or more write operations on the first region of the memory array, the controller is operable to retrieve the one or more write commands from the buffer and perform the one or more write operations after the first duration.

9. The device of claim 7, wherein the controller is operable to: During the first duration, receive one or more write commands from the host device; and The decision to perform a write operation corresponding to the one or more write commands on the second region of the memory array is based at least in part on setting the operating mode during the first duration to suppress the application of the write signal to the first region of the memory array.

10. The device of claim 7, wherein the controller is operable to: The first duration is determined at least in part based on a second duration during which the number of write operations are performed or the rate at which the number of write operations are performed.

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