A redundant column repair method of a simulating compute-in-memory array and a compute-in-memory chip

Abstract

The application discloses a redundancy column repair method of an analog memory-computing array and a memory-computing integrated chip, and the scheme comprises the following steps: determining the current working mode of the analog memory-computing array; if the working mode is a computing mode, performing analog computation on all physical columns in a normal column region in a physical column sequence, without skipping a physical column marked as a bad column, so as to maintain the alignment relationship between the physical column and an ADC, and storing the computation results of each physical column in the output data stream in the physical column sequence; and then performing analog computation on the redundancy physical columns in a redundancy column region in sequence, and according to the bad column number recorded in a redundancy column replacement list, the computation results of the redundancy columns are returned to the logical positions corresponding to the bad column number in the output data stream in the digital domain, so as to cover the invalid results generated by the bad column in the normal column computation stage; wherein the redundancy column replacement list is traversed in parallel while the normal column is computed. The application can realize efficient array defect repair without increasing the complexity of the analog path.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits and semiconductor memory technology, and more specifically, to a method for repairing redundant columns in an analog in-memory computing array and an in-memory computing chip. Background Technology

[0002] In traditional memory designs (such as SRAM, DRAM, or traditional non-volatile memory), redundancy is typically introduced to improve chip yield. When a bad pixel or bad column is detected in the array, the hardware skips the bad column directly through a lookup table and maps the address that originally pointed to the bad column to a pre-set redundant column, thus completing the defect repair without affecting the upper-level controller.

[0003] However, with the development of artificial intelligence technology, RRAM is widely used in analog-to-in-memory (CIM) arrays. In these arrays, multiplication and addition operations are performed directly in the analog domain. Currents or voltages from multiple columns are converged and quantized by an analog-to-digital converter (ADC). The calculation process is inherently dependent on the grouping and physical alignment of the ADC. If the traditional memory's "skip and replace" strategy is directly adopted, signals that should be processed by specific ADC channels will be misaligned, severely disrupting the alignment between the ADC and the physical columns. Forcing signal routing and realignment in the analog domain requires designing extremely complex analog multiplexers and switching networks. This not only incurs huge hardware area overhead but also introduces additional parasitic resistances and capacitances, severely impacting calculation accuracy and speed.

[0004] Therefore, how to achieve efficient and low-overhead redundant column repair in analog in-memory arrays without disrupting the alignment between the ADC and the physical columns has become an urgent technical problem to be solved. Summary of the Invention

[0005] This specification provides a method for repairing redundant columns in a simulated in-memory computing array and an integrated in-memory computing chip to overcome at least one technical problem existing in related technologies.

[0006] According to a first aspect of the embodiments of this specification, a method for repairing redundant columns in an analog in-memory computing array is provided, applied to an analog in-memory computing array comprising normal column regions and redundant column regions, wherein the physical column groups of the array are connected to multiple analog-to-digital converters (ADCs); the method determines the current operating mode by identifying the currently received command type or reading a mode status register, the operating mode including a programming mode and a computing mode; wherein, if the current operating mode is a computing mode, the method includes: Simulation calculations are performed on all physical columns in the normal column region in the order of physical columns, without skipping physical columns marked as bad columns, in order to maintain the alignment between physical columns and ADC, and the calculation results of each physical column are stored in the output data stream in the order of physical columns to form the first calculation result sequence; Simulation calculations are performed sequentially on the redundant physical columns within the redundant column region. Based on the bad column number recorded in the redundant column replacement list, the calculation results of the redundant columns are returned to the logical position of the corresponding bad column number in the output data stream in the digital field, overwriting the invalid results generated by the bad column during the normal column calculation stage. While calculating all physical columns within the normal column region, the redundant column replacement list is traversed in parallel to determine the information of the replaced columns recorded in the redundant column replacement list.

[0007] In some optional implementations, if the current operating mode is programming mode, then in response to a programming command, a table is looked up to determine whether the target logical column address matches the redundant column replacement list; if it matches, the programming address is redirected to the corresponding redundant physical column for programming; if it does not match, the original physical column corresponding to the target logical column address is directly programmed.

[0008] In some alternative implementations, the step of looking up a table to determine whether the target logical column address matches the redundant column replacement list in response to a programming command includes: By using a multi-path parallel lookup table circuit, multiple records in the redundant column replacement list are queried in parallel to determine whether the target logical column address is recorded in the redundant column replacement list.

[0009] In some optional implementations, the redundant column replacement list includes N register entries, where N is a positive integer. Each register entry stores a logical column number to be replaced. The N register entries correspond one-to-one with the N redundant physical columns in the redundant column region. The nth register entry corresponds to the nth redundant physical column in the redundant column region, where n = 0, 1, ..., N-1. The physical mapping of the logical column number to be replaced stored in the nth register entry is fixed to use the nth redundant physical column.

[0010] In some alternative implementations, the replaced logical column numbers stored in each register entry are arranged in sequence, and for inapplicable register entries, their values ​​are set to a preset invalid flag.

[0011] In some optional implementations, the redundant column replacement list includes N register entries, where N is a positive integer. Each register entry corresponds one-to-one with N redundant physical columns in the redundant column region, and each register entry is used to store the logical column number to be replaced. The step of determining whether the target logical column address matches the redundant column replacement list in response to a programming command includes: In response to the programming command, a query is performed among the N register entries to determine if any register entry stores a value equal to the target logical column address; if such a value exists, a match is determined, and the programming address is redirected to the redundant physical column corresponding to that register entry.

[0012] In some optional implementations, the step of performing the simulation calculation operation on all physical columns within the normal column region in physical column order includes: Starting from the first physical column of the normal column region, the process sequentially traverses to the last physical column of the normal column region, performs analog domain multiplication and addition operations on each physical column, and outputs the calculation results of each physical column sequentially to the output data stream in the order of the physical columns.

[0013] The steps of sequentially performing simulation calculations on redundant physical columns within the redundant column region include: Starting from the initial physical column of the redundant column region, simulated domain multiplication and addition operations are performed sequentially on each redundant physical column to obtain the calculation result corresponding to that redundant physical column.

[0014] In some optional implementations, the step of assigning the calculation result of the redundant column in the digital domain to the logical position corresponding to the bad column number in the output data stream includes: The digital state machine reads the number of the column to be replaced corresponding to the calculated redundant physical column from the redundant column replacement list, generates an address control signal based on the number of the column to be replaced, and writes the calculation result of the redundant physical column into the output data stream at the logical position corresponding to the number of the column to be replaced, so as to cover the invalid results at the same logical position in the first calculation result sequence.

[0015] In some optional implementations, the analog in-memory array includes M groups of analog-to-digital converters (ADCs), where M is a positive integer. Each group of ADCs corresponds to a fixed number of normal physical columns and redundant physical columns. Logical column numbers are assigned to each group of ADCs according to an interleaving rule. The logical number corresponding to the k-th column of the N-th ADC is M×k+N, where N is the ADC group index, N=0,1,…,M-1, and k is the position number within the group. The step of parallel traversing the redundant column replacement list includes: within the time window of performing simulated domain multiplication and addition operations on all physical columns in the normal column region, the hardware logic pre-traverses all register entries of the redundant column replacement list to determine the numbers of all replaced columns and their correspondence with the redundant physical columns, so as to be directly used for result occupancy when the subsequent redundant physical column calculation is completed.

[0016] According to a second aspect of the embodiments of this specification, a memory computing chip is provided, comprising: At least one analog in-memory array comprising normal column regions and redundant column regions, wherein the physical column groups of the array are connected to multiple analog-to-digital converters (ADCs); A redundant register set includes N register entries, where N is a positive integer. Each register entry stores a logical column number to be replaced. The N register entries correspond one-to-one with the N redundant physical columns in the redundant column region. The nth register entry corresponds to the nth redundant physical column in the redundant column region, where n = 0, 1, ..., N-1. The physical mapping of the logical column number to be replaced stored in the nth register entry is fixed to use the nth redundant physical column. The control circuit is configured to determine the operating mode by identifying the command type or reading the mode status register. In programming mode, in response to a programming command, it uses a multi-channel parallel lookup table circuit to determine whether the target logical column address matches the redundant register group. If it matches, the programming address is redirected to the corresponding redundant physical column for programming; if it does not match, the original physical column corresponding to the target logical column address is programmed directly. In calculation mode, the control circuit controls the analog in-memory array to perform analog calculations on all physical columns in the normal column area in physical column order, without skipping physical columns marked as bad columns, so as to maintain the alignment relationship between the physical columns and the ADC. At the same time, it traverses the redundant register group in parallel to determine the column number to be replaced. The digital domain result processing circuit is configured to be controlled by a digital state machine. After the physical column calculation in the redundant column region is completed, according to the bad column number recorded in the redundant register group, the calculation result of the redundant column is returned to the logical position of the corresponding bad column number in the output data stream in the digital domain after ADC quantization, so as to cover the invalid results generated by the bad column in the normal column calculation stage.

[0017] The beneficial effects of the embodiments in this specification are as follows: In this application's technical solution, the current operating mode of the analog in-memory array is determined by identifying the currently received command type or reading the mode status register. If it is in programming mode, the target logical column address is looked up in response to the programming command to determine whether it matches the redundant column replacement list. If it matches, the programming address is redirected to the corresponding redundant physical column for programming; otherwise, the original physical column corresponding to the target logical column address is programmed directly. In calculation mode, all physical columns within the normal column range are calculated sequentially, without skipping bad columns marked for replacement, while simultaneously traversing the redundant column replacement list in parallel. Then, the redundant columns are calculated sequentially, and the calculation results are returned to the corresponding logical column positions in the output data stream to overwrite invalid results. Since the result repositioning in the computation mode occurs entirely in the digital domain after ADC quantization rather than the analog domain, this solution can maintain a strict alignment relationship between the ADC and the physical columns while ensuring the correctness of programming and the integrity of computation alignment through a mode-specific customization strategy. This is equivalent to transforming the complex signal routing replacement that needs to be completed in the analog domain in traditional solutions into state management and result rearrangement in the digital domain. Moreover, the table lookup operation is completed in parallel within the normal column computation window without adding extra latency. Thus, this solution can effectively avoid the impact of parasitic parameters on the accuracy and speed of analog computation without introducing complex hardware such as analog multiplexers and switching networks, achieving efficient and low-overhead array defect repair. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or related technologies of this specification, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a method for repairing redundant columns in a simulated in-memory array, provided as an embodiment of this specification; Figure 2 This is an overall architecture diagram of the RRAM analog in-memory array in the technical solution of this specification, used to show the mapping relationship between ADC groups, storage columns and redundancy columns. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the embodiments of this application.

[0021] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another.

[0022] The technical solution of this application will be described in detail below with reference to the accompanying drawings. The analog in-memory array involved in this application refers to an array structure built on non-volatile storage media such as resistive random access memory (RRAM), capable of directly performing analog domain multiplication and addition operations at the location of the storage cell. Unlike traditional digital domain computing, the analog in-memory array utilizes physical principles such as Kirchhoff's laws to perform the multiplication of weights and input signals at the intersection of word lines and bit lines of the array, and converges the current or voltage signals from multiple columns for output, thereby achieving high-efficiency parallel analog computing. This array architecture includes normal storage columns and redundant columns. The technical solution of this application is based on the above array architecture and achieves efficient array defect repair without increasing the complexity of the analog path through a differentiated redundancy replacement strategy based on different modes.

[0023] Furthermore, the technical solution of this application employs different redundancy replacement strategies based on the two different operating modes of the analog in-memory array: programming mode and computation mode. In programming mode, a replacement strategy of real-time table lookup and address redirection is used, while in computation mode, the replacement of physical signal routing in the analog domain is abandoned, and a mechanism of "physical order computation without skipping bad columns" combined with "digital domain result rearrangement" is adopted instead.

[0024] The technical solution of this application will be described in detail below with reference to the accompanying drawings, such as... Figure 1 As shown, the method may include: Step 102: Determine the current working mode by identifying the type of command currently received or by reading the mode status register. The working mode includes programming mode and calculation mode.

[0025] In the embodiments of this specification, the analog in-memory computing array typically involves two distinct operational phases during operation: programming mode and computation mode. Programming mode refers to the phase where weight data is written to each memory cell in the array. This phase requires precise control of the impedance state of each memory cell to correctly represent the weight values ​​of the neural network. Computation mode refers to the phase where the array, after weight configuration, performs analog domain multiplication and addition operations. This phase applies the input feature vector to the array's word lines and reads the converged current or voltage signal at the bit line side, which is then quantized into a digital output by an analog-to-digital converter (ADC). These two modes differ fundamentally in their working mechanisms, timing, and performance requirements. Programming mode requires support for data writing in any address order to flexibly configure the weight distribution of each layer of the neural network, while computation mode requires maintaining a strict alignment between the ADC and the physical columns to ensure the correctness of the analog calculation results.

[0026] In this application's technical solution, the operating mode can be determined by identifying the type of the currently received command or by reading the mode status register. Specifically, when the array controller receives an external command, it can determine whether the current command is a programming command or a calculation command by parsing the opcode or command type field in the command. A programming command triggers the programming mode, and a calculation command triggers the calculation mode. Alternatively, the array can be equipped with a mode status register, the value of which is automatically maintained by the hardware according to the currently executing operation phase. The software or hardware control logic can determine the current operating mode by reading the value of this register. These two methods can coexist; for example, the mode can be identified by command type during normal operation, and the current status can be confirmed by reading the status register during debugging or initialization. This application does not impose specific limitations on this. After determining the current operating mode using the above methods, differentiated redundant column repair strategies are subsequently adopted for different modes.

[0027] Step 104: If the current working mode is calculation mode, perform simulated calculation operations on all physical columns in the normal column area in physical column order, without skipping physical columns marked as bad columns, so as to maintain the alignment relationship between physical columns and ADC, and store the calculation results of each physical column in the output data stream in physical column order to form the first calculation result sequence; perform simulated calculation operations on the redundant physical columns in the redundant column area in sequence, and according to the bad column number recorded in the redundant column replacement list, return the calculation results of the redundant columns to the logical position of the corresponding bad column number in the output data stream in the digital field, overwriting the invalid results generated by the bad columns in the normal column calculation stage.

[0028] In the embodiments described in this specification, the redundant column repair strategy in the computation mode differs from that in the programming mode. Its main design idea is to abandon the physical signal routing replacement in the analog domain and instead adopt a mechanism of physical order computation combined with digital domain result rearrangement. The normal column region can refer to the physical column intervals in the array that serve as the primary computational resources, where the columns undertake most of the analog multiply-accumulate operations. The redundant column region can refer to the pre-set spare physical column intervals in the array, which are activated as alternative resources when normal columns exhibit defects.

[0029] In traditional redundancy replacement strategies, hardware skips bad columns during computation and shifts the results of subsequent columns forward to fill the gaps. However, this approach causes problems in analog in-memory arrays (IMA). Specifically, the multiply-accumulate operations in IMA rely on the grouping and physical alignment of the ADCs. The "grouping and physical alignment of the ADCs" refers to the fact that each column in the array is fixedly connected to a specific channel of a particular ADC group via metal wires embedded during chip manufacturing. This connection cannot be changed after chip completion. The output signal of each column is quantized by the ADC channel corresponding to its physical location. Therefore, during computation, the position in the data stream must strictly match the order of the physical columns; there is a fixed one-to-one correspondence between ADC channels and physical columns. Skipping bad columns and changing the computation order will cause the signals that should have been processed by specific ADC channels to become misaligned, disrupting the alignment between the ADC and the physical columns. This results in the quantization results failing to accurately reflect the true computational values ​​of each column. Any operation that "skips a column and shifts subsequent columns" will disrupt this alignment, causing a misalignment between the data read by the ADC and its physical location. If signal routing realignment is forced in the analog domain, complex analog multiplexers and switching networks need to be designed. This not only results in a large hardware area overhead, but also introduces additional parasitic resistance and capacitance, which adversely affects the accuracy and speed of analog calculations.

[0030] This application's technical solution transfers this operation from the analog domain to the digital domain. In computation mode, the array performs calculations according to the physical column order, without skipping any column, regardless of whether it is marked as a bad column to be replaced, thus ensuring that the output signals of all physical columns remain aligned with the corresponding ADC channels. The hardware first performs analog domain multiplication and addition operations sequentially on all physical columns in the normal column region, and the calculation results of each physical column are output to the output data stream in physical column order. Due to the existence of bad columns, the logical position corresponding to the bad column in the output data stream stores invalid calculation results, but no replacement or correction operation is performed at this time. After the calculation in the normal column region is completed, the hardware then calculates the redundant physical columns in the redundant column region one by one. For the calculation result of each redundant physical column, the hardware, according to the correspondence recorded in the redundant column replacement list, places the result in the correct logical column position in the output data stream, that is, the logical position that the bad column replaced by the redundant column should have occupied, thereby overwriting the invalid results previously generated by the bad column. The entire placement process occurs in the digital domain after ADC quantization and does not involve any physical connection changes in the analog domain, so it does not introduce additional parasitic parameters or interfere with the analog calculation path.

[0031] Step 106: While calculating all physical columns within the normal column area, traverse the redundant column replacement list in parallel to determine the information of the replaced columns recorded in the redundant column replacement list.

[0032] In the embodiments of this specification, the timing optimization method for table lookup latency is to utilize the time window required for normal column calculation to complete the traversal of the redundant column replacement list, so that the table lookup operation no longer occupies additional computation cycles. The time window for performing simulated domain multiplication and addition operations on all physical columns within the normal column region can be understood as the entire time period from the start of calculation on the first normal column to the completion and output of the last normal column calculation. Since the number of normal columns is usually much larger than the number of redundant columns, this time window has sufficient duration for the hardware logic to complete the traversal of the redundant column replacement list. For example, in a specific embodiment, if there are 8000 normal columns, assuming the calculation time for each column is 1 microsecond, the entire normal column calculation window is as long as 8 milliseconds. The table lookup operation required to traverse 192 register entries can usually be completed in the tens to hundreds of nanoseconds. Therefore, the hardware logic has sufficient time to complete the entire traversal of the redundant column replacement list within the normal column calculation window and store the results in an internal mapping table. Since this traversal operation is performed in parallel with the normal column calculation and does not occupy additional computation cycles, the table lookup latency is hidden.

[0033] Specifically, the hardware logic can initiate a parallel task at the start of normal column computation to sequentially read each register entry and record the valid replaced column number and its index. When normal column computation is complete, this mapping table is ready. Subsequently, during the redundant column computation phase, after each redundant column is computed, the hardware directly retrieves the corresponding replaced column number from the mapping table without needing to read the registers again. This design ensures that subsequent redundant column computation results can be stored without waiting for a table lookup operation, thus guaranteeing the continuous operation of the in-memory array.

[0034] To more clearly illustrate the complete workflow of the technical solution of this application, the following uses a specific parameter example to explain the entire process from register configuration, programming mode to calculation mode.

[0035] In one specific embodiment of this application, the simulated in-memory array has a total of 8192 physical columns, numbered from 0 to 8191. The normal column region comprises columns 0 to 7999 (8000 columns in total), and the redundant column region comprises columns 8000 to 8191 (192 columns in total). The 192 redundant columns are divided into 8 groups of 24 columns each. 192 13-bit registers are used as a redundant column replacement list, with each register storing the logical column number to be replaced.

[0036] Suppose that during production testing, logical columns 5, 12, and 31 are found to be faulty columns. During the redundancy register configuration phase, according to the column replacement mapping rules, the column number recorded in the nth redundant column register is fixed and replaced with the redundant column using physical number n+8000. Therefore, the 0th register entry stores the value 5, indicating that logical column 5 is replaced by redundant physical column 8000; the 1st register entry stores the value 12, indicating that logical column 12 is replaced by redundant physical column 8001; and the 2nd register entry stores the value 31, indicating that logical column 31 is replaced by redundant physical column 8002. The remaining register entries, since there are no corresponding faulty columns to record, have their values ​​set to the invalid flag 1FFF. The values ​​in all valid register entries are arranged in order (5, 12, 31 in this example, i.e., ascending order), conforming to the configuration rules of the redundant column replacement list.

[0037] After register configuration, the chip enters the actual operation phase. When the array controller recognizes the received command as a programming command, it determines the current operating mode as programming mode. In programming mode, when the upper-level controller issues a programming command requesting the writing of weight data to logical column 5, the hardware uses a multi-channel parallel lookup table circuit to search for the target logical column address 5 in the redundant column replacement list. The lookup table circuit finds that the value stored in the 0th register entry is equal to 5, confirming a match. The hardware then determines the corresponding redundant physical column as physical column 8000 based on the matched register entry index 0, redirects the programming address from "logical column 5" to "physical column 8000," and the data is written to the spare physical column 8000, preventing data loss due to damage to the original physical column corresponding to logical column 5.

[0038] When the array controller recognizes the received command as a calculation command, it determines the current operating mode as calculation mode. In calculation mode, the array enters the analog domain multiply-accumulate operation stage. The hardware first performs analog domain multiply-accumulate operations on all physical columns in the normal column region (columns 0-7999) in physical column order, without skipping any bad columns marked for replacement; that is, the original physical columns corresponding to logical columns 5, 12, and 31 still participate in the calculation. The calculation results of each column are output to the output data stream in physical column order, forming the first calculation result sequence. In this sequence, positions 5, 12, and 31 store invalid calculation results caused by bad columns, but their positions have been pre-occupied. Simultaneously, within the time window of normal column calculation, the hardware logic traverses 192 register entries in parallel, establishing a complete mapping table of "replaced column number → redundant physical column". Subsequently, the hardware enters the redundant column region calculation phase. First, redundant physical column 8000 is calculated, yielding the correct result. The digital state machine reads the value 5 from the 0th register entry, generates an address control signal, and writes this result to position 5 in the output data stream, overwriting the invalid result of the bad column 5. Then, redundant physical column 8001 is calculated, and its result is moved to position 12. Next, redundant physical column 8002 is calculated, and its result is moved to position 31. Finally, in the output data stream, all the invalid results originally generated by the bad columns are overwritten by the correct results of the spare columns, and the entire repair process does not alter any physical connections in the analog domain.

[0039] As can be seen from the above examples, from the identification and determination of the working mode, to register configuration, real-time redirection in programming mode, and then to physical order calculation and digital domain realignment in computation mode, the steps in this application have a temporal sequence. The final output data stream contains correct calculation results at all locations, and the entire repair process does not require adding complex signal routing or switching networks to the analog domain.

[0040] In this application's technical solution, the current operating mode of the analog in-memory array is determined by identifying the currently received command type or reading the mode status register. If it is in programming mode, the target logical column address is looked up in response to the programming command to determine whether it matches the redundant column replacement list. If it matches, the programming address is redirected to the corresponding redundant physical column for programming; otherwise, the original physical column corresponding to the target logical column address is programmed directly. In calculation mode, all physical columns within the normal column range are calculated sequentially, without skipping bad columns marked for replacement, while simultaneously traversing the redundant column replacement list in parallel. Then, the redundant columns are calculated sequentially, and the calculation results are returned to the corresponding logical column positions in the output data stream to overwrite invalid results. Since the result repositioning in the computation mode occurs entirely in the digital domain after ADC quantization rather than the analog domain, this solution can maintain a strict alignment relationship between the ADC and the physical columns while ensuring the correctness of programming and the integrity of computation alignment through a mode-specific customization strategy. This is equivalent to transforming the complex signal routing replacement that needs to be completed in the analog domain in traditional solutions into state management and result rearrangement in the digital domain. Moreover, the table lookup operation is completed in parallel within the normal column computation window without adding extra latency. Thus, this solution can effectively avoid the impact of parasitic parameters on the accuracy and speed of analog computation without introducing complex hardware such as analog multiplexers and switching networks, achieving efficient and low-overhead array defect repair.

[0041] Based on the technical solutions described above, this specification also provides some specific implementation schemes, which are described below.

[0042] In an optional embodiment, if the current working mode is programming mode, then in response to a programming command, a table is looked up to determine whether the target logical column address matches the redundant column replacement list; if it matches, the programming address is redirected to the corresponding redundant physical column for programming; if it does not match, the original physical column corresponding to the target logical column address is directly programmed.

[0043] In the embodiments described in this specification, redundant column repair in programming mode follows the basic logic of real-time table lookup and address redirection. A programming command can refer to an instruction issued by the upper-level controller to write specific weighted data into a designated memory cell. This instruction typically includes target address information and the data value to be written. The target logical column address can refer to the logical column number specified by the programming command, which is visible at the system application level. This number is assigned a specific physical meaning and signal processing path during the array design phase, but may have a mapping relationship with the actual physical column location.

[0044] A redundant column replacement list refers to a pre-configured set of registers that records the logical column numbers corresponding to all bad columns detected as unusable. In practical applications, during production testing or operation, arrays may develop some memory cell columns that cannot function properly due to process defects, wear and tear, or other reasons. If these bad columns are not handled, they will affect the overall yield and computational accuracy of the chip. Therefore, hardware designers pre-set several spare columns, i.e., redundant physical columns, in the array and record the correspondence between the logical numbers of bad columns and the redundant physical columns through a redundant column replacement list.

[0045] When the hardware detects that the current operating mode is programming mode, upon receiving a programming command, it first checks the redundant column replacement list to determine if the target logical column address is recorded as a bad column. If a match is found, it indicates that the original physical column corresponding to that logical column is damaged and cannot perform normal programming operations. In this case, the hardware automatically redirects the programming address to the redundant physical column bound to that logical column and writes the data to the spare column. If a match is not found, it indicates that the original physical column corresponding to the target logical column address is in normal working condition, and the hardware directly performs programming operations on the original physical column corresponding to the target logical column address. This real-time redirection mechanism ensures the correctness and integrity of data writing in programming mode, and the entire table lookup and redirection process is transparent to the upper-level controller, without affecting the timing compatibility of programming commands.

[0046] In an optional embodiment, the step of determining whether the target logical column address matches the redundant column replacement list in response to a programming command may specifically include: By using a multi-path parallel lookup table circuit, multiple records in the redundant column replacement list are queried in parallel to determine whether the target logical column address is recorded in the redundant column replacement list.

[0047] In the embodiments described in this specification, the lookup operation of the redundant column replacement list in programming mode needs to meet timing requirements. In practical applications, programming commands may be issued continuously at a high frequency, requiring the hardware to complete the address lookup and return the result in a short time; otherwise, it will become a system performance bottleneck. A multi-channel parallel lookup circuit can refer to a hardware logic circuit specifically designed for redundant column replacement list lookups. It can contain multiple sets of parallel comparator channels, capable of simultaneously comparing and judging multiple register records in the redundant column replacement list. For example, in a specific implementation, 8 to 32-channel parallel lookup circuits can be used, with each lookup channel working independently and without interference.

[0048] To better understand the advantages of multi-channel parallel lookup, consider a specific scenario: if the redundant column replacement list contains 192 register entries, and the lookup latency requirement for programming commands is limited to within 10 clock cycles, a single-channel serial lookup would require at least 192 cycles to complete a full lookup, exceeding the timing constraint. However, with a 32-channel parallel lookup circuit, the 192 register entries are divided into 32 groups of 6, with comparators in all groups working simultaneously. All comparisons can be completed in just 6 cycles, and an additional cycle is used to summarize the results, for a total of 7 cycles to complete the lookup, meeting the 10-cycle timing requirement. This multi-channel parallel hardware design means that the lookup latency is no longer directly proportional to the size of the replacement list, but is determined by both the parallelism and the latency of the single-channel comparator. When the target logical column address is input into the lookup circuit, each comparator simultaneously compares that address with the value stored in its assigned register entry. If any comparator hits, it outputs a hit signal and its corresponding register entry index. This index can be directly associated with the corresponding redundant physical column address for use by subsequent address redirection logic. If all comparators miss, it outputs a miss signal, and the hardware continues to perform programming operations on the original physical columns.

[0049] Through the design of the above-mentioned multi-parallel lookup table circuit, the redundant column replacement lookup operation in programming mode can be completed within a short time delay, meeting the timing requirements of high-frequency programming commands. At the same time, its hardware overhead increases controllably with the increase of parallelism, and it has good scalability.

[0050] In an optional embodiment, the redundant column replacement list may include N register entries, where N is a positive integer. Each register entry stores a logical column number to be replaced. The N register entries correspond one-to-one with the N redundant physical columns in the redundant column region. The nth register entry corresponds to the nth redundant physical column in the redundant column region, where n = 0, 1, ..., N-1. The physical mapping of the logical column number to be replaced stored in the nth register entry is fixed to use the nth redundant physical column.

[0051] In the embodiments of this specification, the mapping relationship between the redundant column replacement list and the redundant physical columns is defined. That is, there is a one-to-one correspondence between N register entries and N redundant physical columns in the redundant column region. This can be understood as each register entry in the redundant column replacement list not existing in isolation, but being bound to a specific redundant physical column. Specifically, the nth register entry corresponds to the nth redundant physical column in the redundant column region. This one-to-one fixed mapping relationship allows the hardware to perform address redirection and result homing without additional lookups or conversions; it can simply directly index the corresponding register entry based on the sequence number of the currently processed redundant physical column.

[0052] To illustrate this one-to-one correspondence more clearly, please refer to the example of the redundant column replacement list structure shown in Table 1. Taking the parameters mentioned earlier as an example, the redundant column replacement list contains 192 register entries (row numbers 0-191), and the redundant column area is physical columns 8000-8191. Each register entry in the list stores a logical column number to be replaced, indicating that the corresponding logical column has been detected as a bad column, and its physical mapping has been fixedly replaced with the redundant physical column corresponding to the row number. Table 1 illustrates this correspondence using a partial row number example: ; As shown in Table 1, each row (i.e., each register entry) is bound to a specific physical column within the redundant column region. Row 0 corresponds to physical column 8000, row 1 to physical column 8001, and so on, with row 191 corresponding to physical column 8191. When the hardware sees the bad column number stored in row n, it knows to replace it with physical column 8000+n, thus eliminating the need for an additional lookup in the mapping table, as the row number itself determines which spare column to replace it with.

[0053] It should be noted that the arrangement in Table 1 (index 3 is an invalid flag, index 4 stores 67) is one possible configuration result under the fixed mapping rule of "one-to-one binding of register indices with redundant physical columns". Here, "ordered arrangement" only means that the valid values ​​satisfy a monotonic order relationship; it does not require that valid register entries occupy adjacent register positions consecutively. In actual engineering implementation, different arrangement results can be obtained through different allocation strategies while adhering to the fixed mapping rule and the ordered arrangement rule. This does not affect the basic principles and effects of the technical solution in this application.

[0054] To more clearly illustrate the fixed mapping relationship between register row numbers and redundant physical columns, please refer to Table 2: ; In other words, when the hardware sees bad column number 5 in row 0, it knows to replace it with physical column 8000; when it sees bad column number 12 in row 1, it knows to replace it with physical column 8001, thus eliminating the need for additional lookups in the mapping table.

[0055] The fixed mapping relationship in this application simplifies hardware implementation. For example, during the lookup process in programming mode, if the target logical column address is found to be stored in the 3rd register entry, the hardware can directly deduce its corresponding redundant physical column as the starting address of the redundant column region plus 3, without needing to perform another address mapping conversion. Similarly, during the homing process in computation mode, when calculating the nth redundant physical column, the hardware directly reads the nth register entry to obtain the number of the column to be replaced, without needing to search through content addressing or other methods. This fixed mapping method is simpler in hardware implementation than dynamic mapping or content-addressable mapping, has a faster lookup speed, does not require complex content comparison and address decoding logic, and is suitable for in-memory computing array chips with limited area and power consumption.

[0056] In an optional embodiment, the replaced logical column numbers stored in each register entry can be arranged in sequence, and for inapplicable register entries, their values ​​can be set to a preset invalid flag.

[0057] In the embodiments of this specification, the organization of values ​​stored in register entries is further defined. The replaced logical column numbers stored in each register entry are arranged sequentially. Here, "sequentially" means that all valid bad column numbers are written into the corresponding register entries in a monotonic order (either ascending or descending). Ascending and descending arrangements are technically equivalent, both enabling a regular distribution of data in the list and providing conditions for parallel lookup circuits in programming mode to employ strategies such as block comparisons. For ease of understanding, the following embodiments of this specification use ascending arrangement as an example, but this does not constitute a limitation on the scope of protection. Those skilled in the art can replace it with descending arrangement to obtain the same technical effect. The choice between ascending and descending order is a one-time decision determined during the configuration phase based on design needs; the technical solution of this application does not require dynamic switching of the arrangement direction at runtime.

[0058] "Write sequentially" means that when filling registers, the numbers are stored into register entries one by one in monotonic order (from smallest to largest or from largest to smallest) according to the bad column numbers. However, entries are only filled when available, and it is not required that all positions be filled. Invalid entries are skipped (by filling in an invalid flag). In other words, "sequentially" emphasizes that the writing order is monotonic and ordered, rather than requiring that the register indices be consecutive.

[0059] Taking Table 1 as an example (arrivaled), the valid bad column numbers are arranged in ascending order as 5, 12, 31, 67, 7912. Register entry 0 stores 5, register entry 1 stores 12, register entry 2 stores 31; register entry 3 has no corresponding bad column to record, so it is filled with an invalid flag 1FFF; register entry 4 stores 67; ...; register entry 191 stores 7912. The monotonic order is not broken, i.e., 5 is the smallest, written to index 0; 7912 is the largest, written to index 191. The invalid flag is filled in for register entry 3, while 67 is written to index 4. For inapplicable register entries, their values ​​can be set to a preset invalid flag. In practical applications, not all redundant columns will be enabled. When the number of bad columns is less than the total number of redundant columns, some register entries will not have corresponding bad columns to record. For these inapplicable register entries, their values ​​are set to a specific value outside the normal column address range as an invalidation flag. For example, in a specific embodiment, the invalidation flag can be set to 1FFF (the maximum value of a thirteen-bit binary number). This invalidation flag can be identified during the table lookup process, allowing the multi-path parallel lookup circuit to skip these invalid entries and only compare valid register entries.

[0060] Another advantage of setting an invalidation flag in this scheme is its application in subsequent dynamic maintenance scenarios. After the chip is put into use, if a new bad column is detected, its number needs to be inserted into the appropriate position in the redundant column replacement list to maintain monotonic order. If an invalidation flag (i.e., a free register entry) already exists in the list, the hardware can directly write the new bad column number into that free entry without moving any existing valid data. For example, assuming index 3 in Table 1 is a free entry (invalidation flag), when a new bad column number 20 is detected, since 20 is between 12 and 31, the hardware can directly write 20 into index 3, making the list 5, 12, 20, 31, 67, 7912, still maintaining ascending order, and without moving any existing data. In contrast, if all register entries are filled with valid values ​​(no invalidation flag), inserting a new value requires shifting all valid values ​​after the insertion position sequentially, resulting in additional data movement overhead. Therefore, the existence of the invalidation flag in this scheme provides flexible empty slots for dynamic updates.

[0061] In an optional embodiment, the redundant column replacement list includes N register entries, where N is a positive integer. Each register entry corresponds one-to-one with the N redundant physical columns in the redundant column region, and each register entry is used to store the logical column number to be replaced. The step of determining whether the target logical column address matches the redundant column replacement list in response to a programming command may include: In response to the programming command, a query is performed among the N register entries to determine if any register entry stores a value equal to the target logical column address; if such a value exists, a match is determined, and the programming address is redirected to the redundant physical column corresponding to that register entry.

[0062] In the embodiments described in this specification, the table lookup operation in programming mode is implemented at the hardware level by comparing the values ​​of register entries.

[0063] Once the hardware recognizes the current operating mode as programming mode and receives the programming command, it parses the target logical column address. The lookup control logic then initiates a parallel query operation on all register entries in the redundant column replacement list. The query condition is to check if any register entry stores a value equal to the target logical column address. Since each register entry stores the logical column number marked as bad, this comparison operation essentially determines whether the target logical column address belongs to a set of pre-marked bad columns.

[0064] For example, if the target logical column address is 15, and the value stored in the second register entry of the redundant column replacement list is 15, then a hit occurs. In this case, the hardware determines the corresponding redundant physical column as the starting address of the redundant column region plus 2 (i.e., physical column 8002) based on the index number 2 of that register entry. Then, it redirects the programming address to physical column 8002, and the data is finally written to this redundant column. If the target logical column address is 20, but no register entry in the list stores 20, then a hit occurs, and the hardware continues to write the data to the original physical column 20.

[0065] If the query result indicates that the target logical column address is equal to the value stored in a register entry, a match is determined. At this point, the hardware determines the corresponding redundant physical column based on the index number of that register entry in the list, i.e., if that register entry is the nth register entry. According to the fixed mapping rule that the nth register entry corresponds to the nth redundant physical column, the hardware redirects the programming address to the physical address of that redundant physical column, and the data is subsequently written to that redundant physical column. If the query result indicates that no value equal to the target logical column address is found in any of the register entries, a match is determined, and the hardware continues to perform programming operations on the original physical column corresponding to the target logical column address.

[0066] Throughout the entire table lookup and redirection process, the hardware control logic remains transparent to the upper-level programming interface. The upper-level controller only needs to issue programming commands according to the original logical column address, without needing to care whether the target column is a bad column or to handle the details of address redirection.

[0067] In an optional embodiment, the step of performing simulation calculations on all physical columns within the normal column region in physical column order may include: Starting from the first physical column of the normal column region, the process sequentially traverses to the last physical column of the normal column region, performs analog domain multiplication and addition operations on each physical column, and outputs the calculation results of each physical column sequentially to the output data stream in the order of the physical columns.

[0068] The step of sequentially performing simulation calculations on redundant physical columns within the redundant column region may include: Starting from the initial physical column of the redundant column region, simulated domain multiplication and addition operations are performed sequentially on each redundant physical column to obtain the calculation result corresponding to that redundant physical column.

[0069] In the embodiments of this specification, the physical order calculation step of the normal column region is a fundamental step in the calculation mode redundant column repair method, the purpose of which is to maintain the consistency between the execution order and the output order of the physical columns. At the same time, the calculation step of the redundant column region is a continuation of the calculation of the normal column region, and its execution method is consistent with that of the normal column, also following the physical column order and ADC alignment principles.

[0070] Starting from the first physical column of the normal column region and traversing sequentially to the last physical column, the hardware control logic can be understood as initiating analog domain multiplication and addition operations column by column in ascending order of physical column addresses. This ensures that the word line voltage configuration and bit line read operations for each column are completed sequentially according to a preset timing sequence. For each physical column, the analog domain multiplication and addition operation process is as follows: when an input voltage signal is applied to the word line corresponding to that column, each memory cell in that column generates a current of corresponding magnitude according to its different resistance states. These currents converge at the bit line terminals in the column direction, forming an analog current or voltage signal characterizing the multiplication and addition result.

[0071] Taking a specific array configuration as an example, assume the normal column area consists of physical columns 0 to 7999, totaling 8000 columns. The hardware initiates analog calculations sequentially for each column, starting from column 0, then column 1, column 2, and so on up to column 7999. After each column is calculated, the analog output signal for that column is quantized into a digital value by the corresponding ADC channel and immediately written sequentially to the corresponding slot in the output data stream. For example, the result of column 0 is written to position 0 of the data stream, the result of column 1 to position 1, and so on. If column 5 is marked as a bad column, its output result, although invalid, is still written to position 5 of the data stream during calculation, maintaining the integrity of the order and preventing skipping. This sequential output method ensures that each position in the output data stream corresponds to the order of the physical columns; even if the content of some positions is invalid, the position number itself does not shift. It is precisely because of this physical order alignment that subsequent redundant column results can cover the correct logical positions.

[0072] After the calculations in the normal column region are completed, the hardware starts from the first physical column of the redundant column region and performs analog domain multiplication and addition operations on each redundant physical column sequentially. Taking the specific configuration mentioned above as an example, the redundant column region consists of physical columns 8000 to 8191, a total of 192 columns. The hardware starts from column 8000, then columns 8001, 8002, and so on up to column 8191, performing analog multiplication and addition operations one by one. After each column is calculated, its quantization result is temporarily stored in a temporary register, ready for subsequent repositioning operations. Since the redundant physical columns are tested and verified to be intact, the calculation results of each column are valid and can be directly used to correct invalid data in bad columns. In the actual calculation timing, after the normal column calculations are completed, the calculations of the redundant columns are usually performed continuously without other operations inserted in between. Simultaneously, since the traversal of the redundant column replacement list has been completed in advance during the normal column calculations, after each redundant column is calculated, its corresponding replaced column number is ready, and the repositioning operation can be executed immediately.

[0073] After each physical column completes its analog domain multiplication and addition operation, its output analog signal is synchronously quantized into a digital value by the corresponding ADC channel. Because the operation is performed sequentially by physical column without skipping any columns, the output signal of each physical column is always quantized by its fixed ADC channel. The alignment between the ADC channel and the physical column remains intact throughout the calculation, preventing signal misalignment or rerouting in the analog domain. After the calculation results of each column are quantized into digital values, they are written sequentially to the corresponding slots in the output data stream, forming the first calculation result sequence. In the first calculation result sequence, if a bad column marked for replacement exists within the normal column area, the output slot corresponding to that bad column stores an invalid result. However, the logical position occupied by this invalid result in the output data stream has been pre-reserved, providing a target write address for the digital field of subsequent redundant column calculation results. Through this "first reserve, then overwrite" approach, subsequent correction operations can replace the invalid results of bad columns through digital field write control without changing the analog physical connections.

[0074] In an optional embodiment, the step of assigning the calculation result of the redundant column in the digital domain to the logical position corresponding to the bad column number in the output data stream may include: The digital state machine reads the number of the column to be replaced corresponding to the calculated redundant physical column from the redundant column replacement list, generates an address control signal based on the number of the column to be replaced, and writes the calculation result of the redundant physical column into the output data stream at the logical position corresponding to the number of the column to be replaced, so as to cover the invalid results at the same logical position in the first calculation result sequence.

[0075] In the embodiments of this specification, the digital domain result reset step is a component of the computational mode redundancy repair mechanism. Its function is to transform the analog domain physical column replacement operation into digital domain write address control. The digital state machine can refer to a finite state control circuit composed of register logic and combinational logic, capable of executing corresponding operations according to a preset state transition sequence based on input state conditions and control signals. In the application scenario of this application, the digital state machine is configured during the redundancy column calculation phase to execute the corresponding reset operation triggered by the completion signal of each redundant physical column.

[0076] Specifically, after a redundant physical column completes an analog domain multiplication-addition operation and outputs a quantization result, the digital state machine reads the corresponding register entry of that redundant physical column in the redundant column replacement list and obtains the number of the replaced column stored therein. Since there is a one-to-one fixed mapping between the register entries in the redundant column replacement list and the redundant physical columns, the digital state machine can index the corresponding register entry based on the index of the currently processed redundant physical column. For example, if the current calculation is for redundant physical column 8000, the digital state machine reads the 0th register entry in the redundant column replacement list. If the value stored in this register entry is 5, it indicates that redundant physical column 8000 is used to replace logical column 5. The digital state machine then generates an address control signal, points the write pointer to the 5th position in the output data stream, and writes the calculation result of redundant column 8000 to that position, overwriting the invalid data originally generated by column 5 (the bad column).

[0077] Similarly, if the value stored in the first register entry is 12, then after calculating the redundant column 8001, its result is written to the 12th position of the output data stream. Through this pipelined operation of reading and writing one by one, the calculation results of all redundant columns are written to their corresponding bad column positions, thus completing the correction of the output data stream.

[0078] After obtaining the column number to be replaced, the digital state machine generates a corresponding write address control signal based on that number. This control signal positions the write pointer of the output data stream to the logical location corresponding to the column number to be replaced, i.e., the slot originally occupied by the bad column in the output data stream. Subsequently, the digital state machine writes the calculation result of the current redundant physical column to this logical location, overwriting the invalid results generated by the bad column during the calculation phase in the normal column area.

[0079] In this scheme, the repositioning operation is completed in the digital domain using read / write control logic. It does not require altering the physical connections in the analog computing path, nor does it introduce additional analog switches, multiplexers, or signal rerouting networks. Therefore, it does not introduce parasitic parameters and does not affect the computational accuracy and speed of the in-memory array. The entire repositioning process is transparent to the array's analog computing portion; the analog domain maintains its original physical structure, and the redundancy repair operation is encapsulated within the digital logic.

[0080] In an optional embodiment, the analog in-memory array may include M groups of analog-to-digital converters (ADCs), where M is a positive integer. Each group of ADCs corresponds to a fixed number of normal physical columns and redundant physical columns. Logical column numbers are assigned to each group of ADCs according to an interleaving rule. The logical number corresponding to the k-th column of the N-th ADC is M×k+N, where N is the ADC group index, N=0,1,…,M-1, and k is the position number within the group. The step of parallel traversing the redundant column replacement list may include: within the time window of performing simulated domain multiplication and addition operations on all physical columns in the normal column region, the hardware logic pre-traverses all register entries of the redundant column replacement list to determine the numbers of all replaced columns and their correspondence with the redundant physical columns, so as to be directly used for result occupancy when the subsequent redundant physical column calculation is completed.

[0081] In the embodiments of this specification, the ADC grouping architecture and logical column numbering rules of the analog in-memory array are components of the interface between the array physical design and the system application layer.

[0082] The analog in-memory array contains M groups of analog-to-digital converters (ADCs). Each group of ADCs corresponds to a fixed number of normal physical columns and redundant physical columns. The normal columns in each group are used to perform regular analog multiply-accumulate operations, while the redundant columns serve as backup resources to replace columns with functional abnormalities (i.e., bad columns) discovered during production testing or operation. Logical column numbers can be assigned to each group of ADCs according to an interleaving rule. Specifically, the logical number corresponding to the k-th column of the N-th ADC group is M×k+N, where N is the ADC group index (N=0,1,…,M-1), and k is the position number within the group. That is, the remainder of the logical number modulo M determines its ADC group, while the quotient determines its position number within the group. Figure 2Taking M=8 as an example, this interleaving allocation method is illustrated. In a specific embodiment, M=8 means there are 8 ADC groups (ADC 0~ADC 7), corresponding to 8 physical column groups (Group 0~Group 7). Each ADC group contains 1024 physical columns, including 1000 normal columns and 24 redundant columns. The figure distinguishes between normal columns (light fill) and redundant columns (dark fill) using different fill styles, showing the distribution of redundant columns at the end of each group. There are a total of 8000 normal columns and 192 redundant columns across the 8 groups, totaling 8192 columns. The logical column numbers are allocated according to the interleaving rules. The logical number of the kth column in the Nth ADC group is 8k+N. For example, ADC 0 is responsible for logical numbers 0, 8, 16, 24... (modulo 8, remainder is 0), ADC 1 is responsible for logical numbers 1, 9, 17, 25... (modulo 8, remainder is 1), and so on. The numbering sequence listed below Groups 0~7 in the figure presents this allocation rule. In this scheme, the interleaving allocation method allows the physical columns corresponding to adjacent logical numbers to be distributed in different ADC groups in the output data stream.

[0083] In practical array design, due to the physical limitations of the driving capability and quantization accuracy of a single ADC, it is usually necessary to divide the physical columns of a large-scale array into multiple ADC groups, with each group having a dedicated ADC responsible for quantizing the analog signals of its corresponding physical column. This grouping architecture ensures that the output signal of each physical column can be quantized under reasonable electrical conditions.

[0084] The logical column numbers are assigned to each group of analog-to-digital converters (ADCs) according to an interleaving rule. The logical number corresponding to the k-th column of the Nth ADC group is M×k+N. This interleaving rule means that the logical column numbers are not assigned consecutively according to the physical order of the ADC groups, but rather the columns with the same position number in each ADC group (i.e., the 0th, 1st, 2nd, etc. within each group) are interleaved. Specifically, the 0th column of the 0th ADC group corresponds to logical number 0, the 0th column of the 1st ADC group corresponds to logical number 1, ..., the 0th column of the (M-1)th ADC group corresponds to logical number M-1, then the 1st column of the 0th ADC group corresponds to logical number M, the 1st column of the 1st ADC group corresponds to logical number M+1, and so on. For example, when M=8, logical numbers 0-7 correspond to the 0th columns of the 8 different ADC groups, logical numbers 8-15 correspond to the 1st columns of the 8 different ADC groups, and so on. This distribution pattern has been implemented in... Figure 2 Presented in the middle.

[0085] In this scheme, the interleaving allocation method, combined with the physical order calculation strategy in the calculation mode, produces a certain synergistic effect. Because the calculation mode executes in physical column order without skipping bad columns, the alignment between physical columns and ADC channels is maintained. Furthermore, the interleaving allocation rule allows columns from different ADC groups to be distributed alternately within any physical location interval, resulting in a staggered arrangement of data from each ADC group in the output data stream of the calculation results.

[0086] In the step of parallel traversal of the redundant column replacement list, the hardware logic pre-traverses all register entries of the redundant column replacement list within the time window for performing analog domain multiply-add operations on all physical columns within the normal column region, determining all column numbers to be replaced and their correspondence with the redundant physical columns. The details of this operation have been described in step 106; its purpose is to complete the table lookup operation within the time window of the normal column calculation, without adding extra calculation cycles. When the subsequent redundant physical column calculations are completed, the hardware assigns each calculation result to its corresponding logical location according to the pre-determined correspondence.

[0087] In an optional embodiment, corresponding to the above method embodiment, this application also provides a memory computing chip. This chip includes at least one analog memory array, a redundant register set, a control circuit, and a digital domain result processing circuit.

[0088] The analog in-memory computing array (IMC) comprises normal column regions and redundant column regions. The physical columns of the array are grouped and connected to multiple analog-to-digital converters (ADCs). Specifically, a chip may contain one or more IMCs, each with a structure consistent with the array structure described in the preceding method embodiments, i.e., including normal column regions and redundant column regions. The physical columns are connected to the corresponding ADC channels according to the grouping rules used in the array design. Multiple arrays can operate independently or collaborate to complete larger-scale computing tasks.

[0089] A redundant register set is used to store the numbers of the replaced logical columns. In one embodiment of this application, the redundant register set includes N register entries, where N is a positive integer. Each register entry stores a number of the replaced logical column. The N register entries correspond one-to-one with the N redundant physical columns in the redundant column region. The nth register entry corresponds to the nth redundant physical column in the redundant column region, where n = 0, 1, ..., N-1. The physical mapping of the replaced logical column number stored in the nth register entry is fixed to use the nth redundant physical column. This register structure corresponds to the redundant column replacement list in the aforementioned method embodiment and is the data storage basis for implementing the redundant column repair function on the chip.

[0090] The control circuit is configured to determine the current operating mode by recognizing the command type or reading the mode status register. In programming mode, the control circuit responds to programming commands by using a multi-channel parallel lookup table circuit to determine whether the target logical column address hits the redundant register set. If it does, the programming address is redirected to the corresponding redundant physical column for programming; otherwise, the original physical column corresponding to the target logical column address is programmed directly. In computation mode, the control circuit controls the analog in-memory array to perform analog computations on all physical columns in the normal column region in physical column order, without skipping physical columns marked as bad, to maintain the alignment between the physical columns and the ADC. Simultaneously, while performing analog computations on all physical columns in the normal column region, the redundant register set is traversed in parallel to determine the column number to be replaced recorded in the redundant register set. The control circuit can be implemented using a state machine or microcontroller logic, and its specific implementation can employ digital circuit design techniques known in the art.

[0091] The digital domain result processing circuit is configured to, after the physical column calculation within the redundant column region is completed, return the calculation result of the redundant column to the logical position corresponding to the bad column number in the output data stream in the ADC-quantized digital domain, based on the bad column number recorded in the redundant register group, so as to overwrite the invalid results generated by the bad column during the normal column calculation stage. The digital domain result processing circuit can implement the return control through a digital state machine. Its operation corresponds to the digital domain result return step in the aforementioned method embodiment, that is, it reads the replacement column number corresponding to the calculated redundant physical column from the redundant register group, generates an address control signal based on this number, and writes the calculation result of the redundant physical column into the logical position corresponding to the replacement column number in the output data stream.

[0092] Through the description of the above chip embodiments, the hardware-level implementation of the technical solution of this application has been explained. The various circuit modules in the chip cooperate with each other to jointly realize the functions described in the foregoing method embodiments, such as real-time table lookup redirection in the programming mode, physical order calculation and digital domain result placement in the calculation mode, and table lookup delay hiding. Those skilled in the art should understand that the various circuit modules in the above chip embodiments can be implemented using digital circuit design techniques known in the art, and their specific implementation does not constitute a limitation on the scope of protection of this application.

[0093] Through the description of the above embodiments, the technical solution of this application has been explained in terms of redundant column repair mechanism in programming mode and computing mode, digital domain result placement method, configuration and management rules of redundant column replacement list, timing optimization of lookup delay, and ADC grouping and logical column interleaving allocation. Those skilled in the art should understand that the technical features of the above embodiments can be combined with each other to form more implementation schemes without conflict. At the same time, the technical solution of this application is not limited to RRAM in-memory arrays, but is applicable to any analog in-memory array with column as the computing granularity (including but not limited to RRAM, PCM, FeFET and other non-volatile memory arrays), as long as the calculation results need to be aggregated and output in the digital domain, this solution can be used to achieve redundancy repair.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for repairing redundant columns in a simulated in-memory array, characterized in that, An analog-to-in-memory computing array is applied to an array containing normal column regions and redundant column regions, wherein the physical column groups of the array are connected to multiple analog-to-digital converters (ADCs); the current operating mode is determined by identifying the type of the currently received command or reading the mode status register, wherein the operating mode includes a programming mode and a computation mode; wherein, if the current operating mode is a computation mode, the method includes: Simulation calculations are performed on all physical columns in the normal column region in the order of physical columns, without skipping physical columns marked as bad columns, in order to maintain the alignment between physical columns and ADC, and the calculation results of each physical column are stored in the output data stream in the order of physical columns to form the first calculation result sequence; Simulation calculations are performed sequentially on the redundant physical columns within the redundant column region. Based on the bad column numbers recorded in the redundant column replacement list, the calculation results of the redundant columns are returned to the logical position of the corresponding bad column number in the output data stream in the digital field, overwriting the invalid results generated by the bad columns during the normal column calculation phase. While calculating all physical columns within the normal column region, the redundant column replacement list is traversed in parallel to determine the information of the replaced columns recorded in the redundant column replacement list.

2. The method for repairing redundant columns in a simulated in-memory array according to claim 1, characterized in that, If the current working mode is programming mode, then in response to the programming command, the table is looked up to determine whether the target logical column address matches the redundant column replacement list; if it matches, the programming address is redirected to the corresponding redundant physical column for programming. If no match is found, the original physical column corresponding to the target logical column address is programmed directly.

3. The method for repairing redundant columns in a simulated in-memory array according to claim 2, characterized in that, The step of determining whether the target logical column address matches the redundant column replacement list in response to a programming command includes: By using a multi-path parallel lookup table circuit, multiple records in the redundant column replacement list are queried in parallel to determine whether the target logical column address is recorded in the redundant column replacement list.

4. The method for repairing redundant columns in a simulated in-memory array according to claim 1, characterized in that, The redundant column replacement list includes N register entries, where N is a positive integer. Each register entry stores a logical column number to be replaced. The N register entries correspond one-to-one with the N redundant physical columns in the redundant column region. The nth register entry corresponds to the nth redundant physical column in the redundant column region, where n = 0, 1, ..., N-1. The physical mapping of the logical column number to be replaced stored in the nth register entry is fixed to use the nth redundant physical column.

5. The method for repairing redundant columns in a simulated in-memory array according to claim 4, characterized in that, The replaced logical column numbers stored in each register entry are arranged in sequence, and for inapplicable register entries, their values ​​are set to a preset invalid flag.

6. The method for repairing redundant columns in a simulated in-memory array according to claim 2, characterized in that, The redundant column replacement list includes N register entries, where N is a positive integer. Each register entry corresponds one-to-one with the N redundant physical columns in the redundant column area. Each register entry is used to store the logical column number to be replaced. The step of determining whether the target logical column address matches the redundant column replacement list in response to a programming command includes: In response to the programming command, query among the N register entries whether any register entry stores a value equal to the target logical column address; If it exists, a hit is confirmed, and the programming address is redirected to the redundant physical column corresponding to that register entry.

7. The method for repairing redundant columns in a simulated in-memory array according to claim 1, characterized in that, The steps of performing simulation calculations on all physical columns within the normal column region in physical column order include: Starting from the first physical column of the normal column region, the process is traversed sequentially to the last physical column of the normal column region. Simulated domain multiplication and addition operations are performed on each physical column, and the calculation results of each physical column are output to the output data stream in the order of the physical columns. The steps of sequentially performing simulation calculations on redundant physical columns within the redundant column region include: Starting from the initial physical column of the redundant column region, simulated domain multiplication and addition operations are performed sequentially on each redundant physical column to obtain the calculation result corresponding to that redundant physical column.

8. The method for repairing redundant columns in a simulated in-memory array according to claim 1, characterized in that, The step of assigning the calculation result of the redundant column in the digital domain to the logical position of the corresponding bad column number in the output data stream includes: The digital state machine reads the number of the column to be replaced corresponding to the calculated redundant physical column from the redundant column replacement list, generates an address control signal based on the number of the column to be replaced, and writes the calculation result of the redundant physical column into the output data stream at the logical position corresponding to the number of the column to be replaced, so as to cover the invalid results at the same logical position in the first calculation result sequence.

9. The method for repairing redundant columns in a simulated in-memory array according to claim 1, characterized in that, The analog-to-in-memory array contains M groups of analog-to-digital converters, where M is a positive integer. Each group of analog-to-digital converters corresponds to a fixed number of normal physical columns and redundant physical columns. Logical column numbers are assigned to each group of analog-to-digital converters according to an interleaving rule. The logical number corresponding to the k-th column of the N-th group of analog-to-digital converters is M×k+N, where N is the group index of the analog-to-digital converter, N=0,1,…,M-1, and k is the position number within the group. The step of parallel traversing the redundant column replacement list includes: within the time window of performing simulated domain multiplication and addition operations on all physical columns in the normal column region, the hardware logic pre-traverses all register entries of the redundant column replacement list to determine the numbers of all replaced columns and their correspondence with the redundant physical columns, so as to be directly used for result occupancy when the subsequent redundant physical column calculation is completed.

10. A memory computing chip, characterized in that, include: At least one analog in-memory array comprising normal column regions and redundant column regions, wherein the physical column groups of the array are connected to multiple analog-to-digital converters (ADCs); A redundant register set includes N register entries, where N is a positive integer. Each register entry stores a logical column number to be replaced. The N register entries correspond one-to-one with the N redundant physical columns in the redundant column region. The nth register entry corresponds to the nth redundant physical column in the redundant column region, where n = 0, 1, ..., N-1. The physical mapping of the logical column number to be replaced stored in the nth register entry is fixed to use the nth redundant physical column. The control circuit is configured to determine the operating mode by identifying the command type or reading the mode status register. In programming mode, in response to the programming command, it determines whether the target logical column address hits the redundant register group through a multi-channel parallel lookup table circuit. If it hits, the programming address is redirected to the corresponding redundant physical column for programming. If it does not hit, the original physical column corresponding to the target logical column address is directly programmed. In the computing mode, the analog in-memory array is controlled to perform analog calculations on all physical columns in the normal column area in the order of physical columns, without skipping physical columns marked as bad columns, so as to maintain the alignment relationship between physical columns and ADC. At the same time, the redundant register group is traversed in parallel to determine the column number to be replaced. The digital domain result processing circuit is configured to be controlled by a digital state machine. After the physical column calculation in the redundant column region is completed, according to the bad column number recorded in the redundant register group, the calculation result of the redundant column is returned to the logical position of the corresponding bad column number in the output data stream in the digital domain after ADC quantization, so as to cover the invalid results generated by the bad column in the normal column calculation stage.

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