An efficiency optimization modulation method for hybrid three-level grid-connected converter
Patent Information
- Application Number
- CN202611542858.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-10-08
- Publication Date
- 2026-11-03
AI Technical Summary
Existing efficiency optimization methods for hybrid three-level grid-connected converters have limitations across the full power operating range. Hardware soft switching increases costs, zero-voltage switching frequency fluctuates greatly, and discontinuous pulse width modulation has a limited peak current clamping area under low power factor conditions, failing to effectively optimize the switching and conduction losses of bridge arm devices.
The power factor adaptive clamping region determination condition is adopted, and the switching and conduction losses of the bridge arm devices are optimized by using a dual current path switching drive sequence. This includes obtaining the modulation voltage of the converter grid-connected feedback control output, calculating the phase shift voltage and clamping region, constructing the phase bridge arm switching function of the converter, and obtaining the switching transistor drive signal sequence.
Under full power factor conditions, the switching losses of bridge arm devices were reduced by 27.7% and the conduction losses by 16.2%, while under low power factor conditions, the switching losses were reduced by 15.3% and the conduction losses by 8.3%, thus improving system efficiency.
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Figure CN123034735A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics technology, and more specifically to an efficiency optimization modulation method for hybrid three-level grid-connected converters. Background Technology
[0002] Hybrid three-level grid-connected converters based on Si and SiC configurations overcome the inherent physical limitations of single-device devices, effectively balancing cost and performance. Efficiency is the core performance indicator of this type of converter, directly determining the economic efficiency of system operation.
[0003] Currently, existing efficiency optimization methods mainly include hardware soft-switching schemes, zero-voltage switching frequency conversion schemes, and discontinuous pulse width modulation (DPWM) schemes. Hardware soft-switching schemes achieve zero-current or zero-voltage switching conditions for the power devices in the main circuit by designing auxiliary resonant circuits. In comparison, zero-voltage switching frequency conversion schemes do not require additional auxiliary devices; they increase current ripple and change the current direction by adjusting the switching frequency to meet the zero-voltage condition. Discontinuous pulse width modulation (DPWM) technology clamps a phase potential to a specific level, preventing switching action during the clamping period and thus eliminating corresponding switching losses. The larger the current in the clamping region, the more significant the reduction in switching losses. However, the above schemes do not consider topological characteristics to optimize device conduction losses.
[0004] In summary, while existing converter efficiency optimization methods each have their advantages, they still have certain limitations: hardware soft switching requires additional auxiliary components, resulting in higher costs and more complex control; while frequency conversion soft switching eliminates the need for auxiliary circuits, it suffers from large switching frequency fluctuations, increased conduction losses, or high dependence on sensors; discontinuous pulse width modulation (DPWM) generally suffers from limited peak current clamping areas under low power factor conditions, making it difficult to achieve comprehensive loss optimization across the entire power operating range. Furthermore, the aforementioned solutions do not consider topology characteristics to optimize the conduction losses of bridge arm devices. Therefore, to meet the actual operational needs of hybrid three-level grid-connected converters, it is urgent to research a method for improving efficiency across the entire operating domain through the coordinated optimization of switching and conduction losses, reducing power losses under various operating conditions and increasing investment returns. Summary of the Invention
[0005] In view of this, the present invention provides an efficiency optimization modulation method for hybrid three-level grid-connected converters, which at least solves the problem that existing converter efficiency optimization modulation methods are difficult to implement across the full power operating range.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: An efficiency-optimized modulation method for hybrid three-level grid-connected converters includes the following steps: S1: Obtain the three-phase normalized modulation voltage output of the converter's grid-connected feedback control. u a, u b and u c ; S2: Based on the rotation angle With power factor angle The relationship between them, calculation , and Corresponding phase shift voltage , and ; S3: Determine the current phase-shift voltage based on the power factor adaptive clamping region determination condition that considers midpoint potential balance. , and The corresponding clamping area; S4: Calculate the current voltage zero-sequence component based on the clamping region it falls into, and calculate the current modulation wave based on the current zero-sequence component; S5: Construct the phase bridge arm switching function of the converter based on the modulation wave, and obtain the converter switching transistor drive signal sequence. Among them, the switching drive signal sequence of the O clamping region is switched to the dual current path switching drive sequence: For each phase, the two external switches connected to the positive bus P and the negative bus N are disconnected, and the two internal switches connected to the midpoint O and the two clamping switches are closed.
[0007] Preferably, the rotation angle With power factor angle The relationship between them is: .
[0008] Preferably, the phase-shifting voltage , and The calculation method is as follows: .
[0009] Preferably, the power factor adaptive clamping region determination condition considering midpoint potential balance is as follows: O-state clamping region determination conditions: ; In the formula, , , Phase shift voltages , and The maximum, median, and minimum values in the data; For clamp phase bridge arm identification, ; The DC-side voltage imbalance is expressed as follows: ; In the formula, U C1 Indicates split capacitor Voltage, U C2 Indicates split capacitor Voltage; The condition for determining the clamping region in state P is: ; In the formula, This is the O-state clamping flag. =0 indicates that not all inequalities in the O-state clamping region determination condition are satisfied. =1 indicates that all inequalities in the O-state clamping region determination condition are satisfied; Indicates the amplitude of the phase-shifted voltage; The midpoint potential equilibrium angle is obtained by PI feedback control. ; In the formula, , , The proportional gain of the PI controller. The integral coefficient of the PI controller; the N-state clamping region determination condition is: .
[0010] Preferably, the specific content of S4 is as follows: The zero-order component z0 is: ; Modulated wave The parsing expression is: ; In the formula, This refers to the DC-side voltage imbalance.
[0011] Preferably, the specific content of the converter phase bridge arm switching function constructed based on the modulation wave in S5 is as follows: ; ; ; In the formula, Indicates the phase bridge arm switch status, including , , , and state; "&&" represents a triangular carrier wave with an amplitude of 0 to 1; "&&" represents a logical AND operation.
[0012] Preferably, the specific content of obtaining the converter switching transistor drive signal sequence is as follows: the main switching transistor is connected to the positive bus P and the negative bus N, and the two external switching transistors are respectively denoted as... and Let the two internal switching transistors connected to the midpoint O be denoted as and ,in This is the auxiliary switch tube on the P side of the positive busbar. The auxiliary switch transistors on the N side of the negative busbar are denoted as follows: [Implied: Auxiliary switch transistors on the N side of the negative busbar], and the two clamping switch transistors are denoted as [Implied: Auxiliary switch transistors on the N side of the negative busbar], ... and ;in express Any phase; In state P, the switching sequence ( , , , , , (1, 0, 1, 0, 1, 0); In state N, the switching sequence ( , , , , , (0, 1, 0, 1, 0, 1); In the state, the switch sequence ( , , , , , (0, 1, 1, 0, 1, 0); In the state, the switch sequence ( , , , , , (0, 1, 1, 0, 0, 1); In state 0, the switching sequence ( , , , , , (0, 1, 1, 0, 1, 1); In this context, "1" indicates that the switch is on, and "0" indicates that the switch is off.
[0013] As can be seen from the above technical solution, compared with the prior art, the present invention discloses an efficiency optimization modulation method for hybrid three-level grid-connected converters, which has the following beneficial effects: (1) On the one hand, traditional efficiency optimization modulation methods do not consider the impact of power factor on converter operating efficiency. As the power factor decreases, the overlap between the bridge arm clamping region and the current peak region narrows, and the switching loss gradually increases. Therefore, it only has better switching loss characteristics under a single power factor operating point. However, the present invention introduces power factor adaptive P, O, N state clamping, which increases the overlap between the clamping region and the π / 3 region of the phase current peak, thereby further reducing the switching loss of the bridge arm device under full power factor conditions. Compared with the traditional method, the present invention can reduce the switching loss of the converter phase bridge arm by 27.7% under quasi-capacitive operating conditions and by 15.3% under quasi-inductive operating conditions.
[0014] (2) On the other hand, traditional efficiency-optimized modulation methods only configure a single current path mode in the O-state clamping region under a single power factor operating point, and the device conduction loss is not fully optimized across the entire power factor range. The method proposed in this invention fully considers the topology characteristics and activates the set dual current path mode in the power factor adaptive O-state clamping region, effectively reducing the device on-resistance. Furthermore, as the power factor decreases, the duration of this mode increases, thereby further reducing the conduction loss of the bridge arm devices. Compared with traditional methods, this invention can reduce the conduction loss of the converter phase bridge arm by 16.2% under quasi-capacitive operating conditions and by 8.3% under quasi-inductive operating conditions. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 A flowchart illustrating an efficiency optimization modulation method for hybrid three-level grid-connected converters provided by this invention; Figure 2 A simplified circuit diagram of a hybrid three-level grid-connected converter provided in an embodiment of the present invention; Figure 3 A schematic diagram comparing the total switching losses of the A-phase bridge arm devices using different strategies under various operating conditions, provided for embodiments of the present invention. Figure 4 A schematic diagram comparing the total conduction loss of phase A bridge arm devices under different strategies in various operating conditions, provided for embodiments of the present invention. Figure 5 This diagram illustrates the system efficiency measured by various methods under different operating conditions, as provided in the embodiments of the present invention. Detailed Implementation
[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] This invention provides an efficiency-optimized modulation method for hybrid three-level grid-connected converters, as shown in the figure, comprising the following steps: S1: Obtain the three-phase normalized modulation voltage output of the converter's grid-connected feedback control. u a , u b and u c ; S2: Based on the rotation angle With power factor angle The relationship between them, calculation , and Corresponding phase shift voltage , and ; S3: Determine the current phase-shift voltage based on the power factor adaptive clamping region determination condition that considers midpoint potential balance. , and The corresponding clamping area; S4: Calculate the current voltage zero-sequence component based on the clamping region it falls into, and calculate the current modulation wave based on the current zero-sequence component; S5: Construct the phase bridge arm switching function of the converter based on the modulation wave, and obtain the converter switching transistor drive signal sequence. Among them, the switching drive signal sequence of the O clamping region is switched to the dual current path switching drive sequence: For each phase, the two external switches connected to the positive bus P and the negative bus N are disconnected, and the two internal switches connected to the midpoint O and the two clamping switches are closed.
[0019] It should be noted that: Simplified circuit of hybrid three-level grid-connected converter, such as Figure 2 As shown, where, and All are DC bus capacitors. and Main switch transistor, and As an auxiliary switching transistor, and For clamping switch transistors, , and All are AC-side filter inductors. , and Both are AC side output current. , and Both are AC side output voltages.
[0020] To further implement the above technical solution, the rotation angle With power factor angle The relationship between them is: .
[0021] To further implement the above technical solution, phase-shifting voltage , and The calculation method is as follows: .
[0022] To further implement the above technical solution, the power factor adaptive clamping region determination condition considering midpoint potential balance is as follows: O-state clamping region determination conditions: ; In the formula, , , Phase shift voltages , and The maximum, median, and minimum values in the data; For clamp phase bridge arm identification, ; The DC-side voltage imbalance is expressed as follows: ; In the formula, U C1 Indicates split capacitor Voltage, U C2 Indicates split capacitor Voltage; The condition for determining the clamping region in state P is: ; In the formula, This is the O-state clamping flag. =0 indicates that not all inequalities in the O-state clamping region determination condition are satisfied. =1 indicates that all inequalities in the O-state clamping region determination condition are satisfied; Indicates the amplitude of the phase-shifted voltage; The midpoint potential equilibrium angle is obtained by PI feedback control. ; In the formula, , , The proportional gain of the PI controller. The integral coefficient of the PI controller; the N-state clamping region determination condition is: .
[0023] To further implement the above technical solution, the specific content of S4 is as follows: The zero-order component z0 is: ; Modulated wave The parsing expression is: ; In the formula, This refers to the DC-side voltage imbalance.
[0024] To further implement the above technical solution, the specific content of the converter phase bridge arm switching function constructed based on the modulation wave in S5 is as follows: ; ; ; In the formula, Indicates the phase bridge arm switch status, including , , , and state; "&&" represents a triangular carrier wave with an amplitude of 0 to 1; "&&" represents a logical AND operation.
[0025] To further implement the above technical solution, the specific content of obtaining the converter switching transistor drive signal sequence is as follows: The main switching transistor is connected to the positive bus P and the two external switching transistors connected to the negative bus N, respectively denoted as... and Let the two internal switching transistors connected to the midpoint O be denoted as and ,in This is the internal switch tube on the P side of the positive busbar. The internal switch transistors on the N side of the negative busbar are denoted as follows: [Insert transistor name here] and ;in express Any phase; In state P, the switching sequence ( , , , , , (1, 0, 1, 0, 1, 0); In state N, the switching sequence ( , , , , , (0, 1, 0, 1, 0, 1); In the state, the switch sequence ( , , , , , (0, 1, 1, 0, 1, 0); In the state, the switch sequence ( , , , , , (0, 1, 1, 0, 0, 1); In state 0, the switching sequence ( , , , , , (0, 1, 1, 0, 1, 1); In this context, "1" indicates that the switch is on, and "0" indicates that the switch is off.
[0026] The specific details of the converter switching transistor drive signal sequence are shown in Table 1: Table 1 ; The invention will be further illustrated by experiments below: To verify the correctness and effectiveness of the method proposed in this invention, simulation and experimental tests were conducted. The system simulation and experimental parameters are shown in Table 2.
[0027] Table 2 ; (1) Simulation test A hybrid three-level converter simulation model was created in the PLECS platform, and the corresponding device parameter files were imported. The SiC device model is C3M0060065J, and the Si device model is IKW30B65ET7. The following six simulation conditions were set: Operating Condition 1: Power Factor Angle Output active power P out =315W; Operating Condition 2: Power Factor Angle Output active power P out = 315W; Operating Condition 3: Power Factor Angle Output active power P out = 4922W; Operating Condition 4: Power Factor Angle Output active power P out = 2630W; Operating Condition 5: Power Factor Angle Output active power P out = 2630W; Operating Condition 6: Power Factor Angle Output active power P out = 630W.
[0028] Under the aforementioned operating conditions, device losses were tested using both ADPWM and the method proposed in this invention. Considering the symmetry of the converter topology, the device loss of phase A bridge arm was selected as a representative indicator. The total switching and conduction losses of phase A bridge arm devices under the above operating conditions using the traditional method and the proposed method are plotted as follows: Figure 3 and Figure 4 As shown in the figure, the proposed method can effectively reduce the switching and conduction losses of the A-phase bridge arm devices under different operating conditions, and its advantages are particularly prominent under low power factor conditions, demonstrating the strong potential of this method to optimize conduction losses across the entire operating domain. Specifically, the A-phase bridge arm... Under these conditions (quasi-capacitive operating conditions), switching losses are reduced by 27.7%. Under these conditions (quasi-inductive operating conditions), switching losses are reduced by 15.3%; the A-phase bridge arm at the power factor angle... Under these conditions (quasi-capacitive operating conditions), conduction losses are reduced by 16.2%, and the power factor angle is [missing information]. Under these conditions (quasi-inductive operating conditions), conduction loss is reduced by 8.3%.
[0029] (2) Experimental testing Power factor angle and The results of the statistical comparison of system efficiency under different control methods under the operating conditions are as follows: Figure 5 As shown in the figure. Experimental results show that, compared to traditional methods, the method proposed in this invention... The efficiency optimization was most significant under the operating condition, with an efficiency improvement of 0.938%; Under the operating conditions, the efficiency improvement was 0.278%; Under the same operating conditions, the system efficiency of the two control methods is basically equivalent. In summary, the method proposed in this invention has a more significant advantage under low power factor conditions and exhibits superior efficiency across the entire operating domain.
[0030] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. An efficiency-optimized modulation method for hybrid three-level grid-connected converters, characterized in that, Includes the following steps: S1: Obtain the three-phase normalized modulation voltage output of the converter's grid-connected feedback control. u a , u b and u c ; S2: Based on the rotation angle With power factor angle The relationship between them, calculation , and Corresponding phase shift voltage , and ; S3: Determine the current phase-shift voltage based on the power factor adaptive clamping region determination condition that considers midpoint potential balance. , and The corresponding clamping area; S4: Calculate the current voltage zero-sequence component based on the clamping region it falls into, and calculate the current modulation wave based on the current zero-sequence component; S5: Construct the phase bridge arm switching function of the converter based on the modulation wave, and obtain the converter switching transistor drive signal sequence. Among them, the switching drive signal sequence of the O clamping region is switched to the dual current path switching drive sequence: For each phase, the two external switches connected to the positive bus P and the negative bus N are disconnected, and the two internal switches connected to the midpoint O and the two clamping switches are closed.
2. The efficiency optimization modulation method for hybrid three-level grid-connected converters according to claim 1, characterized in that, Rotation angle With power factor angle The relationship between them is: 。 3. The efficiency optimization modulation method for hybrid three-level grid-connected converters according to claim 1, characterized in that, Phase shift voltage , and The calculation method is as follows: 。 4. The efficiency optimization modulation method for hybrid three-level grid-connected converters according to claim 1, characterized in that, The power factor adaptive clamping region determination condition considering midpoint potential balance is: O-state clamping region determination conditions: ； In the formula, , , Phase shift voltages , and The maximum, median, and minimum values in the data; For clamp phase bridge arm identification, ; The DC-side voltage imbalance is expressed as follows: ； In the formula, U C1 Indicates split capacitor Voltage, U C2 Indicates split capacitor Voltage; The condition for determining the clamping region in state P is: ； In the formula, This is the O-state clamping flag. =0 indicates that not all inequalities in the O-state clamping region determination condition are satisfied. =1 indicates that all inequalities in the O-state clamping region determination condition are satisfied; Indicates the amplitude of the phase-shifted voltage; The midpoint potential equilibrium angle is obtained by PI feedback control. ； In the formula, , , The proportional gain of the PI controller. The integral coefficient of the PI controller; the N-state clamping region determination condition is: 。 5. The efficiency optimization modulation method for hybrid three-level grid-connected converters according to claim 1, characterized in that, The specific content of S4 is as follows: The zero-order component z0 is: ； Modulated wave The parsing expression is: ； In the formula, This refers to the DC-side voltage imbalance.
6. The efficiency optimization modulation method for hybrid three-level grid-connected converters according to claim 1, characterized in that, The specific content of the converter phase bridge arm switching function constructed based on the modulation wave in S5 is as follows: ； ； ； In the formula, Indicates the phase bridge arm switch status, including , , , and state; "&&" represents a triangular carrier wave with an amplitude of 0 to 1; "&&" represents a logical AND operation.
7. The efficiency optimization modulation method for hybrid three-level grid-connected converters according to claim 6, characterized in that, The specific content for obtaining the converter switching transistor drive signal sequence is as follows: The two main switching transistors connected to the positive bus P and the negative bus N are respectively denoted as... and Let the two auxiliary switching transistors connected to the midpoint O be denoted as and ,in This is the auxiliary switch tube on the P side of the positive busbar. The auxiliary switch transistors on the N side of the negative busbar are denoted as follows: [Implied: Auxiliary switch transistors on the N side of the negative busbar], and the two clamping switch transistors are denoted as [Implied: Auxiliary switch transistors on the N side of the negative busbar], ... and ;in express Any phase; In state P, the switching sequence ( , , , , , (1, 0, 1, 0, 1, 0); In state N, the switching sequence ( , , , , , (0, 1, 0, 1, 0, 1); In the state, the switch sequence ( , , , , , (0, 1, 1, 0, 1, 0); In the state, the switch sequence ( , , , , , (0, 1, 1, 0, 0, 1); In state 0, the switching sequence ( , , , , , (0, 1, 1, 0, 1, 1); In this context, "1" indicates that the switch is on, and "0" indicates that the switch is off.