Modulation method and system for common-mode voltage of high-voltage direct-hanging energy storage non-isolation topology

Abstract

The application discloses a common-mode voltage modulation method and system of a high-voltage direct-hanging energy storage non-isolation topology, and the method comprises the following steps: generating a driving signal of a sub-module by using pulse width modulation; in the modulation process, the carrier of each sub-module of a cascade phase is phase-shifted one by one, and the phase-shift angle is θ cj =(j‑1)2πk / N, wherein θ cj represents the phase-shift angle θ c of the jth sub-module of the cascade phase, and k is a natural number with a value range of 1 to 2N‑1; by phase-shifting the carrier of the sub-module, the common-mode voltage vector sum of the sub-module on the cascade phase is kept as a constant value, and the leakage current generated by the common-mode voltage of the sub-module in the total parasitic capacitance voltage of the cascade phase is eliminated. By using the above technical scheme, the common-mode voltage vector sum of the sub-module in the cascade phase is kept as a constant value by phase-shifting the carrier of the sub-module in the cascade phase with a specific phase-shift angle, so that the leakage current generated by the common-mode voltage and the parasitic capacitance is eliminated.

Description

Technical Field

[0001] This invention relates to the field of high-capacity high-voltage direct-connected energy storage technology, and in particular to a common-mode voltage modulation method and system for a non-isolated topology of high-voltage direct-connected energy storage. Background Technology

[0002] Against the backdrop of the ongoing energy transition, the large-scale integration of renewable energy, and the rapid development of new power systems, battery energy storage technology is rapidly upgrading towards larger capacity, higher voltage, and lower cost. Hundred-MW and even GW-level energy storage power stations have become an important component of new power systems. Traditional large-capacity battery energy storage system (BESS) projects commonly employ multi-unit parallel expansion and connection to the grid via power frequency transformers. However, the extensive use of power frequency transformers leads to significant losses, resulting in low system efficiency, large size, and high cost. Furthermore, the complex control of multi-unit parallel operation easily triggers system stability issues, making it unsuitable for the construction and operation requirements of hundred-megawatt to gigawatt-level large-capacity energy storage power stations.

[0003] To address the inherent shortcomings of traditional solutions, high-voltage direct-connected chain energy storage technology based on cascaded H-bridge (CHB) topology is gradually becoming the mainstream development direction.

[0004] However, current research on large-capacity high-voltage direct-connected energy storage technologies and modulation strategies focuses primarily on improving differential-mode performance, neglecting systematic research on leakage current issues caused by common-mode voltage in non-isolated (transformer-isolated) topologies. In non-isolated structures, the power units of chain-type energy storage systems are directly connected to the batteries due to the elimination of transformers. In large-capacity energy storage systems, batteries are often composed of multiple individual cells connected in series, resulting in a larger volume and introducing parasitic capacitance to the battery cabinet. The high-frequency switching of power devices may generate high-frequency varying common-mode voltages that act on these parasitic capacitances, forming leakage current through the high-voltage grid grounding wire. This leads to decreased communication reliability in the power grid system and poses safety hazards to personnel. Summary of the Invention

[0005] Purpose of the invention: This invention provides a common-mode voltage modulation method and system for a high-voltage direct-connected energy storage non-isolated topology, aiming to solve the technical problem of leakage current caused by common-mode voltage in the existing high-voltage direct-connected energy storage non-isolated topology.

[0006] Technical Solution: This invention provides a common-mode voltage modulation method for a non-isolated topology of high-voltage direct-connected energy storage, comprising: the non-isolated topology includes three-phase cascaded phases, with the positive voltage terminal of each cascaded phase connected to a three-phase AC bus and the negative voltage terminal grounded; each cascaded phase includes 2N cascaded sub-modules, where N is a non-zero natural number, each sub-module is connected to a battery array, the battery array is housed in a battery cabinet, the battery array introduces parasitic capacitance to the battery cabinet, and the cascaded phase experiences leakage current to ground based on the fluctuation of the parasitic capacitance voltage; the sub-modules in the cascaded phase are configured as H-bridge structures; pulse width modulation is used to generate drive signals for the sub-modules, and during the modulation process, the carrier wave of each sub-module in each cascaded phase is phase-shifted sequentially, with a phase shift angle of θ. cj =(j-1)2πk / N, where θ cj The phase shift angle θ of the j-th submodule in the cascaded phase is represented by... c k is a natural number ranging from 1 to 2N-1; by phase shifting the carrier of the submodule, the common-mode voltage vector sum of the submodules on the cascaded phase is kept constant, which is used to eliminate the leakage current generated by the common-mode voltage of the factor module in the total parasitic capacitance voltage of the cascaded phase.

[0007] Specifically, during modulation, the carrier of each cascaded phase submodule is phase-shifted sequentially, with a phase shift angle of θ. cj =kπ, by phase shifting the carrier of the submodule, the differential mode voltage vector sum of the submodules on the cascaded phase is reduced, which is used to eliminate the leakage current generated by the differential mode voltage of the factor module in the total parasitic capacitance voltage of the cascaded phase.

[0008] Specifically, during the modulation process, the modulation amplitude values ​​of the sub-modules in each cascaded phase are set to be equal.

[0009] Specifically, unipolar pulse width modulation is used for the sub-modules of each cascaded phase.

[0010] Specifically, for each cascaded phase submodule, unipolar sinusoidal pulse width modulation is used.

[0011] Specifically, during the modulation process, the carrier of each cascaded phase submodule is phase-shifted, with a phase difference of π between the carriers of adjacent submodules, while eliminating leakage current generated by the common-mode voltage and differential-mode voltage of the factor module.

[0012] Specifically, in each cascaded phase, an AC filter inductor with the same inductance value is provided at both the positive and negative voltage terminals.

[0013] Specifically, parasitic capacitance acts on the connection lines between the submodule and the battery array.

[0014] Specifically, filters are installed on the connection lines between the submodule and the battery array.

[0015] The present invention also provides a common-mode voltage modulation system for a high-voltage direct-connected energy storage non-isolated topology, for performing the common-mode voltage modulation method for any of the high-voltage direct-connected energy storage non-isolated topologies provided by the present invention.

[0016] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: By performing a specific phase shift on the carrier of the sub-module in the cascaded phase, the common-mode voltage vector sum of the sub-module in the cascaded phase is kept constant, thereby eliminating leakage current caused by common-mode voltage and parasitic capacitance; furthermore, by performing a specific phase shift on the carrier of the sub-module in the cascaded phase, in conjunction with unipolar sinusoidal pulse width modulation, the differential-mode voltage vector sum of the sub-module in the cascaded phase is made zero, thereby eliminating leakage current caused by differential-mode voltage and parasitic capacitance. Attached Figure Description

[0017] Figure 1 A schematic diagram of the structure of the large-capacity high-voltage direct-connected energy storage non-isolated cascade topology provided by the present invention; Figure 2 A simplified main circuit diagram of the non-isolated cascaded topology for high-capacity high-voltage direct-connected energy storage provided by the present invention; Figure 3 A simplified structural diagram of a large-capacity, high-voltage direct-connected energy storage non-isolated cascade topology with parasitic capacitance parameters and symmetrical inductance arrangement provided by the present invention. Figure 4 for Figure 3 A simplified equivalent model diagram; Figure 5 A schematic diagram illustrating the modulation principle of common-mode voltage vector phase shifting for the cascaded phase submodules provided by this invention; Figure 6 A schematic diagram of the structure of the CHB rectifier with four H-bridge sub-modules in a non-isolated topology cascaded phase provided by the present invention; Figure 7 This is a schematic diagram showing the relationship between the amplitude and phase of the modulated wave and the carrier wave within the power frequency cycle under the unipolar PWM modulation scheme provided by this invention. Figure 8 A schematic diagram showing the relationship between the amplitude and phase of the modulated wave and the carrier wave during the switching cycle under the unipolar PWM modulation scheme provided by the present invention; Figure 9 The voltage u between the left bridge arm point 1 and the right bridge arm point 2 of the A-phase submodule H1 provided by this invention and the reference point n. 1n and u 2n and its common-mode voltage u cm_A1 Differential mode voltage u dm_A1 A waveform diagram; Figure 10The common-mode voltage u of the four sub-modules H1, H2, H3, and H4 under the switching frequency scale provided by this invention cm_A1 u cm_A2 u cm_A3 and u cm_A4 and its A-phase total mode voltage u cm_A A waveform diagram; Figure 11 This is a schematic diagram of the differential mode voltage of phase A within a power frequency cycle under synchronous carrier modulation. Figure 12 This is a waveform diagram of the common-mode voltage of phase A, the total parasitic capacitance voltage, and the leakage current during the power frequency cycle under synchronous carrier modulation. Figure 13 This is a schematic diagram of the waveform of the differential mode voltage of phase A within the power frequency cycle under the carrier uniform phase shift modulation method provided by the present invention. Figure 14 This is a waveform diagram of the common-mode voltage of phase A, the total parasitic capacitance voltage, and the leakage current during the power frequency cycle under the carrier uniform phase-shift modulation method provided by the present invention. Detailed Implementation

[0018] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0019] See Figure 1 This is a schematic diagram of the structure of the non-isolated cascaded topology of high-capacity high-voltage direct-connected energy storage provided by the present invention.

[0020] In this non-isolated cascaded topology, the AC connection is a 35kV or higher high-voltage AC busbar. The non-isolated cascaded topology includes three cascaded phases (phase A, phase B, and phase C). The positive voltage terminals of each cascaded phase (points A, B, and C in the diagram) are connected to the three-phase AC busbar, while the negative voltage terminals of each cascaded phase are connected to the same point and then grounded (point O in the diagram). Each cascaded phase includes 2N cascaded sub-modules (H1 to Hn / H1 to H2N), where N is a non-zero natural number, U... dc This indicates the DC bus voltage on the submodule side. Each submodule is configured as an H-bridge structure, including four switching transistors. As shown in the figure, positions 1 and 2 in each submodule are points for cascading with adjacent submodules, or as the positive and negative voltage terminals of the cascaded phase. Position n is the voltage reference point of the submodule. Each submodule is connected to the battery array, and filters (capacitors and inductors) are installed on the connection lines between the submodules and the battery array. Each submodule manages the battery array through its own independent Battery Management System (BMS). This non-isolated cascaded topology, which does not use a power frequency transformer for isolation, has many advantages such as high efficiency, small size, and low cost.

[0021] See Figure 2 This is a simplified main circuit diagram of the non-isolated cascaded topology for high-capacity high-voltage direct-connected energy storage provided by the present invention.

[0022] like Figure 2 As shown, where u a u b and u c These represent the three phases of the power grid, and the current flowing through the corresponding cascaded phases is i. A i B and i C L f This refers to the AC filter inductor. The AC filter inductors on both the positive and negative voltage terminals can be symmetrically arranged. The switching transistors in the three-phase cascaded phase submodule are S and S respectively. 1 / 2 / 3 / 4_a1-a2N S 1 / 2 / 3 / 4_b1-b2N and S 1 / 2 / 3 / 4_c1-c2N The output voltages of the submodules are u 12_a1-a2n u 12_b1-b2n and u 12_c1-c2n .

[0023] See Figure 3 This is a simplified structural diagram of a large-capacity, high-voltage direct-connected energy storage non-isolated cascade topology with parasitic capacitance parameters and symmetrical inductance arrangement, provided by the present invention.

[0024] like Figure 3 As shown, the parasitic capacitance acts on the positive and negative DC connection lines between the submodule and the battery array, and is represented by C. PVij That is, the j-th parasitic capacitance on the i-th submodule.

[0025] according to Figure 3 As shown, the following can be obtained for calculating the common-mode voltage u of the j-th submodule. cmj Sum and difference mode voltage u dmj Formulas (1) and (2): u cmj =(u 1nj +u 2nj ) / 2, formula (1); u dmj =u 1nj -u 2nj , formula (2); Among them, u 1nj This represents the voltage at position 1 of the j-th submodule in the attached diagram relative to the voltage reference point position n, u 2nj This indicates the voltage at position 2 of the j-th submodule in the attached diagram relative to the voltage reference point position n. Positions 1 and 2 constitute the output port of the submodule.

[0026] In practical implementation, the output voltage of the submodule can be obtained from formulas (1) and (2): u 1nj =u cmj +u dmj / 2, formula (3); u 2nj =u cmj -u dmj / 2, formula (4).

[0027] Based on formulas (3) and (4), a simplified equivalent model can be established as follows: Figure 4 As shown, where i cmj This represents the leakage current flowing through the j-th submodule.

[0028] right Figure 4 Applying Kirchhoff's laws, we obtain formula (5) as follows: , formula (5), Among them, u Ajo express Figure 4 The j-th submodule corresponds to A j Point-to-point voltage; v cmj That is, u cmj , representing the common-mode voltage of the j-th submodule, v dmj That is, u dmj Z represents the differential-mode voltage of the j-th submodule; pv Indicates parasitic capacitance C PV The impedance, Z L Indicates AC filter inductor L f impedance; e g Indicates the power grid voltage source (corresponding to) Figure 4 u in A ), that is, the phase voltage of the high-voltage bus, i j This represents the current flowing through the main power circuit (inductor branch) of the j-th submodule; u njo This represents the parasitic capacitance voltage of the j-th submodule.

[0029] For the formula group of formula (5) above, the first term is the current equation of the top sub-module node of the cascaded phase, the second term is the current equation of the general node of the middle sub-module of the cascaded phase, the third term is the current equation of the bottom sub-module node of the cascaded phase, the fourth term is the voltage relationship equation between adjacent sub-modules, and the fifth term is the potential relationship equation of the same sub-module.

[0030] In practical implementation, based on the above formula (5), the following formula (6) can be obtained to calculate the total leakage current i flowing through the cascaded phase A. cm_A : i cm_A =CPV1 (du n1o / dt)+C PV2 (du n2o / dt)+......+C PV2N (du n2No / dt)=C PV (du nto / dt), formula (6). Among them, C PV1 C PV2 To C PV2N These represent the parasitic capacitances on the 1st, 2nd to 2Nth submodules of phase A, respectively. nto This represents the sum of the parasitic capacitance voltages of all submodules in phase A (and similarly for phases B and C).

[0031] According to formula (6), the total leakage current of phase A (and similarly phases B and C) is proportional to the rate of change of the sum of the parasitic capacitance voltages of all submodules in that phase. Therefore, if leakage current needs to be suppressed, the goal is to minimize the sum of the parasitic capacitance voltages u of all submodules. nto The fluctuation frequency and amplitude, and even try to maintain u nto If the value is constant, meaning the rate of change is 0, then the total leakage current i cm_A It can be eliminated.

[0032] Based on Z pv >>Z L The parasitic capacitance impedance is much greater than the AC filter inductor impedance. Therefore, most of the high-frequency common-mode voltage acts on the parasitic capacitance, while the mains voltage mainly acts on the inductor and load circuit. Therefore, in the high-frequency leakage current circuit, the mains voltage e g The effect is mainly reflected in the low-frequency range, and its impact on the high-frequency leakage current can be ignored. Therefore, u nto It can be simplified to the following formula (7): u nto ≈Ne g -(1 / 2)Σ j=1 2N (2N+1-2k)u dmj -Σ j=1 2N u cmj , formula (7).

[0033] In formula (7), Ne g The term represents the grid voltage component. Because the power frequency component changes slowly, the resulting leakage current is extremely small and can be ignored; (1 / 2)Σ j=1 2N (2N+1-2k)u dmjThe term represents the differential-mode voltage component, where the coefficient (2N+1-2k) indicates that the influence weight of the submodule at different locations on the voltage varies, and exhibits central antisymmetry; Σ j=1 2N u cmj The term represents the common-mode voltage component. Therefore, the key to suppressing leakage current is to minimize the sum of the parasitic capacitance voltages of the cascaded phases, u. nto The common-mode voltage component and the differential-mode voltage component remain constant.

[0034] In specific implementation, u cmj and u dmj Expressed in Fourier series form, we obtain the following formulas (8) and (9): , formula (8), , formula (9), Where, ω c θ represents the submodule switching angular frequency (carrier angular frequency). c The phase shift angle of the submodule carrier, u 1n and u 2n These represent the voltages at positions 1 and 2 marked on the submodules in the attached diagram relative to the voltage reference point at position n, respectively. A j The value of the high-frequency common-mode voltage component of the j-th submodule in the cascaded phase is represented by m, which represents the harmonic order. m b m A m and B m U represents the Fourier expansion coefficients, i.e., the amplitude weights of the corresponding harmonics. dc t represents the DC bus voltage on the submodule side, and t represents time.

[0035] Based on formula (8), it can be shown that the carrier phase shift angle θ can be adjusted. c This changes the phase relationship of the common-mode voltage between submodules.

[0036] Based on formula (9), m=2n in the subscript of the summation symbol. This indicates that under pulse width modulation, the differential mode voltage output by the H-bridge submodule contains the second carrier harmonic, that is, the frequency of the differential mode voltage is twice that of the common mode voltage, that is, the carrier angular frequency of the differential mode voltage is twice that of the common mode voltage.

[0037] When 2N H-bridge submodules are cascaded, the sum of the common-mode voltages u of the submodules on the i-th cascaded phase is... cm_i The formula is as follows (10): u cm_i =Σ j=1 2N u cmj =Σ j=1 2N Aj cos(mω c t+mθ cj ), formula (10).

[0038] Where, θ cj Let θ represent the phase shift angle of the j-th submodule in the cascaded phase. According to the formula (10), there exists a phase shift angle 2kπ / 2N, where 1≤k≤2N-1, which is a natural number ranging from 1 to 2N-1. The carriers of the submodules in the cascaded phase are phase shifted one by one, that is, the phase shift angle θ of the j-th submodule is... cj =(j-1)2πk / N, which makes the common-mode voltage vector sum of all sub-modules in the cascaded phase a constant value, i.e., the following formula (11): , formula (11).

[0039] See Figure 5 This is a schematic diagram of the modulation principle of the common-mode voltage vector phase shift of the cascaded phase sub-module provided by the present invention.

[0040] The common-mode voltage expression of the submodule in formula (5) is rewritten in vector form A. j ∠θ cj Then the common-mode voltage vector diagram of each submodule can be obtained, such as Figure 5 As shown, the common-mode voltage components of all submodules cancel each other out, and the vector sum is a constant value.

[0041] Therefore, according to the above formula (6), the common-mode voltage component in the parasitic capacitor voltage can remain constant under the above carrier phase shift angle provided by the present invention, and a considerable portion of the leakage current can be eliminated.

[0042] In this embodiment of the invention, pulse width modulation (PWM) is used to generate the drive signal for the sub-module. During the modulation process, the carrier of each cascaded phase sub-module is phase-shifted sequentially, with the phase shift angle being: θ cj =(j-1)2πk / N, Where, θ cj The phase shift angle θ of the j-th submodule in the cascaded phase is represented by... c k is a natural number ranging from 1 to 2N-1; By phase-shifting the carrier wave of the submodule, the common-mode voltage vector sum of the submodules in the cascaded phase is kept constant, which is used to eliminate the leakage current generated by the common-mode voltage of the factor module in the total parasitic capacitance voltage of the cascaded phase.

[0043] In practical implementation, according to the above formula (7), the coefficients of the differential-mode voltage components of the cascaded phase sub-modules are centrally antisymmetric (increasing / decreasing according to a fixed value). Combining formulas (8) and (9), it can be seen that the differential-mode voltage frequency is twice the common-mode voltage, that is, the phase difference θ of the common-mode voltage of each sub-module is... c The phase difference 2θ of the differential mode voltage of each submodule c Therefore, when θ cj =kπ,u nto The differential-mode voltage components cancel each other out.

[0044] In this embodiment of the invention, during the modulation process, the carrier of each cascaded phase submodule is phase-shifted sequentially, with the phase shift angle being: θ cj =kπ, By phase-shifting the carrier wave of the submodule, the differential-mode voltage vector sum of the submodules on the cascaded phase is reduced, which is used to eliminate the leakage current generated by the differential-mode voltage of the factor module in the total parasitic capacitance voltage of the cascaded phase.

[0045] In this embodiment of the invention, during the modulation process, the modulation amplitude values ​​of the sub-modules of each cascaded phase are set to be equal.

[0046] In practical implementation, the modulation amplitude of each submodule in a cascaded phase is set to 1 / (2N) of the original modulation amplitude. By equally distributing the modulation amplitude, the differential-mode voltage output by each submodule in the cascaded phase is completely consistent in both fundamental and high-frequency ripple amplitudes. This can better reduce the differential-mode voltage vector sum of the submodules in the cascaded phase, thus achieving a zero differential-mode voltage vector sum.

[0047] In this embodiment of the invention, unipolar pulse width modulation is used for each cascaded phase submodule.

[0048] In practical implementation, the output of the H-bridge submodule can be made to be in +U using unipolar pulse width modulation (PWM) or unipolar sinusoidal pulse width modulation (SPWM). dc Between and 0, or −U dc Switching between 0 and 0. During each switching cycle, the output voltage undergoes two transitions (once on the rising edge and once on the falling edge), effectively doubling the switching frequency and the differential-mode harmonics. The differential-mode voltage frequency is twice the common-mode voltage frequency.

[0049] Based on the above conditions, the phase shift angle θ of the j-th submodule cj =(j-1)2πk / N, the phase shift angle θ of the j-th submodule cj=kπ, and employing unipolar sinusoidal pulse width modulation. It can be seen that, for each cascaded phase submodule, the carrier wave is phase-shifted, with a phase difference of π between the carrier waves of adjacent submodules. This simultaneously eliminates the leakage current generated by the common-mode voltage and differential-mode voltage of the submodules. The vector sum of the common-mode voltages of the submodules is constant, while the vector sum of the differential-mode voltages is low, even zero. Therefore, the parasitic capacitance voltage fluctuation of the cascaded phase submodules can be low, or even constant, thereby suppressing or even eliminating leakage current.

[0050] In this embodiment of the invention, in each cascaded phase, the AC filter inductors on both sides of the positive and negative voltage terminals are symmetrically arranged; that is, the positive and negative voltage terminals of the cascaded phase are provided with AC filter inductors L of equal inductance values. f This setup ensures that the electrical environment of each submodule is consistent, resulting in the same high-frequency impedance across all submodules. This provides a uniform impedance distribution in the high-frequency common-mode circuit. If the inductors are asymmetrical, the parasitic capacitance of some submodules may resonate locally with the asymmetrical inductors, causing the sum of the parasitic capacitance voltages of the cascaded submodules to fail to maintain a constant value, thus generating leakage current.

[0051] See Figure 6 This is a schematic diagram of the non-isolated cascaded CHB rectifier comprising four H-bridge submodules provided by the present invention. The DC-side voltage U of each submodule is shown below. dc =800V, the effective value of the AC side voltage is U 12_ij =306V (i=a,b,c; j=1,2,3,4), switching frequency f of the switching device. s =2kHz, modulation ratio m=0.8.

[0052] See Figure 7 and Figure 8 These are schematic diagrams showing the relationship between the amplitude and phase of the modulation wave and the carrier wave of each cascaded phase sub-module during the power frequency cycle and the switching cycle, respectively, under the unipolar PWM modulation scheme.

[0053] from Figure 7 It can be seen that the positive and load wave amplitude values ​​of each submodule are 1 / 4, and the modulation wave u m1 to u m4 The amplitude is m / 4 (i.e., 0.2), and each group of modulated waves and its corresponding carrier waves are arranged at 1 / 2 intervals in the vertical direction.

[0054] from Figure 8It can be seen that the positive carrier car+ or the load wave car- of the four sub-modules are shifted by 180°, resulting in a 180° phase difference between the carriers of sub-modules H1 and H2, and a 180° phase difference between the carriers of H3 and H4. The carriers of H1 and H3 are in phase, and the carriers of H2 and H4 are in phase. That is, the carriers car1+ and car3+ are in phase, the carriers car1- and car3- are in phase, the carriers car2+ and car4+ are in phase, the carriers car2- and car4- are in phase, the carriers car1- and car2+ are in phase, the carriers car1+ and car2- are in phase, the carriers car3- and car4+ are in phase, and the carriers car3+ and car4- are in phase.

[0055] See Figure 9 It refers to the voltage u between the left bridge arm point 1 and the right bridge arm point 2 of the A-phase submodule H1 provided by this invention and the reference point n. 1n and u 2n and its common-mode voltage u cm_A1 Differential mode voltage u dm_A1 The waveform diagram shows that the common-mode voltage waveform of a single module is a three-level waveform, namely 0, U... dc / 2 (400V) and U dc (800V).

[0056] See Figure 10 The common-mode voltage u of the four sub-modules H1, H2, H3 and H4 under the switching frequency scale provided by this invention cm_A1 u cm_A2 u cm_A3 and u cm_A4 and its A-phase total mode voltage u cm_A The waveform diagram shows that, due to the 180° phase difference between the left and right bridge arm carrier phases of submodule H1 and the left and right bridge arm carrier phases of H2, the resulting common-mode voltage u cm_A1 and u cm_A2 They cancel each other out, meaning the sum of the common-mode voltages remains constant at U. dc Similarly, because the carrier phases of the left and right bridge arms of submodule H3 differ from the carrier phases of the left and right bridge arms of H4 by 180° respectively, the resulting common-mode voltage u cm_A3 and u cm_A4 They also cancel each other out, meaning the sum of the common-mode voltages remains constant at U. dc Therefore, the total mode voltage u of the cascaded phases is constant. cm_A =2U dc =1600V.

[0057] See Figure 11 It is the phase differential voltage u of phase A within the power frequency cycle under synchronous carrier modulation. dm_A Waveform diagram; see reference Figure 12It is the common-mode voltage u of phase A within the power frequency cycle under synchronous carrier modulation. cm_A Total parasitic capacitance voltage u cpv_A and leakage current i cm_A The waveform diagram shows that, under synchronous carrier modulation, the differential mode voltage u of phase A... dm_A It is a three-level circuit, and the common-mode voltages of each sub-module do not cancel each other out. The total common-mode voltage of phase A is u. cm_A There is no constant total voltage u across the parasitic capacitance of phase A. cpv_A The current is not constant, causing leakage current i cm_A There was no inhibition.

[0058] See Figure 13 It refers to the differential mode voltage u of phase A within the power frequency cycle under the carrier uniform phase shift modulation method provided by this invention. dm_A Waveform diagram; see reference Figure 14 It refers to the common-mode voltage u of phase A within the power frequency cycle under the carrier uniform phase-shift modulation method provided by this invention. cm_A Total parasitic capacitance voltage u cpv_A and leakage current i cm_A The waveform diagram shows that with a uniform 180° phase shift of the carrier, the differential mode voltage u of phase A... dm_A It's still a three-level circuit, but the common-mode voltages of each submodule cancel each other out, resulting in a total common-mode voltage u of phase A. cm_A The voltage is constant, and the differential-mode components also cancel each other out, resulting in a total voltage u across the parasitic capacitance of phase A. cpv_A To achieve a constant leakage current i cm_A The inhibition.

[0059] The present invention also provides a common-mode voltage modulation system for a high-voltage direct-connected energy storage non-isolated topology, for performing the common-mode voltage modulation method for any of the high-voltage direct-connected energy storage non-isolated topologies provided by the present invention.

Claims

1. A common-mode voltage modulation method for a high-voltage direct-connected energy storage non-isolated topology, characterized in that, include: The non-isolated topology includes three-phase cascaded phases, with the positive voltage terminal of each cascaded phase connected to the three-phase AC bus and the negative voltage terminal grounded; each cascaded phase includes 2N cascaded sub-modules, where N is a non-zero natural number, and each sub-module is connected to a battery array, which is housed in a battery cabinet. The battery array introduces parasitic capacitance to the battery cabinet, and the cascaded phase experiences leakage current to ground based on fluctuations in the parasitic capacitance voltage; the sub-modules in the cascaded phase are configured as H-bridge structures. The driving signal for the sub-module is generated using pulse width modulation. During the modulation process, the carrier wave of each cascaded phase sub-module is phase-shifted sequentially, with the phase shift angle being: i cj =(j-1)2πk / N, Where, θ cj The phase shift angle θ of the j-th submodule in the cascaded phase is represented by... c k is a natural number ranging from 1 to 2N-1; By phase-shifting the carrier wave of the submodule, the common-mode voltage vector sum of the submodules in the cascaded phase is kept constant, which is used to eliminate the leakage current generated by the common-mode voltage of the factor module in the total parasitic capacitance voltage of the cascaded phase.

2. The common-mode voltage modulation method for a non-isolated high-voltage direct-connected energy storage topology according to claim 1, characterized in that, The drive signal generated by the pulse width modulation submodule includes: During modulation, the carrier of each cascaded phase submodule is phase-shifted sequentially, with the phase shift angle being: i cj =kπ, By phase-shifting the carrier wave of the submodule, the differential-mode voltage vector sum of the submodules on the cascaded phase is reduced, which is used to eliminate the leakage current generated by the differential-mode voltage of the factor module in the total parasitic capacitance voltage of the cascaded phase.

3. The common-mode voltage modulation method for a non-isolated high-voltage direct-connected energy storage topology according to claim 2, characterized in that, The drive signal generated by the pulse width modulation submodule includes: During modulation, the modulation amplitude values ​​of the sub-modules of each cascaded phase are set to be equal.

4. The common-mode voltage modulation method for a non-isolated high-voltage direct-connected energy storage topology according to claim 2, characterized in that, For each cascaded phase submodule, unipolar pulse width modulation is used.

5. The common-mode voltage modulation method for a non-isolated high-voltage direct-connected energy storage topology according to claim 4, characterized in that, For each cascaded phase submodule, unipolar sinusoidal pulse width modulation is used.

6. The common-mode voltage modulation method for a non-isolated high-voltage direct-connected energy storage topology according to claim 4, characterized in that, The drive signal generated by the pulse width modulation submodule includes: During modulation, the carrier of each cascaded phase submodule is phase-shifted, and the phase difference between the carriers of adjacent submodules is π. At the same time, leakage current generated by the common-mode voltage and differential-mode voltage of the factor module is eliminated.

7. The common-mode voltage modulation method for a non-isolated high-voltage direct-connected energy storage topology according to claim 1, characterized in that, In each cascaded phase, an AC filter inductor with equal inductance is provided at both the positive and negative voltage terminals.

8. The common-mode voltage modulation method for a non-isolated high-voltage direct-connected energy storage topology according to claim 1, characterized in that, Parasitic capacitance acts on the connection lines between the submodule and the battery array.

9. The common-mode voltage modulation method for a non-isolated high-voltage direct-connected energy storage topology according to claim 1, characterized in that, A filter is installed on the connection line between the submodule and the battery array.

10. A common-mode voltage modulation system for a high-voltage direct-connected energy storage non-isolated topology, characterized in that, Common-mode voltage modulation method for performing the high-voltage direct-connected energy storage non-isolated topology according to any one of claims 1 to 9.

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