On-chip cryogenic optical interface integrating photodetector and noise-canceling transimpedance amplifier and cryogenic system

Abstract

The application discloses an on-chip low-temperature optical interface integrated with a photoelectric detector and a noise cancellation transimpedance amplifier and a low-temperature system, relates to the technical field of photoelectric integrated circuits and quantum computing systems, and solves the technical problem of lacking a low-temperature optical interface meeting the limited heat budget requirement in low-temperature quantum measurement and control and cross-temperature optical interconnection. The on-chip low-temperature optical interface comprises a photoelectric detector, a noise cancellation transimpedance amplifier, a double common-gate current multiplexing input stage, a bias circuit and an output synthesis stage. The double common-gate current multiplexing input stage comprises a first MOS being an NMOS, a second MOS being a PMOS, a first resistor and a second resistor with the same resistance. The source of the first MOS and the source of the second MOS are connected and connected to an optical current. The drain of the first MOS is used as a first output node, and the drain of the second MOS is used as a second output node. The output synthesis stage is used for synthesizing the voltage of the first output node and the voltage of the second output node and outputting a synthesized voltage.

Description

Technical Field

[0001] This invention relates to the fields of optoelectronic integrated circuits and quantum computing systems, and particularly to an on-chip cryogenic optical interface and cryogenic system that integrates a photodetector and a noise-cancelling transimpedance amplifier. Background Technology

[0002] As the computational scale of superconducting quantum computing systems expands, complex digital processing is typically deployed at room temperature due to the limited cooling power of the cryogenic cavity. The quantum processor at the cryogenic end needs to establish a cross-temperature communication link with the processor at room temperature to exchange large amounts of data. Therefore, a high-speed, low-power, and low-heat-load data interface needs to be configured at the cryogenic end.

[0003] Compared to traditional metal cables, which suffer from heat conduction, attenuation, crosstalk, and complex wiring, and wireless or terahertz interfaces, which have issues with transceiver power consumption, electromagnetic interference, and system stability, fiber optic data transmission has become a significant candidate for cryogenic cross-temperature communication links due to its advantages such as low thermal conductivity, high bandwidth, electromagnetic interference resistance, and reusability. Fiber optic data transmission requires a cryogenic optical interface at the cryogenic end to receive optical signals transmitted from the room-temperature end via fiber optics and convert them into a voltage recognizable by a quantum processor. In reality, incident light absorbed by the on-chip photodetector and surrounding structures is converted into heat, forming a photothermal load; the CMOS transimpedance amplifier, used to convert the photocurrent output from the photodetector into a voltage recognizable by the quantum processor, generates electrical power consumption during its operation, forming an electrothermal load. These photothermal and electrothermal loads, given the limited cooling power of the cryogenic cavity, become a burden on heat dissipation affecting the cryogenic cavity's cooling control.

[0004] In the process of realizing this invention, the inventors discovered at least the following problems in the prior art: There is a lack of low-temperature optical interfaces that meet the finite thermal budget requirements for low-temperature quantum measurement and control and cross-temperature optical interconnects. Summary of the Invention

[0005] The purpose of this invention is to provide an on-chip cryogenic optical interface and cryogenic system integrating a photodetector and a noise-cancelling transimpedance amplifier, thereby solving the technical problem of the lack of cryogenic optical interfaces that meet the finite thermal budget requirements for cryogenic quantum measurement and control and cross-temperature region optical interconnects in the prior art. The various technical effects of the preferred solutions among the many technical solutions provided by this invention are detailed below.

[0006] To achieve the above objectives, the present invention provides the following technical solution: The present invention provides an on-chip low-temperature optical interface for an integrated photodetector and a noise-cancelling transimpedance amplifier, comprising: the photodetector including one or more photodiodes for converting optical signals into photocurrents; the noise-cancelling transimpedance amplifier including a dual common-gate current-multiplexed input stage, a bias circuit, and an output combining stage; the dual common-gate current-multiplexed input stage including a first MOS (NMOS), a second MOS (PMOS), a first resistor, and a second resistor with the same resistance value; the source of the first MOS and the source of the second MOS are connected and connected to the photocurrent, the drain of the first MOS is connected to the power supply terminal as a first output node through the first resistor, and the drain of the second MOS is connected to ground as a second output node through the second resistor; the bias circuit provides bias voltages for the gates of the first MOS and the second MOS, and provides a reverse bias voltage for the photodiodes; the output combining stage is used to combine the voltages of the first output node and the second output node, and outputs the combined voltage.

[0007] Preferably, the bias circuit includes a third MOS (NMOS), a fourth MOS (PMOS), and a third resistor; the gate and drain of the third MOS are both connected to the power supply terminal and are also connected to the gate of the first MOS; the source of the third MOS is connected to the source of the fourth MOS, the drain of the fourth MOS is connected to ground through the third resistor, and the gates of the fourth MOS and the second MOS are both connected to a first bias voltage source.

[0008] Preferably, the resistance value of the third resistor is N times the resistance value of the first resistor, where N is greater than 1.

[0009] Preferably, the bias circuit further includes an operational amplifier, the positive input terminal of which is connected to the source of the first MOS and the source of the second MOS, the negative input terminal of which is connected to a reference voltage source, and the output terminal of which is connected to the gate of the second MOS.

[0010] Preferably, the photodetector includes M photodiodes connected in series, the anode of the first photodiode is connected to ground, the cathode of the m-th photodiode is connected to the anode of the (m+1)-th photodiode, and the cathode of the M-th photodiode is connected to the source of the first MOS and the source of the second MOS, respectively, where 1 ≤ m < M.

[0011] Preferably, the on-chip low-temperature optical interface adopts standard CMOS technology.

[0012] Preferably, the output synthesis stage includes a first AC amplifier circuit for amplifying the AC component of the voltage of the first output node, and a second AC amplifier circuit for amplifying the AC component of the voltage of the second output node, and the synthesized voltage is obtained by synthesizing the voltage at the output terminal of the first AC amplifier circuit and the voltage at the output terminal of the second AC amplifier circuit.

[0013] Preferably, the output terminal of the first AC amplifier circuit is connected to the output terminal of the second AC amplifier circuit.

[0014] Preferably, the output synthesis stage includes a differential circuit and a current mirror output circuit; the differential circuit converts the voltage of the first output node into a first differential perturbation current signal and converts the voltage of the second output node into a second differential perturbation current signal; the first differential perturbation current signal and the second differential perturbation current signal are simultaneously injected into the current mirror output circuit to change the voltage of a preset node in the current mirror output circuit, and the preset node serves as the output terminal of the output synthesis stage.

[0015] The present invention also provides a cryogenic system for superconducting quantum computing, including a cryogenic cavity, a quantum processor located in the cryogenic cavity, and an on-chip cryogenic optical interface provided by the present invention; the on-chip cryogenic optical interface is used to receive optical signals and convert the optical signals into the synthesized voltage, and the output terminal of the output synthesizing stage is connected to the signal input terminal of the quantum processor.

[0016] Implementing one of the above-described technical solutions of the present invention has the following advantages or beneficial effects: This invention leverages the high impedance, capacitance, and current-source input characteristics of an on-chip photodiode to the subsequent transimpedance amplifier. It configures a dual common-gate current-multiplexed input stage. The photocurrent output from the photodetector flows into a loop consisting of the source and drain of the first MOS transistor, and the drain and source of the second MOS transistor. This loop is converted into a signal voltage component in phase at the drains of both the first and second MOS transistors. Due to the high impedance of the photodiode, the channel thermal noise current of the first MOS transistor does not enter the photocurrent output path of the photodetector; instead, it flows into the source-drain loop of the second MOS transistor, forming a channel thermal noise voltage component at the drain of the second MOS transistor. This noise voltage component is related to the first MOS transistor's current characteristics. The channel thermal noise voltage components of the drain are out of phase. Therefore, during the process of the output synthesizing stage synthesizing the voltage of the first output node (the drain of the first MOS) and the voltage of the second output node (the drain of the second MOS), all or part of the channel thermal noise voltage components can be canceled, and the transconductance utilization efficiency can be improved. Due to the improved signal-to-noise ratio after noise cancellation, the required incident light power can be reduced under the same signal-to-noise ratio, thereby reducing the photothermal load. At the same time, the multiplexing of the common gate branch where the first MOS is located and the common gate branch where the second MOS is located in the dual common gate current multiplexing input stage can reduce the front-end power consumption, thereby reducing the electrothermal load. This enables the low-temperature optical interface to meet the limited thermal budget requirements in low-temperature quantum measurement and control and cross-temperature optical interconnection. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the low-temperature optical interface in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the photodetector in one example of Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the photodetector in another example of Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the circuit structure of the low-temperature optical interface in a preferred embodiment of the present invention. Figure 5 This is a schematic diagram of the noise cancellation principle of the first MOS M1 in the dual common gate current multiplexing input stage of the present invention; Figure 6 This is a schematic diagram of the noise cancellation principle of the second MOS M2 in the dual common gate current multiplexing input stage of the present invention; Figure 7This is a circuit structure diagram of the low-temperature optical interface in another preferred embodiment of the present invention; Figure 8 This is a circuit structure diagram of the low-temperature optical interface in another preferred embodiment of the present invention; Figure 9 This is a system block diagram of the cryogenic system for superconducting quantum computing in Embodiment 2 of the present invention; Figure 10 This is a micrograph of the on-chip photodiode of this invention; Figure 11 These are the photocurrent test results of the on-chip photodiode of this invention; Figure 12 This invention relates to the relationship between the characteristic frequency and current density of NMOS / PMOS and the matching design points; Figure 13 These are the simulation results of the transimpedance gain frequency response and noise of this invention; Figure 14 This is the output eye diagram of the low-temperature optical interface of the present invention when the input data stream is calibrated with an envelope tracking baseline at an input photocurrent of 4μA. Figure 15 This is the output eye diagram of the low-temperature optical interface of the present invention when the input photocurrent is 20μA and the input data stream is calibrated to 1Gbps using envelope tracking baseline. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be used to implement the present invention. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of the present invention disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of the present invention.

[0019] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0020] To illustrate the technical solution described in this invention, specific embodiments are described below, showing only the parts related to the embodiments of this invention.

[0021] Example 1: like Figure 1 As shown, this invention provides an on-chip cryogenic optical interface integrating a photodetector and a noise-cancelling transimpedance amplifier, comprising: a photodetector including one or more photodiodes for converting optical signals into photocurrents. ;like Figure 4 and Figure 7 As shown, the noise-canceling transimpedance amplifier includes a dual common-gate current-multiplexed input stage, a bias circuit, and an output combining stage. The dual common-gate current-multiplexed input stage includes a first MOS M1 (NMOS), a second MOS M2 (PMOS), and a first resistor R1 and a second resistor R2 with the same resistance value. The sources of the first MOS M1 and the second MOS M2 are connected and connected to a photocurrent. The drain of the first MOS M1 serves as the first output node and is connected to the power supply terminal AVDD via the first resistor R1. The drain of the second MOS M2 serves as the second output node and is connected to ground via the second resistor R2. The bias circuit provides bias voltages for the gates of the first MOS M1 and the second MOS M2, and for the photodiode (e.g., ...). Figure 7 The PD in the middle provides a reverse bias voltage; the output synthesis stage is used to synthesize the voltage of the first output node and the voltage of the second output node, and outputs the synthesized voltage.

[0022] In this embodiment, the equivalent input impedance of the photocurrent input node (the source of the first MOS M1 and the source of the second MOS M2) Transconductance of NMOS input transistor (first MOS M1) and transconductance of PMOS input transistor (second MOS M2) The joint decision can be approximated as: ; Compared to the traditional single common gate structure, this invention utilizes the transconductance of two input transistors to reduce the input impedance and improve the transconductance utilization efficiency per unit power consumption.

[0023] In this embodiment, both the first MOS M1 and the second MOS M2 operate in a common-gate configuration, with their sources interconnected and serving as signal input terminals, and their drains serving as signal output terminals. Specifically, the first MOS M1, the first resistor R1, and the power supply terminal AVDD form the first common-gate branch, while the second MOS M2, the second resistor R2, and ground form the second common-gate branch. A bias circuit provides voltage to the cathode of the photodiode in the photodetector, placing the photodiode in a reverse-biased state. Simultaneously, it ensures that the gate voltage of the first MOS M1 is higher than its source voltage, and the source voltage of the second MOS M2 is higher than its gate voltage, ensuring that both MOS M1 and MOS M2 operate in a conducting state (forming a conductive channel between their sources and drains). The first and second common-gate branches form a current loop, providing a stable bias current path for the photodiode. When an optical signal enters from the light-receiving area of ​​the photodetector, it causes the reverse-biased photodiode to generate a photocurrent from the cathode to the anode. In the current loop formed by the first common-gate branch and the second common-gate branch, the voltages of the first output node and the second output node will both be affected by the photocurrent. As the voltage changes (both voltage changes are in phase), the first MOS transistor M1 and the second MOS transistor M2 simultaneously participate in photocurrent readout, achieving common-gate current multiplexing. The equivalent input impedance at the photocurrent input point is determined by the transconductance of the two input transistors. Compared to a traditional single common-gate input stage, this structure utilizes the transconductance of the two input transistors (M1 and M2) to reduce the input impedance. The RC time constant formed by the on-chip photodiode junction capacitance, pad capacitance, and interconnect parasitic capacitance with the input impedance is reduced, thereby improving readout bandwidth and reducing intersymbol interference. Therefore, under the same input impedance target, the bias current required for a single input transistor can be reduced, improving transconductance utilization efficiency per unit power consumption.

[0024] This invention further utilizes the output synthesis stage to synthesize the voltage of the first output node and the voltage of the second output node, so that the synthesized voltage can double the signal voltage component converted by photocurrent, thereby improving the front-end signal-to-noise ratio.

[0025] In addition, such as Figure 5 As shown, the channel thermal noise current of the first MOS M1 Channel thermal noise voltage component at the drain of the first MOS M1 Represented as: Due to the high impedance characteristics of the photodiode, the channel thermal noise current of the first MOS M1 is... It will not enter the photocurrent output path of the photodetector (i.e., the cathode of the photodiode PD), but will only flow into the second common-gate branch, where it forms a channel thermal noise voltage component at the drain of the second MOS M2. Thermal noise voltage components of the two channels and Their phases are opposite. Similarly, as... Figure 6 As shown, the channel thermal noise current of the second MOS M2 The channel thermal noise voltage component at the drain of the second MOS M2 is expressed as: Due to the high impedance characteristics of the photodiode, the channel thermal noise current of the second MOS M2... It will not enter the photocurrent output path of the photodetector (i.e., the cathode of the photodiode PD), but will only flow into the first common-gate branch, where it forms a channel thermal noise voltage component at the drain of the first MOS M1. Thermal noise voltage components of the two channels and Their phases are opposite.

[0026] As can be seen from the above analysis, because the channel thermal noise voltage components of the drain of the first MOS M1 and the drain of the second MOS M2 have opposite phase characteristics, during the process of the output synthesizing stage synthesizing the voltage of the first output node (drain of the first MOS M1) and the voltage of the second output node (drain of the second MOS M2), all or part of the channel thermal noise voltage components can be canceled, further improving the front-end signal-to-noise ratio, improving the transconductance utilization efficiency, reducing the required incident light power, and thus reducing the photothermal load. At the same time, the multiplexing current of the first common gate branch and the second common gate branch can reduce the front-end power consumption, thereby reducing the electrothermal load, so that the low-temperature optical interface can meet the limited thermal budget requirements in low-temperature quantum measurement and control and cross-temperature zone optical interconnection.

[0027] Since the noise cancellation effect depends on the amplitude and phase relationship of the noise components on the first and second output nodes, the high-frequency characteristics of the upper and lower branches (the first common-gate branch where M1 is located and the second common-gate branch where M2 is located) need to be matched as closely as possible. Mismatch can be reduced by using load impedance matching, gm / Id (transconductance / drain current) method to select transistor size and bias point, input transistor characteristic frequency matching, symmetrical wiring, common-center layout, dummy devices, and parasitic extraction and correction.

[0028] In this embodiment, the bias circuit is not limited to the existing reference voltage source and resistor divider network. The resistor divider network divides the voltage output by the base voltage source to obtain multiple bias voltages that satisfy the reverse bias of the gate of the first MOSM1, the gate of the second MOSM2, and the photodiode in the noise cancellation transimpedance amplifier.

[0029] In this embodiment, the output synthesis stage is not limited to existing addition circuits, and will not be described in detail here.

[0030] In this embodiment, the photodetector includes only one photodiode. Alternatively, the photodetector includes two or more photodiodes connected in parallel or series. While connecting photodiodes in parallel increases the photocurrent, it also increases parasitic capacitance, reducing the circuit's response speed (bandwidth) and affecting high-speed response performance.

[0031] Therefore, preferably, the photodetector includes M photodiodes connected in series. The anode of the first photodiode is connected to ground, the cathode of the m-th photodiode is connected to the anode of the (m+1)-th photodiode, and the cathode of the M-th photodiode is connected to the source of the first MOS M1 and the source of the second MOS M2, where 1 ≤ m < M. By connecting the photodiodes in series, the photocurrent is not increased, but the dark current (leakage current) is reduced. Since dark current is one of the main sources of noise in the photocurrent, the signal-to-noise ratio of the photocurrent is significantly improved, thereby further reducing the required incident light power and reducing the photothermal load.

[0032] In this embodiment, preferably, the entire on-chip low-temperature optical interface is fabricated using standard CMOS technology, and the photodetector is also fabricated using standard CMOS technology, so that it can be integrated on the same substrate as the noise-canceling transimpedance amplifier using standard CMOS technology. No special modifications to the standard CMOS process flow are required, which is beneficial for monolithic integration and multi-channel expansion.

[0033] In one example, Figure 2 The internal structure of the photodetector is shown, including two photodiodes connected in series, PD1 and PD2. A bias voltage is applied to the cathode of PD2. The anode of PD2 is electrically connected to the cathode of PD1, and the voltage is... The anode of PD1 is connected to ground. For each photodiode, the bottom layer is a P-type substrate (PSUB). Within the P-type substrate, there are an N-well region (NW), a heavily doped P+ region (P+), and a heavily doped N+ region (N+). The heavily doped N+ region (N+) is located above the N-well region (NW). A heavily doped P+ region (P+) is located on each side of the N-well region (NW). A cathode metal electrode is electrically connected to the heavily doped N+ region (N+), and an anode metal electrode is electrically connected to the heavily doped P+ region (P+).

[0034] In another example, Figure 3 The internal structure of the photodetector is shown, which is a photodiode array. It is formed using bulk silicon CMOS technology with a P-type epitaxial substrate (PSUB), deep N-well (DNW), P-well (PW), heavily doped P+ region (P+), heavily doped N+ region (N+), shallow trench isolation structure, and metal electrodes. Multiple PN junctions are used to expand the photogenerated carrier collection area.

[0035] When incident light illuminates the light-receiving area of ​​a photodetector, electron-hole pairs are generated in the depletion region or its vicinity. Photogenerated carriers are collected under the influence of a built-in electric field and an applied bias, forming a photocurrent. By applying a preset bias to different doped regions, the carrier migration path and velocity can be adjusted, improving the low-temperature photoelectric response. This also reduces misalignment caused by spot shift and suppresses on-chip common-mode interference, making it suitable for low-temperature applications with optical path thermal drift and alignment errors.

[0036] In a preferred embodiment of this example, such as Figure 4 , Figure 7 and Figure 8 As shown, the bias circuit includes a third MOS M3 (NMOS), a fourth MOS M4 (PMOS), and a third resistor R3. The gate and drain of the third MOS M3 are both connected to the power supply terminal AVDD and also to the gate of the first MOS M1, providing a stable bias voltage to the gate of the first MOS M1. The source of the third MOS M3 is connected to the source of the fourth MOS M4, and the drain of the fourth MOS M4 is connected to ground through the third resistor R3. The gates of the fourth MOS M4 and the second MOS M2 are both connected to the first bias voltage source VB1. The bias circuit can be implemented using an existing reference voltage source and a resistor divider network. Specifically, the first bias voltage source VB1 is obtained by dividing the voltage from the output of the reference voltage source using a resistor divider network.

[0037] In this preferred embodiment, the third MOS M3 and the fourth MOS M4 in the bias circuit also operate in a common-gate mode, with their sources interconnected. The gate of the third MOS M3 is interconnected with the gate of the first MOS M1, and the gate of the fourth MOS M4 is interconnected with the gate of the second MOS M2. The bias voltage of the gate of the first MOS M1 is the power supply terminal AVDD, and the bias voltages of the gates of the second MOS M2 and the fourth MOS M4 are both the first bias voltage source VB1. The connection circuit structure between the third MOS M3 and the fourth MOS M4 is the same as that between the first MOS M1 and the second MOS M2. Therefore, the current in the connection path between the third MOS M3 and the fourth MOS M4 is... This can limit the current in the connection path between the first MOS M1 and the second MOS M2. If the dimensions of the first MOS M1 and the second MOS M2 are N times the dimensions of the third MOS M3 and the fourth MOS M4, or if the resistance of the third resistor R3 is N times the resistance of the first resistor R1, then the current in the connection path between the first MOS M1 and the second MOS M2 is... Further preferably, N is greater than 1, which is equivalent to the current of the bias circuit being one-Nth of the connection path current of the first MOS M1 and the second MOS M2, thus further saving power consumption. At this time, if the resistance of the first resistor R1 and the second resistor R2 is R, then the DC voltage of the first output node is limited to: The DC voltage of the second output node is limited to: Similarly, the voltage at the photocurrent input position, i.e. the voltage at the source of the first MOS M1 and the source of the second MOS M2, is clamped between 0.5V and 1.0V to provide a stable reverse bias voltage for the photodiode.

[0038] In this preferred embodiment, to further improve the stability of the reverse bias voltage of the photodiode, as is further preferred, Figure 7 and Figure 8 As shown, the bias circuit also includes an operational amplifier P. The positive input terminal of the operational amplifier P is connected to the source of the first MOS M1 and the source of the second MOS M2, respectively, and the negative input terminal of the operational amplifier P is connected to the reference voltage source. The output of operational amplifier P is connected to the gate of the second MOS M2.

[0039] Understandably, operational amplifier P operates in negative feedback mode. According to the virtual short principle, the potentials at the positive and negative input terminals of operational amplifier P are the same. Therefore, the reverse bias voltage on the cathode of photodiode PD is clamped to a fixed value. This improves the operational reliability of the photodiode. Furthermore, the output of operational amplifier P is connected to the gate of the second MOS M2, allowing the gate of the second MOS M2 to receive a fixed voltage less than [value missing]. The voltage is used as the first bias voltage source VB1.

[0040] When the optical signal is an optical communication signal, especially a high-speed optical communication signal, the voltage of the first output node and the voltage of the second output node need to be isolated by an isolation capacitor to separate their DC level differences, and the combined voltage is obtained by combining them in the AC domain. Therefore, in a preferred embodiment, such as Figure 4 and Figure 7 As shown, the output combining stage includes a first AC amplifier circuit for amplifying the AC component of the voltage at the first output node (i.e., the drain voltage of the first MOS M1), and a second AC amplifier circuit for amplifying the AC component of the voltage at the second output node (i.e., the drain voltage of the second MOS M2). The combined voltage is obtained by combining the voltage at the output terminals of the first and second AC amplifier circuits. Assuming the first and second AC amplifier circuits are structurally symmetrical, the combining method is not limited to using existing AC adder circuits. Further preferred methods include... Figure 4 and Figure 7 As shown, the output terminals of the first AC amplifier circuit and the second AC amplifier circuit are directly connected, and the voltage output by the first AC amplifier circuit and the voltage output by the second AC amplifier circuit are superimposed to obtain the composite voltage. .

[0041] In this preferred embodiment, such as Figure 4 and Figure 7 As shown, the first AC amplifier circuit includes a sixth MOS M6, a fifth MOS M5, a first capacitor C1, a second capacitor C2, a fourth resistor R4, and a fifth resistor R5. The first output node is connected to the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2, respectively. The first capacitor C1 and the second capacitor C2 respectively block the DC component of the voltage at the first output node, allowing only the AC component to pass through. The second terminal of the first capacitor C1 is connected to the first terminal of the fourth resistor R4 and the gate of the fifth MOS M5. The second terminal of the second capacitor C2 is connected to the second terminal of the fifth resistor R5 and the gate of the sixth MOS M6. The source of the fifth MOS M5 is connected to the power supply terminal AVDD, the drain of the sixth MOS M6 is connected to the drain of the fifth MOS M5, and the source of the sixth MOS M6 is connected to ground. The second terminal of the fourth resistor R4 is connected to the second bias voltage source VB2, and the second terminal of the fifth resistor R5 is connected to the third bias voltage source VB3. The fifth MOS M5 is a PMOS, and the sixth MOS M6 is an NMOS.

[0042] Similarly, the second bias voltage source VB2 and the third bias voltage source VB3 can be obtained by dividing the voltage at the output terminal of the reference voltage source through the existing resistor voltage divider network. The voltages of the second bias voltage source VB2 and the third bias voltage source VB3 are both lower than the power supply terminal AVDD, providing DC bias for the gate of the fifth MOS M5 and the gate of the sixth MOS M6.

[0043] The working principle of the first AC amplifier circuit is as follows: After the DC component of the voltage at the first output node is isolated by the first capacitor C1 and the second capacitor C2, when the AC component of the first output node changes positively (increases), the gate voltage of the fifth MOS M5 increases accordingly, and its source-gate voltage drop decreases, which weakens the conduction capability of the source and drain of the fifth MOS M5 (the drain-source current decreases). At the same time, the gate voltage of the sixth MOS M6 also increases with the positive change of the AC component of the first output node, and its gate-source voltage drop increases, which enhances the conduction capability of the source and drain of the sixth MOS M6, increases its drain-source current, and decreases the drain voltage of the sixth MOS M6. Therefore, the output voltage of the drain of the fifth MOS M5 and the drain of the sixth MOS M6 (the two interconnected drains serve as the output terminals of the first AC amplifier circuit) decreases. Conversely, when the AC component of the first output node changes negatively (decreases), the gate voltage of the fifth MOS M5 decreases accordingly, and its source-gate voltage drop increases, thereby enhancing the source and drain conduction capability of the fifth MOS M5 (increasing the drain-source current). At the same time, the gate voltage of the sixth MOS M6 also decreases as the AC component of the first output node changes negatively (decreases), weakening the source and drain conduction capability of the sixth MOS M6, reducing its drain-source current, and increasing the drain voltage of the sixth MOS M6. Therefore, the output voltage of the drains of the fifth MOS M5 and the sixth MOS M6 (the two interconnected drains serve as the output terminals of the first AC amplifier circuit) increases.

[0044] In this preferred embodiment, such as Figure 4 and Figure 7As shown, the second AC amplifier circuit includes an eighth MOS M8, a seventh MOS M7, a third capacitor C3, a fourth capacitor C4, a sixth resistor R6, and a seventh resistor R7. The second output node (the drain of the second MOS M2) is connected to the first terminals of the third capacitor C3 and the fourth capacitor C4, respectively. The third capacitor C3 and the fourth capacitor C4 are used to block the DC component of the voltage at the second output node, allowing only the AC component to pass through. The second terminal of the third capacitor C3 is connected to the first terminal of the sixth resistor R6 and the gate of the seventh MOS M7. The source of the seventh MOS M7 is connected to the power supply terminal AVDD. The drain of the seventh MOS M7 and the drain of the eighth MOS M8 are interconnected and serve as the output terminal of the second AC amplifier circuit. Preferably, the output terminals of the first and second AC amplifier circuits are directly connected and serve as the output terminal of the output combining stage. The second terminal of the fourth capacitor C4 is connected to the gate of the eighth MOS M8 and the first terminal of the seventh resistor R7, respectively. The source of the eighth MOS M8 is connected to ground. The seventh MOS M7 is a PMOS, and the eighth MOS M8 is an NMOS. The second terminal of the sixth resistor R6 is connected to the second bias voltage source VB2, and the second terminal of the seventh resistor R7 is connected to the third bias voltage source VB3. The second bias voltage source VB2 and the third bias voltage source VB3 provide DC bias for the gate of the seventh MOS M7 and the gate of the eighth MOS M8.

[0045] As can be seen, the second AC amplifier circuit has the same structure and working principle as the first AC amplifier circuit. Specifically, after the DC component of the voltage at the second output node is isolated by the third capacitor C3 and the fourth capacitor C4, when the AC component of the second output node changes positively (increases), the gate voltage of the seventh MOS M7 increases accordingly, and the source-gate voltage drop of the seventh MOS M7 decreases, which weakens the conduction capability of the source and drain of the seventh MOS M7 (the drain-source current decreases). At the same time, the gate voltage of the eighth MOS M8 also increases with the positive change of the AC component of the second output node, and the gate-source voltage drop of the eighth MOS M8 increases, which strengthens the conduction capability of the source and drain of the eighth MOS M8 (the drain-source current increases), and the drain voltage of the eighth MOS M8 decreases. Therefore, the output voltage of the drain of the seventh MOS M7 and the drain of the eighth MOS M8 (the two interconnected drains serve as the output terminals of the second AC amplifier circuit) decreases. When the AC component of the second output node changes negatively (decreases), the gate voltage of the seventh MOS M7 decreases accordingly, and the source-gate voltage drop of the seventh MOS M7 increases, thereby enhancing the source and drain conduction capability of the seventh MOS M7 (increasing the drain-source current). At the same time, the gate voltage of the eighth MOS M8 also decreases following the negative change of the AC component of the second output node, and the gate-source voltage drop of the eighth MOS M8 decreases, thereby weakening the source and drain conduction capability of the eighth MOS M8 (decreasing the drain-source current), and increasing the drain voltage of the eighth MOS M8. Therefore, the output voltage of the drains of the seventh MOS M7 and the eighth MOS M8 (the two interconnected drains serve as the output terminals of the second AC amplifier circuit) increases.

[0046] Since the voltage at the first output node is in phase with the voltage at the second output node, the output voltages of the first AC amplifier circuit and the second AC amplifier circuit are also in phase. By directly connecting the output terminals of the first and second AC amplifier circuits, voltage superposition can be achieved to obtain a composite voltage. .

[0047] When it is necessary to retain the DC component or low-frequency component of the optical signal, or when the optical signal is a low-frequency sensor signal (such as a current detection signal) or a signal from other non-high-speed optical communication scenarios, the output combining stage is DC-coupled combining. Therefore, in a preferred embodiment, such as Figure 8As shown, the output synthesizer stage includes a differential circuit and a current mirror output circuit. The differential circuit converts the voltage of the first output node into a first differential perturbation current signal and the voltage of the second output node into a second differential perturbation current signal. The first and second differential perturbation current signals are simultaneously injected into the current mirror output circuit to change the voltage of a preset node in the current mirror output circuit. The preset node serves as the output terminal of the output synthesizer stage. The user can select the preset node from the constant current path of the current mirror output circuit as needed.

[0048] In this preferred embodiment, such as Figure 8 As shown, the differential circuit includes a ninth MOS M9 and a tenth MOS M10, both PMOS, and an eleventh MOS M11 and a twelfth MOS M12, both NMOS. The sources of the ninth MOS M9 and the tenth MOS M10 are both connected to the power supply terminal AVDD. The gate of the ninth MOS M9 is connected to the first output node, and the gate of the tenth MOS M10 is connected to the second bias voltage source VB2. The voltage of the first output node and the second bias voltage source VB2 constitute the differential input voltage signal. The ninth MOS M9 and the tenth MOS M10 convert the differential input voltage signal into a pair of differential small-signal currents of equal magnitude and opposite direction, namely the first differential disturbance current signal. The gate of the eleventh MOS M11 is connected to the second output node, and the gate of the twelfth MOS M12 is connected to the third bias voltage source VB3. The sources of the eleventh MOS M11 and the twelfth MOS M12 are both connected to ground. The voltage of the second output node and the third bias voltage source VB3 constitute a differential input voltage signal. The eleventh MOS M11 and the twelfth MOS M12 are used to convert the differential input voltage signal into a pair of differential small signal currents of equal magnitude and opposite direction, namely the second differential disturbance current signal.

[0049] like Figure 8As shown, the current mirror output circuit includes PMOS transistors M13, M14, M15, and M16, and NMOS transistors M17, M18, M19, and M20. The sources of M13 and M14 are connected to the power supply terminal AVDD. The gates of M13 and M14 are connected. The drain of M13 is connected to the drain of M11 and the source of M15. The drain of M14 is connected to the drain of M12 and the source of M16. The drain of M14 is connected to the drain of M12 and the source of M16. The gate of M15 is connected to the gate of M16. The gate of M15 is connected to the gate of M16. The drain of M15 serves as the positive output terminal of the output combining stage and is connected to the gate of M16. The drain of M17 is connected; the drain of the sixteenth MOS M16 serves as the negative output terminal of the output combining stage and is connected to the drain of the eighteenth MOS M18. The preset nodes include the drains of the seventeenth MOS M17 and the eighteenth MOS M18. The voltage difference between the positive and negative output terminals of the output combining stage is used as the combining voltage. The gate of the seventeenth MOS M17 is connected to the gate of the eighteenth MOS M18. The source of the seventeenth MOS M17 is connected to the drain of the tenth MOS M10 and the drain of the nineteenth MOS M19, respectively. The source of the eighteenth MOS M18 is connected to the drain of the ninth MOS M9 and the drain of the twentieth MOS M20, respectively. The gate of the nineteenth MOS M19 is connected to the gate of the twentieth MOS M20. The sources of the nineteenth MOS M19 and the twentieth MOS M20 are both connected to ground.

[0050] In this preferred embodiment, the thirteenth MOS M13, fourteenth MOS M14, fifteenth MOS M15, and sixteenth MOS M16 all operate in common-gate mode, forming a symmetrical dual-rail constant current source. The seventeenth MOS M17, eighteenth MOS M18, nineteenth MOS M19, and twentieth MOS M20, all NMOS transistors, also operate in common-gate mode, serving as the active load of the constant current source. After the first and second differential perturbation current signals are injected into the constant current source, they attempt to change the current flowing into the active load. The MOS transistors in the active load, under bias constraints, resist this change, ultimately converting it into a large voltage fluctuation between the positive and negative output terminals of the output synthesizer stage. Furthermore, the first and second differential perturbation current signals are in phase, achieving voltage superposition at the output of the output synthesizer stage, thereby efficiently converting the first and second differential perturbation current signals into a high-gain synthesized voltage. .

[0051] It should be noted that, in order to successfully implement the above process, the gates of the thirteenth MOS M13 to the twentieth MOS M20 in the current mirror output circuit are each set with their own bias voltage (not shown). The specific setting method can refer to the gate bias voltage setting method of the existing common source cascode circuit, which will not be repeated here.

[0052] Example 2: This invention discloses a cryogenic system for superconducting quantum computing, such as... Figure 9 As shown, the cryogenic system includes a cryogenic cavity, a quantum processor located inside the cryogenic cavity, and an on-chip cryogenic optical interface provided in Embodiment 1; the on-chip cryogenic optical interface is used to receive optical signals and convert the optical signals into a synthesized voltage, and the output terminal of the output synthesizer is connected to the signal input terminal of the quantum processor.

[0053] In this embodiment, the quantum processor can acquire the voltage at the output of the output synthesis stage via an analog-to-digital sampling interface. The data information transmitted from the room-temperature processor to the quantum processor is converted into an optical signal, which is not limited to transmission of the optical signal to the light-receiving area of ​​the photodetector via optical fiber or on-chip optical waveguide. The on-chip photodetector completes the low-temperature photoelectric conversion, and the noise-cancelling transimpedance amplifier directly performs low-impedance, low-noise transimpedance readout of the photocurrent. The on-chip photodetector and the noise-cancelling transimpedance amplifier form a synergistic relationship oriented towards the low-temperature thermal budget: noise cancellation reduces the required incident light power and reduces photothermal load; current multiplexing reduces front-end power consumption and reduces electrothermal load. The above two effects together make this invention applicable to low-temperature quantum measurement and control and cross-temperature optical interconnects with limited cooling power scenarios. Without changing the standard CMOS process flow, the synergistic integration of the on-chip photodiode and the noise-cancelling transimpedance amplifier is achieved, reducing the parasitic interconnection of discrete devices and improving the integration and scalability of multi-channel low-temperature optical interfaces.

[0054] Experimental verification: 1. Low-temperature testing and verification of photodetectors In this experiment, the photodetector consists of only one photodiode, also known as an on-chip photodiode, as shown in the micrograph. Figure 10 As shown, an on-chip photodiode was fabricated using standard CMOS technology, and its photoresponse under room temperature and low temperature conditions was tested. During the test, a 532nm green laser and a 637nm red laser were selected as the incident light sources. The light signal was introduced into the low-temperature test environment via optical fiber and irradiated the light-receiving area of ​​the on-chip photodiode. The on-chip photodiode generated a photocurrent under reverse bias conditions, which was measured using a semiconductor parameter analyzer.

[0055] Under certain test conditions, the reverse bias voltage of the on-chip photodiode is 1V, and the incident light power is 1mW. Figure 11 The photocurrent test results of the on-chip photodiode are presented, showing that at room temperature, the on-chip photodiode generates approximately 61.3 μA of photocurrent for 637 nm light and approximately 36.8 μA of photocurrent for 532 nm light; at a low temperature of 7 K, the on-chip photodiode generates approximately 55.8 μA of photocurrent for 637 nm light and approximately 34.2 μA of photocurrent for 532 nm light. These tests demonstrate that the on-chip photodiode fabricated using standard CMOS technology can still generate readable photocurrent at low temperatures, and can be used as the input photocurrent source for the noise cancellation transimpedance amplifier of this invention.

[0056] 2. Simulation Verification of Noise Cancellation Transimpedance Amplifier The cryogenic optical interface includes a photodetector and a noise-cancelling transimpedance amplifier connected to it. The photodetector includes one or more photodiodes. The photodetector can be equivalently represented as an input model with a photocurrent source connected in parallel with junction capacitance, pad capacitance, and interconnect parasitic capacitance. To verify the readout capability of the noise-cancelling transimpedance amplifier for the output photocurrent of the on-chip photodiode, in the simulation, an equivalent input capacitance can be used to simulate the on-chip photodiode and its interconnect parasitics, and a current signal can be input to the noise-cancelling transimpedance amplifier.

[0057] The transimpedance amplifier is implemented using CMOS technology. The dual common-gate current-multiplexed input stage consists of a complementary NMOS transistor (M1) and a PMOS transistor (M2) forming a dual common-gate structure. The input photocurrent signal is injected from the common input node of the dual common-gate input stage and converted into voltage signals at the first and second output nodes via the upper and lower branches. The output combining stage combines the voltages of the two output nodes to output the amplified transimpedance voltage signal, i.e., the combined voltage.

[0058] To ensure the phase and bandwidth of the high-frequency paths are as consistent as possible, a design method based on gm / Id (transconductance / drain current) can be used to optimize transistor size and bias point, making the characteristic frequencies of the NMOS and PMOS input transistors as similar as possible. For example, in a 28nm CMOS process, the target characteristic frequency can be selected as 15GHz; for the NMOS input transistor, gm / Id=18 is selected, corresponding to a bias current density of approximately 4μA / μm; for the PMOS input transistor, gm / Id=10 is selected, corresponding to a bias current density of approximately 10μA / μm. Simultaneously, the load resistances of the upper and lower branches are kept symmetrical, both set to 1kΩ, to improve the consistency of the AC characteristics of the two output nodes. Figure 12The relationship between NMOS / PMOS characteristic frequencies and current densities, as well as matching design points, are illustrated. The transimpedance amplifier is implemented using a 28nm CMOS process, with a supply voltage of 1.8V and an input capacitor of 0.5pF. Through a dual common-gate current multiplexing structure and a synthesis structure, this transimpedance amplifier achieves a transimpedance gain of approximately 82dBΩ and a DC current of approximately 370μA in simulations. Within the signal band, the output noise level can be suppressed to approximately 10.5pA / √Hz. Figure 13 These are the simulation results of the transimpedance gain frequency response and noise of this invention.

[0059] For a 1Gbps input data stream, Figure 14 and Figure 15 The output eye diagrams of the low-temperature optical interface of this invention are shown for 1Gbps input data streams calibrated using envelope tracking baseline at input photocurrents of 4μA and 20μA, respectively. It can be seen that the output eye diagram remains well-opened within the input current range of 4μA to 20μA, indicating that this structure can meet the readout requirements of gigabits per second current-mode input signals.

[0060] In the above experimental verification process, the process node, power supply voltage, input capacitance, bias current, transimpedance gain, noise level, and input dynamic range are all parameters of a specific implementation method, used to illustrate the feasibility of the present invention, and should not be construed as limiting the scope of protection of the present invention. In other embodiments, the transistor size, bias current, load impedance, and synthesis stage size can be adjusted according to the target rate, input capacitance, input photocurrent range, power budget, and process node.

[0061] The embodiment is merely a specific example and does not indicate that this is the only way to implement the present invention.

[0062] The above description is merely a preferred embodiment of the present invention. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. An on-chip cryogenic optical interface integrating a photodetector and a noise-cancelling transimpedance amplifier, characterized in that, include: The photodetector includes one or more photodiodes for converting optical signals into photocurrents; The noise cancellation transimpedance amplifier includes a dual common-gate current-multiplexed input stage, a bias circuit, and an output combining stage; The dual common gate current multiplexing input stage includes a first MOS which is an NMOS, a second MOS which is a PMOS, a first resistor and a second resistor with the same resistance value; the source of the first MOS and the source of the second MOS are connected and connected to the photocurrent; the drain of the first MOS serves as the first output node and is connected to the power supply terminal through the first resistor; the drain of the second MOS serves as the second output node and is connected to ground through the second resistor. The bias circuit provides bias voltages for the gates of the first MOS and the second MOS, and provides a reverse bias voltage for the photodiode; The output synthesis stage is used to synthesize the voltage of the first output node and the voltage of the second output node, and output the synthesized voltage.

2. The on-chip low-temperature optical interface for the integrated photodetector and noise-cancelling transimpedance amplifier according to claim 1, characterized in that, The bias circuit includes a third MOS that is an NMOS, a fourth MOS that is a PMOS, and a third resistor; The gate and drain of the third MOS are both connected to the power supply terminal and are also connected to the gate of the first MOS; the source of the third MOS is connected to the source of the fourth MOS, the drain of the fourth MOS is connected to ground through the third resistor, and the gate of the fourth MOS and the gate of the second MOS are both connected to the first bias voltage source.

3. The on-chip low-temperature optical interface for the integrated photodetector and noise-cancelling transimpedance amplifier according to claim 2, characterized in that, The resistance of the third resistor is N times the resistance of the first resistor, where N is greater than 1.

4. The on-chip low-temperature optical interface for the integrated photodetector and noise-cancelling transimpedance amplifier according to claim 2, characterized in that, The bias circuit further includes an operational amplifier, the positive input terminal of which is connected to the source of the first MOS and the source of the second MOS, the negative input terminal of which is connected to a reference voltage source, and the output terminal of which is connected to the gate of the second MOS.

5. The on-chip low-temperature optical interface for the integrated photodetector and noise-cancelling transimpedance amplifier according to claim 1, characterized in that, The photodetector includes M photodiodes connected in series. The anode of the first photodiode is connected to ground, the cathode of the m-th photodiode is connected to the anode of the (m+1)-th photodiode, and the cathode of the M-th photodiode is connected to the source of the first MOS and the source of the second MOS, respectively, where 1 ≤ m < M.

6. The on-chip cryogenic optical interface for the integrated photodetector and noise-cancelling transimpedance amplifier according to claim 1, characterized in that, The on-chip low-temperature optical interface uses standard CMOS technology.

7. The on-chip cryogenic optical interface for the integrated photodetector and noise-cancelling transimpedance amplifier according to any one of claims 1-6, characterized in that, The output synthesis stage includes a first AC amplifier circuit for amplifying the AC component of the voltage of the first output node, and a second AC amplifier circuit for amplifying the AC component of the voltage of the second output node. The synthesized voltage is obtained by combining the voltage at the output terminal of the first AC amplifier circuit and the voltage at the output terminal of the second AC amplifier circuit.

8. The on-chip cryogenic optical interface for the integrated photodetector and noise-cancelling transimpedance amplifier according to claim 7, characterized in that, The output terminal of the first AC amplifier circuit is connected to the output terminal of the second AC amplifier circuit.

9. The on-chip cryogenic optical interface for the integrated photodetector and noise-cancelling transimpedance amplifier according to any one of claims 1-6, characterized in that, The output synthesis stage includes a differential circuit and a current mirror output circuit; The differential circuit converts the voltage of the first output node into a first differential perturbation current signal and the voltage of the second output node into a second differential perturbation current signal. The first differential perturbation current signal and the second differential perturbation current signal are simultaneously injected into the current mirror output circuit to change the voltage of a preset node in the current mirror output circuit. The preset node serves as the output terminal of the output synthesis stage.

10. A cryogenic system for superconducting quantum computing, characterized in that, Includes a cryogenic cavity, a quantum processor located within the cryogenic cavity, and an on-chip cryogenic optical interface as described in any one of claims 1-9; The on-chip cryogenic optical interface is used to receive optical signals and convert the optical signals into the synthesized voltage. The output terminal of the output synthesizer is connected to the signal input terminal of the quantum processor.

Images