A 50% duty cycle symmetric tripler

Abstract

The application relates to the field of integrated circuit design, in particular to a 50% duty cycle symmetric tripler, which is composed of three series-connected ring-shaped gated inverters, the control ends of the three gated inverters are respectively connected with a clock signal CLK, and the output ends of the gated inverters output a frequency-division signal with a frequency of one-third of the CLK and a 50% duty cycle. The scheme designed in the application is used for realizing a 50% duty cycle symmetric tripler circuit, and is easy to realize and has higher precision.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, specifically to a symmetrical frequency divider with a duty cycle of 50%. Background Technology

[0002] In the field of integrated circuit design, the multiphase clock generation module is a key module that determines the sample-and-hold timing performance of the converter. As the core of the clock generation unit, the frequency divider circuit needs to output a clock signal with a specific division ratio and a duty cycle of 50%.

[0003] Traditional crossover circuits, such as Figure 1 As shown, it consists of two D flip-flops and a NAND gate, and the output waveform is as follows. Figure 2 As shown, the output duty cycle is 66.6%. It can achieve a three-way frequency divider function, but it cannot achieve a 50% duty cycle. Traditional three-way frequency dividers often cause the duty cycle to deviate from 50% (e.g., 33.3% or 66.6%), leading to a severe imbalance in sampling and holding times. This timing asymmetry not only causes timing misalignments between pipeline stages but also forces designers to compensate for timing margins by increasing power consumption, reducing system efficiency. In the prior art, other designs, such as the 50% duty cycle continuous integer divider disclosed in CN120320767A, achieve this function by adding additional peripheral circuitry to a traditional continuous integer programmable divider. However, this requires inserting XOR / NOT combinational logic into the clock path, which introduces glitches and circuit redundancy.

[0004] Therefore, there is an urgent need for a symmetrical three-way frequency divider that can accurately achieve a duty cycle of 50%. Summary of the Invention

[0005] In view of this, this application discloses a symmetrical frequency divider with a duty cycle of 50% to solve the duty cycle imbalance problem caused by traditional frequency dividers in multifunctional RF-SOCs in the prior art, including:

[0006] A symmetrical frequency divider with a duty cycle of 50% consists of three gated inverters connected in series in a ring. The control terminals of the three gated inverters are respectively connected to the clock signal CLK, and the output terminals of the gated inverters output a frequency divider signal with a frequency of one-third of CLK and a duty cycle of 50%.

[0007] The gated inverter consists of two PMOS transistors P0 and P0', and two NMOS transistors N0 and N0'. The source of P0' is connected to the power supply, the drain of P0' is connected to the source of P0, the drain of P0 is connected to the drain of N0, the source of N0 is connected to the drain of N0', and the source of N0' is grounded. The gates of P0 and N0 are interconnected, serving as the input (IN) of the gated inverter. The gates of P0' and N0' are interconnected, serving as the control (OE) of the gated inverter. The drain of P0 serves as the output (OUT) of the gated inverter.

[0008] This application provides a symmetrical three-way frequency divider design with a duty cycle of 50%, which can effectively solve the contradiction between three-way frequency division and time symmetry, and eliminate the need for additional power consumption compensation for the ADC. It is easy to implement and has high accuracy, supports flexible three-way frequency division sampling rate, and has good application prospects. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a traditional frequency divider in the prior art;

[0010] Figure 2 This is a schematic diagram of the output waveform of a traditional frequency divider in the prior art;

[0011] Figure 3 This is a schematic diagram of a gated inverter in an embodiment of this application;

[0012] Figure 4 This is a schematic diagram of a symmetrical frequency divider with a 50% duty cycle in an embodiment of this application;

[0013] Figure 5 This is a schematic diagram of the output waveform of a symmetrical frequency divider with a duty cycle of 50% in an embodiment of this application;

[0014] Figure 6 This is a schematic diagram of a differential structure symmetrical frequency divider in an embodiment of this application. Detailed Implementation

[0015] To make the objectives, technical solutions, features, and advantages of this application clearer and to facilitate a better understanding of the technical solutions of this application by those skilled in the art, the following detailed description of this application is provided in conjunction with the accompanying drawings and embodiments.

[0016] Example 1:

[0017] This embodiment includes a symmetrical frequency divider with a duty cycle of 50%, which consists of three gated inverters connected in series. The control terminals of the three gated inverters are respectively connected to the clock signal CLK, and the output terminals of the gated inverters output a frequency divider signal with a frequency of one-third of CLK and a duty cycle of 50%.

[0018] The gated inverter, such as Figure 3 As shown, it consists of two PMOS transistors P0 and P0', and two NMOS transistors N0 and N0'. The source of P0' is connected to the power supply, the drain of P0' is connected to the source of P0, the drain of P0 is connected to the drain of N0, the source of N0 is connected to the drain of N0', and the source of N0' is grounded. The gates of P0 and N0 are interconnected, serving as the input (IN) of the gated inverter. The gates of P0' and N0' are interconnected, serving as the control (OE) of the gated inverter. The drain of P0 serves as the output (OUT) of the gated inverter.

[0019] The truth table of the gated inverter is shown in Table 1. When OE=0, the output will either remain in the previous state or be 1 depending on the input IN. When OE=1, the output will either remain in the previous state or be 0 depending on the input IN.

[0020] Table 1. Truth Table for Gated Inverters

[0021] OUT OE=0 OE=1 IN=0 1 Keep IN=1 Keep 0

[0022] Furthermore, to ensure that the three gated inverters have a defined initial state, the gated inverters are also configured with two NMOS devices N1 and N2 and one PMOS device P1. When RST is '1', nodes X1, X2, and X3 are '0', '1', and '0', respectively.

[0023] Construction as Figure 4 The symmetrical frequency divider with a 50% duty cycle shown includes: three gated inverters, one PMOS transistor P1, and two NMOS transistors N1 and N2. The output of the first gated inverter is connected to the input of the second gated inverter and the drain of N1. The output of the second gated inverter is connected to the input of the third gated inverter and the drain of P1. The output of the third gated inverter is connected to the input of the first gated inverter and the drain of N2. The sources of N1 and N2 are grounded, and their gates receive a reset signal RST. The source of P1 is connected to the power supply, and its gate receives an inverted reset signal RSTN. The control terminals of the first, second, and third gated inverters are connected to the clock signal CLK. The output of the third gated inverter serves as the output terminal CLK_OUT of the symmetrical frequency divider, outputting a frequency-divided signal with a frequency one-third of CLK and a 50% duty cycle.

[0024] Circuit analysis and testing of the above symmetrical frequency divider yielded the following results: Figure 5 The output circuit waveform diagram is shown.

[0025] When RST is '1': the circuit is in a reset state, and nodes X1, X2, and X3 are '0', '1', and '0' respectively.

[0026] When RST is '0':

[0027] At time t0, CLK='0', therefore node X2 must either maintain its previous state '1' or be '1'. Thus, we can determine that node X2 is definitely '1'. Based on the state of node X2, we can deduce that node X3 maintains its previous state '0'. Furthermore, based on the state of node X3, we can deduce that node X1 is definitely '1'.

[0028] At time t1, CLK='1', therefore node X3 either remains in its previous state '0' or is '0', thus we can determine that node X3 must be '0'. Based on the state of node X3, we can deduce that node X1 remains in its previous state '1'. Furthermore, based on the state of node X1, we can deduce that node X2 must be '0'.

[0029] At time t2, CLK='0', therefore node X1 must either remain in its previous state '1' or be '1'. Thus, we can determine that node X1 is definitely '1'. Based on the state of node X1, X2 remains in its previous state '0'. And based on the state of node X2, we can deduce that X1 must be '1'.

[0030] By following this pattern, a three-way frequency divider with a 50% duty cycle can be formed.

[0031] Example 2:

[0032] This embodiment includes a symmetrical three-way frequency divider with a duty cycle of 50%. The difference from Embodiment 1 is that the symmetrical three-way frequency divider with a duty cycle of 50% provided in this embodiment adopts a differential structure.

[0033] like Figure 6 As shown, the differential structure symmetrical divider consists of 6 gated inverters, 6 inverters, 3 PMOS transistors P1~P3, and 3 NMOS transistors N1~N3, wherein:

[0034] The output terminal of the first gated inverter is connected to the input terminal of the second gated inverter and the drain of N1, respectively, as the X1 terminal;

[0035] The output of the second gated inverter is connected to the input of the third gated inverter and the drain of P1, respectively, as the X2 terminal;

[0036] The output terminal of the third gated inverter is connected to the input terminal of the first gated inverter and the drain of N2, respectively, as the X3 terminal;

[0037] The output of the fourth gated inverter is connected to the input of the fifth gated inverter and the drain of P2, respectively, as the X1N terminal;

[0038] The output of the fifth gate inverter is connected to the input of the sixth gate inverter and the drain of N3, respectively, as the X2N terminal;

[0039] The output of the sixth gate inverter is connected to the input of the fourth gate inverter and the drain of P3, respectively, as the X3N terminal;

[0040] Six inverters are grouped in pairs, with the input and output terminals of the two inverters in each group connected to each other to form a bistable latch; three bistable latches are arranged sequentially between X1 and X1N, X2 and X2N, and X3 and X3N.

[0041] The sources of N1, N2, and N3 are grounded, and their gates receive the reset signal RST.

[0042] The sources of P1, P2, and P3 are connected to the power supply terminal, and their gates receive the inverted reset signal RSTN.

[0043] The control terminals of the first, second, and third gated inverters are connected to the clock signal CLK, respectively; the control terminals of the fourth, fifth, and sixth gated inverters are connected to the inverted clock signal CLKN, respectively.

[0044] Finally, it should be noted that the above description only depicts some embodiments of this application. For those skilled in the art, various changes, modifications, substitutions, and variations can be conceived of these embodiments without departing from the principles and spirit of this application. The scope of protection of this application is defined by the appended claims and their equivalents, and all the above-mentioned behaviors should be covered within the scope of protection of this application.

[0045] Furthermore, in the above description of the embodiments, unless otherwise explicitly specified and limited, if the terms "upper," "lower," "horizontal," "inner," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the invention is usually placed during use, they are only for the convenience of describing this application and simplifying the description, and do not limit or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application; if the terms "first," "second," etc., appear, they are only used to distinguish the description and should not be construed as indicating or implying relative importance. The components shown and described in the accompanying drawings and embodiments can be arranged and designed in various different configurations. The term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. "Horizontal" simply means that its direction is more horizontal than "vertical," not that the structure must be completely horizontal, but rather that it can be slightly tilted. The terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

Claims

1. A symmetrical frequency divider with a duty cycle of 50%, characterized in that, It consists of three gated inverters connected in series in a ring. The control terminals of the three gated inverters are respectively connected to the clock signal CLK. The output terminal of the gated inverter outputs a frequency-divided signal with a frequency of one-third of CLK and a duty cycle of 50%.

2. The symmetrical frequency divider with a duty cycle of 50% according to claim 1, characterized in that, The gated inverter is composed of two PMOS transistors P0 and P0', and two NMOS transistors N0 and N0'; wherein, the source of P0' is connected to the power supply terminal, the drain of P0' is connected to the source of P0, the drain of P0 is connected to the drain of N0, the source of N0 is connected to the drain of N0', and the source of N0' is grounded. The gates of P0 and N0 are interconnected, serving as the input terminal IN of the gated inverter; The gates of P0' and N0' are interconnected, serving as the control terminal OE of the gated inverter; The drain of P0 serves as the output terminal OUT of the gated inverter.

3. The symmetrical frequency divider with a duty cycle of 50% according to claim 2, characterized in that, The gated inverter is also equipped with two NMOS devices N1 and N2 and one PMOS device P1 to ensure that the gated inverter has a defined initial state.

4. The symmetrical frequency divider with a duty cycle of 50% according to claim 2, characterized in that, The symmetrical frequency divider consists of three gated inverters, one PMOS transistor P1, and two NMOS transistors N1 and N2, wherein: The output of the first gated inverter is connected to the input of the second gated inverter and the drain of N1, respectively. The output of the second gated inverter is connected to the input of the third gated inverter and the drain of P1, respectively. The output of the third gated inverter is connected to the input of the first gated inverter and the drain of N2, respectively. The sources of N1 and N2 are grounded, and their gates receive the reset signal RST. The source of P1 is connected to the power supply terminal, and the gate receives the inverted reset signal RSTN. The control terminals of the first gated inverter, the second gated inverter, and the third gated inverter are respectively connected to the clock signal CLK; The output of the third gated inverter is used as the output of the symmetrical frequency divider CLK_OUT, which outputs a frequency divider signal with a frequency of one-third of CLK and a duty cycle of 50%.

5. The symmetrical frequency divider with a duty cycle of 50% according to claim 2, characterized in that, The symmetrical three-way frequency divider adopts a differential structure.

6. The symmetrical frequency divider with a duty cycle of 50% according to claim 5, characterized in that, The differential symmetrical frequency divider consists of 6 gated inverters, 6 inverters, 3 PMOS transistors P1~P3, and 3 NMOS transistors N1~N3, wherein: The output terminal of the first gated inverter is connected to the input terminal of the second gated inverter and the drain of N1, respectively, as the X1 terminal; The output of the second gated inverter is connected to the input of the third gated inverter and the drain of P1, respectively, as the X2 terminal; The output terminal of the third gated inverter is connected to the input terminal of the first gated inverter and the drain of N2, respectively, as the X3 terminal; The output of the fourth gated inverter is connected to the input of the fifth gated inverter and the drain of P2, respectively, as the X1N terminal; The output of the fifth gate inverter is connected to the input of the sixth gate inverter and the drain of N3, respectively, as the X2N terminal; The output of the sixth gate inverter is connected to the input of the fourth gate inverter and the drain of P3, respectively, as the X3N terminal; Six inverters are grouped in pairs, with the input and output terminals of the two inverters in each group connected to each other to form a bistable latch; three bistable latches are arranged sequentially between X1 and X1N, X2 and X2N, and X3 and X3N. The sources of N1, N2, and N3 are grounded, and their gates receive the reset signal RST. The sources of P1, P2, and P3 are connected to the power supply terminal, and their gates receive the inverted reset signal RSTN. The control terminals of the first, second, and third gated inverters are connected to the clock signal CLK, respectively; the control terminals of the fourth, fifth, and sixth gated inverters are connected to the inverted clock signal CLKN, respectively.

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