Digital modulation signal generation method and system

Abstract

The embodiment of the present disclosure discloses a digital modulation signal generation method and system. The method comprises: acquiring a main clock, obtaining PN code order bits, a primitive polynomial, initial values of a current state value, an output bit width, a bit mask and an enable signal at the rising edge thereof; when the enable signal is at a valid level, converting the primitive polynomial coefficient into a matrix and iterating the output bit width times to obtain a parameter storage matrix; performing state recursion on the current state value based on the matrix and the bit mask to obtain a feedback value vector, and updating the current state value based on the vector under the driving of a BIT clock; and based on the comparison result of the PN code order bits and the output bit width, intercepting valid bits from the updated state value as parallel output to obtain a PN sequence, thereby generating a digital modulation signal for communication test of a wideband receiver. The method converts the PN sequence generation from serial bit-by-bit recursion to parallel multi-bit shift, and the symbol rate is no longer limited by the bit generation rate, supporting high symbol rate and large bandwidth signal output.

Description

Technical Field

[0001] This disclosure relates to the field of digital communication technology, and in particular to a method and system for generating digital modulated signals. Background Technology

[0002] In receiver testing, the vector signal source needs to generate a PN sequence (pseudo-random sequence) through an internal PN sequence generator, and then output a digital modulated signal after modulation for receiver bit error rate statistics and demodulation performance verification.

[0003] Traditional digital modulation signal generation methods use PN sequence generators based on LFSR (linear feedback shift register) with a serial structure, outputting only 1 bit of data per clock cycle.

[0004] However, in the serial structure, the PN code generation rate is locked by the master clock, which results in the symbol rate of higher-order modulation being much lower than that of the master clock. For example, the maximum symbol rate of 256QAM under a 100MHz clock is only 12.5MHz, which cannot meet the current high-speed broadband receiver's testing requirements for large bandwidth and high symbol rate digital modulation signals, becoming the core bottleneck restricting equipment performance. Summary of the Invention

[0005] In view of this, the present disclosure provides a digital modulation signal generation method and system that can transform the generation of PN sequences from serial bit-by-bit recursion to parallel multi-bit shifting, increasing the number of output bits per cycle to several times the original output bit width, enabling multiple bits required for high-order modulation to be provided in parallel, no longer limited by the bit generation rate, thereby supporting the output of high symbol rate, large bandwidth digital modulation signals and meeting the testing requirements of high-speed broadband receivers.

[0006] In a first aspect, embodiments of this disclosure provide a method for generating a digital modulated signal, employing the following technical solution: Get the master clock; At the rising edge of the master clock, the operating parameters are acquired; wherein, the operating parameters include the number of PN code order bits, primitive polynomial, initial value, output bit width, bit mask and enable signal; When the enable signal is at an active level, the coefficients of the primitive polynomial are converted into an active bit marker matrix. Perform iterative operations on the effective bit marker matrix to obtain a parameter storage matrix; wherein, the number of iterations is equal to the output bit width; Using the initial value as the starting value of the current state value, and based on the parameter storage matrix and the bit mask, the current state value is recursively processed to obtain the feedback value vector; Driven by the BIT clock, the current state value is updated based on the feedback value vector to obtain the updated state value; Based on the comparison result between the PN code order bits and the output bit width, valid bits are extracted from the updated state value as parallel output to obtain a PN sequence that conforms to the output bit width; Based on the PN sequence, a digital modulation signal is generated for communication testing of a broadband receiver.

[0007] Optionally, when the enable signal is active, converting the coefficients of the primitive polynomial into an effective bit-stamp matrix includes: When the enable signal is active, a two-dimensional matrix is ​​initialized; wherein the number of rows and columns of the two-dimensional matrix are both equal to N, and N is the maximum output bit width that can support PN sequences; Iterate through each coefficient of the primitive polynomial; If the coefficient of the i-th term is 1, then all elements in the i-th row of the two-dimensional matrix are set to 1; If the coefficient of the i-th term is 0, then all elements in the i-th row of the two-dimensional matrix are set to 0; After the traversal is complete, the two-dimensional matrix is ​​used as the valid bit marker matrix.

[0008] Optionally, performing iterative operations on the effective bit marker matrix to obtain the parameter storage matrix includes: Initialize an identity matrix as the initial value of the parameter storage matrix; wherein the number of rows and columns of the identity matrix are both equal to N, and N is the maximum output bit width that can support PN sequences; In each iteration, each row of the current parameter storage matrix is ​​bitwise ANDed with the row number of the corresponding row in the effective bit tag matrix, and then modulo-2 addition is performed on all bitwise AND results. Shift the current parameter storage matrix down one row, and fill the first row that is now empty after the shift with the result of the modulo-2 addition operation. When the number of iterations equals the output bit width, the current parameter storage matrix is ​​used as the final parameter storage matrix.

[0009] Optionally, the step of using the initial value as the starting value of the current state value, and performing state recursion on the current state value based on the parameter storage matrix and the bit mask to obtain a feedback value vector includes: At the rising edge of the enable signal, the initial value is loaded into the shift register as the current state value of the shift register; the number of bits in the shift register is equal to N. At the rising edge of the BIT clock, each row of the parameter storage matrix is ​​bitwise ANDed with the current state value and the bitmask, and the bitwise AND results of each row are XORed and reduced to obtain the feedback value corresponding to each row. The feedback values ​​of each row constitute the feedback value vector.

[0010] Optionally, updating the current state value based on the feedback value vector under BIT clock driving to obtain the updated state value includes: At the rising edge of the BIT clock, the current state value is shifted towards the higher bit of the shift register, and the number of bits shifted is equal to the output bit width. Discard the high-order bits that are shifted out, and fill the empty low-order bits with the low-order bits of the feedback value vector.

[0011] Optionally, the step of extracting valid bits from the updated state value as parallel output based on the comparison result of the PN code order bits and the output bit width to obtain a PN sequence conforming to the output bit width includes: When the number of bits of the PN code order is greater than the output bit width, the consecutive bits of the updated state value starting from the number of bits of the PN code order are taken as valid output, the number of consecutive bits is equal to the output bit width, the valid output is taken as the low bit of the PN sequence, and the high bit of the PN sequence is padded with zeros. When the number of bits of the PN code order is not greater than the output bit width, the consecutive bits of the update state value starting from the least significant bit are taken as the valid output, the number of consecutive bits is equal to the output bit width, the valid output is taken as the low bit of the PN sequence, and the high bits of the PN sequence are padded with zeros.

[0012] Optionally, the digital modulation signal generation method further includes: When the operating parameters remain unchanged, the updated state value is used as the current state value for the next round of state recursion. The steps of state recursion, state update, and output interception are repeated until the enable signal becomes invalid, and a PN sequence that conforms to the output bit width is continuously output.

[0013] Secondly, this disclosure also provides a digital modulation signal generation system, the system including a parameter configuration unit, a matrix operation unit, a feedback calculation unit, a shift register, an output selection unit, and a modulation unit; The parameter configuration unit is used to acquire the master clock; and to acquire the operating parameters at the rising edge of the master clock; wherein the operating parameters include the number of PN code order bits, primitive polynomial, initial value, output bit width, bit mask and enable signal; When the enable signal is at an active level, the coefficients of the primitive polynomial are converted into an active bit marker matrix. The matrix operation unit is used to perform iterative operations on the effective bit marker matrix to obtain a parameter storage matrix; wherein the number of iterations is equal to the output bit width; The feedback calculation unit is used to take the initial value as the starting value of the current state value, and perform state recursion on the current state value based on the parameter storage matrix and the bit mask to obtain the feedback value vector. The shift register is used to update the current state value based on the feedback value vector under the BIT clock drive, and obtain the updated state value. The output selection unit is used to extract valid bits from the updated state value as parallel output based on the comparison result between the PN code order bits and the output bit width, so as to obtain a PN sequence that conforms to the output bit width. The modulation unit is used to generate a digital modulation signal for communication testing of a broadband receiver based on the PN sequence.

[0014] Optionally, the parameter configuration unit is specifically used to initialize a two-dimensional matrix when the enable signal is at an active level; wherein the number of rows and columns of the two-dimensional matrix are both equal to N, and N is the maximum output bit width that can support PN sequences; Iterate through each coefficient of the primitive polynomial; If the coefficient of the i-th term is 1, then all elements in the i-th row of the two-dimensional matrix are set to 1; If the coefficient of the i-th term is 0, then all elements in the i-th row of the two-dimensional matrix are set to 0; After the traversal is complete, the two-dimensional matrix is ​​used as the valid bit marker matrix.

[0015] Optionally, the matrix operation unit is specifically used to initialize an identity matrix as the initial value of the parameter storage matrix; wherein the number of rows and columns of the identity matrix are both equal to N, and N is the maximum output bit width that can support PN sequences; In each iteration, each row of the current parameter storage matrix is ​​bitwise ANDed with the row number of the corresponding row in the effective bit tag matrix, and then modulo-2 addition is performed on all bitwise AND results. Shift the current parameter storage matrix down one row, and fill the first row that is now empty after the shift with the result of the modulo-2 addition operation. When the number of iterations equals the output bit width, the current parameter storage matrix is ​​used as the final parameter storage matrix.

[0016] Optionally, the feedback calculation unit is specifically used to load the initial value into the shift register at the rising edge of the enable signal, as the current state value of the shift register; the number of bits in the shift register is equal to N; At the rising edge of the BIT clock, each row of the parameter storage matrix is ​​bitwise ANDed with the current state value and the bitmask, and the bitwise AND results of each row are XORed and reduced to obtain the feedback value corresponding to each row. The feedback values ​​of each row constitute the feedback value vector.

[0017] Optionally, the shift register is specifically used to shift the current state value towards the higher bit direction of the shift register at the rising edge of the BIT clock, and the number of bits shifted is equal to the output bit width; Discard the high-order bits that are shifted out, and fill the empty low-order bits with the low-order bits of the feedback value vector.

[0018] Optionally, the output selection unit is specifically used to take consecutive bits of the updated state value starting from the number of bits of the PN code order as valid output when the number of bits of the PN code order is greater than the output bit width, take the valid output as the low bit of the PN sequence, and pad the high bit of the PN sequence with zeros. When the number of bits of the PN code order is not greater than the output bit width, the consecutive bits of the update state value starting from the least significant bit are taken as the valid output, the number of consecutive bits is equal to the output bit width, the valid output is taken as the low bit of the PN sequence, and the high bits of the PN sequence are padded with zeros.

[0019] Optionally, the shift register is further configured to output the updated state value as the current state value for the next round of state recursion to the feedback calculation unit when the operating parameters remain unchanged. The feedback calculation unit, the shift register, and the output selection unit cyclically perform state recursion, state update, and output truncation until the enable signal becomes invalid, and continuously output a PN sequence that conforms to the output bit width.

[0020] Optionally, the system further includes a host computer; The host computer is used to configure the operating parameters and send the operating parameters to the parameter configuration unit.

[0021] Thirdly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform any of the digital modulation signal generation methods described above.

[0022] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions for causing a computer to perform any of the digital modulation signal generation methods described above.

[0023] Fifthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0024] The digital modulation signal generation method provided in this disclosure converts the primitive polynomial into a valid bit marker matrix and performs iterative operations on the matrix with the same number of iterations as the output bit width to obtain a parameter storage matrix. This transforms the recursive rule of advancing one step per clock cycle in serial PN sequence generation into an equivalent mapping rule of advancing the output bit width by one step per hour using the parameter storage clock cycle. Based on this parameter storage matrix and bit mask, state recursion is performed on the current state value, allowing multiple feedback values ​​to be obtained simultaneously within a single bit clock cycle. This enables parallel updates of the current state value, completing multiple state recursions that would require multiple clock cycles in a traditional scheme within one clock cycle. Furthermore, valid bits are extracted from the updated state value as parallel outputs, resulting in the output of a multi-bit PN sequence in each bit clock cycle. At the same system clock frequency, the output rate of the PN sequence is increased from the traditional 1 bit / clock to output bit width / clock, representing a multiple of the original output bit width. Meanwhile, users can generate PN sequences with arbitrary polynomials and output bit widths without redesigning hardware by configuring operating parameters such as the number of PN code order bits, primitive polynomials, and output bit width, significantly improving the flexibility and applicability of the PN sequence generator. This parallel-generated PN sequence provides a high symbol rate bit source for digital modulation signals, enabling them to support high symbol rate outputs for higher-order modulation, thus meeting the testing requirements of broadband receivers for large-bandwidth, high-symbol-rate modulation signals.

[0025] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of a conventional vector signal source employing a serial PN code generation architecture, provided for embodiments of this disclosure; Figure 2 A schematic flowchart illustrating the digital modulation signal generation method provided in this embodiment of the disclosure; Figure 3 A flowchart illustrating the primitive polynomial coefficient transformation method provided in this embodiment of the disclosure; Figure 4 A flowchart illustrating the parameter storage matrix acquisition method provided in this embodiment of the disclosure; Figure 5 A flowchart illustrating the state recursion method provided in this embodiment of the disclosure; Figure 6 A flowchart illustrating the method for updating the current state value provided in this embodiment of the disclosure; Figure 7 A flowchart illustrating the parallel output method provided in this embodiment of the disclosure; Figure 8 This is a block diagram illustrating the principle of a digital modulation signal generation system provided in an embodiment of this disclosure. Detailed Implementation

[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0029] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0030] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0031] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0033] In wireless communication receiver performance testing scenarios, the core testing equipment is a vector signal generator. This generator outputs a standard modulated radio frequency signal to simulate signals from communication transmitters such as base stations, terminals, and satellites. This signal is then connected to the receiver under test (DUT) to verify various receiver performance metrics. Typical testing requirements include receiver sensitivity, demodulation error vector amplitude (EVM), bit error rate (BER), carrier synchronization, frame synchronization, and high-order modulation and demodulation performance. Among these, BER testing and demodulation performance testing are core test items that require the injection of a standard pseudo-random (PN) bit stream.

[0034] During the test, the PN sequence generator inside the vector signal source generates a pseudo-random raw bit data stream. The bit stream is mapped to the corresponding modulation symbols (BPSK / QPSK / 64QAM / 256QAM, etc.). After shaping filtering and carrier modulation, the RF modulation signal is generated and input to the receiver under test. The receiver demodulates and restores the bits, compares them with the PN sequence of the transmitter, and counts the bit error rate and demodulation accuracy to determine the receiver performance.

[0035] Reference Figure 1The diagram illustrates the principle block diagram of an existing vector signal source employing a serial PN code generation architecture. Its signal generation process is as follows: a PN sequence generator generates a raw bit stream serially, outputting 1 bit per master clock cycle; a serial-to-parallel conversion module groups the serial bit stream according to modulation order (e.g., 4 bits per group for 16QAM, 8 bits per group for 256QAM), converting it into parallel symbol data; a symbol mapping module maps each group of bits to the corresponding modulation symbol; and finally, after shaping filtering and carrier modulation, an RF signal is generated and output. In this scheme, the PN sequence generator and the serial-to-parallel conversion module are cascaded together to jointly complete the conversion from raw bits to modulation symbols, providing a data source for subsequent signal modulation.

[0036] In this serial architecture, the bit generation rate of the PN code is completely synchronized and locked to the master clock. The two rates are strictly equal, and there is no independent frequency division or multiplication mechanism, making the serial-to-parallel conversion module a performance bottleneck. In digital modulation, the number of bits carried by one modulation symbol is determined by the modulation order. The symbol rate = PN bit generation rate ÷ number of bits per symbol. Therefore, the higher the modulation order, the lower the maximum output symbol rate under the same clock frequency. Taking a fixed master clock of 100MHz as an example, a 256QAM symbol carries 8 bits, and the maximum symbol rate is only 100MHz ÷ 8 = 12.5MHz.

[0037] When testing key performance indicators of a user's receiver, such as high-speed data stream reception and wideband demodulation performance, a vector signal source is required to provide a high-symbol-rate, high-order modulation signal. However, existing serial architectures have a hard rate limit, severely compressing the symbol rate of high-order modulation. The output modulation signal bandwidth and symbol rate cannot match the testing requirements of next-generation wideband receivers for high-bandwidth, high-symbol-rate modulation signals, becoming a core bottleneck restricting equipment performance.

[0038] To address the aforementioned problems, this disclosure provides a method for generating digital modulated signals, referring to... Figure 2 This includes the following steps: S1: Get the master clock; S2: At the rising edge of the master clock, obtain the operating parameters; among which, the operating parameters include the number of PN code order bits, primitive polynomial, initial value, output bit width, bit mask and enable signal; S3: When the enable signal is at an active level, convert the coefficients of the primitive polynomial into an active bit marker matrix; S4: Perform iterative operations on the effective bit marker matrix to obtain the parameter storage matrix; where the number of iterations is equal to the output bit width; S5: Using the initial value as the starting value of the current state value, and based on the parameter storage matrix and bit mask, perform state recursion on the current state value to obtain the feedback value vector; S6: Driven by the BIT clock, update the current state value based on the feedback value vector and obtain the updated state value; S7: Based on the comparison result between the PN code order bits and the output bit width, extract the valid bits from the updated state value as parallel output to obtain the PN sequence that conforms to the output bit width; S8: Based on the PN sequence, generate a digital modulation signal for communication testing of a broadband receiver.

[0039] The digital modulation signal generation method disclosed herein transforms the primitive polynomial into a valid bit marker matrix and performs iterative operations on this matrix with the same number of output bit widths to obtain a parameter storage matrix. This converts the recursive rule of advancing one step per clock cycle in serial PN sequence generation into an equivalent mapping rule that advances the output bit width by one step per clock cycle. Based on this parameter storage matrix and bit mask, state recursion is performed on the current state value, allowing multiple feedback values ​​to be obtained simultaneously within a single bit clock cycle. This enables parallel updates of the current state value, completing multiple state recursions that would require multiple clock cycles in traditional schemes within a single clock cycle. Furthermore, valid bits are extracted from the updated state value as parallel outputs, enabling the output of a multi-bit PN sequence in each bit clock cycle.

[0040] At the same system clock frequency, the output rate of the PN sequence is increased from the traditional 1 bit / clock to the output bit width / clock, a boost of several times the original output bit width. Simultaneously, users can generate PN sequences with arbitrary polynomials and output bit widths without redesigning hardware by configuring operating parameters such as the PN code order, primitive polynomial, and output bit width, significantly improving the flexibility and applicability of the PN sequence generator. This parallel-generated PN sequence provides a high symbol rate bit source for digital modulation signals, enabling them to support high symbol rate outputs for higher-order modulation, thus meeting the testing requirements of broadband receivers for large-bandwidth, high-symbol-rate modulation signals.

[0041] In S1, a dual-clock architecture is adopted, consisting of a master clock (also known as the system clock) and a BIT (Binary digIT) clock. Both the master clock and the BIT clock are clock signals continuously output by the clock module. The master clock is used for synchronous control and configuration operations, while the BIT clock is used for synchronous bit stream processing.

[0042] In S2, the user configures the operating parameters according to actual needs. At the rising edge of the master clock, it detects whether new operating parameters have been written. If so, a new set of operating parameters is acquired and stored in the configuration register inside the FPGA (Field-Programmable Gate Array). The acquired operating parameters and the bit clock are then combined to execute the subsequent parallel generation process of the PN sequence. The method of detecting new operating parameters at the rising edge of the master clock ensures timely response to configuration updates, guaranteeing that parameter changes take effect immediately in the next master clock cycle. Furthermore, the fixed master clock frequency, using it as the detection reference, avoids timing conflicts between parameter writing and internal state updates.

[0043] Regarding the operating parameters, the PN code order (ORDER) determines the number of stages in the shift register, which in turn determines the period length of the PN sequence, with a maximum period of 2. ORDER-1 The primitive polynomial (FPOLY) specifies the feedback tap position in the form of a coefficient vector, defining the generation rules and code pattern of the PN sequence; the initial value (INIT_STATE) is the initial value of the shift register before the PN sequence generator starts, determining from which state the PN sequence begins to evolve; the output bit width (OUT_WIDTH) specifies the number of bits output in parallel during the BIT clock cycle, determining the parallelism of the PN sequence generator; the bit mask (BIT_MASK) is used to specify which bits in the configuration register are valid, serving as a filtering switch during data writing; the enable signal (ENABLE) is used to control the start and stop of the PN sequence generator, starting the generator when it is valid and maintaining the same state when it is invalid.

[0044] In S3, refer to Figure 3 The flowchart illustrating the primitive polynomial coefficient conversion method shows that "when the enable signal is at an active level, converting the coefficients of each term of the primitive polynomial into an active bit marker matrix" includes the following steps: S31: When the enable signal is active, initialize a two-dimensional matrix; where the number of rows and columns of the two-dimensional matrix are both equal to N, and N is the maximum output bit width that can support PN sequences; S32: Iterate through the coefficients of each term in the primitive polynomial. If the coefficient of the i-th term is 1, set all elements in the i-th row of the two-dimensional matrix to 1. If the coefficient of the i-th term is 0, set all elements in the i-th row of the two-dimensional matrix to 0. S33: After traversal, use the two-dimensional matrix as the valid bit marker matrix.

[0045] The two-dimensional matrix is ​​an N×N matrix.

[0046] In S32, each bit of the primitive polynomial is traversed from least significant bit to most significant bit, with a traversal count of i, where i represents the current term x of the primitive polynomial.i The order of the polynomial is given by i, which ranges from 0 to N-1. Extract the coefficient of the i-th term of the primitive polynomial. The i-th bit of the binary number is FPOLY[i]. If FPOLY[i] = 1, then set all N elements in the i-th row of the two-dimensional matrix to 1; if FPOLY[i] = 0, then set all N elements in the i-th row of the two-dimensional matrix to 0.

[0047] In S33, after the traversal is completed, an N×N effective bit marker matrix FPOLY_MATRIX is obtained. This matrix is ​​used to mark which terms of the order in the primitive polynomial participate in the state recursion. When the i-th row of the matrix is ​​all 1, it means that the i-th term of the primitive polynomial participates in the state recursion; when the i-th row is all 0, it means that the i-th term of the primitive polynomial does not participate in the state recursion.

[0048] The key to primitive polynomials is the coefficient of each term, which can only be 0 or 1. Hardware cannot directly analyze primitive polynomials (such as x). 8 +x 4 The primitive polynomial (+x³+x+1) is transformed into a matrix format that can be directly looked up and operated on by hardware and stored in the configuration register inside the FPGA, laying the data structure foundation for subsequent iterative operations and state recursion.

[0049] In S4, refer to Figure 4 The flowchart illustrating the method for obtaining the parameter storage matrix shows that "performing iterative operations on the valid bit marker matrix to obtain the parameter storage matrix" includes the following steps: S41: Initialize an identity matrix as the initial value of the parameter storage matrix; where the number of rows and columns of the identity matrix are both equal to N; S42: In each iteration, perform a bitwise AND operation between each row of the current parameter storage matrix and the row with the corresponding row number in the effective bit tag matrix, and then perform a modulo-2 addition operation on all bitwise AND results; S43: Shift the current parameter storage matrix down one row and fill the first row after the shift with the result of the modulo-2 addition operation; S44: When the number of iterations equals the output bit width, use the current parameter storage matrix as the final parameter storage matrix.

[0050] In S41, the identity matrix is ​​preset and stored in the FPGA's internal configuration register. The identity matrix I_MATRIX is an N×N matrix with 1s on the diagonal and 0s elsewhere. It is used as the initial value of the parameter storage matrix RAM_MATRIX. Taking 32x32 as an example, the storage format is as follows: RAM_MATRIX[0] = 32'b000000000000000000000000000000001 RAM_MATRIX[1] = 32'b000000000000000000000000000000010 RAM _MATRIX[2] = 32'b000000000000000000000000000000100 … In S42, each row vector RAM_MATRIX[i] of the current parameter storage matrix RAM_MATRIX is bitwise ANDed with each row vector FPOLY_MATRIX[i] of the effective bit marker matrix FPOLY_MATRIX: T_MATRIX[i] = RAM_MATRIX[i] & FPOLY_MATRIX[i], to obtain the effective bit row vector. A bitwise XOR (modulo-2 addition) operation is performed on each effective bit row vector T_MATRIX[i]: TEMP = T_MATRIX[0] ⊕ T_MATRIX[1] ⊕ … ⊕ T_MATRIX[N-1], to obtain the N-bit row vector TEMP.

[0051] In S43, the current parameter storage matrix RAM_MATRIX is shifted down one row: RAM_MATRIX[1]=I_MATRIX[0], RAM_MATRIX[2]=I_MATRIX[1], ..., RAM_MATRIX[N-1]=I_MATRIX[N-2], and the first row RAM_MATRIX[0] is filled with the N-bit row vector TEMP, i.e. RAM_MATIX[0]=TEMP.

[0052] In step S44, the output bit width is W. Steps S42 and S43 are repeated for a total of W iterations. After the iterations are complete, the final parameter storage matrix RAM_MATRIX is obtained, which is essentially an equivalent mapping matrix for pushing W steps. In PN sequence generation, pushing one step means updating the state of the shift register once. In the traditional serial scheme, only one step can be pushed per clock cycle, outputting one bit. Assuming the output bit width W=8, in the parallel scheme, 8 state updates need to be completed in one clock cycle, i.e., pushing 8 steps. In order to calculate the complete state after pushing 8 steps at once, the rule for pushing one step (i.e., the effective bit mark matrix) needs to be applied repeatedly 8 times in advance and merged into an equivalent mapping matrix. This matrix describes the state mapping relationship after pushing 8 steps directly from the current state.

[0053] In S5, refer to Figure 5 The flowchart illustrating the state recursion method shows the following steps: "Using the initial value as the starting value of the current state value, and based on the parameter storage matrix and bit mask, performing state recursion on the current state value to obtain the feedback value vector": S51: On the rising edge of the enable signal, the initial value is loaded into the shift register as the current state value of the shift register; the number of bits in the shift register is equal to N; S52: At the rising edge of the BIT clock, perform a bitwise AND operation on each row of the parameter storage matrix with the current state value and the bit mask, and perform XOR reduction on the bitwise AND results of each row to obtain the feedback value corresponding to each row. The feedback values ​​of each row constitute the feedback value vector.

[0054] In S51, at the rising edge of the enable signal, the initial value INIT_STATE is loaded into the N-bit shift register PN_DATA_SHIFT to set the starting state for the PN sequence generator, such that PN_DATA_SHIFT[N-1:0] = INIT_STATE[N-1:0], ensuring that the sequence evolves from the specified position, thereby guaranteeing the repeatability and determinism of the generated PN sequence.

[0055] In S52, at the rising edge of the BIT clock, each row vector of the parameter storage matrix RAM_MATRIX is traversed. That is, for i=0,1,...,N-1, the i-th row vector of the parameter storage matrix RAM_MATRIX is bitwise ANDed with the current state value and the bit mask. The bitwise AND result of the i-th row is then XORed (all bits are XORed) to obtain the feedback value FB_MATRIX[i] of the i-th row, which is a 1-bit value. The formula for this step is: FB_MATRIX[i]=⋁^(RAM_MATRIX[i]&PN_DATA_SHIFT&BIT_MASK), where ⋁^ represents the XOR reduction operation, that is, XORing all bits: ⋁^(a[N-1:0])=a[N-1]⊕a[N-2]⊕...⊕a[1]⊕a[0], where a[i] represents the i-th bit of vector a.

[0056] After the traversal is complete, an N-bit feedback value vector FB_MATRIX is obtained, which is latched on the rising edge of the BIT clock for use in the next step of updating the shift register.

[0057] The effective bit marker matrix indicates which terms of the primitive polynomial participate in the feedback. Rows with all 1s correspond to participating bits, while rows with all 0s correspond to non-participating bits. After W iterations, this matrix is ​​converted into a parameter storage matrix, which is essentially an equivalent mapping rule for W steps of iteration. Therefore, although the effective bit marker matrix is ​​not directly used for state recursion, iterative operations extend the feedback rules it carries into an equivalent mapping suitable for parallel output, thereby indirectly guiding the state recursion process. This allows W feedback values ​​to be calculated in parallel at the rising edge of the bit clock, based on the current state value, completing W steps of state recursion and achieving the effect of parallel outputting a W-bit PN sequence every bit clock cycle.

[0058] In S6, refer to Figure 6 The flowchart illustrating the method for updating the current state value, "driven by the BIT clock, updates the current state value based on the feedback value vector to obtain the updated state value," includes the following steps: S61: On the rising edge of the BIT clock, shift the current state value towards the higher bit of the shift register, with the number of bits shifted equal to the output bit width; S62: Discard the high-order bits that have been shifted out, and fill the empty low-order bits with the low-order bits of the feedback value vector.

[0059] In S51 and S52, at the rising edge of the BIT clock, a W-bit parallel shift is performed, shifting the current value of PN_DATA_SHIFT to the left by W bits (left is the direction of high bits), discarding the high bits, i.e., PN_DATA_SHIFT[N-1:W]=PN_DATA_SHIFT[N-1-W:0]. The lower W bits of FB_MATRIX are filled into the lower W bits vacated after the left shift. After the assignment is completed, PN_DATA_SHIFT stores the state value of the next BIT clock cycle, i.e., PN_DATA_SHIFT[i]=FB_MATRIX[i], i=0,1,...,N-1.

[0060] When the next rising edge of the BIT clock arrives, the updated PN_DATA_SHIFT is set to PN_DATA_SHIFT[N-1-W:0] and FB_MATRIX[W-1:0]. PN_DATA_SHIFT is N bits, which are used for the next round of feedback calculation and for the current PN sequence output.

[0061] In S7, refer to Figure 7 The flowchart illustrating the parallel output method, which states that "based on the comparison between the PN code order bits and the output bit width, valid bits are truncated from the updated state value as parallel output to obtain a PN sequence that conforms to the output bit width," includes the following steps: S71: When the number of bits of the PN code order is greater than the output bit width, take the consecutive bits of the update status value starting from the number of bits of the PN code order as the valid output. The number of consecutive bits is equal to the output bit width. The valid output is taken as the low bit of the PN sequence, and the high bit of the PN sequence is padded with zeros. S72: When the number of bits of the PN code order is not greater than the output bit width, take the consecutive bits of the update status value starting from the least significant bit as the valid output. The number of consecutive bits is equal to the output bit width. The valid output is used as the low bit of the PN sequence, and the high bits of the PN sequence are padded with zeros.

[0062] In S71, when ORDER > W, the W bits of PN_DATA_SHIFT (starting from the ORDER-1 bit) are taken as valid output, and the high bits are padded with 0. The expression is: PN_DATA_OUT[N-1:0]={ZEROS(NW),PN_DATA_SHIFT[(ORDER-1)-:W]}. The unused ORDER-OUT_WIDTH bits (i.e. the low ORDER-W bits: PN_DATA_SHIFT[ORDER-W-1:0]) are retained in PN_DATA_SHIFT and transferred to the next output through the shift register to participate in the next round of state update.

[0063] In S72, when ORDER≤W, the lower W bits of PN_DATA_SHIFT are taken as valid output, and the higher bits are padded with 0. The expression is: PN_DATA_OUT[N-1:0]={ZEROS(NW),PN_DATA_SHIFT[W-1:0]}. When the bit width of the PN sequence is equal to the output bit width (ORDER=W), the number of higher bits padded with 0 is 0. PN_DATA_OUT is all N bits of PN_DATA_SHIFT.

[0064] The lower W bits of PN_DATA_OUT are the W-bit PN sequence output in parallel during the current BIT clock cycle. If the parameter configuration unit does not detect any new operating parameters, while the operating parameters remain unchanged, the updated state value is used as the current state value for the next round of state recursion. The steps of state recursion, state update, and output truncation (i.e., steps S4-S6) are repeated until the enable signal becomes invalid, and the PN sequence that conforms to the output bit width is continuously output.

[0065] In S8, the parallel output W-bit PN sequence is directly mapped to modulation symbols. After shaping filtering and carrier modulation, an RF digital modulation signal is generated and output to a broadband receiver for bit error rate statistics and demodulation performance verification.

[0066] This solution is applied to vector signal sources. The PN sequence generator serves as the baseband data source for the vector signal source, providing the raw bit stream for subsequent transmission link steps such as symbol mapping, shaping filtering, and carrier modulation. Existing vector signal sources employ a single clock architecture, requiring the symbol rate to be integer-divided according to the modulation order, making it impossible to flexibly configure arbitrary symbol rates according to test requirements. Taking the demodulation capability of a user's broadband receiver (256QAM) as an example, with a 256QAM symbol carrying 8 bits of data and a master clock of 100MHz, the maximum symbol rate of existing serial PN code generation technology is only 12.5MHz; for 64QAM (6 bits per symbol), the maximum symbol rate is approximately 16.67MHz. When testing the high-speed demodulation capability of a user's broadband receiver, the vector signal source is required to provide a high-order modulation signal with a high symbol rate, a requirement that the existing architecture cannot meet.

[0067] This solution employs a dual-clock architecture with a master clock and a bit clock. The master clock drives parameter configuration and matrix operations in symbol mapping, shaping filtering, carrier modulation, and PN sequence generation, while the bit clock drives feedback calculations and shift registers. During output selection, the PN sequence is synchronized back to the master clock. The master clock is consistent with and fixed to the system sampling rate, while the bit clock is independently adjusted according to the symbol rate, thus supporting output at any symbol rate while maintaining a constant system sampling rate. Compared to existing serial PN code generation technologies, this solution increases the symbol rate from the frequency division value limited by the modulation order to the master clock frequency. With a master clock of 100MHz, it can support a maximum symbol rate output of 100MHz, fully meeting the testing requirements of high-speed broadband receivers for high symbol rate modulated signals.

[0068] Reference Figure 8 This disclosure provides a digital modulation signal generation system, which includes a parameter configuration unit, a matrix operation unit, a feedback calculation unit, a shift register, an output selection unit, and a modulation unit; The parameter configuration unit is used to acquire the master clock; at the rising edge of the master clock, it acquires the operating parameters; wherein, the operating parameters include the number of PN code order bits, primitive polynomial, initial value, output bit width, bit mask and enable signal; When the enable signal is at an active level, the coefficients of the primitive polynomial are converted into an active bit marker matrix. The matrix operation unit is used to perform iterative operations on the effective bit marker matrix to obtain the parameter storage matrix; wherein, the number of iterations is equal to the output bit width; The feedback calculation unit is used to take the initial value as the starting value of the current state value, and perform state recursion on the current state value based on the parameter storage matrix and bit mask to obtain the feedback value vector. The shift register is used to update the current state value based on the feedback value vector under the BIT clock drive, and obtain the updated state value. The output selection unit is used to extract valid bits from the updated state value as parallel output based on the comparison result between the PN code order bits and the output bit width, so as to obtain the PN sequence that conforms to the output bit width. The modulation unit is used to generate digital modulation signals based on PN sequences for communication testing of broadband receivers.

[0069] The parameter configuration unit, matrix operation unit, feedback calculation unit, shift register, and output selection unit are components of the PN sequence generator, while the modulation unit includes a symbol mapping module, a shaping filter module, and a carrier modulation module.

[0070] Optionally, the parameter configuration unit is specifically used to initialize a two-dimensional matrix when the enable signal is at an active level; wherein the number of rows and columns of the two-dimensional matrix are both equal to N, and N is the maximum output bit width that can support the PN sequence; Iterate through each coefficient of the primitive polynomial; If the coefficient of the i-th term is 1, then set all elements in the i-th row of the two-dimensional matrix to 1; If the coefficient of the i-th term is 0, then set all elements in the i-th row of the two-dimensional matrix to 0; After the traversal is complete, the two-dimensional matrix is ​​used as the valid bit marker matrix.

[0071] Optionally, the matrix operation unit is specifically used to initialize an identity matrix as the initial value of the parameter storage matrix; wherein the number of rows and columns of the identity matrix are both equal to N; In each iteration, perform a bitwise AND operation between each row of the current parameter storage matrix and the row with the corresponding row number in the effective bit tag matrix, and then perform a modulo-2 addition operation on all bitwise AND results; Shift the current parameter storage matrix down one row, and fill the first row that is now empty after the shift with the result of the modulo-2 addition operation. When the number of iterations equals the output bit width, the current parameter storage matrix is ​​used as the final parameter storage matrix.

[0072] Optionally, the feedback calculation unit is specifically used to load the initial value into the shift register at the rising edge of the enable signal, as the current state value of the shift register; the number of bits in the shift register is equal to N; At the rising edge of the BIT clock, each row of the parameter storage matrix is ​​bitwise ANDed with the current state value and the bit mask. The bitwise AND results of each row are then XORed and reduced to obtain the feedback value corresponding to each row. The feedback values ​​of each row constitute the feedback value vector.

[0073] Optionally, the shift register is specifically used to shift the current state value towards the higher bit of the shift register on the rising edge of the BIT clock, with the number of bits shifted being equal to the output bit width; Discard the high-order bits that are shifted out, and fill the empty low-order bits with the low-order bits of the feedback value vector.

[0074] Optionally, the output selection unit is specifically used to take consecutive bits of the update status value starting from the number of bits of the PN code order as valid output when the number of bits of the PN code order is greater than the output bit width. The number of consecutive bits is equal to the output bit width. The valid output is used as the low bit of the PN sequence, and the high bit of the PN sequence is padded with zeros. When the number of bits in the PN code order is not greater than the output bit width, the consecutive bits starting from the least significant bit of the updated state value are taken as the valid output. The number of consecutive bits is equal to the output bit width. The valid output is used as the low bit of the PN sequence, and the high bits of the PN sequence are padded with zeros.

[0075] Optionally, the shift register is also used to output the updated state value as the current state value for the next round of state recursion to the feedback calculation unit when the operating parameters remain unchanged. The feedback calculation unit, the shift register, and the output selection unit cyclically perform state recursion, state update, and output interception until the enable signal becomes invalid, and continuously output a PN sequence that conforms to the output bit width.

[0076] Optionally, the system also includes a host computer; The host computer is used to configure the operating parameters and send the operating parameters to the parameter configuration unit.

[0077] This solution utilizes the internal hardware resources of an FPGA to build each functional unit. All units operate in parallel, eliminating the need for CPU instruction execution and avoiding the latency overhead caused by serial software processing. By converting the primitive polynomial coefficients into a matrix structure, and using bitmasks and PN code order numbering to control the effective bits, arbitrary polynomial configuration is achieved. Furthermore, the master clock and BIT clock are separated, with independent adjustment of the BIT clock to achieve arbitrary rate PN sequence output. By judging the output bit width and PN code order numbering, arbitrary bit width output is achieved while ensuring PN sequence continuity. The host computer can configure polynomial coefficients and initial state parameters in real time via PCIe, Ethernet, USB, or serial ports, switching operating modes without resynthesizing or downloading the FPGA bitstream. This solution allows a single module to support PN sequence output with arbitrary polynomials, arbitrary rates, and arbitrary bit widths, significantly improving the flexibility and application capabilities of vector signal sources in high-speed communication testing.

[0078] The various variations and specific examples of the digital modulation signal generation method provided above are also applicable to the digital modulation signal generation system provided in this disclosure. Through the foregoing detailed description of the digital modulation signal generation method, those skilled in the art can clearly understand the implementation method of the digital modulation signal generation system. For the sake of brevity, they will not be described in detail here.

[0079] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0080] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0081] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0082] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0083] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0084] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for generating a digital modulated signal, characterized in that, include: Get the master clock; At the rising edge of the master clock, the operating parameters are acquired; wherein, the operating parameters include the number of PN code order bits, primitive polynomial, initial value, output bit width, bit mask and enable signal; When the enable signal is at an active level, the coefficients of the primitive polynomial are converted into an active bit marker matrix. Perform iterative operations on the effective bit marker matrix to obtain a parameter storage matrix; wherein, the number of iterations is equal to the output bit width; Using the initial value as the starting value of the current state value, and based on the parameter storage matrix and the bit mask, the current state value is recursively processed to obtain the feedback value vector; Driven by the BIT clock, the current state value is updated based on the feedback value vector to obtain the updated state value; Based on the comparison result between the PN code order bits and the output bit width, valid bits are extracted from the updated state value as parallel output to obtain a PN sequence that conforms to the output bit width; Based on the PN sequence, a digital modulation signal is generated for communication testing of a broadband receiver.

2. The digital modulation signal generation method according to claim 1, characterized in that, When the enable signal is active, converting the coefficients of the primitive polynomial into an active bit marker matrix includes: When the enable signal is active, a two-dimensional matrix is ​​initialized; wherein the number of rows and columns of the two-dimensional matrix are both equal to N, and N is the maximum output bit width that can support PN sequences; Iterate through each coefficient of the primitive polynomial; If the coefficient of the i-th term is 1, then all elements in the i-th row of the two-dimensional matrix are set to 1; If the coefficient of the i-th term is 0, then all elements in the i-th row of the two-dimensional matrix are set to 0; After the traversal is complete, the two-dimensional matrix is ​​used as the valid bit marker matrix.

3. The digital modulation signal generation method according to claim 1, characterized in that, The iterative operation on the effective bit marker matrix to obtain the parameter storage matrix includes: Initialize an identity matrix as the initial value of the parameter storage matrix; wherein the number of rows and columns of the identity matrix are both equal to N, and N is the maximum output bit width that can support PN sequences; In each iteration, each row of the current parameter storage matrix is ​​bitwise ANDed with the row number of the corresponding row in the effective bit tag matrix, and then modulo-2 addition is performed on all bitwise AND results. Shift the current parameter storage matrix down one row, and fill the first row that is now empty after the shift with the result of the modulo-2 addition operation. When the number of iterations equals the output bit width, the current parameter storage matrix is ​​used as the final parameter storage matrix.

4. The digital modulation signal generation method according to claim 3, characterized in that, The step of using the initial value as the starting value of the current state value, and performing state recursion on the current state value based on the parameter storage matrix and the bit mask to obtain the feedback value vector includes: At the rising edge of the enable signal, the initial value is loaded into the shift register as the current state value of the shift register; the number of bits in the shift register is equal to N. At the rising edge of the BIT clock, each row of the parameter storage matrix is ​​bitwise ANDed with the current state value and the bitmask, and the bitwise AND results of each row are XORed and reduced to obtain the feedback value corresponding to each row. The feedback values ​​of each row constitute the feedback value vector.

5. The digital modulation signal generation method according to claim 4, characterized in that, The step of updating the current state value based on the feedback value vector under the BIT clock drive to obtain the updated state value includes: At the rising edge of the BIT clock, the current state value is shifted towards the higher bit of the shift register, and the number of bits shifted is equal to the output bit width. Discard the high-order bits that are shifted out, and fill the empty low-order bits with the low-order bits of the feedback value vector.

6. The digital modulation signal generation method according to claim 1, characterized in that, The step of extracting valid bits from the updated state value as parallel output based on the comparison result between the PN code order bits and the output bit width, to obtain a PN sequence conforming to the output bit width, includes: When the number of bits of the PN code order is greater than the output bit width, the consecutive bits of the updated state value starting from the number of bits of the PN code order are taken as valid output, the number of consecutive bits is equal to the output bit width, the valid output is taken as the low bit of the PN sequence, and the high bit of the PN sequence is padded with zeros. When the number of bits of the PN code order is not greater than the output bit width, the consecutive bits of the update state value starting from the least significant bit are taken as the valid output, the number of consecutive bits is equal to the output bit width, the valid output is taken as the low bit of the PN sequence, and the high bits of the PN sequence are padded with zeros.

7. The digital modulation signal generation method according to claim 1, characterized in that, Also includes: When the operating parameters remain unchanged, the updated state value is used as the current state value for the next round of state recursion. The steps of state recursion, state update, and output interception are repeated until the enable signal becomes invalid, and a PN sequence that conforms to the output bit width is continuously output.

8. A digital modulation signal generation system, characterized in that, The system includes a parameter configuration unit, a matrix operation unit, a feedback calculation unit, a shift register, an output selection unit, and a modulation unit; The parameter configuration unit is used to acquire the master clock; and to acquire the operating parameters at the rising edge of the master clock; wherein the operating parameters include the number of PN code order bits, primitive polynomial, initial value, output bit width, bit mask and enable signal; When the enable signal is at an active level, the coefficients of the primitive polynomial are converted into an active bit marker matrix. The matrix operation unit is used to perform iterative operations on the effective bit marker matrix to obtain a parameter storage matrix; wherein the number of iterations is equal to the output bit width; The feedback calculation unit is used to take the initial value as the starting value of the current state value, and perform state recursion on the current state value based on the parameter storage matrix and the bit mask to obtain the feedback value vector. The shift register is used to update the current state value based on the feedback value vector under the BIT clock drive, and obtain the updated state value. The output selection unit is used to extract valid bits from the updated state value as parallel output based on the comparison result between the PN code order bits and the output bit width, so as to obtain a PN sequence that conforms to the output bit width. The modulation unit is used to generate a digital modulation signal for communication testing of a broadband receiver based on the PN sequence.

9. The digital modulation signal generation system according to claim 8, characterized in that, The shift register is also used to output the updated state value as the current state value for the next round of state recursion to the feedback calculation unit when the operating parameters remain unchanged. The feedback calculation unit, the shift register, and the output selection unit cyclically perform state recursion, state update, and output truncation until the enable signal becomes invalid, and continuously output a PN sequence that conforms to the output bit width.

10. The digital modulation signal generation system according to claim 8, characterized in that, The system also includes a host computer; The host computer is used to configure the operating parameters and send the operating parameters to the parameter configuration unit.

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