A data hazard elimination and speculation error method and system for a JPEG-LS lossless compression encoder pipeline

Abstract

The application discloses a data hazard elimination and speculation error method and system for a JPEG-LS lossless compression encoder pipeline. The method is used in a conventional encoding pipeline, and the following steps are performed in each clock cycle to realize a zero stall pipeline: a read-write address conflict is detected in real time, when the read-write address is consistent, the latest calculated accumulated absolute error A, accumulated error sum B, prediction deviation C and context count N parameter values in the pipeline are directly forwarded; three kinds of prediction errors are calculated in parallel, and a real error value is selected from the three kinds of prediction errors; the parameter is updated according to the real error value; Golomb encoding parameters K are generated according to the updated parameters, and merror values are obtained by mapping the real error. The method of the application realizes a zero stall pipeline, eliminates a C parameter waiting bubble, is friendly to a BRAM, a data hazard elimination mechanism covers a double mode at the same time, a critical path delay is controllable, and is suitable for high-frequency comprehensive implementation.

Description

Technical Field

[0001] This invention belongs to the field of image compression coding technology, and in particular relates to a method and system for eliminating data hazard and speculative errors in a JPEG-LS lossless compression encoder pipeline. Background Technology

[0002] JPEG-LS (ISO / IEC 14495-1) is an international standard for lossless / near-lossless image compression, with its core algorithm being LOCO-I (Low Complexity Lossless Compression for Images). The LOCO-I algorithm mainly consists of four stages: Median Edge Detector (MED), context modeling, Golomb entropy coding, and run-length coding. While this algorithm has been widely implemented and applied in software, it faces the inherent challenge of read-after-write hazard in hardware pipeline design. Existing technologies, categorized by technical direction, include: JPEG-LS fully pipelined hardware architecture and JPEG-LS parallel processing architecture. In existing JPEG-LS hardware implementations, pipeline data hazards are mainly addressed through two methods: data forwarding and multi-channel parallelism. The following technical drawbacks exist: (1) Incomplete pipeline hazard handling: Existing forwarding schemes mostly use a single path and cannot handle the different timing requirements of multiple context parameters at the same time. The parameter group abcn and the parameter C_error have different effective time points in the pipeline, and a single forwarding strategy cannot satisfy them at the same time.

[0003] (2) Parameter C not being ready causes pipeline stall: In conventional mode coding, the error calculation stage requires the context parameter C, but the value of C needs to go through multiple pipeline stages to be determined. Existing solutions either wait for the value of C to stabilize (introducing cavitation) or simplify the processing path, both of which will reduce throughput or affect coding accuracy.

[0004] (3) Inefficient handling of BRAM read / write conflicts: In FPGA implementation, dual-port BRAMs have data uncertainty issues when reading and writing to the same address. Existing solutions either add extra waiting cycles or use register files to replace BRAM, increasing area overhead.

[0005] (4) Insufficient coordination between run-length encoding and conventional dual-mode: Most existing forwarding schemes only focus on the conventional mode and do not consider the coordination mechanism of data bypass and code stream merging under the run-length encoding interruption mode. Summary of the Invention

[0006] The purpose of this invention is to overcome the above-mentioned defects of the prior art and to propose a method and system for eliminating data hazard and speculative errors in a JPEG-LS lossless compression encoder pipeline.

[0007] In view of this, the present invention proposes a data hazard elimination and speculation error method for JPEG-LS lossless compression encoder pipelines. In a conventional encoding pipeline, the following steps are performed in each clock cycle to achieve a zero-stop pipeline: Real-time detection of read / write address conflicts; when read / write addresses are consistent, the latest calculated cumulative absolute error A, cumulative error sum B, prediction bias C, and context count N values ​​in the pipeline are directly forwarded. The three prediction errors are calculated in parallel, and the true error value is selected from them. Update the parameters based on the actual error value; Based on the updated parameters, the Golomb encoding parameter K is generated, and the merror value is obtained by mapping the actual error.

[0008] As an improvement to the above method, the real-time detection of read / write address conflicts specifically includes: A dual-path independent address comparison is implemented to detect read / write address conflicts of the parameter group and the error value C_error, respectively. The parameter group includes: cumulative absolute error A, cumulative error sum B, prediction bias C, and context count N. When a conflict is detected, the parameter value that has just been updated in the pipeline stage is bypassed and used by the pipeline stage; otherwise, the latest calculated parameter value in the pipeline is forwarded directly.

[0009] As an improvement to the above method, the parallel calculation of three prediction errors and the selection of the true error value specifically includes: Based on the available C value in the current pipeline, C+1, C, and C-1 are used as the three possible values ​​of prediction deviation C, and the corresponding prediction errors Merror_out_1, Merror_out, and Merror_out_0 are calculated in parallel. Once the final updated value of parameter C is determined, it is compared with the three possible values ​​C+1, C, and C-1. The prediction error corresponding to the value that is equal to the final updated value is selected as the true error value and output.

[0010] As an improvement to the above method, the parameter update specifically includes: Phase 1: The prediction error Merror drives the basic summation of the cumulative absolute error A and the cumulative error B; the outputs of this phase are A_pre and B_pre. Second stage: Determine whether the context count N has reached the reset threshold. If yes, perform a halving operation on A, B, and N in parallel. Otherwise, A, B, and N retain their original values. The output of this stage is A_base, B_base, and N_base. The third stage: compare B_pre with integer multiples of N_base in parallel, limit and pull back B according to the comparison results, and generate the adjustment amount delta_C of the prediction deviation C at the same time. Fourth stage: Add the current value of prediction bias C, C_base, to delta_C to get C_pre. Check whether C_pre exceeds the range of 8-bit signed numbers [-128, 127]. If it overflows, saturate and limit the amplitude to the boundary value. Output the updated cumulative absolute error A, cumulative error sum B, prediction bias C, and context count N.

[0011] As an improvement to the above method, the step of generating Golomb coding parameters K based on the updated parameters and obtaining the merror value by mapping the true error specifically includes: Based on the updated cumulative absolute error A and context count N, the Golomb coding parameters K are generated by left-shifting the comparison chain; The error Merror is corrected for sign based on the sign bit of the context index, and then the value of merror is obtained by modulo reduction and range limitation.

[0012] As an improvement to the above method, the method includes performing the following steps before a conventional production line: Receive pixel data streams, perform preprocessing and generate line end markers; Gradient calculation is performed for each pixel in each row of data stream, and the context index Q is obtained through fusion calculation. The encoding mode of the current pixel is determined by a four-state finite state machine. The encoding modes include: normal mode, run-length interruption mode and end-of-row interruption mode. The predicted value of the current pixel is calculated based on the MED algorithm.

[0013] As an improvement to the above method, the method includes performing the following steps after a conventional production line: Receive the K value and the merror value, perform limited-length Golomb encoding, and output the variable-length codeword and its effective length; Pack the bitstream for output.

[0014] On the other hand, the present invention provides a data hazard elimination and speculation error system for JPEG-LS lossless compression encoder pipelines, deployed in a conventional encoding pipeline, comprising: The context address management module is used to detect read and write address conflicts in real time. When the read and write addresses are consistent, the latest calculated cumulative absolute error A, cumulative error sum B, prediction bias C and context count N parameter values ​​in the pipeline are forwarded directly. The three-way error calculation module calculates errors and is used to calculate three types of prediction errors in parallel. The selection module is used to select the true error value from three prediction errors; The context parameter update module is used to update parameters based on the actual error value; and The encoding parameter generation module is used to generate Golomb encoding parameters K based on the updated parameters, and obtain the merror value by mapping the actual error.

[0015] Compared with the prior art, the advantages of the present invention are: 1. Zero-stop pipeline: By using a dual-path independent data bypass mechanism, all pauses caused by context parameter read / write conflicts in the JPEG-LS pipeline are eliminated, achieving a continuous coding throughput of one pixel per clock cycle.

[0016] 2. Eliminate waiting cavitation for C parameter: By calculating the three-way speculation error and selecting the delay, the waiting clock is avoided due to the C parameter not being ready, thus maintaining full pipeline operation while ensuring coding accuracy.

[0017] 3. BRAM-friendly: The write bypass caching mechanism is compatible with the dual-port BRAM feature of FPGAs, eliminating the need to replace BRAM with a register file, thus saving chip area. The initialization module supports fast writing to address 400 and is compatible with standard BRAM depth.

[0018] 4. Dual-mode full coverage: The data hazard elimination mechanism covers both the regular coding mode and the run-length coding mode (including interrupted coding scenarios) to ensure that the pipeline is uninterrupted in both modes.

[0019] 5. High hardware efficiency: All hazard elimination logic is implemented with combinational logic and a small number of registers, with no state machine waiting overhead, controllable critical path delay, and suitable for high-frequency synthesis implementation. Attached Figure Description

[0020] Figure 1 This is a diagram of the overall system and data hazard elimination architecture; Figure 2 This is the overall processing flowchart. Detailed Implementation

[0021] This invention relates to a pipelined data hazard elimination method in a JPEG-LS lossless compression hardware accelerator. A JPEG-LS encoder needs to perform a series of operations for each pixel of an image, including gradient calculation, context modeling (Q-value mapping), edge detection prediction (MED), error calculation, Golomb coding, and context parameter updates. In the hardware implementation, these operations are arranged as a multi-stage pipeline to improve throughput.

[0022] JPEG-LS context parameters A (absolute cumulative error), B (cumulative error), C (prediction bias), and N (context count) are stored in the BRAM, with the context index Q as the address. When processing the current pixel, the pipeline needs to read the updated parameters from the BRAM (read operation) and simultaneously write the new parameters (after processing the current pixel) into the BRAM (write operation). When consecutive pixels have the same or similar Q values, the read address and write address may be the same, resulting in a RAW (Read-After-Write) data hazard, meaning the parameters to be read have not yet been written. The core innovation of this invention lies in eliminating all data hazards without increasing pipeline pauses through three mutually coordinated mechanisms: dual-path address comparison, data bypass forwarding, and three-path prediction error calculation.

[0023] The technical problem to be solved by this invention: (1) Solve the data hazard problem of context parameter reading and writing in the JPEG-LS pipeline: By setting up dual independent address comparators in the pipeline, read and write address conflicts are detected in real time and the latest calculated parameter values ​​in the pipeline are forwarded directly to avoid pipeline stalls.

[0024] (2) Eliminate waiting cavitation caused by the delay of parameter C: By parallel calculation of three possible prediction error values ​​(based on C+1, C, C-1), the correct result is selected after the C value is finally determined, and the waiting period is eliminated.

[0025] (3) Resolve the same address read / write conflict of FPGA dual-port BRAM: Set write bypass cache logic at the output of BRAM. When the read address and write address are detected to be the same, output the newly written register value instead of the old value or uncertain value of BRAM.

[0026] (4) Achieve unified hazard elimination in both normal and run-length encoding modes: The data bypass mechanism is designed in conjunction with the interruption handling and code stream merging logic of the run-length encoding mode to ensure that there is no pipeline interruption in either encoding mode.

[0027] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0028] Example 1 Embodiment 1 of the present invention provides a method for data hazard elimination and speculation error in a JPEG-LS lossless compression encoder pipeline, wherein the following steps are performed in each clock cycle to achieve a zero-stop pipeline: Real-time detection of read / write address conflicts; when read / write addresses are consistent, the latest calculated cumulative absolute error A, cumulative error sum B, prediction bias C, and context count N values ​​in the pipeline are directly forwarded. The three prediction errors are calculated in parallel, and the true error value is selected from them. Update the parameters based on the actual error value; Based on the updated parameters, the Golomb encoding parameter K is generated, and the merror value is obtained by mapping the actual error.

[0029] Example 2 Embodiment 2 of the present invention provides a data hazard elimination and speculation error system for JPEG-LS lossless compression encoder pipelines. For example... Figure 1 The diagram shown is a block diagram of the overall system and data hazard elimination architecture. Figure 2 The diagram shown is the overall processing flowchart.

[0030] Module Function Description: (1) Pixel input and line buffer module (image_ram) It is responsible for receiving external input pixel data streams, using a dual-port BRAM to buffer one row of pixel data for pixel preprocessing and generation of the end-of-row flag (eol). It performs register aligning of pixel signals and enable signals to ensure data synchronization with the pipeline clock domain.

[0031] (2) Gradient calculation and Q-mapping module (grad_cal) Using the four neighboring pixels (Ra, Rb, Rc, Rd) of the current pixel as input, three local gradient values ​​(g1, g2, g3) are calculated. Each gradient is mapped to a 9-level value (-4 to +4) through non-uniform quantization, and then fused to obtain the context index Q (a 9-bit signed number, whose absolute value is an 8-bit Q value). Simultaneously, a four-state finite state machine (FSM) is used to determine the current encoding mode: normal mode (mode 0), run-counting mode (mode 1), interrupted encoding mode (mode 2), and interrupted no-encoding / end-of-line mode (mode 3).

[0032] (3) MED edge detection prediction module (edge_detect) According to the MED algorithm, the predicted value px of the current pixel x is calculated using pixels a, b, and c. When c is between a and b, a + bc is used as the predicted value; otherwise, the smaller / larger value of a and b is used. This module also outputs the positive or negative sign of the context index, sign, for subsequent error calculation.

[0033] (4) Regular mode coding pipeline (regular_mode) This is the core innovative carrier of the present invention, which includes the following sub-modules and is deployed in a conventional coding pipeline: The context address management module is used to detect read and write address conflicts in real time. When the read and write addresses are consistent, the latest calculated cumulative absolute error A, cumulative error sum B, prediction bias C and context count N parameter values ​​in the pipeline are forwarded directly. The three-way error calculation module is used to calculate three types of prediction errors in parallel and select the true error value from them. The error selection module is used to select the true error value from three prediction errors. The context parameter update module is used to update parameters based on the actual error value; The encoding parameter generation module is used to generate Golomb encoding parameters K based on the updated parameters, and obtain the merror value by mapping the actual error.

[0034] Specifically: The context address management module (context_address) implements dual-path independent address comparison, separately detecting read / write address conflicts for parameter group abcn and parameter C_error. When a conflict is detected, the parameter value just updated in the subsequent pipeline stage is bypassed and used by the preceding stage (i.e., "breaking the closed-loop logic"). This module also maintains two levels of register cache (q_reg4 → q_2_ram_reg5) to ensure that the address of parameter updates written back to RAM is synchronized with the parameter value.

[0035] The three-way error calculation module (error_uint) addresses the issue that the parameter C may be uncertain due to pipeline delays. It simultaneously instantiates three error calculation subunits (error_deal), each taking c_1 (i.e., C+1), c_0 (i.e., C), and c_-1 (i.e., C-1) as inputs, respectively, and calculates the prediction error Merror in parallel for the three cases. The three calculations are independent of each other and can be completed within a single cycle.

[0036] The error selection module (error_select) selects the correct prediction error from three paths based on the comparison between the actual output C value (c_out_select) and the C value used in the inference stage (c_error_select). This module is a three-to-one data selector, implementing a pipeline optimization strategy of "parallel inference first, then delayed selection".

[0037] The context parameter update module (context_updater) updates four parameters—A (cumulative absolute error), B (cumulative sum of errors), C (prediction bias), and N (context count)—based on the selected true error Merror. The update rules include: a normalization strategy that halves the parameters when N≥64; four levels of boundary limiting for B (B+2N, B+N, B, BN); and adaptive sign adjustment for C when it overflows in the B / N direction. All updates are performed using combinational logic in a single cycle.

[0038] The encoding parameter generation module (coder_variables) generates Golomb encoding parameters k by left-shifting the comparison chain based on the updated parameters A and N; at the same time, it maps the error Merror to obtain the merror value (including sign handling, parity correction and range limitation).

[0039] (5) Run-length encoding module (run_length_code + run_interrupt) It operates in run-length mode (mode 1 / 2 / 3). run_length_code looks up the index value (run_index) and J parameters in the J table based on the run count value (run_count) given by the gradient calculation module; run_interrupt performs special prediction on interrupted samples (using only the two neighboring pixels a and b), calculates the Golomb coding parameters k_run and merror_run in run-length interruption mode, and maintains two sets of context counters (nn1 / nn2 corresponding to the two cases of a!=b and a==b).

[0040] (6) Golomb encoding module (golomb) It receives the k and merror values ​​from either the normal mode or the run-length interrupted mode, performs limited-length Golomb encoding, and outputs a variable-length codeword (bitstream) and its effective length (len). It supports limited-length Golomb encoding mode, switching to qbpp bit-based encoding when the code length exceeds the threshold.

[0041] (7) Bitstream selection and merging module (within compression) Depending on the current encoding mode, select or concatenate Golomb code and run-length encoded codewords. In normal mode, output the Golomb code directly; in interrupt encoding mode, shift the run-length encoded code segment to the left and merge it with the Golomb code segment bitwise or bitwise; in end-of-line interrupt mode, only output the run-length encoded code segment.

[0042] (8) Parameter caching module (para_cache) Five dual-port BRAMs are instantiated (to store A, B, C, N, and C_error respectively). The BRAMs are addressed using context index Q. When the read address and write address are the same (detected by the EQ_rd_wr_addr_abcn and EQ_rd_wr_addr_c_error signals), the register value just written in the pipeline is directly output (write bypass) to avoid read / write conflicts at the same address in the BRAM.

[0043] (9) Bitstream Packaging Output Module The variable-length Golomb codeword is shifted and accumulated to a 128-bit register. When the register is full, it is written to enable output. If the last frame is less than 128 bits, it is left-aligned and padded with zeros under the completion signal.

[0044] (10) Parameter initialization module (initial_para) After each reset, initialization values ​​(A=1024, B=0, C=0, N=1) are written to all BRAM addresses (depth 400). After 400 clock cycles, an initialization completion signal is generated, and pixel input is started. 1) Dual-path independent data bypass mechanism (core innovation) The key innovation of this invention lies in the data hazard elimination mechanism (the context_address module in conjunction with the para_cache module). The workflow of this mechanism is as follows: Step 1: Address Comparison. The system maintains three context index registers: q is the Q value of the current pixel (first step into the pipeline), q_reg3 is q delayed by one step (used to read the C_error parameter), q_reg4 is q delayed by two steps (used to read the abcn parameter group), and q_2_ram_reg5 is q delayed by three steps (the address where the current pixel parameter is written to RAM).

[0045] Step 2: Independent judgment for both paths. Set up two address comparators: equ_abcn: Compare q_reg4 (the address to read abcn) with q_2_ram_reg5 (the address to write abcn). If they are the same, it means that the parameter to be read is exactly the parameter that the previous pixel in the pipeline has just been updated and is about to be written. At this time, the newly updated register values ​​a_out_ram_reg5 / b_out_ram_reg5 / c_out_ram_reg5 / n_out_ram_reg5 are directly output instead of reading the old value from BRAM.

[0046] equ_c_error: Compares q_reg3 (the address to read C_error) with q_2_ram_reg5 (the address to write C_error). If they are the same, the newly updated C_error value is bypassed instead of being read from BRAM.

[0047] Step 3: BRAM Write Bypass. In the para_cache module, the EQ_rd_wr_addr_abcn_n and EQ_rd_wr_addr_c_error_n registers delay the address comparison result by one clock cycle (aligned with the BRAM output timing). When a read / write conflict is detected, the latest value is retrieved from the pipeline registers (ram_wr_a_reg1 / ram_wr_b_reg1 / ram_wr_c_reg1 / ram_wr_n_reg1) and directly used as the read data output, bypassing the BRAM.

[0048] 2) Three-way prediction error calculation mechanism (core innovation) In a conventional pipeline, error calculation requires parameter C, but the value of C is determined only after a pipelined delay involving "reading C_error from BRAM → error calculation → error selection → context update". To avoid this waiting, the system employs a speculative calculation strategy. Step 1: Three-way parallel computation. In the error_uint module, three error_deal submodules are instantiated simultaneously, taking c_error_select_reg4+1 (i.e., C+1), c_error_select_reg4 (i.e., C), and c_error_select_reg4-1 (i.e., C-1) as inputs to the context parameter C, respectively, and calculating the prediction errors Merror_out_1, Merror_out, and Merror_out_0 in parallel for the three cases.

[0049] Step 2: Delayed Selection. The error_select module obtains the actual C value (c_out_select_reg4), compares it with three predicted values ​​(c_error_select_reg4+1, c_error_select_reg4, c_error_select_reg4-1), and selects the corresponding error value for output. The selection logic is as follows: if the actual C equals the predicted C+1, then Merror_out_1 is selected; if it equals the predicted C, then Merror_out is selected; if it equals the predicted C-1, then Merror_out_0 is selected.

[0050] Step 3: Context Update and Encoding. The selected error value is sent to context_updater to update the A / B / C / N parameters. The updated parameters are then sent to coder_variables to calculate the k and merror values ​​required for Golomb encoding.

[0051] 3) Context parameter adaptive update engine (core innovation) The context parameter update module (context_updater) is one of the core computational units of the JPEG-LS pipeline encoder. In normal encoding mode, it is responsible for adaptively updating four context parameters: A (cumulative absolute error), B (cumulative error sum), C (prediction bias), and N (context count), based on the true prediction error Merror output by the error selection module for the current pixel. The core design goal of this module is to complete all update operations within a single clock cycle using pure combinational logic, without introducing any pipeline dummy operations or state machine waits. This allows it to work in conjunction with the dual-path data bypass (Section 3.4.1) and the three-path speculative error calculation (Section 3.4.2) to achieve a complete zero-stop pipeline.

[0052] I. Parameter Update Data Path The inputs to the update engine include: (a) the true prediction error Merror (signed deviation value) output by the error selection module; (b) the current context parameters A, B, C, and N (from the BRAM read port or dual-path bypass register); and (c) the boundary flag for parameter C (indicating whether C has reached the saturation boundary of -128 or +127). The outputs of the update engine include: the updated A_new, B_new, C_new, and N_new, and the cumulative deviation value C_error_new for C (used for error calculation in the next pixel).

[0053] The entire update process is decomposed into four parallel combinational logic computation stages within a single cycle: Phase 1 (Basic Accumulation): The basic accumulation of A and B is driven by the prediction error: A_pre = A + |Merror|, B_pre = B + Merror. Where |Merror| is the absolute value of Merror (inverted and incremented by one when Merror is negative), and the adder has a bit width of 24 bits (A / B are both 24-bit signed numbers).

[0054] The second stage (normalization decision): Determine whether N has reached the reset threshold of 64 (i.e., whether bit [6] of N is 1). If it is true, perform a halving operation on A, B, and N in parallel; otherwise, keep the original values. This stage outputs N_base, A_base, and B_base as inputs for subsequent limiting.

[0055] The third stage (fourth-level boundary limiting): B_pre is compared in parallel with integer multiples of N_base (+N, -N, +2N, -2N). Based on the comparison results, B is limited and pulled back, and the adjustment amount delta_C of C is generated at the same time.

[0056] Fourth stage (saturation protection): Add C_base and delta_C to get C_pre, check whether C_pre exceeds the range of 8-bit signed numbers [-128, 127]. If it overflows, saturate and limit the amplitude to the boundary value.

[0057] II. Normalization Halving Strategy for N>=64 (1) Design Principle: In the LOCO-I algorithm, the context count N is used to track the cumulative frequency of occurrence of the context index Q. The upper limit of N is constrained by the parameter register bit width (8 bits, maximum 255), and an excessively large N value will cause the update step size of parameters A and B to be relatively small, making the parameters lose sensitivity to changes in the statistical characteristics of the data. The JPEG-LS standard (ISO / IEC 14495-1) stipulates that when N reaches the reset threshold RESET (default value 64), all cumulative parameters must be halved to maintain the dynamic responsiveness of the parameters. The normalization operation is equivalent to applying an exponential forgetting factor to the historical data, so that more recent pixel data has a greater weight in the parameters.

[0058] (2) Triggering condition (pure combinational logic judgment): The normalized trigger signal N_reach_reset is directly driven by bit [6] of N: N_reach_reset = (N[6]== 1'b1), that is, when N>=64, this bit is 1. This judgment is a single-bit combinational logic, without the need for a comparator or threshold judgment. Bit [6] of N is 1, which is equivalent to N belonging to [64, 127] (pre-normalized range). When the normalization condition is true, the following halving operation is performed in parallel: (3) Halving N (logical right shift): N_halved = N>>1, which means logically shifting right by 1 bit, equivalent to dividing by 2 (rounding down). Example: When N=64, N_halved=32; when N=65, N_halved=32 (rounding down). N is an 8-bit unsigned number, and the right shift operation does not require processing the sign bit.

[0059] (4) Halving A (rounding up, i.e., ceil divided by 2): A_halved = (A_pre + 24'd1)>>1, that is, add 1 and shift right by 1 bit to achieve ceil(A_pre / 2). A is a 24-bit unsigned number (the cumulative absolute error is always non-negative). Rounding up can prevent A from decaying to zero too early and maintain the continuity of statistical meaning. For example: when A_pre=5, A_halved=3; when A_pre=4, A_halved=2.

[0060] (5) Halving of B (rounding toward zero): B is a 24-bit signed number (two's complement representation). The halving direction varies depending on the sign. The code example is as follows: If B_pre>= 0 (B_pre

[23] =0), B_halved = (B_pre +24'd1)>>1, that is, rounding up the non-negative number, which is equivalent to ceil(B_pre / 2); if B_pre<0 (B_pre

[23] =1), B_halved = -(((-B_pre) + 24'd1)>>1), that is, rounding up the absolute value and then inverting it, which is equivalent to rounding toward zero. This rule ensures that halving B does not introduce DC deviation: the positive and negative symmetrical B values ​​remain positive and negative symmetrical after halving. For example: when B_pre=+5, B_halved=+3; when B_pre=-5, B_halved=-3. In the hardware implementation, the negative number path is achieved through an adder chain of inverting, adding 1, shifting to the right, and inverting again, with all paths completed within a single clock cycle.

[0061] (6) Normalization Gating (2-to-1 MUX): The halved value after normalization and the original value before halving are selected within a single shot using a 2:1 multiplexer. An example code is as follows: N_base = N_reach_reset ? N_halved : N; A_base = N_reach_reset ? A_halved : A_pre; B_base = N_reach_reset ? B_halved : B_pre. After normalization gating, N_base is incremented by 1 to obtain the new pre-limiting value N: N_new_pre = N_base + 8'd1. Note: The accumulation operation (A_pre = A + |Merror|, B_pre = B + Merror) is completed before normalization; when normalization is triggered, the halving operation applies to the accumulated value (i.e., A_pre and B_pre are halved, not the original A and B), which is consistent with the update order of the JPEG-LS standard.

[0062] III. Level 4 Boundary Limiting Mechanism of B (1) Design Principle: In the LOCO-I algorithm, the cumulative error B should theoretically be maintained within the range of [-N, N]. When the prediction error continues to be biased in the same direction (systematic overestimation or underestimation), B may exceed this range. The JPEG-LS standard adopts a cyclic clipping strategy: each time B exceeds the positive and negative N boundaries, B is pulled back by a distance of N in the zero direction, and the influence of this clipping operation on subsequent predictions is compensated by adjusting the prediction deviation C. In the software implementation, it is executed iteratively in a while loop, but the hardware pipeline requires a fixed single-shot delay. This scheme designs a four-level parallel boundary comparator by analyzing the overflow amplitude in the worst case, and implements single-shot clipping with full combinational logic.

[0063] (2) Worst-case analysis: The upper limit of the absolute value of the prediction error Merror for a single pixel is MAXVAL (for b-bit images, MAXVAL = 2^b - 1, i.e., 255 for 8-bit images and 65535 for 16-bit images). Considering the normalization operation (halved when N>=64), the maximum pre-normalized value of N is 127. The accumulated value of B can accumulate quickly when N is small, but it is halved every time N reaches 64, so the amplitude of B_pre will not grow indefinitely. The four-level amplitude limiting covers a range of ±2N, which can completely cover the worst case for application scenarios with image bit width <=12 bits (such as 8-bit grayscale, 10 / 12-bit medical images).

[0064] (3) Four-level boundary definition and judgment conditions: This solution uses N_new_pre as the benchmark, defines four-level boundary thresholds (±N and ±2N), and covers all possible value spaces of B_pre through five parallel combinational logic comparators. The five conditions are mutually exclusive, and exactly one of them is true: Condition 1 -- Strong positive overflow: B_pre>+2 * N_new_pre, judgment signal cond_pos2 = 1 Condition 2 -- Weak positive overflow: +N_new_pre<B_pre<= +2 * N_new_pre, judgment signal cond_pos1 = 1 Condition 3 -- Normal range: -N_new_pre<= B_pre<= +N_new_pre, judgment signal cond_normal = 1 Condition 4 -- Weak negative overflow: -2 * N_new_pre<= B_pre<-N_new_pre, judgment signal cond_neg1 = 1 Condition 5 -- Strong negative overflow: B_pre<-2 * N_new_pre, judgment signal cond_neg2 = 1 (4) Hardware calculation optimization for 2*N: 2*N is not implemented by a multiplier, but completed by a one-bit left shift via combinational logic: N_times_2 = {N_new_pre, 1'b0}, that is, N_new_pre is shifted left by 1 bit (zero-filled), the result has a bit width of 9 bits, and no multiplier resources are required.

[0065] (5) B clipping operation and C adjustment amount (cascaded MUX chain): The B adjustment amounts and C adjustment amounts corresponding to the four-level clipping are listed as follows: cond_pos2 (strong positive overflow): B = B_pre - 2*N_new_pre, C adjustment amount delta_C = +2 cond_pos1 (weak positive overflow): B = B_pre - N_new_pre, C adjustment amount delta_C = +1 cond_normal (normal range): B = B_pre (unchanged), C adjustment amount delta_C = 0 cond_neg1 (weak negative overflow): B = B_pre + N_new_pre, C adjustment amount delta_C = -1 cond_neg2 (strong negative overflow): B = B_pre + 2*N_new_pre, C adjustment amount delta_C = -2 The clipping of B is completed within a single shot through a two-stage cascaded MUX: the first-stage MUX determines whether ±2N adjustment is needed based on cond_pos2 / cond_neg2; the second-stage MUX determines whether ±N adjustment is needed based on cond_pos1 / cond_neg1. The combinational logic expression is: B_clamped = cond_pos2 ? (B_pre - N_times_2) : cond_neg2 ? (B_pre + N_times_2) : cond_pos1 ? (B_pre - N_new_pre) : cond_neg1 ? (B_pre + N_new_pre) : B_pre.

[0066] (6) Generation of adjustment amount of C (5-to-1 MUX): Synchronized with B limiting, delta_C is generated in parallel by the 5-to-1 multiplexer: delta_C = cond_pos2 ? 2 : cond_pos1 ? 1 : cond_neg1 ? -1 : cond_neg2 ? -2 : 0.

[0067] (7) Residual overflow handling explanation: For 16-bit images and extreme cases where N is extremely small (e.g., N=1~3), B_pre may exceed the range of ±2N (e.g., B_pre=65535 and 2N=6). In this case, cond_pos2 is true, and after executing B-=2N, B may still be greater than N. The four-level limiter in this scheme only performs single-stage limiting because: (a) such extreme cases only occur occasionally at the beginning of the image (N increases rapidly with pixel accumulation); (b) the residual positive deviation after single-stage limiting will continue to trigger limiting by the error accumulation of subsequent pixels, and the algorithm itself has asymptotic convergence; (c) adding more stages will lengthen the critical path of the combinational logic, which is not conducive to high-frequency implementation.

[0068] IV. C's sign adaptive adjustment and overflow protection (1) Design principle: The prediction bias C is an 8-bit signed number (two's complement representation, range [-128, +127]) used for adaptive bias correction of the MED edge detection prediction value. The adaptive adjustment of C follows the closed-loop control principle of [error direction -> parameter correction]: If B remains positive (actual pixel value > predicted value, i.e., systematic underestimation): when B > +N, B is pulled back by a limit, while C increases (delta_C = +1 or +2). The increase in C leads to an increase in subsequent predicted values, reducing the trend of future positive deviation.

[0069] If B remains negative (actual pixel value < predicted value, i.e., systematic overestimation): when B < -N, B is pulled back by limiting, and C is reduced (delta_C = -1 or -2). The reduction of C leads to a decrease in subsequent predicted values, narrowing the trend of future negative deviation.

[0070] This mechanism, which automatically determines the adjustment direction (with the same sign) of C based on the B limiting direction, is called [sign adaptive adjustment]: the sign of delta_C is always consistent with the overflow direction of B_pre (if B overflows positively, C is adjusted positively; if B overflows negatively, C is adjusted negatively). This is automatically guaranteed by the hardware parallel comparator, without the need for additional software judgment or state machine control.

[0071] (2) Graded control of C adjustment: The amplitude of delta_C (0 / ±1 / ±2) is proportional to the overflow level of B: strong positive / negative overflow (|B|>2N) triggers two-level adjustment (±2), weak positive / negative overflow (N<|B|<=2N) triggers single-level adjustment (±1), and no adjustment is made in the normal range (0). This graded design takes into account both adjustment speed and stability: large deviations are quickly corrected (two-level adjustment), small deviations are finely adjusted (single-level adjustment), avoiding over-adjustment and oscillation.

[0072] (3) Calculation of the adjusted C value: C_pre = C_base + delta_C, where C_base is the normalized gating C value. It should be noted that the C parameter itself does not participate in the normalization halving operation: C represents the direction and magnitude ratio of the cumulative deviation, and its absolute value is not determined by the cumulative number of N, so it should not be scaled as N is halved. However, since the updated value of C is directly related to the current overflow level of B, and the overflow judgment of B uses the normalized N_new_pre, the update of C is naturally indirectly affected by normalization (through the triggering time of B limiting).

[0073] (4) Saturation overflow protection of C: Since C is an 8-bit signed number, adding delta_C (maximum plus or minus 2) may exceed the representation range of [-128, +127]. Combinational logic saturation limiting is adopted: if C_pre>+127, then C_new = 8'sd127 (positive saturation, clamped to the maximum positive value); if C_pre<-128, then C_new = -8'sd128 (negative saturation, clamped to the minimum negative value); otherwise C_new = C_pre[7:0] (pass-through within normal range).

[0074] In the hardware implementation, saturation detection is performed by checking the relationship between bit[8] (9-bit extended sign bit) and bit[7] (8-bit sign bit) of C_pre: if bit[8] != bit[7] (i.e., sign extension mismatch), it indicates an overflow: bit[8] = 0 and bit[7] = 1 indicates a positive overflow (> +127), and bit[8] = 1 and bit[7] = 0 indicates a negative overflow (< -128). The saturation value is directly selected by the combinational logic MUX without timing judgment.

[0075] V. Summary of Single-Shot Combination Logic Implementation All the above operations—including normalization decision and halving, four-level boundary limiting of B (including 2N left shift calculation and five-way parallel comparison), and adaptive sign adjustment of C (including delta_C generation and saturation protection)—are completed by pure combinational logic within a single clock cycle. The complete combinational logic critical path of the data path is as follows: Input: Merror (signed prediction error), A, B, C, N (current context parameters) [Level 1] Basic Accumulation: A_pre = A + |Merror| (24-bit unsigned adder); B_pre = B + Merror (24-bit signed adder) [Level 2] Normalization decision: N[6]? -> Parallel halving computation -> 2:1 MUX gating -> N_base, A_base, B_base, N_new_pre = N_base + 1 [Level 3] Level 4 clipping decision: N_times_2 = N_new_pre<<1 -> Five-way parallel signed comparator (24-bit) -> Single-hot code condition vector {cond_pos2, cond_pos1, cond_normal, cond_neg1, cond_neg2} -> B_clamped = Two-stage MUX chain selection (24-bit signed subtractor / adder) -> delta_C = Five-to-one MUX (3-bit signed number: -2 / -1 / 0 / +1 / +2) [Level 4] C Update and Saturation: C_pre = C_base + delta_C (8-bit signed adder, extended to 9 bits) -> C_new = Saturation Limit (compare bit[8] and bit[7], MUX selects saturation value or pass-through value) Output: A_new, B_new (i.e. B_clamped), C_new, N_new (i.e. N_new_pre), all are registered to the next pipeline register.

[0076] Critical path timing analysis: The longest combinational logic path is [24-bit signed adder (B_pre calculation) -> normalized MUX gating -> five 24-bit signed comparators -> two-stage MUX selection chain (2:1 MUX * 2 stages) -> 24-bit subtractor (B-limiting operation)]. In typical FPGA implementations (such as Xilinx 7 series or UltraScale+ architecture), this path has an estimated delay of approximately 10~18ns, which can meet the timing convergence requirements for clock frequencies of 66MHz~100MHz. If the target frequency is higher (such as 150MHz+), a pipelined register can be inserted after the B-limiting MUX chain to move the C update and saturation protection of the fourth stage to the next clock cycle. However, the timing alignment logic of the dual-path bypass mechanism needs to be adjusted synchronously (the number of register clock cycles in the context_address module needs to be increased accordingly).

[0077] In summary, the context parameter adaptive update engine achieves N normalization, B four-level limiting, and C symbol adaptive adjustment through a single shot of the full combination logic. It works in conjunction with the dual-channel independent data bypass (Section 3.4.1) and the three-channel speculative error calculation (Section 3.4.2) to ensure the JPEG-LS pipeline encoder operates continuously with zero downtime in normal mode.

[0078] 4) Golomb coding parameter generation and prediction error mapping engine (core innovation) The encoding parameter generation module (coder_variables), located after the context parameter update module (context_updater) and before the Golomb encoding module (golomb), is a crucial bridge connecting parameter updates and entropy encoding in the conventional mode encoding pipeline. This module receives input in two dimensions: (a) the updated context parameters A (cumulative absolute error, 24-bit unsigned) and N (context count, 8-bit unsigned), used to generate the Golomb encoding parameters k; and (b) the true prediction error Merror (18-bit signed, covering the error range of the 16-bit image), selected by the error_select module, used to map the merror value (a non-negative integer) required to generate the Golomb encoding. All operations are performed by pure combinational logic within a single clock cycle.

[0079] I. Generation of the left-shift comparison chain for Golomb-encoded parameter k (1) Theoretical basis: In the LOCO-I algorithm, the Golomb coding parameter k determines the efficiency and code length of Golomb coding. Given the context parameter A (the accumulated value of cumulative absolute errors) and N (the number of context occurrences), the optimal k value should satisfy the best match for the prediction error magnitude under the geometric distribution assumption. The criterion for determining the k value defined by the JPEG-LS standard is: k is the smallest non-negative integer that satisfies the following inequality: N * (2^k)>= A The intuitive meaning of this inequality is: the average absolute error of the context is A / N, and 2^k is approximately equal to the base value of Golomb coding; k takes the minimum value that meets the condition, so that the Golomb code length matches the error magnitude distribution. Software implementations usually use a for loop to increment the k value to test the condition, but hardware requires a deterministic single-cycle delay.

[0080] (2) Hardware implementation solution - left shift comparison chain: This solution converts the multiplication operation in N*(2^k) into a left shift operation of N (N<<k = N * 2^k), thereby eliminating the multiplier overhead. For the value range of k [0, kmax], kmax+1 comparators are constructed in parallel to simultaneously judge the magnitude relationship between N<<k and A. The value of kmax is related to the image bit width bpp, and the code example is as follows: When bpp<= 8: kmax = 7, that is: k belongs to [0, 7] and is limited by the actual range of A / N When bpp>8: kmax = 15, that is: k belongs to [0, 15] (3) Parallel shift comparator array: For k=0, 1, 2, ..., kmax, calculate simultaneously: N_shifted_k = {N, {k{1'b0}}}, that is: N is shifted left by k bits, and the lower k bits are filled with 0s, which is equivalent to N * 2^k cond_k = (N_shifted_k>= A), that is: a 24-bit unsigned comparator, when N< <k>= True when A is true The shift operations for each path do not require actual barrel shifters—for a given value of k, the bit width of N_shifted_k is 8+k bits, with the high 8 bits representing N and the low k bits padded with zeros. This can be achieved through fixed hard-wired bit concatenation, without consuming any logic gates. The 24-bit comparator (comparing N_shifted_k with A after its bit width is extended to 24 bits) is pure combinational logic, and the kmax+1 comparators operate in complete parallel.

[0081] (4) Priority encoder selects k: The outputs of kmax+1 comparators are fed into the priority encoder in parallel to produce the minimum k value. Since cond_k satisfies monotonicity—if cond_k is true, then cond_j is true for all j>=k (because N*2^(k+1)>= N*2^k, and if N*2^k>= A, then N*2^(k+1) must be>= A)—the priority encoder is equivalent to a leading-one detector, which outputs the index k corresponding to the first true cond_k.

[0082] The specific implementation is a cascaded 2:1 MUX tree, as shown in the code example below: k[3] = cond_8 / / First check k>=8 (the judgment of k[3] is only needed when bpp>8) k[2] = k[3]? cond_12 : cond_4 k[1] = k[3:2]==2'b11 ? cond_14 : k[3:2]==2'b10 ? cond_10 : k[3:2]==2'b01 ? cond_6 : cond_2 k[0] = ... / / Select the corresponding cond according to the 8 cases of k[3:1]. The MUX tree has a depth of 4 levels (corresponding to a 4-bit k value), with each level being a 2:1 MUX, resulting in a total latency of approximately 4 cascaded MUXs plus the latency of one 24-bit comparator. For applications with bpp <= 8 (kmax = 7, k is 3 bits), the MUX tree depth is only 3 levels.

[0083] (5) Boundary protection for k value: The output of the priority encoder needs to pass through two boundary protection logics: Lower limit protection: If all cond_k are false (i.e., N<A), k is forced to 0. When k=0, N*2^0 = N. If N>=A does not hold, it indicates that the average error amplitude A / N>1. At this time, the Golomb base value corresponding to k=0 is 1, which degenerates into unary coding. This situation occurs during the parameter initialization phase (A=1024, N=1) or when the image content changes drastically, and k=0 ensures that the encoder can still work normally without deadlock.

[0084] Upper limit protection: The k value is clamped to kmax. In the JPEG-LS standard, the upper limit of k is determined by the image bit width: for an image with bpp=8, kmax=7, and for an image with bpp=16, kmax=15. The upper limit protection prevents k from exceeding the legal range and causing shift overflow or abnormal encoder status.

[0085] The entire process of k value generation described above — parallel shift splicing, kmax+1 channels of 24-bit comparison, priority encoding MUX tree, and boundary protection — is completed within single-cycle combinational logic. The critical path is: N shift splicing (hardwired with no delay) -> 24-bit comparator -> 4-stage MUX tree -> boundary clamping MUX.

[0086] II. Mapping transformation of the prediction error Merror (1) Mathematical principle of mapping: Golomb coding only processes non-negative integers, while the prediction error Errval is a signed number. The JPEG-LS standard defines a bijection that maps signed prediction errors one-to-one to non-negative integers Merror, so that errors with smaller absolute values (regardless of positive or negative) are mapped to smaller non-negative integers, thereby obtaining shorter code lengths in Golomb coding. A code example is as follows: If Errval >= 0: MErrval = 2 * Errval (positive errors are mapped to even numbers) If Errval < 0: MErrval = -2 * Errval - 1 (negative errors are mapped to odd numbers) The intuitive properties of this mapping: Errval=0 is mapped to MErrval=0; Errval=+1 is mapped to 2; Errval=-1 is mapped to 1; Errval=+2 is mapped to 4; Errval=-2 is mapped to 3; and so on. The mapped sequence is [0,1,2,3,4,5,...], corresponding to the original errors [0,-1,+1,-2,+2,-3,+3,...]. Errors with smaller absolute values are mapped to smaller non-negative integers, which is beneficial for Golomb coding to achieve a high compression ratio.

[0087] (2) Sign correction before mapping: In the conventional mode coding pipeline, the Merror output by the error selection module is the signed prediction error. First, it needs to be corrected based on the sign bit of the context index. A code example is shown below: Errval_signed = (sign == 1'b1) ? -Merror : Merror The `sign` parameter is determined by the MED prediction module when calculating the gradients of neighboring pixels, indicating the directionality of the current context. When `sign=-1`, `Merror` is inverted (two's complement inverted and incremented by one) to ensure that the sign of `Errval_signed` is consistent with the context direction. This correction is crucial for determining the sign of subsequent error mappings.

[0088] (3) Modulo Reduction: The Errval_signed after sign correction may exceed the range of pixel values. The JPEG-LS standard specifies that Errval_signed needs to be reduced to the range of (-RANGE / 2, +RANGE / 2] using modulo operations, where RANGE = 2^bpp (for b-bit lossless encoding, RANGE = MAXVAL + 1). The code example is as follows: If Errval_signed<-RANGE / 2: Errval_mod = Errval_signed + RANGE If Errval_signed>RANGE / 2: Errval_mod = Errval_signed - RANGE Otherwise: Errval_mod = Errval_signed In the hardware implementation, RANGE / 2 = 2^(bpp-1) is half of the maximum pixel value of the image. The decision is made in parallel by comparing the high-order bits of Errval_signed with the threshold of RANGE / 2. The modulo addition and subtraction (+RANGE or -RANGE) are performed by combinational logic adders / subtractors, and are completed in the same time as the MUX gating of the boundary judgment.

[0089] (4) Hardware implementation of signed-unsigned bijective mapping: The Errval_mod after modulo reduction is calculated separately according to the positive and negative signs. The code example is as follows: MErrval = (Errval_mod>= 0) ? (Errval_mod<<1) That is: for positive numbers, left shift by 1 bit, i.e., *2, with the least significant bit equal to 0 (for even numbers). : ((-Errval_mod)<<1) - 1 That is: for negative numbers: invert the value, shift left by 1 bit, and then subtract 1; the least significant bit will be 1 (for odd numbers). Hardware optimization analysis: The judgment of Errval_mod>=0: directly check the sign bit of Errval_mod (the highest bit corresponding to bit

[17] or bpp), single-bit combinational logic.

[0090] Positive path: Errval_mod<<1 (left shift by 1 bit, fill the least significant bit with 0), hard-wired with no delay, output is an even number.

[0091] Negative number path: (-Errval_mod)<<1 - 1 = ((~Errval_mod + 1)<<1) - 1 = (~Errval_mod<<1) + 2 - 1 = (~Errval_mod<<1) + 1. The equivalent implementation is: first, invert Errval_mod (bitwise NOT), then shift left by 1 bit (filling the least significant bit with 0), then add 1 (making the least significant bit 1, i.e., odd number). The key delay in this path is the inversion + shift + addition, all of which are combinational logic.

[0092] The two results are selected by a 2:1 MUX, with the selection signal being the sign bit of Errval_mod.

[0093] The entire mapping process (sign correction, modulo reduction, positive and negative splitting mapping to MUX output) is completed in a single-cycle combinational logic.

[0094] (5) Range Limiting of MErrval: The mapped MErrval is an unsigned number whose numerical range is mapped from the Errmod interval [-RANGE / 2, RANGE / 2], with a theoretical upper limit of RANGE (i.e., 2^bpp). However, the Golomb coding module itself requires the upper limit of the bit width of MErrval for code length calculation and length-limited coding decision. Therefore, a range clamp is applied to MErrval. The code example is as follows: MErrval_bounded = (MErrval>= 2*MAXVAL) ? (2*MAXVAL - 1) : MErrval Where MAXVAL = 2^bpp - 1 (maximum pixel value). This clamp ensures that MErrval does not exceed 2*MAXVAL-1, meaning the bit width of the mapped value does not exceed bpp+1 bits. For an image with bpp=8, the upper limit of MErrval is 511 (9 bits); for an image with bpp=16, the upper limit of MErrval is 131071 (17 bits). This clamp also provides a defined bit width constraint for the downstream Golomb coding module, simplifying its internal data path design.

[0095] III. Module Integration and Interface Timing The `coder_variables` module is positioned in the pipeline as follows: upstream, it receives the outputs of `context_updater` (A_new, B_new, C_new, N_new) and `error_select` (the actual `Merror` and `sign`), and downstream, it drives the `golomb` module (the `k` and `merror` values). Internally, the module contains two fully parallel data paths: Path 1 (k-value generation): A, N -> Parallel shift comparator array -> Priority encoding MUX tree -> Boundary protection -> k-output. The inputs are the updated A and N, and the delay is mainly determined by the 24-bit comparator and the 4-level MUX tree.

[0096] Path 2 (MErrval mapping): Merror, sign -> sign correction -> modulo reduction -> bijective mapping -> range clamping -> MErrval output. The input is the selected real Merror, and the delay is mainly determined by the inverter, adder, and MUX chain.

[0097] The two paths are independent and operate in complete parallel. The overall critical path delay is determined by the larger of the 24-bit comparator + MUX tree in path one (approximately 8~12ns) and the inversion + addition + MUX chain in path two (approximately 6~10ns). In typical FPGA implementations (such as the Xilinx 7 series), the delays of both paths are less than 15ns, which can meet the single-cycle timing convergence requirements for clock frequencies above 66MHz.

[0098] In summary, the encoding parameter generation and prediction error mapping engine, through a combination of parallel left-shift comparison chain and bijective mapping logic, simultaneously completes the determination of Golomb encoding parameters k and the mapping transformation of prediction error Merror within a single cycle. It forms a seamless connection with the context parameter adaptive update engine (Section 3.4.3), together constituting an efficient data path from parameter update to entropy encoding input in the conventional mode encoding pipeline.

[0099] Key technical parameters: (1) Context parameter BRAM depth: 400 addresses (0-399), covering the Q value range defined by the JPEG-LS standard (9-bit signed number, absolute value 0-364).

[0100] (2) BRAM initialization values: A=1024 (24 bits), B=0 (24-bit signed), C=0 (8-bit signed), N=1 (8 bits).

[0101] (3) Golomb coding parameter k: in the range of 0-15, determined by a left shift comparison chain (N<<n ≥ A).

[0102] (4) Limited-length Golomb coding threshold: limit = bpp × 4 (applicable to 8-16 bit image depth).

[0103] (5) Output code stream width: 128 bits (supporting external FIFO interface).

[0104] (6) Run-length index J table: 32 index values (J=0-15), covering run lengths from 0 to 65535+.

[0105] (7) Pixel bit width: supporting 8-16 bits (set via the bpp register).

[0106] (8) NEAR parameter: 0 (lossless mode) or a positive integer value (near-lossless mode), which affects qbpp = (near==0) ? bpp : bpp-1.

[0107] Embodiment 3 Embodiment 3 of the present invention adopts the system of Embodiment 2, and is applied to the lossless compression scenario of spaceborne remote sensing images. The input image is a 16-bit grayscale image with a resolution of 4096×4096 pixels. The working process is as follows: (1) The external controller inputs image row data row by row, and the row_en signal marks the row as valid.

[0108] (2) After system reset, the initialization module completes the initialization of all BRAMs within 401 clock cycles.

[0109] (3) After initial_finish is pulled high, pixel data enters the image_ram to complete row buffering and end-of-row detection.

[0110] (4) One pixel enters the compression pipeline per clock cycle, sequentially going through gradient calculation, mode decision, prediction, error calculation (including three paths of speculation), Golomb coding, and parameter update.

[0111] The variable-length code stream is packed into 128-bit words by the bitstream module and output to the external FIFO.

[0112] Technical results: At a clock frequency of 100MHz, the system throughput can reach 100M pixels / second, and it takes about 167 milliseconds to encode a 4096×4096 image (including initialization overhead). This represents a performance improvement of about 25% compared to the non-bypass solution (which requires about 25% of the pause cycle), while the number of logic units increases by only about 3% (mainly due to the bypass registers and comparators).

[0113] Example 4 Embodiment 4 of the present invention uses the system of Embodiment 2 and applies it to real-time lossless transmission of industrial cameras.

[0114] Input an 8-bit grayscale image with a resolution of 1920×1080 at 60fps. The system can meet real-time processing requirements at a clock speed of 75MHz. A dual-path bypass mechanism ensures continuous inter-frame encoding without frame drops in motion scenes, while three-path inference calculations ensure full pipeline load when the C value changes dynamically.

[0115] Example of parameter settings: When bpp=8: T1=18, T2=67, T3=276 (applicable to fixed configurations with bpp≥12; bpp=8 can be optimized separately). BRAM depth: 400 (covering the Q value range); Bitrate packet width: 128 bits; Run-length table J: 32-level index, covering the range 0~65535+; This system achieves zero-stop operation of the JPEG-LS pipeline encoder with minimal hardware overhead (approximately 3% logic increase) through three collaborative mechanisms: dual-channel data bypass, three-channel inference error calculation, and BRAM write bypass. While maintaining 100% standard compatibility, it significantly improves the encoding throughput.

[0116] It is worth noting that in the embodiments of the above system, the modules included are divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional module are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0117] Key technical points: (1) Dual-path independent address comparison and data bypass mechanism: To address the timing differences in reading parameter group abcn and parameter C_error in the JPEG-LS pipeline, independent address comparators (equ_abcn and equ_c_error) are set up to achieve dual-path independent bypass forwarding. When the read and write addresses are consistent, the latest calculated parameter value in the pipeline is directly bypassed to the previous stage, instead of reading the old value from the BRAM.

[0118] (2) Three-way prediction error calculation and delay selection: When the parameter C is not determined, the prediction error in three cases, C+1, C, and C-1, is calculated in parallel. After the value of C is determined, the true error value is selected by a three-to-one selector. Specifically, it includes three parallel error_deal submodules and selection logic based on the comparison result of c_out_select and c_error_select.

[0119] (3) BRAM write bypass buffer: Set a write bypass register at the output of the dual-port BRAM. When the read address is detected to be equal to the write address, output the latest write pipeline register value instead of the BRAM output value to avoid read and write conflicts at the same address of the FPGA BRAM.

[0120] (4) Context parameter adaptive update engine: including the normalization halving strategy when N≥64, the four-level boundary limit of B (B+2N / B+N / B / BN), and the sign adaptive adjustment of C when B overflows. All combinational logic is completed in one cycle.

[0121] (5) Dual-mode bit stream merging: The bit stream selection and merging logic in the compression module uses {golomb_bit_en, run_bit_en} as the status code to realize bubble-free splicing of Golomb code and run code in normal mode, run interrupt mode, and end-of-line interrupt mode.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.< / k>

Claims

1. A method for eliminating data hazards and recursive errors in a JPEG-LS lossless compression encoder pipeline, characterized in that, In a regular coding pipeline, the following steps are performed in each clock cycle to achieve a zero-stop pipeline: Real-time detection of read / write address conflicts; when read / write addresses are consistent, the latest calculated cumulative absolute error A, cumulative error sum B, prediction bias C, and context count N values ​​in the pipeline are directly forwarded. The three prediction errors are calculated in parallel, and the true error value is selected from them. Update the parameters based on the actual error value; Based on the updated parameters, the Golomb encoding parameter K is generated, and the merror value is obtained by mapping the actual error.

2. The method for eliminating data hazards and predicting errors in a JPEG-LS lossless compression encoder pipeline according to claim 1, characterized in that, The real-time detection of read / write address conflicts specifically includes: A dual-path independent address comparison is implemented to detect read / write address conflicts of the parameter group and the error value C_error, respectively. The parameter group includes: cumulative absolute error A, cumulative error sum B, prediction bias C, and context count N. When a conflict is detected, the parameter value that has just been updated in the pipeline stage is bypassed and used by the pipeline stage; otherwise, the latest calculated parameter value in the pipeline is forwarded directly.

3. The method for data hazard elimination and prediction error in a JPEG-LS lossless compression encoder pipeline according to claim 1, characterized in that, The parallel computation of three prediction errors and the selection of the true error value specifically includes: Based on the available C value in the current pipeline, C+1, C, and C-1 are used as the three possible values ​​of prediction deviation C, and the corresponding prediction errors Merror_out_1, Merror_out, and Merror_out_0 are calculated in parallel. Once the final updated value of parameter C is determined, it is compared with the three possible values ​​C+1, C, and C-1. The prediction error corresponding to the value that is equal to the final updated value is selected as the true error value and output.

4. The method for data hazard elimination and prediction error in a JPEG-LS lossless compression encoder pipeline according to claim 1, characterized in that, The updating of the parameters specifically includes: Phase 1: The prediction error Merror drives the basic summation of the cumulative absolute error A and the cumulative error B; the outputs of this phase are A_pre and B_pre. Second stage: Determine whether the context count N has reached the reset threshold. If yes, perform a halving operation on A, B, and N in parallel. Otherwise, A, B, and N retain their original values. The output of this stage is A_base, B_base, and N_base. The third stage: compare B_pre with integer multiples of N_base in parallel, limit and pull back B according to the comparison results, and generate the adjustment amount delta_C of the prediction deviation C at the same time. Fourth stage: Add the current value of prediction bias C, C_base, to delta_C to get C_pre. Check whether C_pre exceeds the range of 8-bit signed numbers [-128, 127]. If it overflows, saturate and limit the amplitude to the boundary value. Output the updated cumulative absolute error A, cumulative error sum B, prediction bias C, and context count N.

5. The method for data hazard elimination and prediction error in a JPEG-LS lossless compression encoder pipeline according to claim 1, characterized in that, The step of generating Golomb coding parameters K based on the updated parameters and obtaining the merror value by mapping the actual error specifically includes: Based on the updated cumulative absolute error A and context count N, the Golomb coding parameters K are generated by left-shifting the comparison chain; The error Merror is corrected for sign based on the sign bit of the context index, and then the value of merror is obtained by modulo reduction and range limitation.

6. The method for eliminating data hazards and predicting errors in a JPEG-LS lossless compression encoder pipeline according to claim 5, characterized in that, The method includes performing the following steps prior to a conventional production line: Receive pixel data streams, perform preprocessing and generate line end markers; Gradient calculation is performed for each pixel in each row of data stream. The context index Q is obtained by fusion calculation, and the encoding mode of the current pixel is determined by a four-state finite state machine. The encoding modes include: normal mode, run-length interruption mode, and line-end interruption mode; The predicted value of the current pixel is calculated based on the MED algorithm.

7. The method for data hazard elimination and prediction error in a JPEG-LS lossless compression encoder pipeline according to claim 6, characterized in that, The method includes performing the following steps after a conventional production line: Receive the K value and the merror value, perform limited-length Golomb encoding, and output the variable-length codeword and its effective length; Pack the bitstream for output.

8. A data hazard elimination and speculation error system for a JPEG-LS lossless compression encoder pipeline, characterized in that, Deployed in a regular coding pipeline, including: The context address management module is used to detect read and write address conflicts in real time. When the read and write addresses are consistent, the latest calculated cumulative absolute error A, cumulative error sum B, prediction bias C and context count N parameter values ​​in the pipeline are forwarded directly. The three-way error calculation module calculates errors and is used to calculate three types of prediction errors in parallel. The selection module is used to select the true error value from three prediction errors; The context parameter update module is used to update parameters based on the actual error value; and The encoding parameter generation module is used to generate Golomb encoding parameters K based on the updated parameters, and obtain the merror value by mapping the actual error.

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