Semiconductor memory and methods of making the same, semiconductor processing apparatus

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor memory and a preparation method and a semiconductor process equipment thereof. The preparation method of the semiconductor memory comprises the following steps: a gate forming step, forming a write transistor gate, a read transistor outer gate and a read transistor inner gate, wherein the read transistor inner gate is in a ring structure; a removing step, removing the material in the ring-shaped inner part of the read transistor inner gate, the material on the interface side of the write transistor gate to be formed with a gate dielectric layer, and the material between the read transistor outer gate and the read transistor inner gate, and reserving part of the supporting material of the read transistor inner gate; and an active structure forming step, sequentially forming a gate dielectric layer and a channel layer on the exposed surface of the write transistor gate, the exposed surface of the read transistor outer gate and the exposed surface of the read transistor inner gate. The semiconductor memory, the preparation method and the semiconductor process equipment provided by the application do not damage the subsequent channel layer, can optimize the transistor performance, and have high reading accuracy.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor memory and its fabrication method and semiconductor process equipment. Background Technology

[0002] As semiconductor process dimensions shrink, the miniaturization of traditional silicon-based memory (DRAM) faces bottlenecks. On the one hand, there are challenges in fabricating large capacitor structures with ultra-high aspect ratios; on the other hand, the improvement of in-plane storage density is approaching its limit.

[0003] DRAM memory cells, built using the ultra-low leakage current characteristics of oxide semiconductors, have two transistors (a write transistor and a read transistor), which simplifies the need for large capacitors and is less expensive than HBM (High Bandwidth Memory) technology. However, the fabrication methods of DRAM memory cells in related technologies are prone to damaging the channel, affecting transistor performance. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor memory and its fabrication method, so as to improve the technical problem of easy channel damage in the fabrication method of 2TOCDRAM memory cell in related technologies.

[0005] The method for fabricating a semiconductor memory provided by the present invention includes: In the gate formation step, a write transistor gate, a read transistor outer gate, and a read transistor inner gate are formed, wherein the read transistor inner gate is located between the write transistor gate and the read transistor outer gate, and the read transistor inner gate has a ring structure; The removal step involves removing the material inside the annular ring of the inner gate of the read transistor to expose the inner ring wall of the inner gate; removing the material on the interface side of the gate of the write transistor to expose the surface of the gate to expose the surface of the gate to expose the surface of the gate to expose the surface of the write transistor; and removing the material between the outer gate of the read transistor and the inner gate of the read transistor, while retaining a portion of the support material of the inner gate of the read transistor, so that the surface of the outer gate of the read transistor facing the inner gate of the read transistor and a portion of the surface of the outer ring wall of the inner gate of the read transistor are exposed. In the active structure formation step, a gate dielectric layer and a channel layer are sequentially formed on the exposed surface of the write transistor gate, the exposed surface of the read transistor outer gate, and the exposed surface of the read transistor inner gate.

[0006] Preferably, as one possible implementation, the gate formation step includes: A first write hole is formed in a predetermined forming region of the write bit line of the stacked structure, and a first read hole is formed in a predetermined forming region of the read bit line of the stacked structure; wherein, the stacked structure includes an alternately arranged isolation layer and an initial sacrificial layer; A portion of the initial sacrificial layer is removed via the first write aperture to form a write lateral slot; and a portion of the initial sacrificial layer is removed via the first read aperture to form a read outer lateral slot. A first gate conductive layer is formed on the inner wall of the first write hole and the inner wall of the write transverse groove; and a second gate conductive layer is formed on the inner wall of the first read hole and the inner wall of the read transverse groove. The remaining space between the first write hole and the write transverse slot is filled to form a write sacrificial layer; and the remaining space between the first read hole and the read transverse slot is filled to form a first read sacrificial layer.

[0007] Preferably, as one possible implementation, after forming the first read sacrificial layer, the gate formation step further includes: A first read-ground via is formed in a predetermined area at the ground terminal of the read transistor; By removing a portion of the initial sacrificial layer through the first read via, an in-read lateral trench is formed, exposing the sidewalls of the second gate conductive layer that were covered by the initial sacrificial layer. Remove the portion of the second gate conductive layer exposed to the first read hole; A second read sacrificial layer and a third gate conductive layer are sequentially formed on the inner wall of the first read ground hole and the inner wall of the read internal transverse slot; the remaining space of the first read ground hole and the read internal transverse slot is filled to form the third read sacrificial layer.

[0008] Preferably, as one possible implementation, the removal step includes: Remove the write sacrificial layer, the first read sacrificial layer, and the third read sacrificial layer; remove the portion of the second read sacrificial layer located between the third gate conductive layer and the second gate conductive layer to make the read outer lateral slot communicate with the read inner lateral slot; and retain the portion of the second read sacrificial layer located opposite to the second gate conductive layer in the third gate conductive layer to support the third gate conductive layer using the remaining second read sacrificial layer.

[0009] Preferably, as one possible implementation, after forming the third read sacrifice layer, the gate formation step further includes: A second write via is formed in a predetermined formation region of the write bit line, penetrating the write sacrificial layer to expose the first gate conductive layer; a second read bit via is formed in a predetermined formation region of the read bit line, penetrating the first read sacrificial layer to expose the second gate conductive layer; a second read ground via is formed in a predetermined formation region of the ground terminal of the read transistor, penetrating the third read sacrificial layer to expose the third gate conductive layer. The portion of the first gate conductive layer exposed to the second write via is removed, and the remaining first gate conductive layer forms the gate of the write transistor; the portion of the second gate conductive layer exposed to the second read via is removed, forming the outer gate of the read transistor; the portion of the third gate conductive layer exposed to the second read ground via is removed, forming the inner gate of the read transistor.

[0010] Preferably, as one possible implementation, the active structure forming step includes: sequentially forming a gate dielectric layer and a channel layer on the inner walls of the second write hole, the second read hole, the second read ground hole, the write lateral slot, the read outer lateral slot, and the read inner lateral slot; After the active structure formation step, the method further includes: forming the write bit line in the second write hole and the write lateral slot, forming the read bit line in the second read bit hole and the read outer lateral slot, and forming the read transistor ground terminal in the second read ground hole and the read inner lateral slot.

[0011] Preferably, as one possible implementation, after forming the write lateral trench and the read lateral trench and before forming the first gate conductive layer, the gate forming step further includes: thinning the upper and lower trench walls of the write lateral trench and the upper and lower trench walls of the read lateral trench; And / or, after forming the read in lateral trench and before removing the portion of the second gate conductive layer exposed to the first read ground via, the gate forming step further includes: thinning the upper and lower trench walls of the read in lateral trench and removing the portion of the isolation layer protruding from the first gate conductive layer; And / or, after removing the portion of the second gate conductive layer exposed to the first read via and before removing a portion of the isolation layer, the gate forming step further includes: deepening the read in-transverse trench.

[0012] Preferably, as one possible implementation, after the active structure forming step, the method further includes: A storage node, a capacitor dielectric, and a ground terminal are formed; wherein the storage node is located between a read transistor and a write transistor, the capacitor dielectric is connected to and surrounds the storage node, and the capacitor dielectric surrounds the ground terminal.

[0013] Preferably, as one possible implementation, prior to the gate formation step, the method further includes: Remove the portion of the initial sacrificial layer located on both sides of the predetermined formation region of the read transistor to form a read isolation trench; and remove the portion of the initial sacrificial layer located between the predetermined formation regions of two adjacent write transistors to form a write isolation trench. The read isolation slot is filled with isolation material to form a read isolation area; the write isolation slot is filled with isolation material to form a write isolation area.

[0014] Preferably, as one possible implementation, after forming the third read sacrificial layer, the gate formation step further includes: A first process hole is formed between the read isolation region and the write isolation region, penetrating the stacked structure; At least a portion of the material of the initial sacrificial layer is removed through the first process via to form a first lateral process trench to expose the first gate conductive layer; A portion of the material of the first gate conductive layer is removed via the first lateral process trench to expose the write sacrificial layer; The first transverse process groove is filled to form a process sacrificial layer.

[0015] Preferably, as one possible implementation, after the active structure forming step, the method further includes: A second process hole is formed between the read isolation region and the write isolation region, penetrating the stacked structure; The process sacrificial layer is removed through the second process hole to form a second transverse process groove; The portion of the gate dielectric layer of the write transistor exposed to the second lateral process trench is removed, without exposing the gate of the write transistor; and a portion of the material of the second read sacrificial layer is removed to expose the inner gate of the read transistor; Within the second transverse process trench, a storage node is formed, while retaining the first pore; A portion of the material of the storage node is removed through the first aperture to expose the isolation layer covered by the storage node, forming a grounding hole; Through the grounding hole, a portion of the material of the isolation layer is removed to form a third lateral process trench connecting the grounding holes on both sides of the memory node, and at least a portion of the upper and lower surfaces of the memory node is exposed to the third lateral process trench, while the portion of the isolation layer located between the third lateral process trench and the write transistor and the read transistor is retained. A capacitor dielectric is formed on the inner wall of the grounding hole and the third transverse process groove; Fill the remaining space of the grounding hole and the third transverse process groove to form a grounding terminal.

[0016] Preferably, as one possible implementation, forming a storage node within the second transverse process tank includes: sequentially forming a second contact layer and a second adhesion layer on the inner wall of the second transverse process tank; filling the remaining space of the second transverse process tank to form a storage node conductive layer; wherein, the storage node includes a second contact layer, a second adhesion layer, and a storage node conductive layer; And / or, filling the remaining space of the grounding hole and the third transverse process groove includes: forming a barrier layer on the inner wall of the grounding hole and the third transverse process groove; filling the remaining space of the grounding hole and the third transverse process groove to form a grounding conductive layer.

[0017] Preferably, as one possible implementation, after forming the first gate conductive layer and the second gate conductive layer, the method further includes: In the same storage cell, a third process via is formed on the side of the write isolation region opposite to the read isolation region to expose the initial sacrificial layer; a fourth process via is formed on the side of the read isolation region opposite to the write isolation region to expose the initial sacrificial layer. The initial sacrificial layer is removed through the third process hole to form a first transverse groove for the letter line; the initial sacrificial layer is removed through the fourth process hole to form a second transverse groove for the letter line. The first gate conductive layer and the second gate conductive layer are thickened. Fill the remaining space of the third process hole and the horizontal groove of the first character line, and retain the second gap to form a writing line; fill the remaining space of the fourth process hole and the horizontal groove of the second character line, and retain the third gap to form a reading line; Through the second aperture, a portion of the material of the write word line and a portion of the material of the first gate conductive layer are removed sequentially to expose the isolation layer covered by the first gate conductive layer, forming a first word line isolation aperture; through the third aperture, a portion of the material of the read word line and a portion of the material of the second gate conductive layer are removed sequentially to expose the isolation layer covered by the second gate conductive layer, forming a second word line isolation aperture; The isolation holes for the first and second letter lines are filled with insulating material.

[0018] The semiconductor memory provided by the present invention includes a read transistor and a write transistor, and the semiconductor memory is prepared by any of the semiconductor memory preparation methods described above.

[0019] The semiconductor process equipment provided by the present invention includes a process chamber, an air intake assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller includes at least one processor and at least one memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements the semiconductor memory fabrication method described in any of the above claims.

[0020] Compared with the prior art, the beneficial effects of the present invention are as follows: The fabrication method of this invention can form an annular inner gate of a read transistor. Based on this structure, by removing the material inside the annular inner gate, a through hole can be formed on the inner side of the annular inner gate, exposing the inner ring wall of the read transistor inner gate. By removing the material on the interface side of the write transistor gate to be formed as the gate dielectric layer, a slot can be formed on the interface side of the write transistor gate, exposing the surface of the write transistor gate to be formed as the gate dielectric layer. By removing the material between the outer gate and the inner gate of the read transistor, a slot can be formed between the inner gate and the outer gate, exposing the surface of the outer gate facing the inner gate and a portion of the surface of the outer ring wall of the inner gate. During the material removal process, a portion of the supporting material of the inner gate is retained, so that the inner gate can be independent of the outer gate. After material removal is completed, a gate dielectric layer can be formed on the exposed surfaces of the write transistor gate, the read transistor outer gate, and the read transistor inner gate to cover the exposed surfaces of the write transistor gate, the read transistor outer gate, and the read transistor inner gate. Then, a channel layer is formed on the exposed surfaces of the gate dielectric layer. Thus, the fabrication of the gate and active structure of the semiconductor memory is completed.

[0021] It should be noted that in this invention, the formation processes of the write transistor gate, read transistor outer gate, read transistor inner gate, and gate dielectric layer are all performed before the formation process of the channel layer. Therefore, it will not damage the subsequent channel layer, optimize transistor performance, and thus optimize the performance of the semiconductor memory. In addition, the read transistor obtained by this invention has an outer gate and an inner gate. The inner gate can store data, and the outer gate can enable the selection of the read transistor. When a memory cell is not selected, its row can be completely turned off. Therefore, when reading memory cells in other rows, the unselected memory cells will not contribute leakage current, thereby significantly improving the reading accuracy. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0023] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor memory according to an embodiment of the present invention; Figure 2-Figure 28b A schematic diagram of the structure corresponding to the corresponding steps of the semiconductor memory fabrication method provided in the embodiments of the present invention; Figure 29a and Figure 29b This is a cross-sectional view of a semiconductor memory provided in an embodiment of the present invention; Figure 30 This is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of the present invention. Detailed Implementation

[0024] One related technology is the vertical CAA (channel-all-around) transistor structure based on IGZO (Indium Gallium Zinc Oxide). This structure utilizes two transistors stacked vertically to form a 2T0C DRAM memory cell, where the write transistor is on top and the read transistor is below. Charge is written to the gate of the read transistor, and the DRAM state can be read non-destructively based on the current of the read transistor. However, this 2T0C DRAM memory cell structure requires each layer of transistors to be fabricated separately, making true three-dimensional stacking impossible. Furthermore, the memory nodes are floating, and during high-density integration, parasitic capacitance affects the memory node potential, leading to unstable read transistor current. The read transistor switching state is only related to the memory node potential, resulting in significant cross-leakage within the array.

[0025] Related technology two involves a 2T0C DRAM cell based on a Channel-side Word-Line (CSWL) structure. In this structure, the back gate of the read transistor is connected to the drain of the write transistor. The back gate capacitance serves as the storage capacitance, and the outer gate of the read transistor acts as the read gate. In this 2T0C DRAM cell, the back gate of the read transistor is deposited on its channel. Therefore, it is formed after the channel and requires the removal of the sacrificial layer. This damages the channel of the read transistor, affecting its performance. Furthermore, the channels of the read transistor and the write transistor are fabricated separately, complicating the manufacturing process. Although true three-dimensional stacking can be achieved, the memory nodes remain floating. During high-density integration, parasitic capacitance still affects the memory node potential, and the read transistor current remains unstable.

[0026] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0028] Figure 1 A schematic flowchart of a method for fabricating a semiconductor memory according to an embodiment of the present invention is provided, the method comprising: S102, gate forming step, forming the write transistor gate, the read transistor outer gate and the read transistor inner gate, wherein the read transistor inner gate is located between the write transistor gate and the read transistor outer gate, and the read transistor inner gate is a ring structure.

[0029] Specifically, see Figure 18 The write transistor gate 371, the read transistor outer gate 372, and the read transistor inner gate 373 are preferably formed simultaneously, but they can also be formed in stages. When formed simultaneously, the three are made of the same material; when formed in stages, the three can be made of the same or different materials.

[0030] S104, Removal Step: Remove the material inside the annular ring of the inner gate of the read transistor to expose the inner ring wall of the inner gate of the read transistor; remove the material on the interface side of the gate dielectric layer to be formed of the write transistor gate to expose the surface of the gate dielectric layer to be formed of the write transistor gate; and remove the material between the outer gate of the read transistor and the inner gate of the read transistor, retaining part of the support material of the inner gate of the read transistor to expose the surface of the outer gate of the read transistor facing the inner gate of the read transistor and part of the surface of the outer ring wall of the inner gate of the read transistor.

[0031] Specifically, see Figure 18 , Figure 19a and Figure 19b The material between the outer gate 372 and the inner gate 373 of the read transistor, the material inside the annular layer of the inner gate 373 of the read transistor, and the material on the interface side of the gate dielectric layer to be formed covering the gate 371 of the write transistor are preferably removed simultaneously, but can also be removed in stages.

[0032] S106, Active structure formation step, a gate dielectric layer and a channel layer are sequentially formed on the exposed surface of the write transistor gate, the exposed surface of the read transistor outer gate, and the exposed surface of the read transistor inner gate.

[0033] Specifically, see Figures 19a-20bThe gate dielectric layer 410 of the exposed surfaces of the write transistor gate 371, the read transistor outer gate 372, and the read transistor inner gate 373 is preferably formed simultaneously, but it can also be formed in stages. When formed simultaneously, the materials of the three are the same; when formed in stages, the materials of the three can be the same or different. The channel layer 420 of the exposed surfaces of the write transistor gate 371, the read transistor outer gate 372, and the read transistor inner gate 373 is preferably formed simultaneously, but it can also be formed in stages. When formed simultaneously, the materials of the three are the same; when formed in stages, the materials of the three can be the same or different.

[0034] The fabrication method in this embodiment can form an annular inner gate 373 of the read transistor. Based on this structure, by removing the material inside the annular inner gate 373, a through hole can be formed on the inner side of the annular inner gate 373, exposing the inner ring wall of the read transistor inner gate 373. By removing the material on the interface side of the write transistor gate 371 where the gate dielectric layer 410 to be formed can be formed, a slot can be formed on the interface side of the write transistor gate 371, exposing the surface of the write transistor gate 371 where the gate dielectric layer 410 to be formed can be exposed. By removing the material between the read transistor outer gate 372 and the read transistor inner gate 373, a slot can be formed between the read transistor inner gate 373 and the read transistor outer gate 372, exposing the surface of the read transistor outer gate 372 facing the read transistor inner gate 373 and a portion of the surface of the outer ring wall of the read transistor inner gate 373. During the material removal process, a portion of the support material of the read transistor inner gate 373 is retained, so that the read transistor inner gate 373 can be independent of the read transistor outer gate 373. After material removal is completed, a gate dielectric layer 410 is formed on the exposed surfaces of the write transistor gate 371, the read transistor outer gate 372, and the read transistor inner gate 373. The gate dielectric layer 410 covers the exposed surfaces of the write transistor gate 371, the read transistor outer gate 372, and the read transistor inner gate 373. Then, a channel layer 420 is formed on the exposed surfaces of the gate dielectric layer 410. Thus, the fabrication of the gate and active structure of the semiconductor memory is completed.

[0035] It should be noted that in this embodiment, the formation processes of the write transistor gate 371, the read transistor outer gate 372, the read transistor inner gate 373, and the gate dielectric layer 410 are all performed before the formation process of the channel layer 420. Therefore, they will not damage the subsequent channel layer 420, thus optimizing transistor performance and consequently optimizing the performance of the semiconductor memory. Furthermore, the read transistor fabricated in this embodiment has an outer gate and an inner gate. The inner gate can store data, and the outer gate can enable the selection of the read transistor. When a memory cell is not selected, its row can be completely turned off. Therefore, when reading memory cells in other rows, the unselected memory cells will not contribute leakage current, thereby significantly improving read accuracy.

[0036] See Figure 2 Before the gate formation step S102 described above, an isolation layer 110 and an initial sacrificial layer 120 can be alternately deposited on the substrate to form a stacked structure. Specifically, the material of the isolation layer 110 can be silicon oxide, and the material of the initial sacrificial layer 120 can be silicon nitride. Both can be achieved by methods such as chemical vapor deposition and physical vapor deposition. In addition, this combination of materials can make the isolation layer and the initial sacrificial layer have a high etching selectivity, thereby reducing damage to the initial sacrificial layer when the isolation layer is removed in the subsequent process; similarly, the damage to the isolation layer can be reduced when the initial sacrificial layer is removed in the subsequent process.

[0037] The gate formation step S102 described above may specifically include the following steps: S201, see S201. Figure 4a and Figure 4b A first write hole 311 is formed in the predetermined forming area of ​​the write bit line of the stacked structure, and a first read bit hole 312 is formed in the predetermined forming area of ​​the read bit line of the stacked structure.

[0038] The first write hole 311 and the first read hole 312 can both be formed by etching the stacked structure using methods such as plasma etching. Preferably, they are formed simultaneously, but they can also be formed in steps.

[0039] S202, see S202. Figure 5a and Figure 5b A portion of the initial sacrificial layer 120 is removed via the first write hole 311 to form a write lateral groove 313; and a portion of the initial sacrificial layer 120 is removed via the first read hole 312 to form a read lateral groove 314.

[0040] The internal space of the write lateral trench 313 can serve as a reserved space for the subsequent formation of the gate and related structures of the write transistor, while the internal space of the read lateral trench 314 can serve as a reserved space for the subsequent formation of the outer gate and related structures of the read transistor. Both the write lateral trench 313 and the read lateral trench 314 can be formed by etching the initial sacrificial layer using methods such as free radical etching or wet etching. Preferably, they are formed simultaneously, but they can also be formed in stages.

[0041] S203, see S203. Figure 7a and Figure 7b A first gate conductive layer 321 is formed on the inner wall of the first write hole 311 and the inner wall of the write transverse groove 313; and a second gate conductive layer 322 is formed on the inner wall of the first read hole 331 and the inner wall of the read transverse groove 314.

[0042] The first gate conductive layer 321 can serve as the initial structure for forming the write transistor gate 371 in subsequent processes, and the second gate conductive layer 322 can serve as the initial structure for forming the read transistor outer gate 372 in subsequent processes. The first gate conductive layer 321 and the second gate conductive layer 322 can be made of materials with good conductivity such as titanium nitride, and can be formed by atomic layer deposition. Preferably, they are formed simultaneously, but they can also be formed in stages.

[0043] S204, see also Figure 7a and Figure 7b The remaining space of the first write hole 311 and the write transverse slot 313 is filled to form a write sacrificial layer 323; and the remaining space of the first read hole 312 and the read transverse slot 314 is filled to form a first read sacrificial layer 324.

[0044] The write sacrificial layer 323 serves as a protective layer for the first gate conductive layer 321, and the first read sacrificial layer 324 serves as a protective layer for the second gate conductive layer 322. Their presence prevents subsequent processes from affecting the integrity of the write transistor gate 371 and the read transistor outer gate 372. The write sacrificial layer 323 and the first read sacrificial layer 324 can be made of silicon nitride and can be formed by chemical vapor deposition. Preferably, they are formed simultaneously, but they can also be formed in stages.

[0045] S205, see S205. Figure 8a and Figure 8b A first read-ground hole 331 is formed in a predetermined forming region at the ground terminal of the read transistor.

[0046] The predetermined formation area of ​​the read transistor ground terminal is located between the predetermined formation area of ​​the write bit line and the predetermined formation area of ​​the read bit line. The first read ground hole 331 can be formed by etching the stacked structure using methods such as plasma etching.

[0047] S206, see S206. Figure 9a and Figure 9b Through the first read-ground via 353, a portion of the initial sacrificial layer 120 is removed to form an internal transverse trench 332, exposing the sidewall of the second gate conductive layer 322 that was covered by the initial sacrificial layer 120.

[0048] The read-inner lateral trench 332 serves as a reserved space for the subsequent formation of the read transistor inner gate 373 and its related structures. It exposes the sidewalls of the second gate conductive layer 322 that were originally covered by the initial sacrificial layer 120, facilitating the subsequent local removal of the second gate conductive layer 322. The read-inner lateral trench 332 can be formed by etching the initial sacrificial layer 120 using methods such as free radical etching or wet etching.

[0049] S207, see S207. Figure 10a and Figure 10b The portion of the second gate conductive layer 322 exposed to the first read hole 331 is removed. This step can be achieved by etching the second gate conductive layer 322 using methods such as free radical etching or wet etching.

[0050] After removing the portion of the second gate conductive layer 322 exposed to the first read ground via 353, the second gate conductive layer 322 will form an opening connecting to the read internal transverse groove 332, which meets the structural requirements of the read transistor. Preferably, after removing the portion of the second gate conductive layer 322 exposed to the first read ground via 331, a groove is formed in the first read sacrificial layer 324 so that the second gate conductive layer 322 breaks more completely at the removed location.

[0051] S208, see S208. Figures 12a-13b A second read sacrificial layer 341 and a third gate conductive layer 342 are sequentially formed on the inner wall of the first read ground hole 331 and the inner wall of the read internal transverse groove 332; the remaining space of the first read ground hole 331 and the read internal transverse groove 332 is filled to form a third read sacrificial layer 343.

[0052] The third gate conductive layer 342 serves as the initial structure for forming the inner gate 373 of the read transistor in subsequent processes. The second read sacrificial layer 341 serves as a protective layer for the second gate conductive layer 322 and also as a supporting structure for the third gate conductive layer 342, providing a foundation for the subsequent formation of the outer gate 372 and inner gate 373 of the read transistor. The third read sacrificial layer 343 serves as a protective layer for the third gate conductive layer 342. The material of the second read sacrificial layer 341 can be polycrystalline silicon, amorphous silicon, etc., and it can be formed by chemical vapor deposition. The material of the third gate conductive layer 342 can be a material with good conductivity, such as titanium nitride, and it can be formed by atomic layer deposition. The material of the third read sacrificial layer 343 can be silicon nitride, and it can be achieved by chemical vapor deposition.

[0053] S209, see S209. Figure 17a and Figure 17bA second write via 351 is formed in a predetermined formation region of write bit line 510, penetrating the write sacrificial layer 323, to expose the first gate conductive layer 321; a second read via 352 is formed in a predetermined formation region of read bit line 520, penetrating the first read sacrificial layer 324, to expose the second gate conductive layer 322; and a second read ground via 352 is formed in a predetermined formation region of read transistor ground terminal, penetrating the third read sacrificial layer 343, to expose the third gate conductive layer 342.

[0054] The second write hole 351, the second read hole 352, and the second read ground hole 353 can all be formed by etching methods such as plasma etching. It is preferred that the three are formed simultaneously, but they can also be formed in stages.

[0055] After this step is completed, the portion of the first gate conductive layer 321 originally formed on the wall of the first write via 351 can be exposed, while the portion originally formed on the wall of the first write lateral trench 313 is still covered by the remaining write sacrificial layer 323; the portion of the second gate conductive layer 322 originally formed on the wall of the first read via 312 can be exposed, while the portion originally formed on the wall of the first read outer lateral trench 314 is still covered by the remaining first read sacrificial layer 324, the remaining second read sacrificial layer 341 and the remaining third read sacrificial layer 343; the portion of the third gate conductive layer 342 originally formed on the wall of the first read ground via 331 can be exposed, while the portion originally formed on the wall of the first read inner lateral trench 332 is still covered by the third read sacrificial layer 343.

[0056] S210, see S210. Figure 17a and Figure 18 The portion of the first gate conductive layer 321 exposed to the second write via 311 is removed, leaving the remaining first gate conductive layer 321 to form the write transistor gate 371; the portion of the second gate conductive layer 322 exposed to the second read via 352 is removed, forming the read transistor outer gate 372; the portion of the third gate conductive layer 342 exposed to the second read ground via 353 is removed, forming the read transistor inner gate 373. This step can be achieved using methods such as free radical etching or wet etching.

[0057] In this configuration, the inner gate 373 of the read transistor is located between the outer gate 372 of the read transistor and the gate 371 of the write transistor. The cross-section of the inner gate 373 is annular, while the cross-sections of both the gate 371 and the outer gate 372 are approximately C-shaped, with the C-shaped openings facing the inner gate 373. This arrangement allows for the stacking of multiple memory cells along the thickness direction of the stacked structure. The number of memory cell layers can be controlled by the number of layers in the stacked structure, thereby achieving a three-dimensional stacked memory cell array.

[0058] See Figures 18-19bSpecifically, step S104 may include: removing the write sacrificial layer 323, the first read sacrificial layer 324, and the third read sacrificial layer 343; removing the portion of the second read sacrificial layer 341 located between the third gate conductive layer 342 and the second gate conductive layer 322, so that the read outer lateral trench 314 and the read inner lateral trench 332 are connected; and retaining the portion of the second read sacrificial layer 341 located opposite to the second gate conductive layer 322, so as to use the remaining second read sacrificial layer 341 to support the third gate conductive layer 342. In this way, space is provided for the subsequent formation of the active structure, and the inner gate 373 of the read transistor can be supported in a predetermined position. Specifically, this can be achieved through methods such as free radical etching, atomic layer etching, and wet etching.

[0059] See Figure 20a and Figure 20b Specifically, step S106 may include: sequentially forming a gate dielectric layer 410 and a channel layer 420 on the inner walls of the second write via 351, the second read via 352, the second read ground via 353, the write lateral trench 313, the read outer lateral trench 314, and the read inner lateral trench 332, thereby completing the fabrication of the active structure. The gate dielectric layer 410 can be made of one or more combinations of hafnium oxide, aluminum oxide, silicon oxide, zirconium oxide, lanthanum oxide, and tantalum oxide, while the channel layer 420 can be made of an oxide semiconductor material containing elements such as indium, gallium, zinc, tin, and aluminum. Both can be formed by atomic layer deposition.

[0060] See Figure 20a and Figure 20b After step S106 above, the method provided in this embodiment further includes: forming a write bit line 510 in the second write hole 351 and the write transverse groove 313, forming a read bit line 520 in the second read bit hole 352 and the read outer transverse groove 314, and forming a read transistor ground terminal 530 in the second read ground hole 352 and the read inner transverse groove 332, thus completing the preparation of the terminal conductive stack.

[0061] Specifically, a first contact layer 541 can be formed on the inner walls of the second write hole 351, the second read hole 352, the second read ground hole 353, the write lateral groove 313, the read outer lateral groove 314, and the read inner lateral groove 332; then, a first adhesion layer 542 can be formed on the inner walls of the second write hole 351, the second read hole 352, the second read ground hole 353, the write lateral groove 313, the read outer lateral groove 314, and the read inner lateral groove 332; finally, a terminal conductive layer 543 can be filled in the remaining space of the second write hole 351, the second read hole 352, the second read ground hole 353, the write lateral groove 313, the read outer lateral groove 314, and the read inner lateral groove 332.

[0062] The first contact layer 541 can be made of an oxide conductor material containing elements such as indium, zinc, and tin, and can be formed by atomic layer deposition. The first adhesion layer 542 can be made of titanium nitride and can be formed by atomic layer deposition. The terminal conductive layer 543 can be made of tungsten, ruthenium, molybdenum, etc., and can be achieved by chemical vapor deposition.

[0063] The first contact layer 541, the first adhesive layer 542, and the terminal conductive layer 543 formed in the second write hole 351 and the write transverse groove 313 can form a write bit line 510. The first contact layer 541, the first adhesive layer 542, and the terminal conductive layer 543 formed in the second read hole 352 and the read outer transverse groove 314 can form a read bit line 520. The first contact layer 541, the first adhesive layer 542, and the terminal conductive layer 543 formed in the second read ground hole 353 and the read inner transverse groove 332 can form a read transistor ground terminal 530.

[0064] In some alternative embodiments, see Figure 6 In step S102 above, after forming the write lateral trench 313 and the read lateral trench 314 and before forming the first gate conductive layer 321, the following step is also included: thinning the upper and lower trench walls of the write lateral trench 313 and the read lateral trench 314 to increase the volume ratio of the write transistor and the read transistor in the stacked structure, thereby improving performance and integration density. Specifically, this can be achieved by etching the isolation layer 110 using methods such as free radical etching and wet etching.

[0065] In some alternative embodiments, see Figure 9a and Figure 9b In step S102 above, after forming the read-in lateral trench 332 and before removing the portion of the second gate conductive layer 322 exposed to the first read ground via 331, the following steps are also included: thinning the upper and lower trench walls of the read-in lateral trench 332 and removing the portion of the isolation layer 110 protruding from the first gate conductive layer 321, so as to increase the volume ratio of the read transistor in the stacked structure and improve performance and integration density. Specifically, the isolation layer 110 can be etched by methods such as free radical etching and wet etching.

[0066] In some alternative embodiments, see Figure 11a and Figure 11b In step S102 above, after removing the portion of the second gate conductive layer 322 exposed to the first read ground via 331 and before removing a portion of the isolation layer 110, the gate formation step further includes: deepening the read internal lateral trench 332 to ensure the structural reliability of the read transistor. Specifically, this can be achieved by etching the initial sacrificial layer 120 and the first read sacrificial layer 324 using methods such as free radical etching and wet etching.

[0067] See Figure 29a and Figure 29b After step S106 above, the method provided in this embodiment may further include: forming a storage node 630, a capacitor dielectric 670, and a ground terminal 680; wherein, the storage node 630 is located between the read transistor and the write transistor, the capacitor dielectric 670 is connected to and surrounds the storage node 630, and the capacitor dielectric 670 surrounds the ground terminal 680. In this way, a small capacitor can be grounded, which can avoid the influence of parasitic capacitance on the potential of the storage node 630 and improve the current stability of the read transistor.

[0068] See Figure 3 In some optional embodiments, prior to step S102 above, the method provided in this embodiment further includes: removing portions of the initial sacrificial layer 120 located on both sides of the predetermined formation region of the read transistor to form a read isolation trench; and removing portions of the initial sacrificial layer 120 located between the predetermined formation regions of two adjacent write transistors to form a write isolation trench. An isolation material is filled into the read isolation trench to form a read isolation region 210; an isolation material is filled into the write isolation trench to form a write isolation region 220. The read isolation trench and the write isolation trench can be formed by etching a stacked structure; the material of the read isolation region 210 and the write isolation region 220 can be silicon oxide, which can be formed by chemical vapor deposition.

[0069] On the one hand, when performing step S102, the read isolation region 210 and the write isolation region 220 can serve as the removal boundary of the initial sacrificial layer 120, forming the lateral boundaries of the write lateral slot 313, the read outer lateral slot 314 and the read inner lateral slot 332, providing a basis for obtaining storage cells of a predetermined size in the future; on the other hand, the existence of the read isolation region 210 and the write isolation region 220 can also separate storage cells in different rows in the same layer, providing a basis for arranging multiple storage cells in the same layer.

[0070] In step S102 above, after forming the third read sacrifice layer 343, the following steps are also included: S211, see also Figure 14 A first process hole 361 is formed between the read isolation area 210 and the write isolation area 220, penetrating the stacked structure.

[0071] The first process hole 361 can be formed by plasma etching of a stacked structure.

[0072] S212, see S212. Figure 15a and Figure 15b At least a portion of the material of the initial sacrificial layer 120 is removed through the first process hole 361 to form a first lateral process trench 362 to expose the first gate conductive layer 321.

[0073] The first transverse process trench 362 can be formed by etching the initial sacrificial layer 120 through methods such as free radical etching and wet etching.

[0074] S213, see also Figure 16 A portion of the material of the first gate conductive layer 321 is removed via the first lateral process trench 362 to expose the write sacrificial layer 323.

[0075] This step can be achieved by etching the first gate conductive layer 321 using methods such as free radical etching or wet etching.

[0076] S214, see also Figure 16 The first transverse process groove 362 is filled to form a process sacrificial layer 363.

[0077] The process sacrificial layer 363 can be made of silicon nitride. Preferably, the material of the process sacrificial layer 363 is consistent with the material of the initial sacrificial layer 120. The process sacrificial layer 120 can be formed by chemical vapor deposition.

[0078] Thus, by removing part of the material of the first gate conductive layer 321, the source and drain electrodes formed subsequently can be exposed.

[0079] Following step S106 above, the method provided in this embodiment may further include: S301, see S301. Figure 25 A second process hole 610 is formed between the read isolation area 210 and the write isolation area 220, penetrating the stacked structure.

[0080] The second process hole 610 can be formed by etching the stacked structure using methods such as plasma etching.

[0081] S302, see S302. Figure 26a and Figure 26b The process sacrificial layer 363 is removed through the second process hole 610 to form the second transverse process groove 620.

[0082] The second transverse process trench 620 can be formed by etching the process sacrificial layer 363 through methods such as free radical etching, atomic layer etching, and wet etching.

[0083] S303, see S303. Figure 26a and Figure 26b The portion of the gate dielectric layer 410 of the write transistor exposed to the second lateral process trench 620 is removed, and the gate 371 of the write transistor is not exposed; and a portion of the material of the second read sacrificial layer 341 is removed to expose the inner gate 373 of the read transistor.

[0084] This step can be achieved by etching the second read sacrificial layer 341 and the gate dielectric layer 410 of the write transistor using methods such as free radical etching, atomic layer etching, and wet etching.

[0085] S304, see S304. Figure 27a and Figure 27b Within the second transverse process groove 620, a storage node 630 is formed, and the first aperture 640 is retained.

[0086] Since the write transistor gate 371 is not exposed to the second lateral process trench 620, the memory node 630 formed in the second lateral process trench 620 and the write transistor gate 371 can be separated by the gate dielectric layer 410 between them; at the same time, since the read transistor inner gate 373 is exposed to the second lateral process trench 620, the memory node 630 can directly contact the read transistor inner gate 373.

[0087] S305, see S305. Figure 28b Through the first aperture 640, a portion of the material of the storage node 630 is removed to expose the isolation layer 110 covered by the storage node 630, forming a grounding aperture 650.

[0088] The grounding hole 650 can be formed by etching back the memory node 630 within the first aperture 640. The etching back method can be any one of free radical etching, atomic layer etching, wet etching, etc., to disconnect the memory nodes 630 of different layers.

[0089] S306, see S306. Figure 28a and Figure 28b By removing part of the material of the isolation layer 110 through the grounding hole 650, a third lateral process trench 660 is formed connecting the grounding holes 650 on both sides of the memory node 630, and at least part of the upper and lower surfaces of the memory node 630 is exposed to the third lateral process trench 660, while the portion of the isolation layer 110 located between the third lateral process trench 362 and the write transistor and read transistor is retained.

[0090] The third transverse process trench 362 can be formed by etching the isolation layer 110 through methods such as free radical etching, atomic layer etching, and wet etching.

[0091] S307, see S307. Figure 29a and Figure 29b A capacitor dielectric 670 is formed on the inner wall of the grounding hole 650 and the third transverse process groove 660.

[0092] The capacitor dielectric 670 can be made of one or more combinations of hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and niobium oxide, and can be formed by atomic layer deposition.

[0093] S308, see also Figure 29a and Figure 29b The remaining space of the grounding hole 650 and the third transverse process groove 660 is filled to form the grounding terminal 680.

[0094] The grounding terminal 680 can be formed by deposition.

[0095] It should be noted that the third transverse process groove 660 and the grounding hole 650 can form a groove surrounding the storage node 630, thereby the capacitor dielectric 670 and the grounding terminal 680 formed therein can surround the storage node 630 to form a grounding small capacitor.

[0096] See also Figure 28a and Figure 28b Specifically, step S304 may include: forming a second contact layer 631 and a second adhesion layer 632 sequentially on the inner wall of the second transverse process tank 620; filling the remaining space of the second transverse process tank 620 to form a storage node conductive layer 633, wherein the second contact layer 631, the second adhesion layer 632, and the storage node conductive layer 633 can constitute the storage node 630. The material of the second contact layer 631 may be an oxide conductor containing elements such as indium, zinc, and tin, which can be formed by atomic layer deposition; the material of the second adhesion layer 632 may be titanium nitride, which can be formed by atomic layer deposition; the material of the storage node conductive layer 633 may be tungsten, ruthenium, molybdenum, etc., which can be formed by chemical vapor deposition, and retaining the first pore 640.

[0097] See also Figure 29a and Figure 29b Specifically, step S308 may include: forming a barrier layer 681 on the inner wall of the grounding hole 650 and the third transverse process trench 660; filling the remaining space of the grounding hole 650 and the third transverse process trench 660 to form a grounding conductive layer 682, wherein the barrier layer 681 and the grounding conductive layer 682 can form the grounding terminal 680. The material of the barrier layer 681 can be titanium nitride, which can be formed by atomic layer deposition; the material of the grounding conductive layer 682 can be tungsten, ruthenium, molybdenum, etc., which can be formed by chemical vapor deposition.

[0098] After forming the first gate conductive layer 321 and the second gate conductive layer 322, the method provided in this embodiment may further include: S401, see S401. Figure 21 In the same storage cell, a third process via 711 is formed on the side of the write isolation region 220 opposite to the read isolation region 210 to expose the initial sacrificial layer 120; a fourth process via 712 is formed on the side of the read isolation region 210 opposite to the write isolation region 220 to expose the initial sacrificial layer 120.

[0099] The third process hole 711 can be formed by etching the write isolation region 220 through methods such as plasma etching, and the fourth process hole 712 can be formed by etching the read isolation region 210 through methods such as plasma etching.

[0100] S402, see S402. Figure 22a and Figure 22b The initial sacrificial layer 120 is removed through the third process hole 711 to form the first transverse groove 721 of the character line; the initial sacrificial layer 120 is removed through the fourth process hole 712 to form the second transverse groove 722 of the character line.

[0101] The first word line lateral trench 721 and the second word line lateral trench 722 can be formed by etching the initial sacrificial layer 120 using methods such as free radical etching and wet etching. After the first word line lateral trench 721 is formed, the first gate conductive layer 321 (write transistor gate 371) will be exposed; after the second word line lateral trench 722 is formed, the second gate conductive layer 322 (read transistor outer gate 372) will be exposed.

[0102] S403, see S403. Figure 23 The first gate conductive layer 321 and the second gate conductive layer 322 are thickened.

[0103] Specifically, the material of the first gate conductive layer 321 can be deposited on the inner wall of the third process hole 711 and the inner wall of the first word line transverse groove 721 to thicken the first gate conductive layer 321; the material of the second gate conductive layer 322 can be deposited on the inner wall of the fourth process hole 712 and the inner wall of the second word line transverse groove 722 to thicken the second gate conductive layer 322.

[0104] S404, see also Figure 23 The remaining space of the third process hole 711 and the first character line transverse groove 721 is filled, and the second hole 731 is retained to form the writing line 741; the remaining space of the fourth process hole 712 and the second character line transverse groove 722 is filled, and the third hole 732 is retained to form the reading line 742.

[0105] The writing line 741 and the reading line 742 can be made of one or more combinations of titanium nitride, tungsten, ruthenium, and molybdenum, and both can be formed by atomic layer deposition or chemical vapor deposition.

[0106] S405, through the second aperture 731, a portion of the material of the write word line 741 and a portion of the material of the first gate conductive layer 321 are removed in sequence to expose the isolation layer 110 covered by the first gate conductive layer 321, forming a first word line isolation hole; through the third aperture 73, a portion of the material of the read word line 742 and a portion of the material of the second gate conductive layer 322 are removed in sequence to expose the isolation layer covered by the second gate conductive layer 322, forming a second word line isolation hole.

[0107] The first and second word line isolation holes can both be formed by etching back. Specifically, they can be formed by free radical etching, atomic layer etching, wet etching, and other methods.

[0108] S406, see S406. Figure 24a and Figure 24b The isolation hole for the first letter line and the separation between the second letter line are filled with isolation material.

[0109] The isolation material filled in the isolation hole of the first word line and the isolation between the second word line is the same as the material of the write isolation area 220 and the read isolation area 210. In this way, the write word line 741 and the read word line 742 of different layers can be separated.

[0110] In this embodiment, the write transistor and the read transistor are fabricated together, which simplifies the process.

[0111] See Figure 29a and Figure 29b An embodiment of the present invention provides a semiconductor memory including a read transistor and a write transistor, and the semiconductor memory is manufactured using the method of any of the above embodiments.

[0112] Figure 30 A semiconductor process apparatus provided according to one embodiment of the present invention includes a process chamber 20, an inlet assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C, and a controller (not shown in FIG5). The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the method of any of the above embodiments.

[0113] For example, the controller can be a host computer or a slave computer. The controller can open the valve of the air inlet assembly 20A to introduce the corresponding process gas into the process chamber 20; the controller can also control the flow rate of the process gas by controlling the opening and closing degree of the valve of the air inlet assembly 20A. The controller can also control the evacuation assembly 20D to evacuate the process chamber 20, thereby controlling the gas pressure inside the process chamber 20 and removing reaction byproducts.

[0114] The upper electrode assembly 20B includes an RF coil 21, an upper RF power supply 23, and an upper matching unit 25. The controller is also used to control the upper RF power supply 23 to provide upper electrode power to the RF coil 21 through the upper matching unit 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma.

[0115] The lower electrode assembly 20C includes a wafer carrier 22, a lower RF power supply 24, and a lower matching unit 26. The controller further controls the lower RF power supply 24 to provide lower electrode power to the lower electrode of the wafer carrier 22 through the lower matching unit 26, thereby providing an RF bias voltage to the lower electrode of the wafer carrier 22 to adsorb plasma above the target film layer and bombard the target film layer. The wafer carrier 22 includes an electrostatic chuck.

[0116] The semiconductor process equipment in this application embodiment can be either an inductively coupled plasma (ICP) etching apparatus or a capacitively coupled plasma (CCP) etching apparatus. This application embodiment does not limit the type of semiconductor process equipment.

[0117] The semiconductor process equipment provided in this embodiment of the invention has the same technical features as the semiconductor memory fabrication method provided in the above embodiments, so it can also solve the same technical problems and achieve the same technical effects.

[0118] This embodiment also provides a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions cause the processor to implement the above-described method for fabricating a semiconductor memory.

[0119] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described equipment and apparatus can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0120] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, and read-only memory (ROM). Various media that can store program code, such as random access memory (RAM), magnetic disks, or optical disks.

[0121] In the description of this invention, it should be noted that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a semiconductor memory, characterized in that, include: In the gate formation step, a write transistor gate, a read transistor outer gate, and a read transistor inner gate are formed, wherein the read transistor inner gate is located between the write transistor gate and the read transistor outer gate, and the read transistor inner gate has a ring structure; The removal step involves removing the material inside the annular ring of the inner gate of the read transistor to expose the inner ring wall of the inner gate; removing the material on the interface side of the gate of the write transistor to expose the surface of the gate to expose the surface of the gate to expose the surface of the gate to expose the surface of the write transistor; and removing the material between the outer gate of the read transistor and the inner gate of the read transistor, while retaining a portion of the support material of the inner gate of the read transistor, so that the surface of the outer gate of the read transistor facing the inner gate of the read transistor and a portion of the surface of the outer ring wall of the inner gate of the read transistor are exposed. In the active structure formation step, a gate dielectric layer and a channel layer are sequentially formed on the exposed surface of the write transistor gate, the exposed surface of the read transistor outer gate, and the exposed surface of the read transistor inner gate.

2. The method for fabricating a semiconductor memory according to claim 1, characterized in that, The gate formation step includes: A first write hole is formed in a predetermined forming region of the write bit line of the stacked structure, and a first read hole is formed in a predetermined forming region of the read bit line of the stacked structure; wherein, the stacked structure includes an alternately arranged isolation layer and an initial sacrificial layer; A portion of the initial sacrificial layer is removed via the first write aperture to form a write lateral slot; and a portion of the initial sacrificial layer is removed via the first read aperture to form a read outer lateral slot. A first gate conductive layer is formed on the inner wall of the first write hole and the inner wall of the write transverse groove; and a second gate conductive layer is formed on the inner wall of the first read hole and the inner wall of the read transverse groove. The remaining space between the first write hole and the write transverse slot is filled to form a write sacrificial layer; and the remaining space between the first read hole and the read transverse slot is filled to form a first read sacrificial layer.

3. The method for fabricating a semiconductor memory according to claim 2, characterized in that, After forming the first read-sacrificial layer, the gate formation step further includes: A first read-ground via is formed in a predetermined area at the ground terminal of the read transistor; By removing a portion of the initial sacrificial layer through the first read via, an in-read lateral trench is formed, exposing the sidewalls of the second gate conductive layer that were covered by the initial sacrificial layer. Remove the portion of the second gate conductive layer exposed to the first read hole; A second read sacrificial layer and a third gate conductive layer are sequentially formed on the inner wall of the first read ground hole and the inner wall of the read internal transverse slot; the remaining space of the first read ground hole and the read internal transverse slot is filled to form the third read sacrificial layer.

4. The method for fabricating a semiconductor memory according to claim 3, characterized in that, The removal step includes: Remove the write sacrificial layer, the first read sacrificial layer, and the third read sacrificial layer; remove the portion of the second read sacrificial layer located between the third gate conductive layer and the second gate conductive layer to make the read outer lateral slot communicate with the read inner lateral slot; and retain the portion of the second read sacrificial layer located opposite to the second gate conductive layer in the third gate conductive layer to support the third gate conductive layer using the remaining second read sacrificial layer.

5. The method for fabricating a semiconductor memory according to claim 3, characterized in that, After forming the third read sacrifice layer, the gate formation step further includes: A second write via is formed through the write sacrificial layer in a predetermined formation region of the write bit line to expose the first gate conductive layer; a second read bit via is formed through the first read sacrificial layer in a predetermined formation region of the read bit line to expose the second gate conductive layer; a second read ground via is formed through the third read sacrificial layer in a predetermined formation region of the ground terminal of the read transistor to expose the third gate conductive layer. The portion of the first gate conductive layer exposed to the second write via is removed, and the remaining first gate conductive layer forms the gate of the write transistor; the portion of the second gate conductive layer exposed to the second read via is removed, forming the outer gate of the read transistor; the portion of the third gate conductive layer exposed to the second read ground via is removed, forming the inner gate of the read transistor.

6. The method for fabricating a semiconductor memory according to claim 5, characterized in that, The active structure forming step includes: sequentially forming a gate dielectric layer and a channel layer on the inner walls of the second write hole, the second read hole, the second read ground hole, the write lateral slot, the read outer lateral slot, and the read inner lateral slot; After the active structure formation step, the method further includes: forming the write bit line in the second write hole and the write lateral slot, forming the read bit line in the second read bit hole and the read outer lateral slot, and forming the read transistor ground terminal in the second read ground hole and the read inner lateral slot.

7. The method for fabricating a semiconductor memory according to claim 3, characterized in that, After forming the write lateral trench and the read lateral trench, and before forming the first gate conductive layer, the gate forming step further includes: thinning the upper and lower trench walls of the write lateral trench and the upper and lower trench walls of the read lateral trench. And / or, after forming the read in lateral trench and before removing the portion of the second gate conductive layer exposed to the first read ground via, the gate forming step further includes: thinning the upper and lower trench walls of the read in lateral trench and removing the portion of the isolation layer protruding from the first gate conductive layer; And / or, after removing the portion of the second gate conductive layer exposed to the first read via and before removing a portion of the isolation layer, the gate forming step further includes: deepening the read in-transverse trench.

8. The method for fabricating a semiconductor memory according to any one of claims 1-7, characterized in that, After the active structure forming step, the method further includes: A storage node, a capacitor dielectric, and a ground terminal are formed; wherein the storage node is located between a read transistor and a write transistor, the capacitor dielectric is connected to and surrounds the storage node, and the capacitor dielectric surrounds the ground terminal.

9. The method for fabricating a semiconductor memory according to any one of claims 3-7, characterized in that, Prior to the gate formation step, the method further includes: Remove the portion of the initial sacrificial layer located on both sides of the predetermined formation region of the read transistor to form a read isolation trench; and remove the portion of the initial sacrificial layer located between the predetermined formation regions of two adjacent write transistors to form a write isolation trench. The read isolation slot is filled with isolation material to form a read isolation area; the write isolation slot is filled with isolation material to form a write isolation area.

10. The method for fabricating a semiconductor memory according to claim 9, characterized in that, After forming the third read sacrifice layer, the gate formation step further includes: A first process hole is formed between the read isolation region and the write isolation region, penetrating the stacked structure; At least a portion of the material of the initial sacrificial layer is removed through the first process via to form a first lateral process trench to expose the first gate conductive layer; A portion of the material of the first gate conductive layer is removed via the first lateral process trench to expose the write sacrificial layer; The first transverse process groove is filled to form a process sacrificial layer.

11. The method for fabricating a semiconductor memory according to claim 10, characterized in that, After the active structure forming step, the method further includes: A second process hole is formed between the read isolation region and the write isolation region, penetrating the stacked structure; The process sacrificial layer is removed through the second process hole to form a second transverse process groove; The portion of the gate dielectric layer of the write transistor exposed to the second lateral process trench is removed, without exposing the gate of the write transistor; and a portion of the material of the second read sacrificial layer is removed to expose the inner gate of the read transistor; Within the second transverse process trench, a storage node is formed, while retaining the first pore; A portion of the material of the storage node is removed through the first aperture to expose the isolation layer covered by the storage node, forming a grounding hole; Through the grounding hole, a portion of the material of the isolation layer is removed to form a third lateral process trench connecting the grounding holes on both sides of the memory node, and at least a portion of the upper and lower surfaces of the memory node is exposed to the third lateral process trench, while the portion of the isolation layer located between the third lateral process trench and the write transistor and the read transistor is retained. A capacitor dielectric is formed on the inner wall of the grounding hole and the third transverse process groove; Fill the remaining space of the grounding hole and the third transverse process groove to form a grounding terminal.

12. The preparation method according to claim 11, characterized in that, The process of forming a storage node within the second transverse process tank includes: sequentially forming a second contact layer and a second adhesion layer on the inner wall of the second transverse process tank; filling the remaining space of the second transverse process tank to form a storage node conductive layer; wherein the storage node includes a second contact layer, a second adhesion layer, and a storage node conductive layer; And / or, filling the remaining space of the grounding hole and the third transverse process groove includes: forming a barrier layer on the inner wall of the grounding hole and the third transverse process groove; filling the remaining space of the grounding hole and the third transverse process groove to form a grounding conductive layer.

13. The method for fabricating a semiconductor memory according to any one of claims 2-7, characterized in that, After forming the first gate conductive layer and the second gate conductive layer, the method further includes: In the same storage cell, a third process via is formed on the side of the write isolation region opposite to the read isolation region to expose the initial sacrificial layer; a fourth process via is formed on the side of the read isolation region opposite to the write isolation region to expose the initial sacrificial layer. The initial sacrificial layer is removed through the third process hole to form a first transverse groove for the letter line; the initial sacrificial layer is removed through the fourth process hole to form a second transverse groove for the letter line. The first gate conductive layer and the second gate conductive layer are thickened. Fill the remaining space of the third process hole and the horizontal groove of the first character line, and retain the second gap to form a writing line; fill the remaining space of the fourth process hole and the horizontal groove of the second character line, and retain the third gap to form a reading line; Through the second aperture, a portion of the material of the write word line and a portion of the material of the first gate conductive layer are removed sequentially to expose the isolation layer covered by the first gate conductive layer, forming a first word line isolation aperture; through the third aperture, a portion of the material of the read word line and a portion of the material of the second gate conductive layer are removed sequentially to expose the isolation layer covered by the second gate conductive layer, forming a second word line isolation aperture; The isolation holes for the first and second letter lines are filled with insulating material.

14. A semiconductor memory, characterized in that, The semiconductor memory includes a read transistor and a write transistor, and the semiconductor memory is prepared by the method of any one of claims 1-13.

15. A semiconductor process apparatus, comprising a process chamber, an inlet assembly, an upper electrode assembly, a lower electrode assembly, and a controller, characterized in that, The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the method for fabricating a semiconductor memory as described in any one of claims 1-13.

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