Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, and belongs to the field of semiconductors. The preparation method of the semiconductor device comprises the following steps: forming a silicon germanium layer on the surface of a silicon substrate, wherein the silicon germanium layer is doped with at least one of a group III element, a group V element and a group IV element; forming a silicon epitaxial layer on the surface of the doped silicon germanium layer; etching the silicon epitaxial layer by using dry etching with the doped silicon germanium layer as an etching stop layer, so as to form a plurality of silicon columns and etching grooves, wherein the silicon columns and the etching grooves are alternately distributed; and removing the silicon substrate from the back surface of the silicon substrate by using chemical mechanical grinding with the doped silicon germanium layer as an etching stop layer. By using a thinner silicon germanium layer as an etching stop layer, the Si lattice defects of the upper silicon epitaxial layer are less when the silicon germanium layer is thinner, the silicon columns formed by subsequent etching are prevented from having lattice defects, the device leakage current is reduced, the array device characteristics are uniform, and the yield is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] 4F 2 DRAM is a high-density dynamic random access memory. To form a 4F... 2 DRAM fabrication begins with the vertical channel transistor (VCT) being fabricated on the front side of the wafer. During VCT fabrication, highly uniform silicon pillars and uniformly deep isolation trenches are first formed by etching the epitaxial layer. Then, the bulk silicon on the back side of the wafer is removed by chemical mechanical polishing (CMP) or wet cleaning. Finally, wiring processes are performed on the back side of the wafer. To form highly uniform silicon pillars and uniformly deep isolation trenches, and to uniformly remove the back side material via CMP, an intermediate film layer must be formed that simultaneously meets the requirements of both the epitaxial layer etching stop layer and the CMP polishing stop layer. Currently, silicon-germanium (SiGe) material is used as this intermediate film layer.

[0003] However, currently, the silicon-germanium material layer, used as an etch stop layer, can only achieve the desired etch selectivity between silicon and germanium and the CMP polishing selectivity by increasing the thickness of the silicon-germanium material layer. However, if the silicon-germanium material layer is too thick, lattice mismatch between silicon-germanium and the silicon material in the epitaxial layer will cause the accumulated compressive strain to exceed the elastic stability range, resulting in crystal defects such as mismatch dislocations and stacking faults at the interface. This leads to wafer warping, and the defects propagate upwards, directly damaging the single-crystal quality of the epitaxial silicon film. Cross-ripples appear in the epitaxial layer, indicating lattice defects in the silicon pillars. This results in increased leakage current in subsequent devices, uneven characteristics of array devices, and decreased yield.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and its fabrication method to solve the problem that, when existing silicon-germanium material layers simultaneously meet the etching selectivity ratio between silicon and germanium and the CMP polishing selectivity ratio, the thickness of the silicon-germanium material layer is too thick, causing defects in the epitaxial layer.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for fabricating a semiconductor device, comprising:

[0007] Provide a silicon substrate;

[0008] A silicon-germanium layer is formed on the surface of the silicon substrate, wherein the silicon-germanium layer is doped with at least one of a group III element, a group V element, and a group IV element;

[0009] A silicon epitaxial layer is formed on the surface of the doped silicon-germanium layer;

[0010] Using the doped silicon-germanium layer as the etching stop layer, the silicon epitaxial layer is etched using dry etching to form multiple silicon pillars and etching trenches, with the silicon pillars and etching trenches distributed alternately.

[0011] The silicon substrate is removed from the back side using a chemical mechanical polishing method, with the doped silicon-germanium layer as the etching stop layer.

[0012] Preferably, the thickness of the doped silicon-germanium layer ranges from 5 nm to 15 nm.

[0013] Preferably, the atomic percentage of doping concentration in the doped silicon-germanium layer is less than or equal to 5%.

[0014] Preferably, the elements doped in the silicon-germanium layer include at least one of boron, phosphorus, and carbon.

[0015] Preferably, the etching gas used in the dry etching process includes a gas containing halogen elements.

[0016] Based on the same inventive concept, the present invention also provides a semiconductor device prepared by means of the method described above.

[0017] Compared with the prior art, the method for fabricating the semiconductor device of the present invention has the following advantages:

[0018] This invention passivates the Ge-like sites inside and on the surface of SiGe by doping the silicon-germanium layer with at least one of Group III, Group V, and Group IV elements, weakening its reactivity with etchants and polishing slurries. This promotes the formation of a denser and more stable composite oxide passivation layer on the SiGe surface, blocking the continuous erosion by etchants and polishing slurries and reducing the removal rate of SiGe itself. However, silicon cannot form a similar stable passivation layer and maintains its original removal rate. This improves the etching selectivity and polishing selectivity of silicon relative to SiGe. The silicon-germanium layer can serve as both the etching termination layer for dry etching trenches on the front side of the silicon substrate and the etching termination layer for CMP on the back side of the silicon substrate. Under both different processes, the selectivity of Si relative to SiGe is improved. Thinner or conventionally thicker silicon-germanium layers can be used as etching stop layers. The thinner the silicon-germanium layer, the fewer Si lattice defects (such as stacking faults and strain distortion) in the upper silicon epitaxial layer, avoiding lattice defects in the silicon pillars formed by subsequent etching, reducing device leakage current, improving the uniformity of array device characteristics, and increasing yield. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a structure after an epitaxial layer is grown on a silicon-germanium material layer.

[0020] Figure 2 It is a kind of Figure 1 A schematic diagram of the structure after the epitaxial layer is etched.

[0021] Figure 3 It is a kind of Figure 1 A schematic diagram of the structure of a wafer after etching.

[0022] Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the structure after a silicon epitaxial layer is grown on a silicon-germanium layer in one embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure after a contact pad is formed on the front side of the substrate in one embodiment of the present invention.

[0025] Figure 7 This is a schematic diagram of the structure after the substrate is removed by chemical mechanical polishing in one embodiment of the present invention.

[0026] Figure 8 This is a schematic diagram of the structure after removing the silicon-germanium layer in one embodiment of the present invention;

[0027] Figure 9 This is a schematic diagram of the structure after bit lines are formed in one embodiment of the present invention.

[0028] In the picture,

[0029] 10. Wafer; 20. Silicon-germanium material layer; 30. Epitaxial layer; 40. Isolation trench; 100. Silicon substrate; 200. Silicon-germanium layer; 300. Silicon epitaxial layer; 310. Silicon pillar; 320. First isolation structure; 330. Word line; 340. Second isolation structure; 350. First dielectric material layer; 360. Contact pad; 370. Second dielectric material layer; 380. Bit line; 390. Third dielectric material layer. Detailed Implementation

[0030] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of the present invention. It should be understood that the accompanying drawings do not necessarily show the specific structure of the invention to scale, and the illustrative features used to illustrate certain principles of the invention in the accompanying drawings are also drawn in a slightly simplified manner. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are used. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0031] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0032] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0033] refer to Figures 1 to 3 As shown, Figure 1 This is a schematic diagram of the structure after an epitaxial layer is grown on a silicon-germanium material layer; Figure 2 It is a kind of Figure 1 A schematic diagram of the structure after etching the epitaxial layer; Figure 3 It is a kind of Figure 1 A schematic diagram of the structure of a wafer after back-side grinding or etching; Reference Figure 1As shown, a silicon-germanium material layer 20 and an epitaxial layer 30 are sequentially deposited on wafer 10. During VCT fabrication, not only do we need to etch highly uniform silicon pillars and uniformly deep isolation trenches 40 on the front side of wafer 10 to form the epitaxial layer 30, but we also need to remove wafer 10 from the back side using chemical mechanical polishing (CMP). If the silicon-germanium material layer 20 is too thin, after etching the epitaxial layer 30, it will form... Figure 2 The isolation trenches 40 shown have varying depths, and because the silicon-germanium material layer 20 is too thin, it damages the underlying wafer. Furthermore, if the silicon-germanium material layer 20 is too thin, when removing wafer 10 from the back side, as... Figure 3 As shown, this will damage the etched silicon pillars, resulting in a decrease in VCT yield.

[0034] To form highly uniform silicon pillars and uniformly deep isolation trenches 40, while uniformly removing wafer 10 from the back side, a thicker silicon-germanium material layer 20 is required. (Continue to reference...) Figure 1 As shown, when the thickness of the silicon-germanium material layer 20 is relatively thick, the epitaxial layer 30 grown on the surface of the silicon-germanium material layer 20 exhibits the following characteristics: Figure 1 Defects such as stacking faults shown at point a indicate lattice defects in the etched silicon pillars, leading to increased leakage current, uneven array device characteristics, and decreased yield in subsequent devices. However, in conventional processes, the thickness of the silicon-germanium material layer 20 (i.e., Figure 1 In the process, d1 is generally set to 15nm, and the thickness of the silicon-germanium material layer 20 in conventional processes cannot meet the process requirements.

[0035] The core idea of ​​this invention is to provide a method for fabricating semiconductor devices that can improve the etching selectivity ratio between the silicon-germanium layer and the epitaxial layer, as well as the polishing selectivity ratio between the silicon-germanium layer and the wafer, without increasing the thickness of the silicon-germanium layer. This avoids defects such as stacking faults in the epitaxial silicon, thereby preventing lattice defects in the silicon pillars formed by etching, reducing leakage current in the subsequently formed devices, ensuring uniformity of array device characteristics, and improving yield.

[0036] To achieve the above-mentioned goals, this invention provides a method for fabricating a semiconductor device, as described above. Figures 4 to 9 A specific embodiment of the disclosed method for fabricating a semiconductor device is described. The method includes the following steps S1 to S5.

[0037] Step S1: Provide a silicon substrate.

[0038] refer to Figure 5 As shown, the silicon substrate 100 is the wafer mentioned above. The silicon substrate 100 can be monocrystalline silicon or polycrystalline silicon.

[0039] Step S2: A silicon-germanium layer is formed on the surface of the silicon substrate, wherein the silicon-germanium layer is doped with at least one of a group III element, a group V element, and a group IV element.

[0040] refer to Figure 5 As shown, a silicon-germanium layer 200 is formed on a silicon substrate 100, and the silicon-germanium layer 200 is doped with at least one of a Group III element, a Group V element, and a Group IV element. Group III elements may include boron (B), gallium (Ga), etc.; Group V elements may include phosphorus (P), arsenic (As), etc.; and Group IV elements may include carbon (C), tin (Sn), etc. In some embodiments, the silicon-germanium layer 200 is formed by epitaxial growth, and during the epitaxial growth process, dopant ions are implanted into the silicon-germanium layer 200 to achieve doping of the silicon-germanium layer 200.

[0041] By doping the silicon-germanium layer 200, the Ge sites inside and on the surface of SiGe can be passivated, weakening their reactivity with etchants and polishing pastes. This promotes the formation of a denser and more stable composite oxide passivation layer on the SiGe surface, blocking the continuous erosion by etchants and polishing pastes and reducing the removal rate of SiGe itself. However, silicon cannot form a similar stable passivation layer, and silicon maintains its original removal rate. This can improve the etching selectivity and polishing selectivity of silicon relative to SiGe.

[0042] In some embodiments, the elements doped in the silicon-germanium layer 200 include at least one of boron (B), phosphorus (P), and carbon (C). After substitutional dopants such as B, P, and C are incorporated into the silicon-germanium layer 200, they can passivate the germanium active sites inside and on the surface of the silicon-germanium, inhibit the etching free radicals between Ge and the etching reagent, and inhibit the reaction of the polishing slurry oxidant. Simultaneously, the doped SiGe surface more readily forms a CO, BO, and PO composite oxide passivation layer, preventing the continuous diffusion of etching and polishing media into the material. B and P can regulate the band structure and electrochemical corrosion potential of the silicon-germanium surface, while C can optimize lattice bonding strength and improve the mechanical properties of the thin film, collectively reducing the removal rate of silicon-germanium during dry etching and chemical mechanical polishing. Silicon is less likely to form a stable passivation layer and maintain its original high removal rate, thereby improving the etching selectivity and polishing selectivity of silicon relative to silicon-germanium.

[0043] In some embodiments, the atomic percentage of doping concentration in the doped silicon-germanium layer is less than or equal to 5%, that is, the total number of doped atoms accounts for ≤5 at.% of the total number of atoms in the silicon-germanium layer 200. By setting the atomic percentage of doping concentration to less than or equal to 5%, low-concentration doped atoms are incorporated into the SiGe lattice in a substitutional manner, generating only localized small elastic strain, and the film remains in a single-crystal state. When the atomic percentage of doping exceeds 5%, it will destroy the single-crystal epitaxial state of the silicon-germanium layer 200 and interfere with the subsequent growth of the silicon epitaxial layer 300. Controlling the atomic percentage of doping to 5% or below can ensure the normal progress of the epitaxial process.

[0044] refer to Figure 5 As shown, in some embodiments, the thickness of the doped silicon-germanium layer ranges from 5 nm to 15 nm. The thickness of the doped silicon-germanium layer 200 (i.e., Figure 5 d2 in the figure can be 5nm, 7nm, 10nm, 15nm, or any value within the range of 5nm to 15nm. By doping the silicon-germanium layer 200, the etching selectivity ratio between the silicon-germanium layer 200 and the silicon epitaxial layer 300, as well as the mask selectivity ratio between the silicon-germanium layer 200 and the silicon substrate 100, can be improved. This allows the silicon-germanium layer 200 to use a conventional thickness, such as 15nm, thereby avoiding defects such as stacking faults on the surface of the silicon epitaxial layer 300 and preventing lattice defects in the silicon pillars formed by subsequent etching. Furthermore, by doping the silicon-germanium layer 200, the etching selectivity ratio between the silicon-germanium layer 200 and the silicon epitaxial layer 300, as well as the mask selectivity ratio between the silicon-germanium layer 200 and the silicon substrate 100, can be improved, which can significantly reduce the thickness of the silicon-germanium layer 200. When growing the silicon epitaxial layer 300 on the surface of the silicon-germanium layer 200, defects such as stacking faults can be avoided on the surface of the silicon epitaxial layer 300, and lattice defects can be avoided in the silicon pillars formed by subsequent etching, thereby reducing device leakage current, ensuring uniformity of array device characteristics, and improving yield.

[0045] Step S3: Form a silicon epitaxial layer on the surface of the doped silicon-germanium layer.

[0046] Continue to refer to Figure 5 As shown, a silicon epitaxial layer 300 is formed on the surface of the doped silicon-germanium layer 200 by epitaxial growth. Figure 5 It can be seen that since the thickness d2 of the silicon-germanium layer 200 is only 5nm≤d2≤15nm, it is possible to avoid defects such as stacking faults on the surface of the silicon epitaxial layer 300.

[0047] Step S4: Using the doped silicon-germanium layer as the etching stop layer, dry etching is used to etch the silicon epitaxial layer to form multiple silicon pillars and etching trenches, with the silicon pillars and etching trenches distributed alternately.

[0048] refer to Figure 6As shown, using a doped silicon-germanium layer 200 as an etch barrier layer, dry etching is employed to etch the silicon epitaxial layer 300, forming multiple silicon pillars 310 and multiple etching trenches, with the silicon pillars 310 and etching trenches distributed alternately. The silicon pillars 310 are used to subsequently form the source, drain, and channel, while the etching trenches form an isolation structure after being filled with insulating material.

[0049] The gases used in dry etching include halogen gases, such as hydrogen bromide (HBr), chlorine (Cl2), and hydrogen chloride (HCl). Since the silicon-germanium layer 200 is doped with at least one of B, P, and C, the selectivity of dry etching between the silicon-germanium layer 200 and the silicon epitaxial layer 300 is improved. By using the doped silicon-germanium layer 200 as an etching barrier layer to etch the silicon epitaxial layer 300, highly uniform silicon pillars 310 and uniformly deep etching trenches can be formed.

[0050] Continue to refer to Figure 6 As shown, after forming the etching trench, an insulating material (e.g., silicon dioxide, silicon nitride, etc.) is filled into the etching trench to form a first isolation structure 320 and a second isolation structure 340. The insulating materials filled in the first isolation structure 320 and the second isolation structure 340 can be the same or different, as long as electrical isolation between the silicon pillars 310 can be achieved.

[0051] After forming the first isolation structure 320 and the second isolation structure 340, the method further includes forming a source electrode, a word line 330 (WL), and a contact pad 360 at one top of a silicon pillar, forming a first dielectric material layer 350 between the contact pads 360, and forming a second dielectric material layer 370 between silicon pillars 310 in other regions. It should be noted that the formation of the first isolation structure 320, the second isolation structure 340, the source electrode, the word line 330 (WL), the contact pads 360, the first dielectric material layer 350, and the second dielectric material layer 370 are already familiar to those skilled in the art and will not be described in detail here.

[0052] Step S5: Remove the silicon substrate from the back side of the silicon substrate by chemical mechanical polishing, using the silicon-doped silicon-germanium layer as the etching stop layer.

[0053] refer to Figure 7As shown, the silicon substrate 100 is removed from the back side of the silicon substrate 100 using a doped silicon-germanium layer 200 as an etch stop layer via chemical mechanical polishing (CMP). Since the silicon-germanium layer 200 is doped with at least one of B, P, and C, the polishing selectivity between the silicon-germanium layer 200 and the silicon substrate 100 is improved. Using the doped silicon-germanium layer 200 as an etch stop layer, the silicon substrate 100 is subjected to CMP treatment. Polishing stops immediately when the silicon-germanium layer 200 is reached, thereby avoiding damage to the silicon pillar 310 during polishing, preventing lattice defects in the silicon pillar 310, reducing device leakage current, improving the uniformity of array device characteristics, and increasing yield.

[0054] When removing the silicon substrate 100 from the back side, the process also includes etch-back to quickly remove the thick silicon substrate 100, wet cleaning to remove polishing residue and surface defects, and avoiding any residue on the silicon substrate 100.

[0055] refer to Figure 8 and Figure 9 As shown, after removing the silicon substrate 100, the silicon-germanium layer 200 is also removed by wet etching to form the following... Figure 8 The structure is shown. Next, ion implantation is performed on the top of the silicon pillar 310 to form a drain. Then, bit lines (BLs) 380 are formed on the top of the silicon pillar, and a third dielectric material layer 390 is filled between the bit lines to achieve electrical isolation between the bit lines 380. It should be noted that the formation of the drain, bit lines 380, and third dielectric material layer 390 is familiar to those skilled in the art and will not be described in detail here.

[0056] Compared to traditional SiGe, which is only used as a single-sided (front or back) process termination layer, this solution adapts low-doped modified SiGe to two removal processes with vastly different mechanisms. Both sides share the same silicon-germanium layer 200 as the termination layer. This single-layer doped silicon-germanium layer 200 serves as both the termination layer for dry etching of the front etching trench of the silicon substrate 100 and the etching termination layer for CMP, etch-back, and wet cleaning of the back etching substrate 100. By doping the silicon-germanium layer 200 with at least one of C, B, and P elements, and with a doping atomic percentage ≤5%, the silicon epitaxial layer is simultaneously improved. The dry etching selectivity between the silicon-germanium layer 300 and the silicon-germanium layer 200, and the CMP mask selectivity between the silicon substrate 100 and the silicon-germanium layer 200, both improve the selectivity of Si relative to SiGe under two different processes. This allows for the use of a thinner or conventionally thicker silicon-germanium layer 200 as the etching selectivity. The thinner the silicon-germanium layer 200, the fewer Si lattice defects (such as stacking faults and strain distortion) in the upper silicon epitaxial layer 300. This avoids lattice defects in the silicon pillars 310 formed by subsequent etching, reduces device leakage current, ensures uniform array device characteristics, and improves yield.

[0057] To achieve the above-described idea, this embodiment also discloses a semiconductor device fabricated using the method described above.

[0058] The semiconductor device disclosed in this embodiment and the semiconductor device fabrication method provided in this embodiment belong to the same inventive concept. Therefore, the semiconductor device provided in this embodiment has at least all the advantages of the semiconductor device fabrication method provided in this embodiment. By doping the silicon-germanium layer 200 to increase the selectivity between the silicon-germanium layer 200, the silicon epitaxial layer 300, and the silicon substrate 100, the silicon-germanium layer 200 can be made thinner. This allows it to serve as both an etching termination layer for dry etching of the front side of the silicon substrate 100 and an etching termination layer for CMP, etch-back, and wet cleaning of the back side of the silicon substrate 100. The thinner the silicon-germanium layer 200, the fewer Si lattice defects (such as stacking faults and strain distortion) in the upper silicon epitaxial layer 300. This avoids lattice defects in the silicon pillars 310 formed by subsequent etching, reduces device leakage current, improves the uniformity of array device characteristics, and increases yield.

[0059] In summary, the above embodiments have provided detailed descriptions of different configurations of semiconductor devices and their fabrication methods. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide a silicon substrate; A doped silicon-germanium layer is formed on the surface of the silicon substrate, wherein the silicon-germanium layer is doped with at least one of a group III element, a group V element, and a group IV element; A silicon epitaxial layer is formed on the surface of the doped silicon-germanium layer; Using the doped silicon-germanium layer as the etching stop layer, the silicon epitaxial layer is etched using dry etching to form multiple silicon pillars and etching trenches, with the silicon pillars and etching trenches distributed alternately. The silicon substrate is removed from the back side using a chemical mechanical polishing method, with the doped silicon-germanium layer as the etching stop layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the doped silicon-germanium layer ranges from 5 nm to 15 nm.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The atomic percentage of doping concentration in the doped silicon-germanium layer is less than or equal to 5%.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The silicon-germanium layer is doped with at least one of boron, phosphorus, and carbon.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching gas used in the dry etching process includes gases containing halogen elements.

6. A semiconductor device, prepared by the method described in any one of claims 1-5.

Images