Semiconductor device, method of operating the same, and memory system

Abstract

Embodiments of the present disclosure provide a semiconductor device, an operating method thereof, and a memory system. The semiconductor device includes a memory cell array including a plurality of memory banks, a memory bank including a plurality of memory blocks, a memory block including a plurality of selection transistors and a plurality of memory cells; a word line coupled to the memory cell; a peripheral circuit coupled to the memory cell array and the word line, the peripheral circuit configured to: in performing a first operation, apply a first voltage to a first word line coupled to a first memory block in a selected memory bank, an input voltage of a gate of at least one selection transistor in the first memory block being a second voltage; and apply a third voltage to a second word line coupled to a second memory block in the selected memory bank, an input voltage of a gate of each selection transistor in the second memory block being a fourth voltage; wherein the first voltage is greater than the third voltage, and the second voltage is greater than the fourth voltage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a semiconductor device and its operating method and a memory system. Background Technology

[0002] In the classic von Neumann computing architecture, the memory device and the processor are separate, and data is transferred between them via a data bus. When executing a command, the processor first reads data from the memory device, processes it, and then writes the updated data back to the memory device. This frequent data movement results in significant power consumption and time overhead. Furthermore, the limited bandwidth of the memory device restricts the processor's processing speed to the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device, an operating method thereof, and a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising: a memory cell array including a plurality of memory banks, each memory bank including a plurality of memory blocks, each memory block including a plurality of select transistors and a plurality of memory cells; a word line coupled to the memory cells; and peripheral circuitry coupled to the memory cell array and the word line, the peripheral circuitry being configured to: in performing a first operation, apply a first voltage to a first word line coupled to a first memory block in a selected memory bank, wherein the input voltage of the gate of at least one select transistor in the first memory block is a second voltage; and apply a third voltage to a second word line coupled to a second memory block in the selected memory bank, wherein the input voltage of the gate of each select transistor in the second memory block is a fourth voltage; wherein the first voltage is greater than the third voltage, and the second voltage is greater than the fourth voltage.

[0005] In some embodiments, the peripheral circuit further includes an input detection circuit configured to detect input information of the selection transistors in the plurality of memory blocks in the selected memory bank during the execution of the first operation; wherein the input information of at least one selection transistor in the first memory block is first input data, and the input information of each selection transistor in the second memory block is second input data.

[0006] In some embodiments, the peripheral circuitry further includes: control logic coupled to the input detection circuitry, the control logic being configured to: apply the second voltage to the gate of the selection transistor in the first memory block where the input information is the first input data, and apply the fourth voltage to the gate of the selection transistor in the first memory block where the input information is the second input data, during the execution of the first operation; and apply the fourth voltage to the gate of each selection transistor in the second memory block.

[0007] In some embodiments, the control logic is configured to: apply a fifth voltage to a third word line coupled to the first memory block in the selected memory bank during the execution of the first operation; and apply a sixth voltage to a fourth word line coupled to the second memory block in the selected memory bank; wherein the fifth voltage is greater than or equal to the sixth voltage, and the first voltage is greater than the fifth voltage.

[0008] In some embodiments, the peripheral circuit further includes a digital-to-analog converter circuit configured to convert the first input data into the second voltage and convert the second input data into the fourth voltage during the execution of the first operation.

[0009] In some embodiments, the memory cell array is configured to store weight data; the semiconductor device further includes a bit line coupled to the selection transistor, the bit line being configured to sense current in the bit line during the execution of the first operation; wherein the current in the bit line is used to indicate an analog signal representing the result of the first operation performed on the input data in all the selection transistors coupled thereto and the weight data in the selected memory cell.

[0010] In some embodiments, the semiconductor device further includes: a first semiconductor structure including the memory cell array; and a second semiconductor structure including the peripheral circuit; wherein the first semiconductor structure and the second semiconductor structure are bonded together.

[0011] In some embodiments, the third voltage is 0V; and / or, the fourth voltage is 0V; and / or, the sixth voltage is 0V.

[0012] In some embodiments, the first operation includes a multiplication-accumulation operation.

[0013] In some embodiments, the semiconductor device includes a NAND-type memory device.

[0014] In a second aspect, embodiments of this disclosure provide a memory system comprising: a semiconductor device as described in the first aspect of this disclosure; and a controller coupled to the semiconductor device and configured to control the semiconductor device.

[0015] In some embodiments, the memory system further includes: an analog-to-digital converter circuit coupled to the semiconductor device, configured to convert an analog signal of the result of the operation performed on the first operation into a digital signal.

[0016] In some embodiments, the memory system further includes a data processing circuit coupled to the analog-to-digital conversion circuit, configured to perform a second operation on the digital signal of the result of the first operation.

[0017] In some embodiments, the second operation includes at least one of compensation, activation, shift, and pooling operations.

[0018] In some embodiments, the memory system further includes: a first semiconductor structure including the memory cell array; a second semiconductor structure including the peripheral circuit and the analog-to-digital conversion circuit; and a third semiconductor structure including the data processing circuit and the controller; wherein the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are bonded together, and the first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure.

[0019] In some embodiments, the memory system further includes: a first semiconductor structure including the memory cell array; a second semiconductor structure including the peripheral circuit; and a third semiconductor structure including the analog-to-digital conversion circuit, the data processing circuit, and the controller; wherein the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are bonded together, and the first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure.

[0020] Thirdly, embodiments of this disclosure provide an operation method for a semiconductor device, the semiconductor device including a memory cell array, the memory cell array including a plurality of memory banks, the memory banks including a plurality of memory blocks, the memory blocks including a plurality of selection transistors and a plurality of memory cells; the operation method including: in performing a first operation, applying a first voltage to a first word line coupled to a first memory block in a selected memory bank, the input voltage of the gate of at least one selection transistor in the first memory block being a second voltage; and applying a third voltage to a second word line coupled to a second memory block in the selected memory bank, the input voltage of the gate of each selection transistor in the second memory block being a fourth voltage; wherein the first voltage is greater than the third voltage, and the second voltage is greater than the fourth voltage.

[0021] In some embodiments, the operation method further includes: during the execution of the first operation, detecting the input information of the selection transistors in the plurality of memory blocks in the selected memory bank; wherein the input information of at least one selection transistor in the first memory block is first input data, and the input information of each selection transistor in the second memory block is second input data.

[0022] In some embodiments, the operation method further includes: applying the second voltage to the gate of the selection transistor in the first memory block where the input information is the first input data, and applying the fourth voltage to the gate of the selection transistor in the first memory block where the input information is the second input data; and applying the fourth voltage to the gate of each of the selection transistors in the second memory block.

[0023] In some embodiments, the operation method further includes: applying a fifth voltage to a third word line coupled to the first memory block in the selected memory bank during the execution of the first operation; and applying a sixth voltage to a fourth word line coupled to the second memory block in the selected memory bank; wherein the fifth voltage is greater than or equal to the sixth voltage, and the first voltage is greater than the fifth voltage.

[0024] In some embodiments, the operation method further includes: converting the first input data into the second voltage and converting the second input data into the fourth voltage during the execution of the first operation.

[0025] In some embodiments, the memory cell array is used to store weight data; the semiconductor device further includes a bit line coupled to the selection transistor; the operation method further includes: sensing the current of the bit line during the execution of the first operation; wherein the current of the bit line is used as an analog signal indicating the result of the first operation performed on the input data in all the selection transistors coupled thereto and the weight data in the selected memory cell.

[0026] In some embodiments, the third voltage is 0V; and / or, the fourth voltage is 0V; and / or, the sixth voltage is 0V.

[0027] In some embodiments, the first operation includes a multiplication-accumulation operation.

[0028] This disclosure provides a semiconductor device, its operating method, and a memory system. In this embodiment, during the execution of a first operation, a first voltage is applied to a first word line coupled to a first memory block in the selected memory bank, and a third voltage is applied to a second word line coupled to a second memory block in the selected memory bank. The first voltage is greater than the third voltage. This improves the read interference experienced by the second memory block during the execution of the first operation and also reduces the power consumption of the semiconductor device. Attached Figure Description

[0029] Figure 1 A schematic diagram of the structure of a semiconductor device including a memory cell array provided in an embodiment of this disclosure;

[0030] Figure 2 This is a schematic diagram of the structure of a storage cell array including storage strings provided in an embodiment of the present disclosure;

[0031] Figure 3 A schematic diagram of the structure of a semiconductor device including peripheral circuitry, provided for embodiments of this disclosure;

[0032] Figure 4 A schematic diagram showing the input voltage selected by the top transistor input to the memory block for some examples;

[0033] Figure 5 A schematic diagram of multiple memory strings coupled to a single bit line, provided as examples;

[0034] Figure 6 A flowchart illustrating the operation of a semiconductor device as an example;

[0035] Figure 7 Voltage timing diagrams for some example semiconductor devices are provided;

[0036] Figure 8 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0037] Figure 9 To Figure 8 A magnified schematic diagram of the memory cell array;

[0038] Figure 10 To Figure 9 A magnified schematic diagram of the memory block structure;

[0039] Figure 11 A schematic diagram illustrating the process of configuring a semiconductor device to perform an operation, as provided in the embodiments of this disclosure;

[0040] Figure 12 To Figure 8 Architecture framework of semiconductor devices Figure 1 ;

[0041] Figure 13 To Figure 8 Architecture framework of semiconductor devices Figure 2 ;

[0042] Figure 14 A schematic flowchart illustrating the operation method of the semiconductor device provided in the embodiments of this disclosure;

[0043] Figure 15 Voltage timing diagram of a semiconductor device provided in the embodiments of this disclosure;

[0044] Figure 16 A block diagram of an electronic device provided in an embodiment of this disclosure;

[0045] Figure 17 A schematic block diagram of a memory card with a memory system provided in an embodiment of this disclosure;

[0046] Figure 18 A schematic block diagram of a solid-state driver with a memory system provided in an embodiment of this disclosure;

[0047] Figure 19 A schematic diagram of a digital-to-analog converter circuit and an analog-to-digital converter circuit provided for embodiments of this disclosure;

[0048] Figure 20 For including Figure 12 A schematic block diagram of the architecture of a semiconductor device's memory system;

[0049] Figure 21 For including Figure 13 A schematic diagram of the memory system architecture of a semiconductor device. Detailed Implementation

[0050] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0052] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0053] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0054] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0057] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a semiconductor device including a memory cell array, provided as an embodiment of this disclosure. Figure 1 As shown, the semiconductor device 100 may include a memory cell array 102 and peripheral circuitry 104 coupled to the memory cell array 102. The memory cell array 102 may be a NAND flash memory cell array, wherein the memory cells 110 are provided in the form of an array of memory strings 108, each memory string 108 on a substrate (…). Figure 1 (Not shown in the diagram) Extending vertically upwards. In some embodiments, each memory string 108 includes a plurality of memory cells 110 that are series-coupled and vertically stacked. Each memory cell 110 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 110. Each memory cell 110 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0058] In some embodiments, each storage cell 110 may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, an SLC may have a first storage state "1" and a second storage state "0", where the threshold voltage distribution of the first storage state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second storage state "0" may correspond to a second voltage range. The first storage state is an erase state, and the second storage state is a programmable state. In some embodiments, each storage cell 110 may be a multi-level cell (MLC) capable of storing more than a single bit of data. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a triple-level cell (TLC)), or four bits of data per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC can have a first storage state "11", a second storage state "10", a third storage state "01", and a fourth storage state "00". Here, the threshold voltage distributions for the first, second, third, and fourth storage states correspond to the first, second, third, and fourth voltage ranges, respectively. The first storage state is the erase state, and the second, third, and fourth storage states are all programming states. Similarly, a TLC can have 8 storage states, including an erase state and 7 programming states; a QLC can have 16 storage states, including an erase state and 15 programming states.

[0059] like Figure 1As shown, each memory string 108 may include a source-selective transistor 114 (SST) at its source end and a drain-selective transistor 118 (DST) at its drain end, wherein the source-selective transistor 114 may also be referred to as a bottom-selective gate (BSG), and the drain-selective transistor 118 may also be referred to as a top-selective gate (TSG). The source-selective transistor 114 and the drain-selective transistor 118 may be configured to activate the selected memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of memory strings 108 in the same memory block 106 are coupled through the same source line 124 (SL) (e.g., common SL). In other words, in some embodiments, all memory strings 108 in the same memory block 106 have an array common source (ACS). In some embodiments, the drain of the drain selection transistor 118 of each memory string 108 is coupled to the corresponding bit line 122 (BL), and can be accessed via the output bus. Figure 1 (Not shown in the diagram) Data is read from or written to bit line 122. In some embodiments, each memory string 108 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the drain select transistor 118) or a deselection voltage (e.g., 0V) to the corresponding drain select transistor 118 via one or more drain selective lines 120 (DSL) (also referred to as top selective lines (TSL)) and / or by applying a selection voltage (e.g., higher than the threshold voltage of the source select transistor 114) or a deselection voltage (e.g., 0V) to the corresponding source select transistor 114 via one or more source selective lines 116 (SSL) (also referred to as bottom selective lines (BSL)).

[0060] like Figure 1As shown, memory strings 108 can be organized into multiple memory blocks 106, each of which can have a source line 124 (e.g., a common SL coupled to ground). In some embodiments, each memory block 106 is a basic data unit for performing an erase operation, i.e., all memory cells 110 on the same memory block 106 are erased simultaneously. To erase memory cells 110 in a selected memory block, an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source lines 124 of the selected memory block and the non-selected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 110 of adjacent memory strings 108 can be coupled via word lines 112 (WL), which select which row of memory cells 110 is affected by read and program operations.

[0061] It should be noted that for SLC, each storage unit can store 1 bit of information, so at the physical layer, the information stored in one storage unit (i.e., one physical page) corresponds to the information of one logical page. For MLC, each storage unit can store 2 bits of information, so at the physical layer, the information stored in one storage unit (i.e., one physical page) corresponds to the information of two logical pages. For TLC, each storage unit can store 3 bits of information, so at the physical layer, the information stored in one storage unit (i.e., one physical page) corresponds to the information of three logical pages. For QLC, each storage unit can store 4 bits of information, so at the physical layer, the information stored in one storage unit (i.e., one physical page) corresponds to the information of four logical pages.

[0062] refer to Figure 2 , Figure 2 This is a schematic diagram of a storage cell array including storage strings, provided as an embodiment of the present disclosure. Figure 2 As shown, the memory string 108 can extend vertically through the memory stack layer 204 above the substrate 202. The substrate 202 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0063] The memory stack 204 may include alternating gate conductive layers 206 and gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 110 in the memory cell array 102. The gate conductive layers 206 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 110 and may extend laterally at the top of the memory stack 204 as a drain select gate line 120, at the bottom of the memory stack 204 as a source select gate line 116, or between the drain select gate line 120 and the source select gate line 116 as a word line 112.

[0064] like Figure 2 As shown, the memory string 108 includes a channel structure extending vertically through the memory stack layer 204. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a memory layer (also referred to as a "charge trap / memory layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, memory layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0065] According to some embodiments, a well (e.g., a P-well and / or an N-well) may be formed in the substrate 202, and the source terminal of the memory string 108 contacts the well. For example, a source line may be coupled to the well to apply an erase voltage to the well (i.e., the source of the memory string 108) during an erase operation. In some embodiments, the memory string also includes a channel plug at the drain terminal of the memory string 108. It should be understood that, although in Figure 2 Additional components, not shown in the diagram, can form the memory cell array 102. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0066] Return to reference Figure 1 The peripheral circuitry 104 can be coupled to the memory cell array 102 via bit line 122, word line 112, source line 124, source-select-gate line 116, and drain-select-gate line 120. The peripheral circuitry 104 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 102 by applying voltage and / or current signals to each selected memory cell 110 and sensing voltage and / or current signals from each selected memory cell 110 via bit line 122, word line 112, source line 124, source-select-gate line 116, and drain-select-gate line 120. The peripheral circuitry 104 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0067] refer to Figure 3 , Figure 3 A schematic diagram of the structure of a semiconductor device including peripheral circuitry, provided for embodiments of this disclosure. For example... Figure 3 As shown, the peripheral circuitry includes a page buffer / sensor amplifier 302, a column driver / bit line driver 304, a row driver / word line driver 306, a voltage generator 308, control logic 310, a register 312, an interface 314 (I / F), and a data bus 316. It should be understood that in some examples, additional components may be included. Figure 3 Additional peripheral circuits not shown in the diagram.

[0068] Page buffer / sensor amplifier 302 can be configured to read data from and program (write) data to memory cell array 102 according to control signals from control logic 310. In another example, page buffer / sensor amplifier 302 can perform a programming verification operation to ensure that data has been correctly programmed into memory cells 110 coupled to selected word line 112. In yet another example, page buffer / sensor amplifier 302 can also sense a low-power signal from bit line 122 representing data bits stored in memory cells 110 and amplify a small voltage swing to a recognizable logic level during read operations. Column driver / bit line driver 304 can be configured to be controlled by control logic 310 and select one or more memory strings 108 by applying a bit line voltage generated from voltage generator 308.

[0069] Row driver / word line driver 306 can be configured to be controlled by control logic 310 and to select / deselect memory blocks 106 of memory cell array 102 and select / deselect word lines 112 of memory blocks 106. Row driver / word line driver 306 can also be configured to drive word lines 112 using word line voltages generated from voltage generator 308. In some embodiments, row driver / word line driver 306 can also select / deselect and drive source select gate line 116 and drain select gate line 120. As described in detail below, row driver / word line driver 306 is configured to perform an erase operation on memory cells 110 coupled to (one or more) selected word lines 112. Voltage generator 308 can be configured to be controlled by control logic 310 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 102.

[0070] Control logic 310 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 312 can be coupled to control logic 310 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 314 can be coupled to control logic 310 and acts as a control buffer to buffer slave devices (…). Figure 3 (Not shown) The interface 314 receives control commands and relays them to control logic 310, and buffers status information received from control logic 310 and relays it to the host. Interface 314 can also be coupled to column driver / bit line driver 304 via data bus 316 and acts as a data input / output (I / O) interface and data buffer to buffer data and relay it to or from memory cell array 102.

[0071] refer to Figure 4 and Figure 5 , Figure 4 The diagram provided here illustrates, for example, how the input voltage is selected by the top-selected transistor input to the memory block. Figure 5 The diagram illustrates multiple memory strings coupled to a single bit line, providing some examples. It should be noted that... Figure 4 and Figure 5 The number of bit lines, the number of memory strings coupled to each bit line, and the number of memory cells in each memory string shown are merely examples, and this disclosure does not limit the specific number of each structure.

[0072] like Figure 4As shown, the input voltage corresponding to the input data can be input via top-select gate lines (i.e., drain-select gate lines) coupled to multiple top-select transistors. The peripheral circuitry is configured to: apply a read voltage Vread to the selected word line WLn coupled to the selected memory block during the first operation using the memory cell array; and apply corresponding input voltages to the multiple top-select gate lines coupled to the selected memory block, for example, applying input voltages Vread to the top-select gate lines TSL0, TSL1, and TSL2 coupled to the selected memory block, respectively. IN0 V IN1 V IN2 A voltage Vpass is applied to the unselected word line coupled to the selected memory block. An analog signal of the computation result can be obtained by sensing the current on the bit line coupled to the selected memory block, for example, by sensing the current I on bit line BL0. D0 and for current I D0 The conversion yields the input voltage V. IN0 The corresponding input data and weight data w 00 The product of the input voltage V IN1 The corresponding input data and weight data w 10 The product of the input voltage V IN2 The corresponding input data and weight data w 20 The sum of these three products. In some embodiments, the first operation includes a multiplication-accumulation operation.

[0073] In some embodiments, such as Figure 5 As shown, taking the selected memory block as an example, which includes 8 memory strings coupled to bit line BL0, 4 memory cells coupled to the selected word line WLn are in the first memory state (i.e., erase state E), and the other 4 memory cells are in the second memory state (i.e., programmable state P). Input data can be input from the 8 top select gate lines TSL0 to TSL7 (or the gates of the 8 top select transistors TSG0 to TSG7). Specifically, the input data can be an input vector including 8 input data, which can include 5 "1"s and 3 "0"s. The digital-to-analog converter can convert each input data of the input vector into a corresponding voltage signal, and the voltage signal is converted into an input voltage to be applied to the top select gate line by a voltage generator. The input voltage is then transmitted to the top select gate line by a driver coupled to the top select gate line. Specifically, 8 input voltages can be applied to the 8 top select gate lines simultaneously. Among them, the input voltage corresponding to "1" includes V IN0 V IN1 V IN4 V IN5 and V IN6This allows the top-select transistors TSG0, TSG1, TSG4, TSG5, and TSG6, respectively coupled to the top-select gate lines TSL0, TSL1, TSL4, TSL5, and TSL6, to be turned on. The input voltages corresponding to "0" include V. IN2 V IN3 V IN7 This allows the top-select transistors TSG2, TSG3, and TSG7, which are respectively coupled to the top-select gate lines TSL2, TSL3, and TSL7, to be turned off.

[0074] In a specific example, such as Figure 5 As shown, the current I on bit line BL0 D0 The sum of the output currents of the eight memory strings coupled to the bit line BL0 is given. The input voltage on the top select gate line coupled to memory strings Str0, Str4, and Str5 causes the top select transistors TSG0, TSG4, and TSG5 to be in the on state. Furthermore, the memory cells in memory strings Str0, Str4, and Str5 coupled to the selected word line WLn have a first storage state (erase state E). Therefore, when memory strings Str0, Str4, and Str5 are turned on, a current greater than or equal to a preset current is generated. The current I on the bit line BL0 is... D0 The sum of the output currents of storage strings Str0, Str4, and Str5 is approximately equal, and the current I... D0 The current generated relative to any one of the storage strings Str0, Str4, and Str5 is approximately 3 times the current. If the weight value stored in the storage cell in the first storage state is equivalent to "1", and the weight value stored in the storage cell in the second storage state is equivalent to "0", then the operation performed by the 8 storage strings coupled to the bit line BL0 can be equivalent to: 1*1+1*0+0*1+0*0+1*1+1*1+1*0+0*0=3.

[0075] Based on NAND flash memory devices as in-memory computing devices, weighted data can be stored in a memory cell array, for example... Figure 5 The memory cell coupled to the selected word line WLn can be in either erase state (E) or programmable state (P); input data can be converted into a voltage signal and input via the top selection gate line, for example, Figure 5 The diagram illustrates that the top selection transistor can be in an on or off state. The analog signal of the result after the first operation can be output via a bit line. Parallel operations on multiple memory strings coupled to a single bit line can perform addition operations, further increasing computing power. The more memory strings coupled to a single bit line, the higher the computing power. In other words, the more memory blocks / strings can be activated at any given time, the higher the computing power.

[0076] refer to Figure 6 , Figure 6 The diagrams illustrate the operation methods of semiconductor devices as examples. Figure 6 As shown, in step S410, the memory bank to be operated on is selected, that is, the selected memory bank is determined. In step S420, all memory blocks / memory strings in the selected memory bank are powered on.

[0077] refer to Figure 7 , Figure 7 Voltage timing diagrams for some example semiconductor devices are provided. For example... Figure 7 As shown, "1" input TSG refers to the drain selection transistor in the memory block with input information "1", and "0" input TSG refers to the drain selection transistor in the memory block with input information "0".

[0078] For all drain-select transistors in the selected memory bank (Sel Bank), some drain-select transistors have an input information of "1". Correspondingly, the input information "1" is converted into a voltage signal and applied to the gate of these drain-select transistors. The input information "1" can be converted into a turn-on voltage Vtsg. Since Vtsg is greater than the threshold voltage of the drain-select transistor, the turn-on voltage Vtsg is applied to the gate of the drain-select transistor, and the drain-select transistor is in the on state. The other drain-select transistors have an input information of "0". Correspondingly, the input information "0" is converted into a voltage signal and applied to the gate of these drain-select transistors. The input information "0" can be converted into a turn-off voltage (e.g., ground voltage Vss). Since the turn-off voltage is less than the threshold voltage of the drain-select transistor, the turn-off voltage is applied to the gate of the drain-select transistor, and the drain-select transistor is in the off state.

[0079] A read voltage Vread is applied to the selected word line (Sel Bank - Sel WL) in the selected memory bank. The purpose of applying the read voltage Vread is to distinguish whether the memory cell coupled to the selected word line is in erase state E or programmable state P. The read voltage Vread is greater than the threshold voltage of the memory cell in erase state E and less than the threshold voltage of the memory cell in programmable state P.

[0080] A pass voltage Vpass is applied to the unselected word line in the selected memory bank. The pass voltage Vpass is greater than the threshold voltage of the memory cell to which the unselected word line is coupled.

[0081] In summary, when the input information is "0", the drain selection transistor is in the off state, and all memory strings containing the drain selection transistor are off memory strings. When the input information is "1", the drain selection transistor is in the on state, and all memory strings containing the drain selection transistor are on memory strings. If the selected memory cell in the memory string containing the drain selection transistor is in the erase state E, then the selected memory cell is in the on state; if the selected memory cell in the memory string containing the drain selection transistor is in the programming state P, then the selected memory cell is in the off state.

[0082] In the above technical solution, all memory blocks / strings in the selected memory bank are powered on. However, the number of conducting memory strings in the selected memory bank is limited, and there may be a large number of deactivated memory strings in the selected memory bank. During the execution of the first operation, the deactivated memory strings will be subject to read disturbance, causing the threshold voltage of the memory cells in the deactivated memory strings to shift upward (Vt Shift High), thereby affecting the current of the memory strings and ultimately affecting the result of the first operation.

[0083] In view of this, in order to solve at least one of the above-mentioned technical problems, this disclosure provides a semiconductor device, an operating method thereon, and a memory system.

[0084] refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 8 As shown, in a first aspect, embodiments of this disclosure provide a semiconductor device 500, which includes: a memory cell array 502 including a plurality of memory banks, each memory bank including a plurality of memory blocks, each memory block including a plurality of select transistors and a plurality of memory cells; word lines coupled to the memory cells; bit lines coupled to the select transistors; and peripheral circuitry coupled to the memory cell array 502, the word lines, and the bit lines.

[0085] In some embodiments, the peripheral circuitry may include a row decoder 506, a page buffer 508, a sensing circuit 510, and a voltage generator 512. Here, the descriptions of the memory cell array, select transistor, word lines, bit lines, row decoder 506, page buffer 508, sensing circuit 510, and voltage generator 512 can be found in the preceding descriptions of these components. Figures 1 to 3 The relevant textual descriptions will not be repeated here.

[0086] In some embodiments, the peripheral circuitry includes: control logic 514; and input detection circuitry 516, which is coupled to control logic 514 and configured to receive input data from a drain-select transistor and detect such input data.

[0087] In some embodiments, the peripheral circuitry includes a digital-to-analog converter circuit 518, which is coupled to control logic 514 and voltage generator 512 and configured to convert input data of the input drain-select transistor into a voltage signal.

[0088] refer to Figure 9 , Figure 9 To Figure 8 A magnified schematic diagram of the memory cell array. (See attached diagram.) Figure 9 As shown, the storage cell array 502 may include multiple storage planes, such as four storage planes: Plane0, Plane1, Plane2, and Plane3. Each storage plane may include multiple storage cells, and each storage cell includes at least one storage block. Figure 9 This diagram illustrates that each storage volume comprises N storage blocks, where N is an integer greater than or equal to 1.

[0089] refer to Figure 10 , Figure 10 To Figure 9 A magnified schematic diagram of the memory block structure. (See attached diagram.) Figure 10 As shown, the memory string includes a drain-select transistor, a memory cell, and a source-select transistor connected in series. The drain of the drain-select transistor can be coupled to a bit line, such as BL1 to BLm, and the gate of the drain-select transistor can be coupled to a drain-select-gate line. The gate of the memory cell can be coupled to a word line, such as WL0, WL1, ..., WL63. The source of the source-select transistor can be coupled to a common source line (CSL), and the gate of the source-select transistor can be coupled to a source-select-gate line. The memory string may also include a dummy bottom memory cell located between the source-select transistor and the memory cell, the gate of which can be coupled to a dummy bottom word line (Bottom Dummy WL); and a dummy top memory cell located between the drain-select transistor and the memory cell, the gate of which can be coupled to a dummy top word line (TopDummy WL). Figure 10 The four drain select transistors TSG0, TSG1, TSG2 and TSG3 coupled to the same bit line are shown for illustrative purposes only. The number of bit lines, the number of memory strings coupled to each bit line and the number of memory cells in each memory string are only examples in this disclosure.

[0090] refer to Figure 11 , Figure 11 This is a schematic flowchart illustrating the configuration of a semiconductor device provided in an embodiment of this disclosure to perform an operation. For example... Figure 11 As shown, the peripheral circuit is configured as follows:

[0091] Step S610: In performing the first operation, a first voltage is applied to the first word line coupled to the first memory block in the selected memory bank, and the input voltage of the gate of at least one selection transistor in the first memory block is a second voltage; and

[0092] Step S620: Apply a third voltage to the second word line coupled to the second memory block in the selected memory bank, and the input voltage of the gate of each selection transistor in the second memory block is a fourth voltage; wherein, the first voltage is greater than the third voltage, and the second voltage is greater than the fourth voltage.

[0093] Here, based on the different input information, the multiple memory blocks included in the selected memory are divided into a first memory block and a second memory block. Among the multiple memory blocks included in the selected memory, if the input information for at least one selection transistor in the memory block is first input data, then the memory block can be identified as the first memory block; if the input information for each selection transistor in the memory block is second input data, then the memory block can be identified as the second memory block. The input information of the first memory block can include two cases: first, the input information for each selection transistor in the first memory block is first input data; second, the input information for some selection transistors in the first memory block is first input data, and the input information for other selection transistors is second input data.

[0094] In some embodiments, the first input data can be "1" and the second input data can be "0". As described above, when the input information of the selected transistor is the first input data "1", the memory string containing the selected transistor belongs to the on-memory string. Since at least one selected transistor in the first memory block has the first input data "1", the first memory block includes at least one on-memory string. When the input information of the selected transistor is the second input data "0", the memory string containing the selected transistor belongs to the off-memory string. Since the input information of each selected transistor in the second memory block is the second input data "0", the second memory block only includes off-memory strings and does not include on-memory strings.

[0095] In this embodiment of the present disclosure, in step S610, during the execution of the first operation, a first voltage is applied to the first word line coupled to the first memory block in the selected memory bank; the first word line is the unselected word line coupled to the first memory block. In step S620, a third voltage is applied to the second word line coupled to the second memory block in the selected memory bank; the second word line is the unselected word line coupled to the second memory block. Considering that the first memory block includes at least one conducting memory string, the first voltage applied to the unselected word line coupled to the first memory block can make the unselected memory cell coupled to the unselected word line in the conducting state. Since the second memory block only includes the deselected memory string, the third voltage applied to the unselected word line coupled to the second memory block is less than the first voltage, so that the unselected memory cell coupled to the unselected word line can be in the conducting state or the deselected state. In this way, the read interference experienced by the second memory block during the execution of the first operation can be improved, and the power consumption of the semiconductor device can also be reduced.

[0096] In one specific embodiment, the third voltage can be 0V.

[0097] In some embodiments, the input detection circuit 516 is configured to: detect the input information of the selected transistors in a plurality of memory blocks in the selected memory bank during the execution of the first operation; wherein the input information of at least one selected transistor in the first memory block is first input data, and the input information of each selected transistor in the second memory block is second input data.

[0098] Here, the input detection circuit 516 is configured to detect the input information of all selection transistors in the plurality of memory blocks included in the selected memory bank, and the control logic 514 is configured to distinguish the first memory block and the second memory block in the plurality of memory blocks included in the selected memory bank according to the detection result.

[0099] In some embodiments, the digital-to-analog converter circuit 518 can convert a first input data "1" into a second voltage and a second input data "0" into a fourth voltage; wherein the second voltage is greater than the fourth voltage. More specifically, the second voltage is greater than the threshold voltage of the selection transistor, and when the second voltage is applied to the gate of the selection transistor, the selection transistor is in the on state; therefore, the second voltage can also be called the on-state voltage Vtsg. The fourth voltage is less than the threshold voltage of the selection transistor, and when the fourth voltage is applied to the gate of the selection transistor, the selection transistor is in the off state; therefore, the fourth voltage can also be called the off-state voltage.

[0100] In one specific embodiment, the fourth voltage can be 0V.

[0101] In some embodiments, control logic 514 is configured to: apply a second voltage to the gate of a selection transistor in the first memory block whose input information is first input data (e.g., the first input data is "1"), and apply a fourth voltage to the gate of a selection transistor in the first memory block whose input information is second input data (e.g., the second input data is "0"); and apply a fourth voltage to the gate of each selection transistor in the second memory block. Here, regardless of whether it is the first memory block or the second memory block, the second voltage is applied to the gate of the selection transistor whose input information is the first input data "1", and the fourth voltage is applied to the gate of the selection transistor whose input information is the second input data "0".

[0102] In some embodiments, control logic 514 is configured to: apply a fifth voltage to a third word line coupled to a first memory block in the selected memory bank during the execution of a first operation, wherein the third word line is the selected word line coupled to the first memory block; and apply a sixth voltage to a fourth word line coupled to a second memory block in the selected memory bank, wherein the fourth word line is the selected word line coupled to the second memory block; wherein the fifth voltage is greater than or equal to the sixth voltage, and the first voltage is greater than the fifth voltage.

[0103] Considering that the first memory block includes at least one active memory string, a fifth voltage, also known as the read voltage Vread, is applied to the selected word line coupled to the first memory block. For example, when the memory cell is SLC, the fifth voltage is greater than the threshold voltage of the selected memory cell with erase state E and less than the threshold voltage of the selected memory cell with programming state P. The second memory block only includes an active memory string, and a sixth voltage is applied to the selected word line coupled to the second memory block. On the one hand, the sixth voltage can be the same as the fifth voltage, that is, the read voltage Vread is applied to the selected word line coupled to the second memory block. In this way, applying the read voltage Vread to the selected word lines coupled to both the first and second memory blocks simplifies the control timing of the semiconductor device operation method. On the other hand, the sixth voltage can also be less than the fifth voltage, that is, the voltage applied to the selected word line coupled to the second memory block is less than the read voltage Vread. In this way, the voltage applied to the selected word line coupled to the second memory block is smaller, which can further reduce the power consumption of the semiconductor device.

[0104] In one specific embodiment, the sixth voltage can be 0V.

[0105] In some embodiments, the digital-to-analog converter circuit 518 is configured to convert a first input data (e.g., "1") into a second voltage and a second input data (e.g., "0") into a fourth voltage during the execution of a first operation. Here, the digital-to-analog converter circuit 518 can convert digital signals into analog signals. Before inputting the first or second input data into the selection transistor, the first and second input data need to be converted into corresponding voltage signals, respectively.

[0106] In some embodiments, the peripheral circuitry is configured to apply a corresponding programming voltage to the selected word line coupled to the selected memory block to program the memory cell coupled to the selected word line before performing the first operation using the memory cell array 502.

[0107] In one specific embodiment, a storage cell in the selected storage block is configured to store one bit of data. Multiple storage cells in the selected storage block have a first storage state and a second storage state. The threshold voltage of a storage cell in the first storage state is less than the threshold voltage of a storage cell in the second storage state. The read voltage Vread is greater than the threshold voltage of the storage cell in the first storage state and less than the threshold voltage of the storage cell in the second storage state. Here, the storage cell in the selected storage block can be an SLC storing one bit of data, the first storage state can be an erase state E, and the second storage state can be a programming state P. The peripheral circuit can be configured to: before performing the first operation, perform a programming operation on the storage cell coupled to the selected word line, writing weighted data into the storage cell according to a certain mapping rule. For an SLC, the weighted data writing process includes applying a corresponding programming voltage to adjust the threshold voltage of a portion of the storage cells coupled to the selected word line to within the range of the threshold voltage distribution corresponding to the second storage state.

[0108] In some embodiments, the memory cell array 502 is configured to store weight data; the bit lines are configured to sense current in the bit lines during the execution of a first operation, or to output current during the execution of a first operation; wherein the current in the bit lines is used as an analog signal indicating the result of the first operation performed on the input data in all the selected transistors coupled thereto and the weight data in the selected memory cells.

[0109] In some embodiments, the current in the bit line can be sensed by peripheral circuitry, and more specifically, the current in the bit line can be sensed by sensing circuitry within the peripheral circuitry. In some embodiments, a current sensor, for example, can be used to convert the current signal output from the bit line into a voltage signal, and the analog-to-digital converter circuit 528 can further convert the voltage signal into a digital signal.

[0110] Return to reference Figure 5As shown, the current on the bit line is the sum of the output currents of all coupled memory strings. The current in each memory string depends on the input information to the selection transistors in the string and the weighted data stored in the selected memory cell. Taking memory string str0 as an example, the input information to the top selection transistor TSG0 is the first input data "1", and the top selection transistor TSG0 is in the on state; the selected memory cell in memory string str0 is in the erase state E, and the selected memory cell in memory string str0 is in the on state. Therefore, memory string str0 is in the on state. Taking memory string str1 as an example, the input information to the top selection transistor TSG1 is the first input data "1", and the top selection transistor TSG0 is in the on state; the selected memory cell in memory string str0 is in the programming state P, and the selected memory cell in memory string str1 is in the off state. Therefore, memory string str1 is in the off state. Taking memory strings str2 and str3 as examples, if the input information for the top selection transistors TSG2 and TSG3 is the second input data "0", then the top selection transistors TSG2 and TSG3 are in the off state. Regardless of whether the selected memory cell in memory string str2 or str3 is in the on or off state, memory strings str2 and str3 are always in the off state. In other words, if either the top selection transistor or the selected memory cell in each memory string is in the off state, then the current in the memory string cannot be detected; only when both the top selection transistor and the selected memory cell are in the on state can the current in the memory string be detected.

[0111] In some embodiments, the first operation includes a multiplication-accumulation operation.

[0112] In some embodiments, the semiconductor device 500 includes a NAND-type memory device.

[0113] refer to Figure 12 , Figure 12 To Figure 8 Architecture framework of semiconductor devices Figure 1 .like Figure 12 As shown, in some embodiments, the first semiconductor structure 520 includes a memory cell array 502; the second semiconductor structure 522 includes a peripheral circuit 504; wherein the first semiconductor structure 520 and the second semiconductor structure 522 are bonded together. Here, the memory cell array 502 may be disposed on a first wafer, and the peripheral circuit 504 may be disposed on a second wafer, bonding the first wafer and the second wafer together.

[0114] refer to Figure 13 , Figure 13 To Figure 8 Architecture framework of semiconductor devices Figure 2 .like Figure 13As shown, in some embodiments, the first semiconductor structure 520 includes a memory cell array 502; the second semiconductor structure 522 includes peripheral circuitry 504 and analog-to-digital converter circuitry 528; wherein the first semiconductor structure 520 and the second semiconductor structure 522 are bonded together. Here, the memory cell array 502 may be disposed on a first wafer, and the peripheral circuitry 504 and analog-to-digital converter circuitry 528 may be disposed on a second wafer, bonding the first wafer and the second wafer together.

[0115] Here, bonding includes hybrid bonding (also known as "metal / dielectric hybrid bonding"), a direct bonding technique that forms bonds between surfaces without the use of intermediate layers such as solder or adhesive, and can simultaneously achieve metal-to-metal and dielectric-to-dielectric bonding. It should be noted that the term "bonding" as used in this disclosure can refer to any suitable bonding technique, such as the hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding mentioned above.

[0116] In some embodiments, the first semiconductor structure 520 further includes a first bonding layer 524, and the second semiconductor structure 522 further includes a second bonding layer 526, wherein the first bonding layer 524 and the second bonding layer 526 are bonded together. The semiconductor device 500 further includes a first bonding interface between the first bonding layer 524 and the second bonding layer 526, wherein data transmission between the first semiconductor structure 520 and the second semiconductor structure 522 is realized through interconnection across the first bonding interface.

[0117] In some embodiments, a first interconnect layer may also be included between the memory cell array 502 and the first bonding layer 524. Figure 12 and Figure 13 (Not shown in the diagram), a second interconnect layer may also be included between the peripheral circuit 504 and the second bonding layer 526. Figure 12 and Figure 13 (Not shown in the diagram). The first and second interconnect layers may include multiple interconnect structures, such as lateral conductive lines or via structures, which may be formed in one or more inter-layer dielectric (ILD) layers. The interconnect structures may include conductive materials, including but not limited to tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), silicides, or any combination thereof. The inter-layer dielectric layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, or any combination thereof.

[0118] In some embodiments, the first bonding layer 524 includes a first bonding contact and a first dielectric layer isolating the first bonding contact, and the second bonding layer 526 includes a second bonding contact and a second dielectric layer isolating the second bonding contact; wherein the first bonding contact and the second bonding contact are bonded, and the first dielectric layer and the second dielectric layer are bonded. The first bonding contact and the second bonding contact may include conductive materials, including but not limited to tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), silicides, or any combination thereof. The first dielectric layer and the second dielectric layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, or any combination thereof. The first bonding contact (or second bonding contact) and the first dielectric layer (or second dielectric layer) in the first bonding layer (or the second bonding layer) can be used to form a hybrid bond, which can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding.

[0119] refer to Figure 14 , Figure 14 This is a flowchart illustrating the operation method of a semiconductor device provided in an embodiment of this disclosure. Figure 14 As shown, in step S710, the memory bank to be operated on is selected, i.e., the selected memory bank is determined. In step S720, the input information of the memory blocks in the memory bank is pre-recorded in the peripheral circuit as either "0" or "1", i.e., the input information of the drain selection transistors in the memory blocks is either "0" or "1". In step S730, the input information of the memory blocks is obtained based on the input information. In step S740, only the memory blocks in the selected memory bank with input information of "1" are powered on, and the memory blocks with all input information of "0" are not powered on. That is, only the first memory block in the selected memory bank (i.e., at least one drain selection transistor in the first memory block has input information of "1") is powered on, and the second memory block in the selected memory bank (i.e., all drain selection transistors in the second memory block have input information of "0") is not powered on. Specifically, the input information of at least one drain selection gate line coupled to the first memory block is "1", and the input information of all drain selection gate lines coupled to the second memory block is "0".

[0120] refer to Figure 15 , Figure 15 A voltage timing diagram of a semiconductor device provided in an embodiment of this disclosure. For example... Figure 15 As shown, a "1" input TSG refers to a drain-select transistor in the first memory block whose input information is "1", and a "0" input TSG refers to a drain-select transistor in both the first and second memory blocks whose input information is "0". A "1" input BLKs refers to at least one drain-select transistor in a memory block whose input information is "1", i.e., the first memory block; a "0" input BLKs refers to all drain-select transistors in a memory block whose input information is "0", i.e., the second memory block.

[0121] A power-on voltage Vtsg is applied to the gate of the drain-select transistor in the first memory block of the selected memory bank where the input information is "1", and a ground voltage Vss is applied to the gate of the drain-select transistor in the first memory block of the selected memory bank where the input information is "0"; a ground voltage Vss is applied to the gate of the drain-select transistor in the second memory block of the selected memory bank where the input information is "0". In other words, a power-on operation can be performed only on the first memory block, while a power-off operation can be performed on the second memory block.

[0122] A read voltage Vread is applied to the selected word line (Sel Bank-Sel WL) in the selected memory bank. In some embodiments, the read voltage Vread may be applied to the selected word line coupled to both the first and second memory blocks in the selected memory bank. In other embodiments, the read voltage Vread may be applied to the selected word line coupled to the first memory block in the selected memory bank, and a ground voltage Vss may be applied to the selected word line coupled to the second memory block in the selected memory bank.

[0123] A pass voltage Vpass is applied to the unselected word line coupled to the first memory block in the selected memory bank. The pass voltage Vpass is greater than the threshold voltage of the memory cell coupled to the unselected word line. A ground voltage Vss is applied to the unselected word line coupled to the second memory block in the selected memory bank, or the unselected word line coupled to the second memory block in the selected memory bank is floated (corresponding to...). Figure 15 The diagram shows Vdd, to avoid read interference with the storage cells in the second storage block.

[0124] refer to Figure 16 , Figure 16 A block diagram of an electronic device provided in an embodiment of this disclosure. (As shown) Figure 16 As shown, in a second aspect, embodiments of this disclosure provide a memory system 804 including: a semiconductor device 500 as described above; and a controller 806 coupled to the semiconductor device 500 and configured to control the semiconductor device 500.

[0125] This disclosure also provides an electronic device 800, which includes: a memory system 804 as described above; and a host 802 coupled to the memory system 804.

[0126] Here, electronic device 800 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having semiconductor devices therein.

[0127] like Figure 16 As shown, the electronic device 800 may include a host 802 and a memory system 804, the memory system 804 having one or more semiconductor devices 500 and a controller 806. The host 802 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 802 may be configured to send data to or receive data from the semiconductor device 500.

[0128] In some embodiments, controller 806 is coupled to semiconductor device 500 and host 802 and is configured to control semiconductor device 500. Controller 806 can manage data stored in semiconductor device 500 and communicate with host 802.

[0129] In some embodiments, the controller 806 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0130] In some embodiments, the controller 806 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0131] Controller 806 can be configured to control the operation of semiconductor device 500, such as read, erase, and program operations. Controller 806 can also be configured to manage various functions related to data stored or to be stored in semiconductor device 500, including but not limited to bad block management, garbage collection, logical address to physical address translation, wear leveling, etc. In some embodiments, controller 806 is also configured to process error correcting codes (ECCs) related to data read from or written to semiconductor device 500.

[0132] Controller 806 can also perform any other suitable function, such as formatting semiconductor device 500. Controller 806 can communicate with external devices (e.g., host 802) according to a specific communication protocol. For example, controller 806 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0133] The controller 806 and one or more semiconductor devices 500 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 804 can be implemented and packaged into different types of end electronic products.

[0134] refer to Figure 17 , Figure 17 This is a schematic block diagram of a memory card with a memory system provided in an embodiment of this disclosure. Figure 17As shown, controller 806 and a single semiconductor device 500 can be integrated into memory card 902. Memory card 902 may include Personal Computer Memory Card International Association (PCMCIA) cards, CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (e.g., MMC, Reduced-Size MMC (RS-MMC), microMMC), SD cards (e.g., SD, miniSD, microSD, Secure Digital High Capacity (SDHC)), UFS, etc. Memory card 902 may also include a connection between memory card 902 and a host (e.g., Figure 16 The memory card connector 904 is coupled to the host 802.

[0135] refer to Figure 18 , Figure 18 This is a schematic block diagram of a solid-state driver with a memory system provided in an embodiment of this disclosure. Figure 18 As shown, controller 806 and multiple semiconductor devices 500 can be integrated into solid-state drive 906. Solid-state drive 906 may also include a connection between solid-state drive 906 and host (e.g., Figure 16 The solid-state drive connector 908 is coupled to the host 802. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 906 is greater than the storage capacity and / or operating speed of the memory card 902.

[0136] refer to Figure 19 , Figure 19 A schematic diagram of a digital-to-analog converter circuit and an analog-to-digital converter circuit is provided for embodiments of this disclosure. (See diagram for example.) Figure 19 As shown, in some embodiments, the memory system further includes an analog-to-digital converter circuit 528 coupled to a semiconductor device, configured to convert the analog signal of the result of the first operation into a digital signal. Here, the control logic 514 in the peripheral circuit 504 can receive input information; the digital-to-analog converter circuit 518 in the peripheral circuit 504 can convert the input information into a corresponding voltage to be applied to the drain-select gate line; the memory cell array 502 can perform the first operation and output the analog signal of the result of the first operation to the analog-to-digital converter circuit 528 through a bit line, and the analog-to-digital converter circuit 528 can convert the analog signal of the operation result into a digital signal.

[0137] Reference 20, Figure 20 For including Figure 12A schematic block diagram of the architecture of a semiconductor device's memory system. (Example) Figure 20 As shown, in some embodiments, the memory system 804 further includes a data processing circuit 808 coupled to the analog-to-digital converter circuit 528, configured to perform a second operation on the digital signal of the result of the first operation.

[0138] In some embodiments, the data processing circuit 808 may include a processor, which may include a dedicated processor, including but not limited to a CPU, a graphics processing unit (GPU), a digital signal processing unit (DSP), a tensor processing unit (TPU), a visual processing unit (VPU), a neural processing unit (NPU), a synergistic processing unit (SPU), a physics processing unit (PPU), and an image signal processor (ISP).

[0139] In some embodiments, the second operation includes at least one of compensation, activation, shift, and pooling operations.

[0140] In one specific embodiment, the memory cell array 502 in the semiconductor device 500 is configured to store a weight matrix to perform multiplication-accumulation operations and output an analog signal of the operation result; the analog-to-digital converter circuit 528 in the semiconductor device 500 is configured to convert the analog signal of the operation result into a digital signal, and the data processing circuit 808 is configured to perform activation operations on the digital signal to generate an output result. In some embodiments, the activation operation can be implemented by an activation function in the NPU, which may include, but is not limited to, a step function, a correction function, a sigmoid function, and a hyperbolic tangent function.

[0141] refer to Figure 21 , Figure 21 For including Figure 13 A schematic block diagram of the architecture of a semiconductor device's memory system. (Example) Figure 21As shown, in some embodiments, the memory system 804 further includes: a first semiconductor structure 520, including a memory cell array 502; a second semiconductor structure 522, including peripheral circuitry 504; and a third semiconductor structure 810, including an analog-to-digital converter circuit 528, a data processing circuit 808, and a controller 806; wherein the first semiconductor structure 520, the second semiconductor structure 522, and the third semiconductor structure 810 are bonded together, and the first semiconductor structure 520 is disposed between the second semiconductor structure 522 and the third semiconductor structure 810. Here, the memory cell array 502 may be disposed on a first wafer, the peripheral circuitry 504 may be disposed on a second wafer, and the analog-to-digital converter circuit 528, the data processing circuit 808, and the controller 806 may be disposed on a third wafer, bonding the first wafer, the second wafer, and the third wafer together.

[0142] like Figure 20 As shown, in some embodiments, the memory system 804 further includes: a first semiconductor structure 520, including a memory cell array 502; a second semiconductor structure 522, including peripheral circuitry 504 and an analog-to-digital converter circuit 528; and a third semiconductor structure 810, including a data processing circuit 808 and a controller 806. The first semiconductor structure 520, the second semiconductor structure 522, and the third semiconductor structure 810 are bonded together, and the first semiconductor structure 520 is disposed between the second semiconductor structure 522 and the third semiconductor structure 810. Here, the memory cell array 502 may be disposed on a first wafer, the peripheral circuitry 504 and the analog-to-digital converter circuit 528 may be disposed on a second wafer, and the data processing circuit 808 and the controller 806 may be disposed on a third wafer, bonding the first wafer, the second wafer, and the third wafer together.

[0143] Here, bonding includes hybrid bonding (also known as "metal / dielectric hybrid bonding"), a direct bonding technique that forms bonds between surfaces without the use of intermediate layers such as solder or adhesive, and can simultaneously achieve metal-to-metal and dielectric-to-dielectric bonding. It should be noted that the term "bonding" as used in this disclosure can refer to any suitable bonding technique, such as the hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding mentioned above.

[0144] In some embodiments, the first semiconductor structure 520 further includes a third bonding layer 812, and the third semiconductor structure 810 further includes a fourth bonding layer 814, wherein the third bonding layer 812 and the fourth bonding layer 814 are bonded together. The memory system 804 further includes a second bonding interface between the third bonding layer 812 and the fourth bonding layer 814, wherein data transfer between the first semiconductor structure 520 and the third semiconductor structure 810 is realized through interconnection across the second bonding interface.

[0145] In some embodiments, a third interconnect layer may also be included between the memory cell array 502 and the third bonding layer 812. Figure 20 and Figure 21 (Not shown in the diagram), a fourth interconnect layer may also be included between the data processing circuit 808, the controller 806, and the fourth bonding layer 814. Figure 20 and Figure 21 (Not shown in the diagram). The third and fourth interconnect layers may include multiple interconnect structures, such as lateral conductive lines or via structures, which may be formed in one or more inter-layer dielectric (ILD) layers. The interconnect structures may include conductive materials, including but not limited to tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), silicides, or any combination thereof. The inter-layer dielectric layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, or any combination thereof.

[0146] In some embodiments, the third bonding layer 812 includes a third bonding contact and a third dielectric layer isolating the third bonding contact, and the fourth bonding layer 814 includes a fourth bonding contact and a fourth dielectric layer isolating the fourth bonding contact; wherein the third bonding contact and the fourth bonding contact are bonded, and the third dielectric layer and the fourth dielectric layer are bonded. The third bonding contact and the fourth bonding contact may include conductive materials, including but not limited to tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), silicides, or any combination thereof. The third dielectric layer and the fourth dielectric layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, or any combination thereof. The third bonding contact (or fourth bonding contact) and the third dielectric layer (or fourth dielectric layer) in the third bonding layer (or fourth bonding layer) can be used to form a hybrid bond, which can simultaneously achieve metal-metal bonding and dielectric-dielectric bonding.

[0147] Combination Figure 8 and Figure 11 As shown, in a third aspect, embodiments of this disclosure provide an operation method for a semiconductor device. The semiconductor device 500 includes a memory cell array 502, the memory cell array 502 includes a plurality of memory cells, each memory cell includes a plurality of memory blocks, and each memory block includes a plurality of select transistors and a plurality of memory cells. The operation method includes:

[0148] Step S610: In performing the first operation, a first voltage is applied to the first word line coupled to the first memory block in the selected memory bank, and the input voltage of the gate of at least one selection transistor in the first memory block is a second voltage; and

[0149] Step S620: Apply a third voltage to the second word line coupled to the second memory block in the selected memory bank, and the input voltage of the gate of each selection transistor in the second memory block is a fourth voltage; wherein, the first voltage is greater than the third voltage, and the second voltage is greater than the fourth voltage.

[0150] In some embodiments, the operation method further includes: detecting input information of selected transistors in a plurality of memory blocks in a selected memory bank during the execution of the first operation; wherein the input information of at least one selected transistor in the first memory block is first input data, and the input information of each selected transistor in the second memory block is second input data.

[0151] In some embodiments, the operation method further includes: applying a second voltage to the gate of a selection transistor in the first memory block whose input information is first input data, and applying a fourth voltage to the gate of a selection transistor in the first memory block whose input information is second input data, during the execution of the first operation; and applying a fourth voltage to the gate of each selection transistor in the second memory block.

[0152] In some embodiments, the operation method further includes: applying a fifth voltage to a third word line coupled to a first memory block in the selected memory bank during the execution of the first operation; and applying a sixth voltage to a fourth word line coupled to a second memory block in the selected memory bank; wherein the fifth voltage is greater than or equal to the sixth voltage, and the first voltage is greater than the fifth voltage.

[0153] In some embodiments, the method further includes: converting first input data into a second voltage and converting second input data into a fourth voltage during the execution of the first operation.

[0154] In some embodiments, the memory cell array is used to store weight data; the semiconductor device further includes bit lines coupled to selection transistors; the operation method further includes: sensing current in the bit lines during the execution of a first operation, or outputting current during the execution of a first operation; wherein the current in the bit lines is used as an analog signal indicating the result of the first operation performed on the input data in all the selection transistors coupled thereto and the weight data in the selected memory cells.

[0155] In some embodiments, the third voltage is 0V; and / or, the fourth voltage is 0V; and / or, the sixth voltage is 0V.

[0156] In some embodiments, the first operation includes a multiplication-accumulation operation.

[0157] This disclosure provides a semiconductor device, its operating method, and a memory system. In this embodiment, during the execution of a first operation, a first voltage is applied to a first word line coupled to a first memory block in the selected memory bank, and a third voltage is applied to a second word line coupled to a second memory block in the selected memory bank. The first voltage is greater than the third voltage. This improves the read interference experienced by the second memory block during the execution of the first operation and also reduces the power consumption of the semiconductor device.

[0158] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0159] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A memory cell array includes multiple memory banks, each memory bank including multiple memory blocks, each memory block including multiple selection transistors and multiple memory cells; Word lines coupled to the memory cell; Peripheral circuitry coupled to the memory cell array and the word lines, the peripheral circuitry being configured as follows: In performing the first operation, a first voltage is applied to a first word line coupled to a first memory block in the selected memory bank, and the input voltage of the gate of at least one selected transistor in the first memory block is a second voltage; and A third voltage is applied to the second word line coupled to the second memory block in the selected memory bank, and the input voltage of the gate of each selected transistor in the second memory block is a fourth voltage; wherein the first voltage is greater than the third voltage, and the second voltage is greater than the fourth voltage.

2. The semiconductor device according to claim 1, characterized in that, The peripheral circuit also includes an input detection circuit, which is configured to: In performing the first operation, the input information of the selection transistors in the plurality of memory blocks in the selected memory bank is detected; wherein, the input information of at least one selection transistor in the first memory block is first input data, and the input information of each selection transistor in the second memory block is second input data.

3. The semiconductor device according to claim 2, characterized in that, The peripheral circuit further includes: control logic coupled to the input detection circuit, the control logic being configured to: In performing the first operation, the second voltage is applied to the gate of the selection transistor in the first memory block where the input information is the first input data, and the fourth voltage is applied to the gate of the selection transistor in the first memory block where the input information is the second input data; and The fourth voltage is applied to the gate of each of the selected transistors in the second memory block.

4. The semiconductor device according to claim 3, characterized in that, The control logic is configured as follows: In performing the first operation, a fifth voltage is applied to the third word line coupled to the first memory block in the selected memory bank; as well as A sixth voltage is applied to the fourth word line coupled to the second memory block in the selected memory bank; wherein the fifth voltage is greater than or equal to the sixth voltage, and the first voltage is greater than the fifth voltage.

5. The semiconductor device according to claim 3, characterized in that, The peripheral circuit further includes a digital-to-analog converter circuit, which is configured to: In performing the first operation, the first input data is converted into the second voltage, and the second input data is converted into the fourth voltage.

6. The semiconductor device according to claim 1, characterized in that, The storage cell array is configured to store weight data; The semiconductor device further includes: a bit line coupled to the selection transistor, the bit line being configured to: In performing the first operation, the current of the bit line is sensed; wherein the current of the bit line is used as an analog signal indicating the result of the operation after the input data in all the selected transistors coupled thereto and the weight data in the selected memory cell are performed on the first operation.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A first semiconductor structure, including the memory cell array; The second semiconductor structure includes the peripheral circuit; wherein the first semiconductor structure and the second semiconductor structure are bonded together.

8. The semiconductor device according to claim 4, characterized in that, The third voltage is 0V; and / or, the fourth voltage is 0V; and / or, the sixth voltage is 0V.

9. The semiconductor device according to claim 1, characterized in that, The first operation includes multiplication and accumulation operations.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a NAND-type memory device.

11. A memory system, characterized in that, The memory system includes: The semiconductor device as claimed in any one of claims 1 to 10; and A controller coupled to the semiconductor device and configured to control the semiconductor device.

12. The memory system according to claim 11, characterized in that, The memory system further includes: an analog-to-digital converter circuit coupled to the semiconductor device, configured to: The analog signal of the result of the first operation is converted into a digital signal.

13. The memory system according to claim 12, characterized in that, The memory system further includes a data processing circuit coupled to the analog-to-digital conversion circuit, configured to: Perform a second operation on the digital signal resulting from the first operation.

14. The memory system according to claim 13, characterized in that, The second operation includes at least one of the following operations: compensation, activation, shift, and pooling.

15. The memory system according to claim 13, characterized in that, The memory system also includes: A first semiconductor structure, including the memory cell array; The second semiconductor structure includes the peripheral circuit and the analog-to-digital conversion circuit; The third semiconductor structure includes the data processing circuit and the controller; wherein the first semiconductor structure, the second semiconductor structure and the third semiconductor structure are bonded together, and the first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure.

16. The memory system according to claim 15, characterized in that, The memory system also includes: A first semiconductor structure, including the memory cell array; The second semiconductor structure includes the peripheral circuitry; The third semiconductor structure includes the analog-to-digital conversion circuit, the data processing circuit, and the controller; wherein the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are bonded together, and the first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure.

17. A method of operating a semiconductor device, characterized in that, The semiconductor device includes a memory cell array, the memory cell array including multiple memory banks, the memory banks including multiple memory blocks, and the memory blocks including multiple selection transistors and multiple memory cells; the operation method includes: In performing the first operation, a first voltage is applied to a first word line coupled to a first memory block in the selected memory bank, and the input voltage of the gate of at least one selected transistor in the first memory block is a second voltage; and A third voltage is applied to the second word line coupled to the second memory block in the selected memory bank, and the input voltage of the gate of each selected transistor in the second memory block is a fourth voltage; wherein the first voltage is greater than the third voltage, and the second voltage is greater than the fourth voltage.

18. The operating method according to claim 17, characterized in that, The operation method further includes: In performing the first operation, the input information of the selection transistors in the plurality of memory blocks in the selected memory bank is detected; wherein, the input information of at least one selection transistor in the first memory block is first input data, and the input information of each selection transistor in the second memory block is second input data.

19. The operating method according to claim 18, characterized in that, The operation method further includes: In performing the first operation, the second voltage is applied to the gate of the selection transistor in the first memory block where the input information is the first input data, and the fourth voltage is applied to the gate of the selection transistor in the first memory block where the input information is the second input data; and The fourth voltage is applied to the gate of each of the selected transistors in the second memory block.

20. The operating method according to claim 19, characterized in that, The operation method further includes: In performing the first operation, a fifth voltage is applied to the third word line coupled to the first memory block in the selected memory bank; and A sixth voltage is applied to the fourth word line coupled to the second memory block in the selected memory bank; wherein the fifth voltage is greater than or equal to the sixth voltage, and the first voltage is greater than the fifth voltage.

21. The operating method according to claim 19, characterized in that, The operation method further includes: In performing the first operation, the first input data is converted into the second voltage, and the second input data is converted into the fourth voltage.

22. The operating method according to claim 17, characterized in that, The memory cell array is used to store weight data; the semiconductor device further includes bit lines coupled to the selection transistor; the operation method further includes: In performing the first operation, the current of the bit line is sensed; wherein the current of the bit line is used as an analog signal indicating the result of the operation after the input data in all the selected transistors coupled thereto and the weight data in the selected memory cell are performed on the first operation.

23. The operating method according to claim 20, characterized in that, The third voltage is 0V; and / or, the fourth voltage is 0V; and / or, the sixth voltage is 0V.

24. The operating method according to claim 17, characterized in that, The first operation includes multiplication and addition operations.

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