Three-dimensional packaging structure

Abstract

The present application provides a three-dimensional packaging structure, which includes a motherboard, an intermediate structure, a memory stack structure and a system chip. The intermediate structure is arranged on the motherboard and is electrically connected to the motherboard through a plurality of first connecting components. The memory stack structure is arranged on the intermediate structure and is electrically connected to the intermediate structure through a plurality of second connecting components, wherein the memory stack structure includes a plurality of memory chips stacked and electrically connected to each other. The system chip is arranged on the memory stack structure and is electrically connected to the memory stack structure through a plurality of third connecting components.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging structure, and more particularly to a three-dimensional (3D) packaging structure with a memory stacking structure suitable for high-bandwidth applications. Background Technology

[0002] As the demand for artificial intelligence grows, stacked packaging structures are becoming increasingly popular for memory manufacturing to reduce costs and accommodate high-bandwidth applications. For example, existing high-bandwidth memory stacked packaging structures include a memory chip package, other types of chips, an interposer, and a packaging substrate. The memory chip package includes a base chip and multiple memory chips stacked on top of it. Other types of chips (such as logic chips) are horizontally adjacent to the memory chip package on the interposer and electrically connected to it. However, to simultaneously meet the high bandwidth requirements, the miniaturization of existing high-bandwidth memory is limited. Therefore, a packaging substrate is necessary to support and electrically connect the interposer on which the memory chip package and various other chips are mounted to prevent warping of the high-bandwidth memory. In other words, the interposer must be located on one side of the packaging substrate and electrically connected to the motherboard via solder balls located on the other side of the packaging substrate.

[0003] For the aforementioned stacked packaging structure, the considerable thickness required to house the memory chip package, interposer, and packaging substrate limits the miniaturization of existing high-bandwidth memory. However, this miniaturization limitation hinders improvements in certain applications, such as edge computing. Furthermore, the inclusion of expensive organic substrates in the packaging substrate further restricts cost reduction. Additionally, the location of the organic substrate between the interposer and the motherboard necessitates heat dissipation through the top of the stacked packaging structure, resulting in lower heat dissipation efficiency. Summary of the Invention

[0004] The present invention relates to a three-dimensional packaging structure in which an intermediate structure is attached to a motherboard by connecting components, without setting a packaging substrate.

[0005] According to an embodiment of the present invention, a three-dimensional packaging structure includes a motherboard, an interposer structure, a memory stack structure, and a system-on-a-chip (SoC). The interposer structure is disposed on the motherboard and electrically connected to the motherboard via a plurality of first connecting components. The memory stack structure is disposed on the interposer structure and electrically connected to the interposer structure via a plurality of second connecting components, wherein the memory stack structure includes a plurality of memory chips stacked and electrically connected to each other. The SoC is disposed on the memory stack structure and electrically connected to the memory stack structure via a plurality of third connecting components.

[0006] Based on the above, in the three-dimensional packaging structure of the present invention, the system chip is disposed and electrically connected to the memory stack structure, the memory stack structure is disposed and electrically connected to the intermediate structure, and the intermediate structure is attached to the motherboard via a first connecting component. Compared with the three-dimensional packaging structure in the prior art, the organic material substrate located between the intermediate structure and the motherboard is omitted in the three-dimensional packaging structure of the present invention. Therefore, the three-dimensional packaging structure of the present invention can have a smaller thickness, which is beneficial for edge computing applications, and has lower manufacturing costs and better heat dissipation performance. Attached Figure Description

[0007] Figure 1 This is a cross-sectional schematic diagram of the three-dimensional packaging structure according to the first embodiment of the present invention;

[0008] Figure 2 This is a cross-sectional schematic diagram of the three-dimensional packaging structure according to the second embodiment of the present invention. Detailed Implementation

[0009] In various embodiments of the present invention, a memory stack structure formed by multiple memory chips is disposed on and electrically connected to an intermediate structure, and the intermediate structure on which the memory stack structure is disposed is disposed on a motherboard and connected to the motherboard via a connecting component. That is, in various embodiments of the present invention, no packaging substrate is disposed between the intermediate structure and the motherboard, thus effectively reducing the thickness and manufacturing cost of the packaging structure, which is beneficial for edge computing applications, and improving the heat dissipation performance of the packaging structure. The embodiments of the present invention will be described in detail below.

[0010] Reference Figure 1 The three-dimensional packaging structure 10 in this embodiment includes a motherboard (MB), an intermediate structure (IP), a memory stack structure (MS), and a system-on-a-chip (SOC). The intermediate structure (IP) is disposed on the motherboard (MB) and electrically connected to it. The memory stack structure (MS) is disposed on the intermediate structure (IP) and electrically connected to it. The system-on-a-chip (SOC) is disposed on the memory stack structure (MS) and electrically connected to it.

[0011] The motherboard (MB) carries the interposer IP, the memory stack structure (MS), and the system-on-a-chip (SoC). Furthermore, the motherboard (MB) may include circuit patterns (not shown) that allow the interposer IP, the memory stack structure (MS), and the SoC to be electrically connected to the motherboard (MB) via various connection components. In this embodiment, the motherboard (MB) may be any motherboard well-known in the art, and this invention is not limited thereto.

[0012] In this embodiment, the interposer IP includes a silicon substrate 100, a lower redistribution layer 102, an upper redistribution layer 104, and a plurality of through-silicon vias (TSVs) 1. The lower redistribution layer 102 and the upper redistribution layer 104 are respectively disposed on the upper and lower surfaces of the silicon substrate 100, and the TSVs 1 are disposed in and penetrate the silicon substrate 100 to connect the lower redistribution layer 102 and the upper redistribution layer 104. In this way, the upper redistribution layer 104 can be electrically connected to the lower redistribution layer 102 through the TSVs 1. Since the main material of the interposer IP is silicon (thermal conductivity of approximately 148 W / (m×K)), the interposer IP can have good thermal conductivity.

[0013] Furthermore, in this embodiment, the intermediate structure IP is connected to the motherboard MB via multiple first connection components CT1. More specifically, the first connection components CT1 are disposed between the intermediate structure IP and the motherboard MB, and are connected to the lower redistribution layer 102 of the intermediate structure IP and the wiring pattern of the motherboard MB, allowing the intermediate structure IP to be electrically connected to the motherboard MB via the first connection components CT1. The first connection components CT1 are, for example, solder balls, and may have a diameter of not less than 0.3 mm, allowing the intermediate structure IP to be securely attached to the motherboard MB. Figure 1 In this paper, the number and layout of the first connecting components CT1 are merely exemplary, and the present invention does not limit them.

[0014] In this embodiment, the memory stack structure MS includes four memory chips 106 stacked and electrically connected to each other to include more than 4000 input / output terminals, but the invention is not limited thereto. In other embodiments, the memory stack structure MS may include more or fewer memory chips 106 depending on actual needs. The memory chips 106 in the memory stack structure MS may be the same or different from each other. The memory chips 106 may be dynamic random access memory chips, but the invention is not limited thereto. Each memory chip 106 includes a plurality of through-silicon vias (TSVs) 2. The TSVs 2 penetrate the memory chip 106. Furthermore, the TSVs 2 in two adjacent memory chips 106 are electrically connected to each other through a plurality of fourth connection components (CT4) to transmit electrical signals in the memory stack structure MS.

[0015] Furthermore, when the through-silicon vias (TSV2s) connected in series via the fourth connection component CT4 are grounded, these TSV2s are not used to transmit electrical signals, but only serve as heat dissipation paths. Through circuit design, a portion of the TSV2s in the memory chip 106 can be used to transmit electrical signals to the interposer IP and the motherboard MB, while the remaining TSV2s can be used to transfer heat to the outside through the interposer IP and the motherboard MB. In this embodiment, the TSV2s located in the central region of the memory chip 106 can serve as heat dissipation paths, but the invention is not limited to this.

[0016] In this embodiment, the fourth connecting component CT4 may be a microbump, but the invention is not limited thereto. In other embodiments, depending on the actual situation, the fourth connecting component CT4 may be a hybrid bump. Figure 1 The number and layout of the fourth connection components CT4 are merely exemplary and are not intended to limit the invention. Furthermore, the adhesive UF2 may be disposed between adjacent memory chips 106 and cover the fourth connection components CT4 to protect them.

[0017] The memory stack structure MS is connected to the intermediate structure IP via multiple second connection components CT2. Furthermore, the second connection components CT2 are disposed between the memory stack structure MS and the intermediate structure IP, and are connected to the upper redistribution layer 104 of the intermediate structure IP and the through-silicon via (TSV2) of the bottommost memory chip 106 in the memory stack structure MS. This allows the memory stack structure MS to be electrically connected to the intermediate structure IP via the second connection components CT2, and also allows heat to be transferred to the outside via the intermediate structure IP and the motherboard MB.

[0018] In this embodiment, the second connecting component CT2 may be a microbump, but the invention is not limited thereto. In other embodiments, depending on the actual situation, the second connecting component CT2 may be a hybrid bump. Figure 1 In this paper, the number and layout of the second connection components CT2 are merely exemplary and are not intended to limit the invention. Furthermore, the base adhesive UF1 can be disposed between the upper redistribution layer 104 of the intermediate structure IP and the lowermost memory chip 106 of the memory stack structure MS, and cover the second connection components CT2 to protect them.

[0019] The System-on-a-Chip (SoC) is electrically connected to the memory stack structure MS via multiple third connection components CT3. Furthermore, the third connection components CT3 are disposed between the SoC and the memory stack structure MS, and are connected to the SoC's connection pads (not shown) and the through-silicon vias (TSV2) of the uppermost memory chip 106 in the memory stack structure MS, enabling the SoC to be electrically connected to the memory stack structure MS via the third connection components CT3. The SoC can be a logic chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a digital signal processing (DSP) chip, an application-specific integrated circuit (ASIC) chip, etc., and this invention does not limit this to any particular type.

[0020] In this embodiment, the third connecting component CT3 may be a microbump, but the invention is not limited thereto. In other embodiments, depending on the actual situation, the third connecting component CT3 may be a hybrid bump. Figure 1 In this paper, the number and layout of the third connection components CT3 are merely exemplary and are not intended to limit the invention. Furthermore, the base adhesive UF3 may be disposed between the system chip SOC and the uppermost memory chip 106 in the memory stack structure MS, and may cover the third connection components CT3 to protect them.

[0021] In the three-dimensional packaging structure 10 of this embodiment, the system-on-a-chip (SOC) is disposed and electrically connected to the memory stack structure MS, the memory stack structure MS is disposed and electrically connected to the intermediary structure IP, and the intermediary structure IP is connected to the motherboard MB via the first connection component CT1. Therefore, compared with the three-dimensional packaging structure in the prior art, the organic material substrate located between the intermediary structure IP and the motherboard MB is omitted. In this way, the thickness of the packaging structure is effectively reduced, which is beneficial for edge computing applications and reduces manufacturing costs.

[0022] Furthermore, in the three-dimensional packaging structure 10 of this embodiment, the intermediate structure IP with good thermal conductivity is directly connected to the mother board MB through the first connecting component CT1, omitting the organic material substrate with poor thermal conductivity (thermal conductivity coefficient of approximately 0.3 W / (m×K)). As a result, compared to the three-dimensional packaging structures in the prior art, the three-dimensional packaging structure 10 can have better heat dissipation performance.

[0023] In the three-dimensional packaging structure 10 of this embodiment, the projected area of ​​the system chip SOC on the motherboard MB is smaller than the projected area of ​​the memory stack structure MS on the motherboard MB. That is, during the manufacturing process of the three-dimensional packaging structure 10, the system chip SOC is formed on the memory stack structure MS using a chip-on-wafer method, but the invention is not limited to this. In other embodiments, depending on actual needs, the system chip SOC may be formed on the memory stack structure MS using a wafer-on-wafer method.

[0024] Figure 2 This is a cross-sectional schematic diagram of the three-dimensional packaging structure according to a second embodiment of the present invention. In this embodiment, the same components as in the first embodiment will be represented by the same reference numerals and will not be described further.

[0025] Reference Figure 2 In the three-dimensional packaging structure 20 of this embodiment, the system-on-a-chip (SOC) can be formed on the memory stack structure MS in a wafer-to-wafer manner. In this way, the edge of the SOC will be aligned with the edge of the memory stack structure MS.

[0026] Based on the above, the three-dimensional packaging structure of this embodiment can have lower manufacturing costs and energy consumption, thereby reducing carbon emissions in the packaging process. Therefore, this invention provides a green semiconductor technology.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-dimensional packaging structure, comprising: motherboard; An intermediate structure is disposed on the motherboard and electrically connected to the motherboard through a plurality of first connecting components; A storage stack structure is disposed on the intermediate structure and electrically connected to the intermediate structure via a plurality of second connection components, wherein the storage stack structure includes a plurality of storage chips stacked on top of each other and electrically connected. as well as The system chip is disposed on the storage stack structure and is electrically connected to the storage stack structure through multiple third connection components.

2. The three-dimensional packaging structure according to claim 1, characterized in that, The intermediary structure includes: Silicon substrate; An upper rewiring layer is disposed on the upper surface of the silicon substrate to connect with the plurality of second connection components; A lower redistribution layer is disposed on the lower surface of the silicon substrate for connection to the plurality of first connection components; and Multiple through-silicon vias are disposed in the silicon substrate to connect the upper rewiring layer and the lower rewiring layer.

3. The three-dimensional packaging structure according to claim 1, characterized in that, The memory chip includes multiple through-silicon vias (TSVs), and adjacent TSVs in two memory chips are electrically connected to each other through multiple fourth connection components.

4. The three-dimensional packaging structure according to claim 3, characterized in that, The fourth connection component includes microbumps or hybrid bumps.

5. The three-dimensional packaging structure according to claim 3, characterized in that, It also includes a base adhesive that covers the plurality of fourth connecting components.

6. The three-dimensional packaging structure according to claim 3, characterized in that, A portion of the plurality of through-silicon vias is electrically connected to the intermediate structure to transmit electrical signals, and the remainder of the plurality of through-silicon vias is grounded to transmit heat energy.

7. The three-dimensional packaging structure according to claim 1, characterized in that, The first connecting component includes solder balls.

8. The three-dimensional packaging structure according to claim 1, characterized in that, The second connection component includes microbumps or hybrid bumps.

9. The three-dimensional packaging structure according to claim 1, characterized in that, The third connection component includes microbumps or hybrid bumps.

10. The three-dimensional packaging structure according to claim 1, characterized in that, The memory chip includes a dynamic random access memory chip.

11. The three-dimensional packaging structure according to claim 1, characterized in that, It also includes a base adhesive that covers the plurality of third connecting components.

12. The three-dimensional packaging structure according to claim 1, characterized in that, It also includes a base adhesive that covers the plurality of second connecting components.

13. The three-dimensional packaging structure according to claim 1, characterized in that, The storage stack structure includes more than 4,000 input / output terminals.

14. The three-dimensional packaging structure according to claim 1, characterized in that, The projected area of ​​the system chip on the motherboard is smaller than the projected area of ​​the storage stack structure on the motherboard.

15. The three-dimensional packaging structure according to claim 1, characterized in that, The edge of the system chip is aligned with the edge of the storage stack structure.

Images