Super junction fast recovery low delta vth device and method of making same
By introducing a Ti/TiN/W plug structure into the superjunction device and optimizing the fabrication process, the problem of large δVTH in existing superjunction fast recovery products was solved, achieving low δVTH and uniform current distribution, thus improving device performance.
Patent Information
- Application Number
- CN202611221430.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-12
- Publication Date
- 2026-11-03
AI Technical Summary
In existing superjunction fast recovery products, the threshold voltage difference δVTH between units is large, resulting in inconsistent on-resistance and affecting device performance.
By employing a Ti/TiN/W plug structure and conventional metal sputtering equipment, and by adding an additional photolithography and etching process, the fabrication process of the superjunction device is optimized to form a Ti/TiN/W plug structure to reduce δVTH.
This achieves a threshold voltage difference δVTH < 1.0V between different units, reduces on-resistance, and improves the uniformity of current distribution and overall efficiency of the device.
Smart Images
Figure CN123035705A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device fabrication technology, specifically relating to a superjunction fast recovery low δVTH device and its fabrication method. Background Technology
[0002] Superjunction MOSFETs achieve optimized low on-resistance and high voltage withstand through alternating P-type and N-type pillar structures, which is a key technology to break through the "silicon limit" of traditional silicon MOSFETs.
[0003] In multi-epitaxial implantation (MEI) processes for superjunction MOSFETs, multiple epitaxial layer growths and p-type ion implantations are necessary to form a matching p-type structure. The number of growth cycles is directly proportional to the cost. Although MEI processes are expensive, they allow for precise charge balance by controlling parameters such as implantation energy and dosage after each epitaxial layer.
[0004] Superjunction fast recovery products are widely used in industrial and electric drive control, new energy vehicles, new energy and energy storage, data centers and communications, lighting and consumer electronics, etc. How to achieve a fast recovery superjunction with low δVTH is of great significance for reducing on-resistance and realizing the large on-resistance caused by poor VTH consistency of different cells in the die. It has important practical significance for the production and manufacturing of fast recovery products for semiconductor power devices. Summary of the Invention
[0005] To address the aforementioned problems in the prior art, this invention provides a superjunction fast recovery low δVTH device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for fabricating a superjunction fast recovery low δVTH device, comprising: S1, Provide a substrate; S2. Fabricate the superjunction alternating P / N pillar structure, gate structure, source / drain region and interlayer dielectric layer on the substrate, and form lead holes; S3. A Ti / TiN barrier layer is formed on the upper surface of the device and inside the lead hole by sputtering; S4. A tungsten layer is deposited on the Ti / TiN barrier layer, and part of the tungsten layer fills the lead hole; S5. Using a reverse etching process, the tungsten layer and a portion of the Ti / TiN barrier layer outside the lead hole are etched away; S6. While protecting the tungsten layer in the lead hole area through photolithography, a Ti / TiN reverse etching process is performed to remove the Ti / TiN barrier layer in the area outside the lead hole. S7. A sputtered AlCu metal layer is formed by photolithography and etching processes to create source and gate metal wiring. S8. A passivation protective layer is deposited, and the passivation layer in the source and gate regions is removed by photolithography and etching processes. S9. The drain electrode is formed through thinning and back-side metal evaporation processes.
[0006] In a second aspect, the present invention provides a superjunction fast recovery low δVTH device, which is prepared using the fabrication method of the superjunction fast recovery low δVTH device described in the first aspect above, comprising: A semiconductor substrate having a superjunction alternating P / N pillar structure, a gate structure, a source / drain region, and an interlayer dielectric layer covering the gate structure and the source / drain region are formed on the semiconductor substrate, and a lead hole is formed in the interlayer dielectric layer, the lead hole penetrating the interlayer dielectric layer and exposing the source / drain region or the gate structure below. A Ti / TiN barrier layer is provided on the inner wall of the lead hole, and a tungsten layer is filled inside the lead hole. The tungsten layer covers the Ti / TiN barrier layer and fills the lead hole. The Ti / TiN barrier layer and the tungsten layer together form a Ti / TiN / W plug structure inside the lead hole. A metal AlCu layer is disposed on the upper surface of the interlayer dielectric layer and on the top of the Ti / TiN / W plug structure. The metal AlCu layer is electrically connected to the Ti / TiN / W plug structure. The metal AlCu layer forms the source and gate electrodes after photolithography patterning. A passivation protective layer is covered above the metal AlCu layer, and the passivation protective layer has openings in the regions where the source and gate electrodes are located; A drain metal layer is disposed on the back side of the semiconductor substrate.
[0007] Compared with the prior art, the beneficial effects of the present invention are as follows: 1) The superjunction fast recovery product prepared using the method of this invention has a threshold voltage difference δVTH < 1.0V between different units, while the existing superjunction fast recovery product has δVTH > 4.0V, representing an improvement of over 75%. The significant reduction in δVTH makes the threshold voltage of each unit cell more consistent, enabling all units to conduct synchronously and fully. This effectively avoids the problem of increased overall equivalent on-resistance of the chip due to insufficient conduction of some units, and the on-resistance of the device is thus significantly reduced.
[0008] 2) This invention can achieve low δVTH manufacturing using conventional metal sputtering equipment, without the need to purchase expensive special equipment; and compared with the existing process flow, it only requires one additional photolithography and etching process, without any modification to the front-end processes (epitaxy, implantation, gate oxide, etc.), and has good industrial promotion value and compatibility.
[0009] 3) Superjunction fast recovery products are widely used in industrial and electric drive control, new energy vehicles, new energy and energy storage, data centers and communications, lighting and consumer electronics, and other fields. The low δVTH superjunction fast recovery device manufactured using this invention can achieve lower conduction losses and better current distribution uniformity in all the above application fields, improving the overall system efficiency and reliability, and has significant industrial application value.
[0010] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0011] Figure 1 This is a schematic flowchart of a method for fabricating a superjunction fast recovery low δVTH device provided in an embodiment of the present invention; Figures 2-16 This is a schematic diagram of the cross-sectional structure of the device formed after different steps in the fabrication process, as provided in the embodiments of the present invention. Figure 17 This is an exemplary cross-sectional structural diagram of the superjunction fast recovery low δVTH device provided in an embodiment of the present invention. Detailed Implementation
[0012] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0013] In a first aspect, embodiments of the present invention provide a method for fabricating a superjunction fast recovery low δVTH device, such as... Figure 1 As shown, the method includes: S1, Provide a substrate.
[0014] Specifically, an N-type silicon substrate can be used.
[0015] S2. Fabricate the superjunction alternating P / N pillar structure, gate structure, source / drain regions and interlayer dielectric layer on the substrate, and form lead vias.
[0016] In this invention, step S2 includes: S21. A superjunction alternating P / N pillar structure is formed on the substrate by employing multiple epitaxial, multiple photolithography and multiple implantation processes.
[0017] Specifically, a superjunction structure is constructed on an N-type silicon substrate using a multi-cycle epitaxial growth and implantation process. Each cycle includes: first, growing an N-type epitaxial layer by chemical vapor deposition, the thickness of which is determined according to the designed breakdown voltage, typically 5–15 μm; then performing photolithography to define the P-pillar region, followed by P-type ion implantation with boron as the implanted impurity, at an implantation energy range of 20–400 keV and a dose range of 5.5 × 10¹¹–5.5 × 10¹³ cm⁻¹. - ²; This cyclic process is repeated 4 to 10 times, ultimately forming an alternating P-pillar and N-pillar structure. During this repetition, the doping concentration along the vertical direction of the P-pillars is controlled by successively increasing the ion implantation dose, ensuring the lowest doping concentration at the bottom of the P-pillars and a gradual increase in doping concentration from bottom to top. An exemplary cross-sectional view of the formed superjunction alternating P / N pillar structure is shown below. Figure 2 As shown.
[0018] S22. Field oxide layer growth, P-pillar push-junction connection, and active region formation are carried out sequentially on the upper surface of the superjunction alternating P / N pillar structure.
[0019] Specifically, a field oxide layer (FOX) is grown on the silicon wafer surface using a high-temperature oxidation furnace tube. The oxidation temperature is approximately 1000–1150°C, and the oxidation time is adjusted according to the required FOX thickness (5000–15000 Å). After field oxidation, pillar drive-in (P-pillar push-in) is performed simultaneously at a temperature typically between 1100°C and 1200°C for a time typically between 100 and 500 minutes to achieve P-pillar connection. An exemplary cross-sectional view of the device after field oxide layer growth and P-pillar push-in connection is shown below. Figure 3 As shown. Next, the active area is opened through photolithography and etching processes. Specifically, the active area (AA) pattern is defined on the photoresist using an active area (AA) photolithography process. Wet etching is then used to remove the field oxide layer on the surface of the active area, exposing the silicon surface and forming the active area. Subsequently, cleaning and sacrificial oxidation are performed to remove the etching damage layer. An exemplary cross-sectional view of the device structure formed after etching is shown below. Figure 4 As shown.
[0020] S23. The gate oxide layer is grown and the polysilicon layer is deposited sequentially. During the polysilicon deposition process, N-type in-situ doping is performed to achieve polysilicon phosphorus doping. Then, the polysilicon layer is patterned through silicon gate photolithography and etching processes to form the gate structure.
[0021] Specifically, the gate oxide layer is grown in a high-temperature oxidation furnace, with a thickness typically ranging from 500 to 2000 Å, at an oxidation temperature of approximately 900 to 1150 °C, under a dry or wet oxygen atmosphere. After gate oxidation, a polycrystalline silicon layer is deposited using low-pressure chemical vapor deposition (LPCVD) at a deposition temperature of approximately 580 to 630 °C, with a thickness of approximately 0.4 to 0.9 μm. During polycrystalline deposition, in-situ N-type doping is performed to achieve polycrystalline silicon phosphorus doping, thereby reducing its resistivity to 20 to 300 Ω / sq. An exemplary cross-sectional view of the device structure formed after gate oxide layer growth and polycrystalline silicon layer deposition is shown below. Figure 5 As shown. Next, the polysilicon gate pattern is realized through silicon gate photolithography and etching processes. Specifically, the gate pattern is defined on the photoresist through silicon gate photolithography, and the polysilicon layer is etched using a dry etching process. The etching gas is usually a mixture of Cl2 and HBr, or a mixture of SF6 and CHF3. The etching stops at the gate oxide layer. After the polysilicon gate pattern is formed, the photoresist is removed and the device is cleaned. An exemplary cross-sectional view of the device structure formed after silicon gate photolithography and etching processes is shown below. Figure 6 As shown.
[0022] S24. Perform P-body implantation and annealing to form a P-well, wherein the implanted impurity is boron, the implantation energy range is 50~150keV, and the dose range is 5×10¹²~1×10¹². 4 cm - ², the annealing environment is N2 / O2, and the annealing temperature is 900~1200℃.
[0023] Specifically, Pbody (P-well) implantation is performed, with boron (B) as the implanted impurity. + The injection energy range is 50~150keV, and the dose range is 5×10¹²~1×10¹². 4 cm - ². After implantation, high-temperature annealing is performed in a nitrogen (N2 / O2) environment at approximately 900–1200°C to activate the implanted boron impurities and promote the formation of a P-well. An exemplary cross-sectional view of the device structure formed after pbody implantation and annealing is shown below. Figure 7 As shown.
[0024] S25. An N+ source region is formed through N+ photolithography, N+ implantation, and annealing. The implanted impurity is arsenic or phosphorus, the implantation energy range is 60~160keV, and the dose range is 5×10¹. 4 ~5×10¹ 5 cm - ².
[0025] Specifically, the source region (N+ region) pattern is defined using N+ lithography, followed by N-type heavy doping implantation, with arsenic (As) as the implanted impurity.+ ) or phosphorus (P + The injection energy range is 60~160keV, and the dose range is 5×10¹. 4 ~5×10¹ 5 cm - ². High-temperature annealing after implantation activates the doped impurities, forming an N+ source region. An exemplary cross-sectional view of the device structure forming the N+ source region is shown below. Figure 8 As shown, the red area within the dark blue area is the N+ source region.
[0026] S26. An interlayer dielectric layer is formed by ILD dielectric layer deposition and reflow process, and lead holes are formed by lead hole photolithography and etching process to expose the source and gate regions below.
[0027] Specifically, an interlayer dielectric (ILD) layer is deposited using chemical vapor deposition (CVD), typically made of undoped silicon glass (USG) or borosilicate glass (BPSG), with a thickness of approximately 5000–20000 Å. Following deposition, a reflow process (high-temperature heat treatment) is performed to planarize the ILD layer surface. The reflow temperature is typically 850–950 °C, and the process is carried out in a nitrogen or oxygen-containing atmosphere. An exemplary cross-sectional view of the device structure with the formed ILD layer is shown below. Figure 9 As shown, a cross-sectional view of the device structure forming the lead hole is as follows. Figure 10 As shown, CT represents the lead hole.
[0028] S3. A Ti / TiN barrier layer is formed on the upper surface of the device and inside the lead hole by sputtering.
[0029] In this invention, S3 includes: S31. Through lead hole injection and annealing, a P-type region is formed at the bottom of the lead hole, wherein the injected impurity is boron, the injection energy range is 20~160keV, and the dose range is 5×10¹. 4 ~5×10¹ 5 cm - ², the annealing temperature range is 900~1000℃.
[0030] Specifically, P-type impurities are implanted through the lead-in hole, and the implanted impurity is boron (B). + The injected energy is approximately 20~160 keV, and the dose is approximately 5×10¹. 4 ~5×10¹ 5 cm - ². Rapid thermal annealing (RTA) is performed after implantation at approximately 900–1000°C to activate the implanted impurities and form a heavily doped P-type region at the bottom of the leadhole, thereby reducing contact resistance. An exemplary cross-sectional view of a device structure with a heavily doped P-type region formed at the bottom of the leadhole is shown below. Figure 11As shown, the yellow area within the dark blue region represents the heavily doped P-type region at the bottom of the lead hole.
[0031] S32. A Ti layer is sputtered onto the upper surface of the device and the sidewalls and bottom of the lead holes using a sputtering process.
[0032] S33. Sputter a TiN layer onto the Ti layer to form a Ti / TiN barrier layer.
[0033] Specifically, a conventional magnetron sputtering system is used to deposit a Ti / TiN bilayer barrier layer structure on the silicon wafer surface. First, a Ti layer (titanium layer) with a thickness of approximately 300–500 Å is sputtered; then, a TiN layer (titanium nitride layer) with a thickness of approximately 500–1500 Å is sputtered. The substrate temperature during sputtering is approximately 400°C, and the sputtering pressure is approximately 2–5 mTorr. The Ti / TiN barrier layer prevents subsequent interdiffusion between AlCu metal and silicon, and also acts as an adhesion / barrier layer between tungsten (W) and the underlying layer. An exemplary cross-sectional view of the device structure with the Ti / TiN barrier layer is shown below. Figure 12 As shown.
[0034] S4. A tungsten layer is deposited on the Ti / TiN barrier layer, and part of the tungsten layer fills the lead hole.
[0035] In this invention, S4 includes: S41. Perform SiH4 pretreatment to prevent subsequent WF6 corrosion of the TiN layer.
[0036] S42. A chemical vapor deposition process is used, with either SiH4 or H2 and WF6 as the reactant gases, to deposit a tungsten layer on the Ti / TiN barrier layer. The deposition temperature range is 350~450℃, so that the tungsten layer fills the lead hole and forms a capping layer on the upper surface of the device.
[0037] Specifically, firstly, a silane (SiH4) pretreatment (SiH4soak) is performed to prevent tungsten hexafluoride (WF6) from corroding the underlying TiN layer. Then, SiH4 or hydrogen (H2) gas, and WF6 gas, are introduced for tungsten chemical vapor deposition, with the deposition temperature maintained at approximately 350–450°C. By controlling the deposition time, tungsten completely fills the lead vias and forms a tungsten layer of a certain thickness on the surface. An exemplary cross-sectional view of the device structure with the tungsten layer is shown below. Figure 13 As shown, Tungsten represents the tungsten layer.
[0038] S5. Through reverse etching process, the tungsten layer and part of the Ti / TiN barrier layer outside the lead hole are etched away.
[0039] In this invention, S5 includes: S51. Using tungsten reverse etching process, the tungsten layer on the upper surface of the device is etched back as a whole to etch away the tungsten layer in the area outside the lead hole, exposing the underlying Ti / TiN barrier layer.
[0040] S52. Continue etching away a portion of the Ti / TiN barrier layer, stopping the etching on the remaining Ti / TiN barrier layer. The tungsten layer inside the lead hole is retained to form a tungsten plug.
[0041] Specifically, a tungsten etch back process is used to etch back the entire device, removing the tungsten layer outside the leadhole and part of the Ti / TiN barrier layer. The etching stops on the remaining Ti / TiN layer, ensuring the tungsten plug inside the leadhole remains intact, forming a tungsten plug contact. An exemplary cross-sectional view of the device structure formed after the tungsten etch back process is shown below. Figure 14 As shown.
[0042] S6. While protecting the tungsten layer in the lead hole area through photolithography, a Ti / TiN reverse etching process is performed to remove the Ti / TiN barrier layer in the area outside the lead hole.
[0043] In this invention, S6 includes: S61. Add a Ti / TiN reverse lithography photomask. Using photolithography, coat the upper surface of the device with photoresist. Through exposure and development, the photoresist covers and protects the tungsten layer inside the lead hole and the Ti / TiN barrier layer located below the tungsten layer.
[0044] S62. Using dry etching or wet etching processes, reverse etching is performed on the Ti / TiN barrier layer exposed outside the lead hole to completely remove the Ti / TiN barrier layer outside the lead hole, while retaining the Ti / TiN / W plug structure inside the lead hole.
[0045] S63, Remove photoresist.
[0046] Step S6 reduces the blocking of H2 by unwanted Ti / TiN regions during the irradiation annealing repair process of fast recovery superjunction products, thereby reducing δVTH. An exemplary cross-sectional view of the device structure formed after the Ti / TiN reverse etching process outside the lead vias is shown below. Figure 15 As shown.
[0047] S7, sputtered metal AlCu layer, source and gate metal wiring is formed by photolithography and etching processes.
[0048] Specifically, an AlCu (aluminum-copper alloy) metal layer is deposited using magnetron sputtering, with a thickness ranging from 2 to 6 μm. The substrate temperature during AlCu sputtering is approximately 200–400 °C, and the sputtering pressure is approximately 2 mT. An exemplary cross-sectional view of the device structure formed after sputtering the AlCu metal layer is shown below. Figure 16 As shown. Next, the gate (G) and source (S) patterns are defined using metal lithography, and unwanted AlCu is removed by dry or wet etching to form the gate and source metal wiring.
[0049] S8. A passivation protective layer is deposited, and the passivation layer in the source and gate regions is removed by photolithography and etching processes.
[0050] Specifically, a silicon nitride (Si3N4) or silicon oxide / silicon nitride composite layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) as a passivation protection layer, with a thickness ranging from 5000 to 20000 Å. Next, the passivation protection layer in the gate and source regions is removed using passivation photolithography and etching processes to expose the metal pads for subsequent packaging wire bonding.
[0051] S9. The drain electrode is formed through thinning and back-side metal evaporation processes.
[0052] Specifically, the back side of the silicon wafer is mechanically thinned to the target thickness (100~400μm). After thinning, back-side metal evaporation is performed, sequentially evaporating multilayer metal systems such as Ti / Ni / Ag (titanium / nickel / silver) or Cr / Ni / Au (chromium / nickel / gold), and then alloying to form the back-side drain (D) ohmic contact electrode. This completes the fabrication of the entire device. An exemplary cross-sectional schematic diagram of the fabricated superjunction fast recovery low δVTH device is shown below. Figure 17 As shown, it should be noted that Figure 17 The substrate and drain are not shown in the figure.
[0053] The present invention has the following effects: 1) δVTH represents the degree of difference (i.e., dispersion) in threshold voltage VTH between different units (cells) on a chip. A superjunction MOSFET consists of thousands of parallel units. If the VTH values of these units are inconsistent, it leads to uneven current distribution. Units with lower VTH turn on first and carry more current, while units with higher VTH turn on later and carry less current. This unevenness results in a higher equivalent on-resistance for the entire chip because the overall current-carrying capacity decreases when some units are not fully turned on. Existing superjunction fast recovery MOSFETs have a δVTH > 4.0V, while the superjunction fast recovery product prepared using the method of this invention has a δVTH < 1.0V, effectively solving the problem of high on-resistance caused by a high VTH after irradiation annealing repair.
[0054] 2) The preparation method proposed in this invention can achieve low δVTH using conventional metal sputtering equipment, requiring only one additional photolithography etching process, and has good compatibility.
[0055] Secondly, embodiments of the present invention provide a superjunction fast recovery low δVTH device, which is fabricated using the aforementioned method for fabricating a superjunction fast recovery low δVTH device. For example, as... Figure 17 As shown, the device includes: The semiconductor substrate has a superjunction alternating P / N pillar structure. A gate structure, source / drain regions, and an interlayer dielectric layer covering the gate structure and source / drain regions are formed on the semiconductor substrate. A lead hole is formed in the interlayer dielectric layer, and the lead hole penetrates the interlayer dielectric layer and exposes the source / drain regions or gate structure below. A Ti / TiN barrier layer is provided on the inner wall of the lead hole, and a tungsten layer is filled inside the lead hole. The tungsten layer covers the Ti / TiN barrier layer and fills the lead hole. The Ti / TiN barrier layer and the tungsten layer together form a Ti / TiN / W plug structure inside the lead hole. A metal AlCu layer is disposed on the upper surface of the interlayer dielectric layer and on the top of the Ti / TiN / W plug structure. The metal AlCu layer is electrically connected to the Ti / TiN / W plug structure. The metal AlCu layer forms the source and gate electrodes after being patterned by photolithography. A passivation protection layer is covered on top of the metal AlCu layer, and the passivation protection layer has openings in the areas where the source and gate electrodes are located; A drain metal layer is disposed on the back side of the semiconductor substrate.
[0056] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0057] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0058] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0059] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0060] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for fabricating a superjunction fast recovery low δVTH device, characterized in that, include: S1, Provide a substrate; S2. Fabricate the superjunction alternating P / N pillar structure, gate structure, source / drain region and interlayer dielectric layer on the substrate, and form lead holes; S3. A Ti / TiN barrier layer is formed on the upper surface of the device and inside the lead hole by sputtering; S4. A tungsten layer is deposited on the Ti / TiN barrier layer, and part of the tungsten layer fills the lead hole; S5. Using a reverse etching process, the tungsten layer and a portion of the Ti / TiN barrier layer outside the lead hole are etched away; S6. While protecting the tungsten layer in the lead hole area through photolithography, a Ti / TiN reverse etching process is performed to remove the Ti / TiN barrier layer in the area outside the lead hole. S7. A sputtered AlCu metal layer is formed by photolithography and etching processes to create source and gate metal wiring. S8. A passivation protective layer is deposited, and the passivation layer in the source and gate regions is removed by photolithography and etching processes. S9. The drain electrode is formed through thinning and back-side metal evaporation processes.
2. The fabrication method of the superjunction fast recovery low δVTH device according to claim 1, characterized in that, S3 includes: S31. Through the lead hole, a P-type region is formed at the bottom of the lead hole by injection and annealing, wherein the injected impurity is boron, the injection energy range is 20~160keV, and the dose range is 5×10¹. 4 ~5×10¹ 5 cm - ², the annealing temperature range is 900~1000℃; S32. A Ti layer is sputtered onto the upper surface of the device and the sidewalls and bottom of the lead hole using a sputtering process; S33. Sputter a TiN layer onto the Ti layer to form a Ti / TiN barrier layer.
3. The method for fabricating the superjunction fast recovery low δVTH device according to claim 2, characterized in that, The thickness of the Ti layer ranges from 300 to 500 Å, and the thickness of the TiN layer ranges from 500 to 1500 Å.
4. The method for fabricating the superjunction fast recovery low δVTH device according to claim 1, characterized in that, S4 includes: S41. Perform SiH4 pretreatment to prevent subsequent WF6 corrosion of the TiN layer; S42. Using chemical vapor deposition, a tungsten layer is deposited on the Ti / TiN barrier layer with either SiH4 or H2 and WF6 as the reactant gas. The deposition temperature range is 350~450℃, so that the tungsten layer fills the lead hole and forms a capping layer on the upper surface of the device.
5. The method for fabricating a superjunction fast recovery low δVTH device according to claim 1, characterized in that, S5 includes: S51. Using a tungsten reverse etching process, the tungsten layer on the upper surface of the device is etched back as a whole to etch away the tungsten layer in the area outside the lead hole, exposing the underlying Ti / TiN barrier layer. S52. Continue etching away a portion of the Ti / TiN barrier layer until the etching stops on the remaining Ti / TiN barrier layer, wherein the tungsten layer inside the lead hole is retained to form a tungsten plug.
6. The method for fabricating a superjunction fast recovery low δVTH device according to claim 1, characterized in that, S6 includes: S61. Add a Ti / TiN reverse lithography photomask. Using photolithography, coat the upper surface of the device with photoresist. Through exposure and development, the photoresist covers and protects the tungsten layer in the lead hole and the Ti / TiN barrier layer located below the tungsten layer. S62. Using dry etching or wet etching processes, reverse etching is performed on the Ti / TiN barrier layer exposed outside the lead hole to completely remove the Ti / TiN barrier layer outside the lead hole, while retaining the Ti / TiN / W plug structure inside the lead hole. S63, Remove photoresist.
7. The method for fabricating a superjunction fast recovery low δVTH device according to claim 1, characterized in that, S2 includes: S21. A superjunction alternating P / N pillar structure is formed on the substrate by employing multiple epitaxial, multiple photolithography and multiple implantation processes. S22. On the upper surface of the superjunction alternating P / N pillar structure, a field oxide layer is grown, P pillar push-junction is connected, and an active region is formed in sequence. S23. The gate oxide layer is grown and the polysilicon layer is deposited sequentially. During the polysilicon deposition process, N-type in-situ doping is performed to achieve polysilicon phosphorus doping. Then, the polysilicon layer is patterned by silicon gate photolithography and etching process to form a gate structure. S24. Perform P-body implantation and annealing to form a P-well, wherein the implanted impurity is boron, the implantation energy range is 50~150keV, and the dose range is 5×10¹²~1×10¹². 4 cm - ², the annealing environment is N2 / O2, and the annealing temperature is 900~1200℃; S25. An N+ source region is formed through N+ photolithography, N+ implantation, and annealing. The implanted impurity is arsenic or phosphorus, the implantation energy range is 60~160keV, and the dose range is 5×10¹. 4 ~5×10¹ 5 cm - ²; S26. An interlayer dielectric layer is formed by ILD dielectric layer deposition and reflow process, and the lead hole is formed by lead hole photolithography and etching process to expose the source region and gate region below.
8. The method for fabricating a superjunction fast recovery low δVTH device according to claim 7, characterized in that, S21 specifically includes: A superjunction structure was constructed on an N-type silicon substrate using a multi-cycle epitaxial growth and implantation process. Each cycle included: first, growing an N-type epitaxial layer by chemical vapor deposition; then, performing photolithography to define the P-pillar region; and finally, performing P-type ion implantation with boron as the impurity. The implantation energy ranged from 20 to 400 keV, and the dose ranged from 5.5 × 10⁻⁶ keV. 11 ~5.5×10 13 cm - ²; Repeat this cycle multiple times to eventually form an alternating P-pillar and N-pillar structure. During the repetition of this cycle, the ion implantation dose is increased successively to minimize the doping concentration at the bottom of the P-pillar and gradually increase the doping concentration from bottom to top.
9. The method for fabricating a superjunction fast recovery low δVTH device according to claim 1, characterized in that, S7 includes: S71. A metal AlCu layer with a thickness of 2~6μm is deposited on the upper surface of the device using magnetron sputtering. The substrate temperature during sputtering is 200~400℃ and the sputtering pressure is 2mT. S72. Define the gate and source patterns on the metal AlCu layer using metal photolithography. S73. Remove the unwanted AlCu metal layer by dry or wet etching process to form gate and source metal wiring.
10. A superjunction fast recovery low δVTH device, characterized in that, The device is prepared by the fabrication method of any one of claims 1 to 9, comprising: A semiconductor substrate having a superjunction alternating P / N pillar structure, a gate structure, a source / drain region, and an interlayer dielectric layer covering the gate structure and the source / drain region are formed on the semiconductor substrate, and a lead hole is formed in the interlayer dielectric layer, the lead hole penetrating the interlayer dielectric layer and exposing the source / drain region or the gate structure below. A Ti / TiN barrier layer is provided on the inner wall of the lead hole, and a tungsten layer is filled inside the lead hole. The tungsten layer covers the Ti / TiN barrier layer and fills the lead hole. The Ti / TiN barrier layer and the tungsten layer together form a Ti / TiN / W plug structure inside the lead hole. A metal AlCu layer is disposed on the upper surface of the interlayer dielectric layer and on the top of the Ti / TiN / W plug structure. The metal AlCu layer is electrically connected to the Ti / TiN / W plug structure. The metal AlCu layer forms the source and gate electrodes after photolithography patterning. A passivation protective layer is covered above the metal AlCu layer, and the passivation protective layer has openings in the regions where the source and gate electrodes are located; A drain metal layer is disposed on the back side of the semiconductor substrate.