A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a low-voltage area, a medium-voltage area and a high-voltage area; sequentially forming a first sidewall material layer and a second sidewall material layer; performing a first modification process to convert part of the second sidewall material layer in the high-voltage area into a silicon oxide layer; performing a second modification process to convert the second sidewall material layer in the medium-voltage area into a silicon oxide layer for serving as a third sidewall material layer in the medium-voltage area; forming a fourth sidewall material layer covering the third sidewall material layer in the medium-voltage area and the high-voltage area; and performing a third modification process to convert the second sidewall material layer in the low-voltage area into a silicon oxide layer for serving as a third sidewall material layer in the low-voltage area. Based on the preparation method, the thickness of the sidewall of the gate structure in the medium-voltage area can be increased to improve the GIDL leakage problem of the medium-voltage area, meanwhile, the use of mask plates and photoresists can be reduced, so that the process cost can be effectively reduced.

Description

Technical Field

[0001] This application relates generally to the technical field of semiconductor devices, and more specifically to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Integrated semiconductor devices are fabricated by combining multiple types of devices together. For example, different types and voltages of transistors can be fabricated on the same substrate, with shallow trench isolation structures separating the transistors. Fabricating different semiconductor devices on the same substrate improves fabrication efficiency and integration density. However, different semiconductor devices have different threshold voltages during fabrication, requiring compatibility with high-frequency and low-power circuits. In particular, the thickness stability of the gate dielectric layer is extremely important during the fabrication of medium-voltage transistors, directly impacting manufacturing yield.

[0003] In the manufacturing process of high-voltage devices, medium-voltage devices, core devices, and memory devices typically use the same sidewall structure design. However, due to the rigid limitations of the spacing between memory devices, the sidewall width cannot be made thick. When medium-voltage devices share the sidewall width with low-voltage devices in memory devices, gate-induced drain leakage current (GIDL) will occur due to the relatively high operating voltage.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To at least partially solve the above problems, this application provides a method for fabricating a semiconductor device, the method comprising: A semiconductor substrate is provided, the semiconductor substrate including a low-voltage region, a medium-voltage region and a high-voltage region, and a corresponding gate structure is formed in the low-voltage region, the medium-voltage region and the high-voltage region respectively; A first sidewall material layer and a second sidewall material layer are formed sequentially, the first sidewall material layer and the second sidewall material layer covering the gate structure and the semiconductor substrate; A first mask layer is formed to cover the second sidewall material layer of the low-pressure area and the medium-pressure area, while exposing the second sidewall material layer of the high-pressure area. A first modification process is performed to modify the second sidewall material layer of the high-voltage zone, transforming the portion of the second sidewall material layer near the top layer of the high-voltage zone into a silicon oxide layer for use as the third sidewall material layer located in the high-voltage zone. A second mask layer is formed to cover the second sidewall material layer of the low-pressure zone, while at least exposing the second sidewall material layer of the medium-pressure zone; A second modification process is performed to modify the second sidewall material layer of the medium-pressure zone, converting the entire second sidewall material layer of the medium-pressure zone into silicon oxide for use as the third sidewall material layer located in the medium-pressure zone. A fourth sidewall material layer is formed to cover the third sidewall material layer of the medium-pressure zone and the high-pressure zone; A third modification process is performed to modify the second sidewall material layer of the low-voltage zone, converting the entire second sidewall material layer of the low-voltage zone into silicon oxide, so as to serve as the third sidewall material layer located in the low-voltage zone.

[0007] Optionally, the thickness of the first sidewall material layer is 70-90 angstroms; and / or The thickness of the second sidewall material layer is 40 angstroms to 60 angstroms; and / or The thickness of the third sidewall material layer located in the high-pressure zone is 25 angstroms to 35 angstroms.

[0008] Optionally, the material of the second sidewall material layer includes silicon nitride; The first modification process includes: The silicon nitride is activated by bombarding the surface of the exposed second sidewall material layer with hydrogen plasma, and the depth of the activation treatment is less than the thickness of the second sidewall material layer. The activated second sidewall material layer is placed in an oxygen-containing atmosphere, causing the activated silicon nitride to be oxidized to form silicon oxide; and / or The second modification process includes: The silicon nitride is activated by bombarding the surface of the exposed second sidewall material layer with hydrogen plasma, and the depth of the activation treatment is not less than the thickness of the second sidewall material layer. The activated second sidewall material layer is placed in an oxygen-containing atmosphere, so that the activated silicon nitride is oxidized to form silicon oxide.

[0009] Optionally, the oxygen-containing atmosphere is air; and / or In the first modification process, the activation time for silicon nitride is 25s-35s; and / or In the second modification process, the activation time for silicon nitride is 50s-70s.

[0010] Optionally, the material of the fourth sidewall material layer includes silicon dioxide; The fourth sidewall material layer covering the third sidewall material layer in the medium-pressure zone and the high-pressure zone includes: The semiconductor substrate is placed in the reaction chamber; A silicon-containing reaction precursor is introduced into the reaction chamber. The reaction precursor selectively adsorbs onto the surface of the third sidewall material layer, but not onto the surface of the second sidewall material layer. An oxygen-containing oxidant is introduced into the reaction chamber, and the oxidant reacts with the reaction precursor adsorbed on the surface of the third sidewall material layer to form a silicon oxide layer as the fourth sidewall material layer.

[0011] Optionally, the reaction precursor comprises diisopropylaminosilane, bis(diethylamino)silane, or bis(tert-butylamino)silane; and / or The oxidant includes ozone.

[0012] Optionally, the thickness of the fourth sidewall material layer is 40-60 angstroms; and / or During the formation of the fourth sidewall material layer, the temperature in the reaction chamber is below 100°C.

[0013] Optionally, the preparation method further includes: forming a fifth sidewall material layer covering the third sidewall material layer in the low-pressure zone and the fourth sidewall material layer in the medium-pressure zone and the high-pressure zone.

[0014] This application also provides a semiconductor device, the semiconductor device comprising: A semiconductor substrate, comprising a low-voltage region, a medium-voltage region, and a high-voltage region, wherein corresponding gate structures are formed in the low-voltage region, the medium-voltage region, and the high-voltage region, respectively; A first sidewall material layer covers the gate structure and the semiconductor substrate; A second sidewall material layer covers the first sidewall material layer in the high-voltage zone; The third sidewall material layer covers the first sidewall material layer of the low-pressure area and the medium-pressure area, as well as the second sidewall material layer of the high-pressure area, and the top surfaces of the third sidewall material layer of the low-pressure area, the medium-pressure area, and the high-pressure area are flush with each other; A fourth sidewall material layer covers the third sidewall material layer in the medium-pressure zone and the high-pressure zone; In the first direction perpendicular to the substrate, the total thickness of the third and fourth sidewall material layers in the medium-pressure zone is greater than the total thickness of the third and fourth sidewall material layers in the high-pressure zone.

[0015] Optionally, the material of the second sidewall material layer includes silicon nitride; and / or The material of the third sidewall layer includes silicon dioxide; and / or The material of the fourth sidewall layer includes silicon dioxide.

[0016] Based on the semiconductor device fabrication method of this application, after depositing the second sidewall material layer, the low-voltage region and the medium-voltage region are first masked by a first mask layer, and the second sidewall material layer of the high-voltage region is modified by a modification process to form a third sidewall material layer located in the high-voltage region; then, the low-voltage region is masked by a second mask layer, and the second sidewall material layer of the medium-voltage region is modified by a modification process to form a third sidewall material layer located in the medium-voltage region; subsequently, a fourth sidewall material layer is deposited in the medium-voltage region and the high-voltage region by a selective deposition process, thereby effectively increasing the thickness of the sidewall material layer in the medium-voltage region; finally, the second sidewall material layer of the low-voltage region is modified by a modification process to form a third sidewall material layer located in the low-voltage region. Thus, on the one hand, it can ensure that the thickness of the sidewall of the gate structure in the medium-voltage region is greater than that in the low-voltage region and the high-voltage region, thereby improving the GIDL leakage problem in the medium-voltage region; on the other hand, the fabrication method of this application only requires two photolithography processes, thereby effectively reducing the number of photolithography processes, reducing the use of masks and photoresists, and thus effectively reducing process costs. Attached Figure Description

[0017] The following drawings, which illustrate embodiments of this application, are incorporated herein by reference and are used to understand this application. The drawings show embodiments of this application and their descriptions, serving to explain the principles of this application. In the drawings: Figure 1 This diagram illustrates a related technology in which gate structures are formed in the low-voltage region, medium-voltage region, and high-voltage region of a semiconductor substrate, respectively. Figure 2 It shows that Figure 1 A simplified planar structural diagram of the corresponding structure; Figures 3A to 3E A cross-sectional schematic diagram of each step in the fabrication method of semiconductor devices in related technologies is shown; Figure 4 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown; Figures 5A to 5F The diagram shows a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application. Detailed Implementation

[0018] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0020] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an ideal or overly formal sense, unless expressly defined herein.

[0024] In the fabrication of high-voltage devices, medium-voltage devices, core devices, and memory devices typically employ the same sidewall structure design. However, due to the rigid limitations imposed by the spacing between memory devices, the sidewall width (thickness) cannot be increased. When medium-voltage devices share the same sidewall width with low-voltage devices within the memory, gate-induced drain leakage current (GIDL) occurs due to the relatively high operating voltage. In related technologies, to improve the GIDL problem in medium-voltage devices, the sidewall thickness in the medium-voltage region is usually increased. Specifically, this can be achieved by increasing the thickness of the oxide layer; however, this process is complex and results in high manufacturing costs.

[0025] Specifically, please refer to Figure 1 , Figure 2 , Figures 3A to 3E ,in, Figure 1A schematic diagram is shown in which gate structures 20 are formed in the low-voltage region 11, medium-voltage region 12 and high-voltage region 13 of the semiconductor substrate 10, respectively; Figure 2 It shows that Figure 1 A simplified planar structural diagram of the corresponding structure, in Figure 2 In the middle, from left to right, are low-pressure zone 11, medium-pressure zone 12 and high-pressure zone 13; Figures 3A to 3E A cross-sectional schematic diagram of each step in the fabrication method of a semiconductor device in the related art is shown. In the related art, the process for forming the oxide layer in the gate sidewall includes: like Figure 3A As shown, the semiconductor substrate 10 includes a low-voltage region 11, a medium-voltage region 12, and a high-voltage region 13. Corresponding gate structures 20 (not shown) are formed in the low-voltage region 11, the medium-voltage region 12, and the high-voltage region 13, respectively. A first sidewall material layer 30 and a second sidewall material layer 40 made of silicon nitride are formed sequentially. The first sidewall material layer 30 and the second sidewall material layer 40 cover the gate structure 20 and the semiconductor substrate 10, wherein the gate structure 20 is not shown.

[0026] like Figure 3B As shown, a first photolithography process is performed using a first mask (not shown) to form a first mask layer 41 on the high voltage region 13 of the semiconductor substrate 10. The first mask layer 41 covers the second sidewall material layer 40 of the high voltage region 13 and exposes the second sidewall material layers 40 of the medium voltage region 12 and the low voltage region 11. Then, a first etching process is performed to remove the excess second sidewall material layers 40 of the medium voltage region 12 and the low voltage region 11. The remaining second sidewall material layers 40 cover the sidewalls of the gate structure 20 in the low voltage region 11, the medium voltage region 12, the high voltage region 13, and the substrate of the high voltage region 13.

[0027] like Figure 3C As shown, a third sidewall material layer 50 of silicon oxide is then formed to cover the low-voltage region 11, medium-voltage region 12 and high-voltage region 13 of the semiconductor substrate 10.

[0028] like Figure 3D As shown, a second photolithography process is then performed using a second mask (not shown) to form a second mask layer 51 on the high voltage region 13 and the medium voltage region 12 of the semiconductor substrate 10. The second mask layer 51 covers the third sidewall material layer 50 of the medium voltage region 12 and the high voltage region 13, and exposes the third sidewall material layer 50 of the low voltage region 11. Then, a second etching process is performed to etch and thin the third sidewall material layer 50 of the low voltage region 11, so that the thickness of the third sidewall material layer 50 of the low voltage region 11 is less than the thickness of the third sidewall material layer 50 of the medium voltage region 12.

[0029] like Figure 3EAs shown, a third photolithography process is then performed using a third mask (not shown) to form a third mask layer 52 on the medium-voltage region 12 and low-voltage region 11 of the semiconductor substrate 10. The third mask layer 52 covers the third sidewall material layer 50 of the medium-voltage region 12 and low-voltage region 11, and exposes the third sidewall material layer 50 of the high-voltage region 13. Then, a third etching process is performed to etch and thin the third sidewall material layer 50 of the high-voltage region 13, so that the top surface of the third sidewall material layer 50 of the high-voltage region 13 is substantially flush with the top surface of the third sidewall material layer 50 of the medium-voltage region 12. Since the high-voltage region 13 has a second sidewall material layer 40, the thickness of the third sidewall material layer 50 of the high-voltage region 13 is less than the thickness of the third sidewall material layer 50 of the medium-voltage region 12. Finally, a silicon nitride layer (not shown) can be formed over the third sidewall material layer 50 of the low-voltage region 11, the medium-voltage region 12, and the high-voltage region 13, and then subsequent processes can be carried out based on this.

[0030] In the above-mentioned semiconductor device fabrication method, the gate structure 20 of the medium-voltage region 12, the gate structure 20 of the low-voltage region 11, and the gate structure 20 of the high-voltage region 13 have different sidewall thicknesses on the same semiconductor product. The thickness of silicon oxide in the sidewall of the gate structure 20 of the medium-voltage region 12 is greater than the thickness of silicon oxide in the sidewall material of the gate structure 20 of the low-voltage region 11 and the gate structure 20 of the high-voltage region 13, thereby improving the GIDL leakage problem of the medium-voltage region 12. However, this solution has a complicated process flow and requires three photolithography processes using a mask, followed by an etching process, resulting in high process costs.

[0031] Therefore, in view of the aforementioned technical problems, embodiments of this application provide a method for fabricating a semiconductor device, such as... Figure 4 As shown, the preparation method mainly includes the following steps: Step S1: Provide a semiconductor substrate, which includes a low-voltage region, a medium-voltage region, and a high-voltage region, and form corresponding gate structures in the low-voltage region, the medium-voltage region, and the high-voltage region, respectively. Step S2: A first sidewall material layer and a second sidewall material layer are formed sequentially, the first sidewall material layer and the second sidewall material layer covering the gate structure and the semiconductor substrate; Step S3: Form a second sidewall material layer covering the low-pressure area and the medium-pressure area with a first mask layer, and expose the second sidewall material layer of the high-pressure area; Step S4: Perform the first modification process to modify the second sidewall material layer of the high voltage zone, and transform the part of the second sidewall material layer near the top layer of the high voltage zone into a silicon oxide layer, so as to be used as the third sidewall material layer located in the high voltage zone. Step S5: Form a second mask layer to cover the second sidewall material layer of the low-pressure area, and at least expose the second sidewall material layer of the medium-pressure area; Step S6: Perform the second modification process to modify the second sidewall material layer of the medium-voltage zone, converting the entire second sidewall material layer of the medium-voltage zone into silicon oxide, so as to serve as the third sidewall material layer located in the medium-voltage zone. Step S7: Form a fourth sidewall material layer covering the third sidewall material layer in the medium-pressure zone and the high-pressure zone; Step S8: Perform the third modification process to modify the second sidewall material layer of the low-voltage zone, converting the entire second sidewall material layer of the low-voltage zone into silicon oxide, so as to serve as the third sidewall material layer located in the low-voltage zone.

[0032] Based on the semiconductor device fabrication method of this application, after depositing the second sidewall material layer, the low-voltage region and the medium-voltage region are first masked by a first mask layer, and the second sidewall material layer of the high-voltage region is modified by a modification process to form the third sidewall material layer located in the high-voltage region; then, the low-voltage region is masked by a second mask layer, and the second sidewall material layer of the medium-voltage region is modified by a modification process to form the third sidewall material layer located in the medium-voltage region; subsequently, a fourth sidewall material layer is deposited in the medium-voltage region and the high-voltage region by a selective deposition process, thereby effectively increasing the thickness of the sidewall material layer in the medium-voltage region; finally, the second sidewall material layer of the low-voltage region is modified by a modification process to form the third sidewall material layer located in the low-voltage region. Thus, on the one hand, it can ensure that the thickness of the sidewall of the gate structure in the medium-voltage region is greater than that of the gate structure in the low-voltage region and the high-voltage region, thereby improving the GIDL leakage problem in the medium-voltage region; on the other hand, the fabrication method of this application only requires two photolithography processes, thereby effectively reducing the number of photolithography processes, reducing the use of masks and photoresists, and thus effectively reducing process costs.

[0033] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0034] Below, for reference Figure 4 , Figures 5A to 5F The method for fabricating the semiconductor device of this application is described in detail; wherein, Figure 4 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown; Figures 5A to 5F The diagram shows a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application.

[0035] The semiconductor device can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of the present invention is explained and illustrated mainly by taking the case of the semiconductor device being a FinFET device.

[0036] For example, the method for fabricating the semiconductor device in this embodiment includes the following steps: First, step S1 is performed to provide a semiconductor substrate 100, which includes a low-voltage region, a medium-voltage region, and a high-voltage region (not shown), and corresponding gate structures are formed in the low-voltage region, the medium-voltage region, and the high-voltage region, respectively.

[0037] In some embodiments, such as Figure 5A As shown, a semiconductor substrate 100 is first provided. The semiconductor substrate 100 may include a substrate (not shown). The substrate may be any suitable semiconductor substrate, such as a silicon substrate. It may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. It may also include multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator stacked (SSOI), silicon on insulator stacked (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI). It may also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0038] In some embodiments, the semiconductor substrate 100 may further include a plurality of fin structures (not shown), the fin structures being formed on the substrate, the number of fin structures being one or more, the width of the fin structures being all the same, or the fin structures being divided into multiple fin groups with different widths, and the lengths of the multiple fin structures being different.

[0039] In some embodiments, the semiconductor substrate 100 may further include a plurality of gate structures (not shown), which are formed on the substrate and spaced apart along a first direction, with the length of the gate structures extending along a second direction, the first and second directions being perpendicular to each other. When the semiconductor device includes a FINFET, the plurality of gate structures may also span across the fins beneath it. It should be noted that the term "spanning," as used in this invention, refers to a gate structure formed on both the upper surface and the side surface of a portion of the fin.

[0040] In some embodiments, the gate structure can be a metal gate structure or a polysilicon gate structure. Taking a polysilicon gate structure as an example, it can include a first polysilicon layer, a silicon nitride layer, and a second polysilicon layer stacked from bottom to top.

[0041] It is understood that the low-voltage, medium-voltage, and high-voltage regions in the semiconductor substrate 100 are divided according to the type of devices on them, and each region can be divided according to the corresponding minimum repeating unit. Furthermore, the number of gate structures disposed on the low-voltage, medium-voltage, and high-voltage regions is set as needed and is not specifically limited. Moreover, the film layer covering the semiconductor substrate 100 will cover the gate structures and the substrate portions between adjacent gate structures.

[0042] Next, step S2 is performed to sequentially form a first sidewall material layer 200 and a second sidewall material layer 300, which cover the gate structure and the semiconductor substrate 100.

[0043] In some embodiments, such as Figure 5A As shown, a first sidewall material layer 200 is deposited on a semiconductor substrate 100, covering the gate structure and the semiconductor substrate 100. Specifically, the material of the first sidewall material layer 200 includes, but is not limited to, silicon carbonitride (SICN), and it can be formed using methods including, but not limited to, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). Its thickness is not limited to a specific value, provided that process requirements are met. For example, in this embodiment, the material of the first sidewall material layer 200 is silicon carbonitride, and the thickness of the first sidewall material layer 200 can be in the range of 70 angstroms to 90 angstroms.

[0044] In some embodiments, such as Figure 5A As shown, a second sidewall material layer 300 is formed over the first sidewall material layer 200. Specifically, the material of the second sidewall material layer 300 may include silicon nitride, silicon carbonitride, or other suitable materials. Methods for forming the second sidewall material layer 300 include, but are not limited to, suitable processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Its thickness is not limited to a specific value, provided that process requirements are met. For example, in this embodiment, the material of the second sidewall material layer 300 includes silicon nitride, and the thickness of the second sidewall material layer 300 may be in the range of 40 angstroms to 60 angstroms.

[0045] Then, step S3 is performed to form a first mask layer 310 covering the second sidewall material layer 300 of the low-pressure area and the medium-pressure area, and to expose the second sidewall material layer 300 of the high-pressure area.

[0046] In some embodiments, such as Figure 5BAs shown, a first mask layer 310 is formed to cover the second sidewall material layer 300 of the low-voltage region and the medium-voltage region. Specifically, a photoresist layer (not shown) can be spin-coated on a semiconductor substrate, and then a first photolithography process is performed using a first mask to pattern the photoresist layer and expose the second sidewall material layer 300 of the high-voltage region. The remaining photoresist layer covers the second sidewall material layer 300 of the low-voltage region and the medium-voltage region to serve as the first mask layer 310, thereby masking the second sidewall material layer 300 of the low-voltage region and the medium-voltage region in subsequent processes.

[0047] Next, step S4 is executed to perform the first modification process, modifying the second sidewall material layer 300 of the high-voltage zone, transforming the portion of the second sidewall material layer 300 near the top layer of the high-voltage zone into a silicon oxide layer, which can then be used as the third sidewall material layer 400 located in the high-voltage zone.

[0048] In some embodiments, such as Figure 5B As shown, the material of the second sidewall material layer 300 includes silicon nitride; the material of the third sidewall material layer 400 includes silicon oxide; the first modification process includes: placing the semiconductor substrate 100 in a reaction chamber and introducing hydrogen gas into the reaction chamber as a reaction gas, while simultaneously exciting the hydrogen gas to form hydrogen plasma by means of a radio frequency power supply or microwave; bombarding the exposed surface of the second sidewall material layer 300 with hydrogen plasma to activate the silicon nitride, thereby forming a modified layer on the surface of the second sidewall material layer 300; then placing the activated second sidewall material layer 300 in an oxygen-containing atmosphere (such as air or other oxygen environment) to oxidize the activated silicon nitride to form a silicon oxide layer, which is used as the third sidewall material layer 400 located in the high-voltage region.

[0049] Understandably, since a portion of the second sidewall material layer 300 needs to be retained in the high-voltage region, the activation depth of the silicon nitride layer in the first modification process is less than the initial thickness of the second sidewall material layer 300. This transforms a portion of the upper layer of the second sidewall material layer 300 into a silicon oxide layer. Specifically, the thickness of the third sidewall material layer 400 located in the high-voltage region can be 25-35 angstroms. The activation depth (i.e., the thickness of the modified layer) is positively correlated with the hydrogen plasma activation time; therefore, the final thickness of the third sidewall material layer 400 can be controlled by controlling the activation time. For example, in the first modification process, the activation time for the silicon nitride layer can be 25-35 seconds.

[0050] Then, step S5 is performed to form a second mask layer 410 covering the second sidewall material layer 300 of the low-pressure area, and at least exposing the second sidewall material layer 300 of the medium-pressure area.

[0051] In some embodiments, such as Figure 5C As shown, a second mask layer 410 is formed to cover the second sidewall material layer 300 of the low-voltage region. For example, the second mask layer 410 can be a photoresist layer, and a second photolithography process is performed using a second mask to pattern the photoresist layer, thereby exposing at least the second sidewall material layer 300 of the medium-voltage region. It is understood that photoresist can be recoated during the formation of the second mask layer 410. Based on this, after the first modification process, the first mask layer 310 can be removed by methods such as ashing, thus facilitating the recoating of photoresist. Alternatively, the first mask layer 310 can be left unremoved, and a second photolithography process can be performed directly using the second mask on top of the first mask layer 310 to remove the photoresist layer of the medium-voltage region. The remaining photoresist layer in the low-voltage region is used as the second mask layer 410 to mask the second sidewall material layer 300 of the low-voltage region in subsequent processes, thereby reducing the amount of photoresist used.

[0052] Next, step S6 is executed to perform the second modification process, which modifies the second sidewall material layer 300 in the medium-voltage zone, converting all of the second sidewall material layer 300 in the medium-voltage zone into silicon oxide, so that it can be used as the third sidewall material layer 400 located in the medium-voltage zone.

[0053] In some embodiments, such as Figure 5C As shown, the material of the second sidewall material layer 300 includes silicon nitride; the material of the third sidewall material layer 400 includes silicon oxide; the second modification process includes: placing the semiconductor substrate 100 in a reaction chamber and introducing hydrogen gas into the reaction chamber as a reaction gas, while simultaneously exciting the hydrogen gas to form hydrogen plasma using a radio frequency power supply or microwave; bombarding the surface of the second sidewall material layer 300 exposed in the medium-pressure region with hydrogen plasma to activate the silicon nitride; then placing the activated second sidewall material layer 300 in an oxygen-containing atmosphere (such as air or other oxygen environment) to oxidize the activated silicon nitride and form a silicon oxide layer, which is used as the third sidewall material layer 400 located in the medium-pressure region.

[0054] Understandably, since the silicon nitride in the second sidewall material layer 300 in the medium-voltage zone needs to be completely converted into silicon oxide, in the second modification process, the activation depth of the silicon nitride is not less than the initial thickness of the second sidewall material layer 300, thereby converting the second sidewall material layer 300 in the medium-voltage zone into a silicon oxide layer. Therefore, the thickness of the third sidewall material layer 400 in the medium-voltage zone is consistent with the initial thickness of the second sidewall material layer 300. In the second modification process, the activation time for the silicon nitride can be 50-70 seconds.

[0055] It is worth mentioning that in the second modification process, the high-voltage region includes a second sidewall material layer 300 made of silicon nitride located below, and a third sidewall material layer 400 made of silicon oxide above the second sidewall material layer 300. The silicon oxide will mask the silicon nitride, thereby preventing the second modification process from converting the remaining silicon nitride in the high-voltage region into silicon oxide. Of course, when forming the second mask layer 410, both the low-voltage and high-voltage regions can be masked simultaneously, exposing only the second sidewall material layer 300 of the medium-voltage region that needs modification. This can effectively ensure that the second modification process does not convert the remaining silicon nitride in the high-voltage region into silicon oxide. After the second modification process, the second mask layer 410 can be removed as needed.

[0056] Then, step S7 is performed to form a fourth sidewall material layer 500 covering the third sidewall material layer 400 in the medium-pressure zone and the high-pressure zone.

[0057] In some embodiments, such as Figure 5D As shown, the material of the fourth sidewall material layer 500 may include silicon oxide; the fourth sidewall material layer 500 can be formed by selective deposition process to cover the third sidewall material layer 400 in the medium-pressure region and the high-pressure region, thereby effectively increasing the thickness of the silicon oxide layer in the medium-pressure region; specifically, the semiconductor substrate 100 is placed in the reaction chamber; a silicon-containing silylamide reaction precursor is introduced into the reaction chamber. Since the surface of the third sidewall material layer 400 of silicon oxide material in the medium-pressure region and the high-pressure region mainly has hydroxyl (-OH) functional groups, while the silicon nitride in the low-pressure region... The surface of the second sidewall material layer 300 mainly contains amino (-NH2) functional groups, while the silylamide reaction precursor has higher chemical reactivity with the -OH groups on the silicon oxide surface. Based on this, the reaction precursor selectively adsorbs onto the surface of the third sidewall material layer 400, but not onto the surface of the second sidewall material layer 300. Then, an oxygen-containing oxidant is introduced into the reaction chamber, and the oxidant reacts with the reaction precursor adsorbed on the surface of the third sidewall material layer 400 to form a silicon oxide layer for use as the fourth sidewall material layer 500. Exemplarily, the thickness of the fourth sidewall material layer 500 can be 40 angstroms to 60 angstroms.

[0058] In the selective deposition process, the reaction temperature in the reaction chamber is below 100°C to prevent excessively high temperatures from degrading the amino (-NH2) functional groups on the silicon nitride surface and thus avoiding the loss of selectivity in the selective deposition process. The silylamide reaction precursor may include diisopropylaminosilane (DIPAS), bis(diethylamino)silane (BDEAS), bis(tert-butylamino)silane (BTBAS), or 1,2-bis(diisopropylamino)disilane (BDIPADS). The oxidant may include ozone.

[0059] It is worth mentioning that when the fourth sidewall material layer 500 is formed by selective deposition, after the second modification process and before the deposition process, the second mask layer 410 can be removed by methods such as ashing. Of course, if the second mask layer 410 only shields the low-voltage area, the second mask layer 410 can be left unremoved and the low-voltage area can be shielded by the second mask layer 410. Then, the fourth sidewall material layer 500 can be formed directly by deposition. After the fourth sidewall material layer 500 is formed, the second mask layer 410 can be removed. If silicon oxide is also deposited on the second mask layer 410, the silicon oxide on the second mask layer 410 can be removed first (e.g., by planarization process), and then the second mask layer 410 can be removed by methods such as ashing.

[0060] Then, step S8 is performed to perform the third modification process, modifying the second sidewall material layer 300 of the low-voltage zone to convert all of the second sidewall material layer 300 of the low-voltage zone into silicon oxide, so as to be used as the third sidewall material layer 400 located in the low-voltage zone.

[0061] In some embodiments, such as Figure 5D , Figure 5E As shown, the material of the second sidewall material layer 300 includes silicon nitride; the material of the third sidewall material layer 400 includes silicon oxide; the third modification process includes: placing the semiconductor substrate 100 in a reaction chamber and introducing hydrogen gas into the reaction chamber as a reaction gas, while simultaneously exciting the hydrogen gas to form hydrogen plasma using a radio frequency power supply or microwave; bombarding the surface of the second sidewall material layer 300 exposed in the low-pressure region with hydrogen plasma to activate the silicon nitride; then placing the activated second sidewall material layer 300 in an oxygen-containing atmosphere (such as air or other oxygen environment) to oxidize the activated silicon nitride and form a silicon oxide layer, which is used as the third sidewall material layer 400 located in the low-pressure region.

[0062] Understandably, since the silicon nitride in the second sidewall material layer 300 in the low-voltage region needs to be completely converted into silicon oxide, in the third modification process, the activation depth of the silicon nitride is not less than the initial thickness of the second sidewall material layer 300. This ensures that the second sidewall material layer 300 in the low-voltage region is completely converted into a silicon oxide layer. Therefore, the thickness of the third sidewall material layer 400 in the low-voltage region is consistent with the initial thickness of the second sidewall material layer 300. In the third modification process, the activation time for the silicon nitride can be 50-70 seconds.

[0063] In some embodiments, such as Figure 5F As shown, after the third modification process, the preparation method may further include: forming a fifth sidewall material layer 600 covering the third sidewall material layer 400 in the low-pressure region and the fourth sidewall material layer 500 in the medium-pressure and high-pressure regions. Specifically, the material of the fifth sidewall material layer 600 may include silicon nitride, silicon carbonitride, or other suitable materials. Methods for forming the fifth sidewall material layer 600 include, but are not limited to, suitable processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Its thickness is not limited to a specific value, provided that process requirements are met. For example, in this embodiment, the material of the fifth sidewall material layer 600 includes silicon nitride, and the thickness of the fifth sidewall material layer 600 may be in the range of 90 angstroms to 110 angstroms.

[0064] This concludes the description of the key steps in the semiconductor device fabrication method of this application. The complete semiconductor device fabrication method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0065] In summary, based on the semiconductor device fabrication method of this application, after depositing the second sidewall material layer 300 of silicon nitride, the low-voltage region and the medium-voltage region are first masked by the first mask layer 310, and a modification process is used to modify a portion of the silicon nitride on the top layer of the high-voltage region to form the third sidewall material layer 400 of silicon oxide located in the high-voltage region; then, the low-voltage region is masked by the second mask layer 410, and a modification process is used to modify all the silicon nitride in the medium-voltage region to form the third sidewall material layer 400 of silicon oxide located in the medium-voltage region; subsequently, a fourth sidewall material layer 500 of silicon oxide is deposited in the medium-voltage region and the high-voltage region by a selective deposition process. Since a portion of silicon nitride remains in the high-voltage region, based on... Therefore, the thickness of silicon oxide in the medium-voltage region is greater than that in the low-voltage and high-voltage regions, thereby increasing the oxide layer thickness in the sidewall material layer of the medium-voltage region. Finally, the silicon nitride in the low-voltage region is modified by a modification process to form the third sidewall material layer 400 in the low-voltage region. Thus, on the one hand, it can be ensured that the oxide layer thickness in the sidewall of the gate structure in the medium-voltage region is greater than that in the sidewall of the gate structure in the low-voltage and high-voltage regions, thereby improving the GIDL leakage problem in the medium-voltage region. On the other hand, the preparation method in this application only requires two photolithography processes, which can effectively reduce the number of photolithography processes, reduce the use of masks and photoresists, and thus effectively reduce process costs.

[0066] Another embodiment of this application provides a semiconductor device that can be prepared by the method described in the foregoing embodiments.

[0067] In some embodiments, such as Figure 5F As shown, the semiconductor device includes: a semiconductor substrate 100, a first sidewall material layer 200, a second sidewall material layer 300, a third sidewall material layer 400, and a fourth sidewall material layer 500; the semiconductor substrate 100 includes a low-voltage region, a medium-voltage region, and a high-voltage region, and corresponding gate structures are formed in the low-voltage region, the medium-voltage region, and the high-voltage region, respectively; the first sidewall material layer 200 covers the gate structure and the semiconductor substrate 100; the second sidewall material layer 300 covers the first sidewall material layer 200 in the high-voltage region; the third sidewall material layer 400... A first sidewall material layer 200 covering the low-voltage and medium-voltage zones, and a second sidewall material layer 300 covering the high-voltage zone, are flush with the top surfaces of a third sidewall material layer 400 covering all three zones. A fourth sidewall material layer 500 covers the third sidewall material layer 400 in both the medium-voltage and high-voltage zones. In a first direction perpendicular to the substrate, the total thickness of the third and fourth sidewall material layers 400 and 500 in the medium-voltage zone is greater than that in the high-voltage zone. This effectively increases the thickness of the sidewall material layer in the medium-voltage zone, thereby improving the GIDL leakage problem in the medium-voltage zone.

[0068] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A semiconductor substrate is provided, the semiconductor substrate including a low-voltage region, a medium-voltage region and a high-voltage region, and a corresponding gate structure is formed in the low-voltage region, the medium-voltage region and the high-voltage region respectively; A first sidewall material layer and a second sidewall material layer are formed sequentially, the first sidewall material layer and the second sidewall material layer covering the gate structure and the semiconductor substrate; A first mask layer is formed to cover the second sidewall material layer of the low-pressure area and the medium-pressure area, while exposing the second sidewall material layer of the high-pressure area. A first modification process is performed to modify the second sidewall material layer of the high-voltage zone, transforming the portion of the second sidewall material layer near the top layer of the high-voltage zone into a silicon oxide layer for use as the third sidewall material layer located in the high-voltage zone. A second mask layer is formed to cover the second sidewall material layer of the low-pressure zone, while at least exposing the second sidewall material layer of the medium-pressure zone; A second modification process is performed to modify the second sidewall material layer of the medium-pressure zone, converting the entire second sidewall material layer of the medium-pressure zone into silicon oxide for use as the third sidewall material layer located in the medium-pressure zone. A fourth sidewall material layer is formed to cover the third sidewall material layer of the medium-pressure zone and the high-pressure zone; A third modification process is performed to modify the second sidewall material layer of the low-voltage zone, converting the entire second sidewall material layer of the low-voltage zone into silicon oxide, so as to serve as the third sidewall material layer located in the low-voltage zone.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the first sidewall material layer is 70-90 angstroms; and / or The thickness of the second sidewall material layer is 40 angstroms to 60 angstroms; and / or The thickness of the third sidewall material layer located in the high-pressure zone is 25 angstroms to 35 angstroms.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The material of the second sidewall material layer includes silicon nitride; The first modification process includes: The silicon nitride is activated by bombarding the surface of the exposed second sidewall material layer with hydrogen plasma, and the depth of the activation treatment is less than the thickness of the second sidewall material layer. The activated second sidewall material layer is placed in an oxygen-containing atmosphere, causing the activated silicon nitride to be oxidized to form silicon oxide; and / or The second modification process includes: The silicon nitride is activated by bombarding the surface of the exposed second sidewall material layer with hydrogen plasma, and the depth of the activation treatment is not less than the thickness of the second sidewall material layer. The activated second sidewall material layer is placed in an oxygen-containing atmosphere, so that the activated silicon nitride is oxidized to form silicon oxide.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The oxygen-containing atmosphere is air; and / or In the first modification process, the activation time for silicon nitride is 25s-35s; and / or In the second modification process, the activation time for silicon nitride is 50s-70s.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the fourth sidewall layer includes silicon dioxide; The fourth sidewall material layer covering the third sidewall material layer in the medium-pressure zone and the high-pressure zone includes: The semiconductor substrate is placed in the reaction chamber; A silicon-containing reaction precursor is introduced into the reaction chamber. The reaction precursor selectively adsorbs onto the surface of the third sidewall material layer, but not onto the surface of the second sidewall material layer. An oxygen-containing oxidant is introduced into the reaction chamber, and the oxidant reacts with the reaction precursor adsorbed on the surface of the third sidewall material layer to form a silicon oxide layer as the fourth sidewall material layer.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The reaction precursor includes diisopropylaminosilane, bis(diethylamino)silane, or bis(tert-butylamino)silane; and / or The oxidant includes ozone.

7. The method for fabricating a semiconductor device according to claim 5, characterized in that, The thickness of the fourth sidewall material layer is 40 angstroms to 60 angstroms; and / or During the formation of the fourth sidewall material layer, the temperature in the reaction chamber is below 100°C.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The preparation method further includes: forming a fifth sidewall material layer covering the third sidewall material layer in the low-pressure zone and the fourth sidewall material layer in the medium-pressure zone and the high-pressure zone.

9. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor substrate, comprising a low-voltage region, a medium-voltage region, and a high-voltage region, wherein corresponding gate structures are formed in the low-voltage region, the medium-voltage region, and the high-voltage region, respectively; A first sidewall material layer covers the gate structure and the semiconductor substrate; A second sidewall material layer covers the first sidewall material layer in the high-voltage zone; The third sidewall material layer covers the first sidewall material layer of the low-pressure area and the medium-pressure area, as well as the second sidewall material layer of the high-pressure area, and the top surfaces of the third sidewall material layer of the low-pressure area, the medium-pressure area, and the high-pressure area are flush with each other; A fourth sidewall material layer covers the third sidewall material layer in the medium-pressure zone and the high-pressure zone; In the first direction perpendicular to the substrate, the total thickness of the third and fourth sidewall material layers in the medium-pressure zone is greater than the total thickness of the third and fourth sidewall material layers in the high-pressure zone.

10. The semiconductor device according to claim 9, characterized in that, The material of the second sidewall material layer includes silicon nitride; and / or The material of the third sidewall layer includes silicon dioxide; and / or The material of the fourth sidewall layer includes silicon dioxide.

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