Heterogeneous integrated chip system, package and control method based on active glass substrate
Patent Information
- Application Number
- CN202611064468.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-17
- Publication Date
- 2026-11-03
AI Technical Summary
In existing heterogeneous integrated chip systems, the glass substrate serves as a passive carrier, leading to increased system complexity and reduced flexibility and reconfigurability of inter-chip interconnect configurations, making it difficult to support highly interactive new computing architectures.
By using an active glass substrate, thin-film transistor circuits are fabricated on the glass substrate to form an interconnect gating network and functional unit array, which directly realizes communication between the control chip and the functional unit, dynamically configures the interconnect topology, and reduces the need for dedicated switching chips.
It reduces system complexity, improves the flexibility and reconfigurability of chip interconnect configurations, reduces overall integration area and material costs, and supports highly interactive new computing architectures.
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Figure CN123035734A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging, specifically to a heterogeneous integrated chip system, packaging, and control method based on an active glass substrate. Background Technology
[0002] Currently, advanced packaging technologies such as CoPoS (Chip-on-Panel-on-Substrate), which uses glass substrates to replace silicon interposers, are gradually gaining more attention. However, whether it is the silicon interposer used in previous 2.5D advanced packaging technologies, such as CoWoS (Chip-on-Wafer-on-Substrate), or the glass substrate used in CoPoS, they are only used as passive carriers for metal traces. The realization of further logic functions still depends on silicon-based switching chips bonded to them. This leads to increased system complexity of heterogeneous integration, reduced flexibility and reconfigurability of inter-chip interconnect configurations, and is not conducive to realizing new computing architectures with higher requirements. Summary of the Invention
[0003] This application discloses a heterogeneous integrated chip system, packaging, and control method based on an active glass substrate. It can effectively reduce the system complexity of heterogeneous integration by utilizing an active glass substrate based on thin-film transistor circuits, while improving the flexibility and reconfigurability of the interconnect configuration between chips, thereby facilitating the support of new computing architectures with higher interactivity requirements.
[0004] The first aspect of this application discloses a heterogeneous integrated chip system based on an active glass substrate, comprising: A glass substrate on which thin-film transistor circuits are fabricated, wherein the thin-film transistor circuits form an interconnect gating network and a functional unit array, respectively. A control chip, which is bonded to the surface of the glass substrate and connected to one or more target functional units in the functional unit array via the interconnect gating network; The interconnection and gating network is used to enable communication between the control chip and the target functional unit. The target functional unit is used to execute the target calculation task under the control of the control chip.
[0005] The second aspect of this application discloses a method for packaging a heterogeneous integrated chip system based on an active glass substrate, comprising: A glass substrate is formed, and wiring and via structures are formed on the glass substrate; Thin-film transistor circuits are fabricated on the surface of the glass substrate, forming interconnect gating networks and functional unit arrays, such that the interconnect gating networks and functional unit arrays are connected through the wiring and via structures. The control chip is bonded to the surface of the glass substrate so that the control chip is connected to the interconnect gating network and the functional unit array through the wiring and via structure, respectively; or, it is connected to the interconnect gating network and connected to the functional unit array through the interconnect gating network.
[0006] A third aspect of this application discloses a control method for a heterogeneous integrated chip system based on an active glass substrate, applied to a heterogeneous integrated chip system. The heterogeneous integrated chip system includes a glass substrate and a control chip. Thin-film transistor circuits are fabricated on the surface of the glass substrate, forming interconnect gating networks and functional unit arrays. The control chip is bonded to the surface of the glass substrate and connected to one or more target functional units in the functional unit array through the interconnect gating networks. The method includes: The first control chip configures the on / off state of each thin-film transistor in the interconnect gating network by sending source signals, and forms a communication connection with the communication target. The communication target is either the second control chip or one of the target functional units in the functional unit array, and the first control chip and the second control chip are any one of the plurality of control chips.
[0007] Compared with related technologies, the embodiments of this application have the following beneficial effects: In this embodiment, the heterogeneous integrated chip system may include a glass substrate and a control chip. A thin-film transistor (TFT) circuit is fabricated on the surface of the glass substrate, which can form an interconnect gating network and a functional unit array. The control chip is bonded to the surface of the glass substrate and connected to one or more target functional units in the functional unit array via the interconnect gating network. The interconnect gating network enables communication between the control chip and the target functional units; the target functional units can execute target computational tasks under the control of the control chip. Therefore, by implementing this embodiment, an active switching network can be formed by directly fabricating TFT circuits on the glass substrate. The resulting active glass substrate does not require a large amount of metal wiring and can directly support the control chip, enabling controllable interconnection and flexible gating between the control chip and the functional unit array. This transforms the glass substrate from a passive carrier into an active functional component, helping to overcome the shortcomings of traditional, rigid, and inflexible metal wiring, and enabling dynamic configuration of the heterogeneous integrated chip system. Furthermore, the functional unit array formed by the TFT circuit can flexibly adapt to different task requirements of the control chip, achieving deep heterogeneous integration under its high-precision gating control. This design can effectively reduce the system complexity of heterogeneous integration, reduce the overall integration area and material cost, while improving the flexibility and reconfigurability of inter-chip interconnect configurations and reducing the need for dedicated switching chips. This is conducive to supporting new computing architectures with higher interactivity requirements while optimizing costs. Attached Figure Description
[0008] Figure 1 This is a three-dimensional structural schematic diagram of a heterogeneous integrated chip system based on an active glass substrate disclosed in an embodiment of this application; Figure 2 This is a cross-sectional structural schematic diagram of a heterogeneous integrated chip system based on an active glass substrate disclosed in an embodiment of this application; Figure 3 This is a schematic diagram of the overall framework of a heterogeneous integrated chip system based on an active glass substrate disclosed in an embodiment of this application; Figure 4A This is a schematic diagram of a connection method for a heterogeneous integrated chip system based on an active glass substrate disclosed in an embodiment of this application; Figure 4B This is a schematic diagram of another connection method for a heterogeneous integrated chip system based on an active glass substrate disclosed in an embodiment of this application; Figure 5 This is a schematic flowchart of a heterogeneous integrated chip system packaging method based on an active glass substrate disclosed in an embodiment of this application; Figure 6 This is a flowchart illustrating a heterogeneous integrated chip system control method based on an active glass substrate disclosed in an embodiment of this application. Detailed Implementation
[0009] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0010] It should be noted that the terms "comprising" and "having" and any variations thereof in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or devices.
[0011] This application discloses a heterogeneous integrated chip system, packaging, and control method based on an active glass substrate. It can effectively reduce the system complexity of heterogeneous integration by utilizing an active glass substrate based on thin-film transistor circuits, while improving the flexibility and reconfigurability of the interconnect configuration between chips, thereby facilitating the support of new computing architectures with higher interactivity requirements.
[0012] The following will be described in detail with reference to the accompanying drawings.
[0013] Please see Figure 1 , Figure 1 This is a three-dimensional structural schematic diagram of a heterogeneous integrated chip system based on an active glass substrate disclosed in an embodiment of this application. Figure 1 As shown, the heterogeneous integrated chip system may include a glass substrate 100 and a control chip 300. A thin-film transistor circuit 200 is fabricated on the surface of the glass substrate 100, which can form an interconnect gating network 210 and a functional unit array 220. Based on this, the control chip 300 can be bonded to the surface of the glass substrate 100 and connected to one or more target functional units in the functional unit array 220 via the interconnect gating network 210, thus achieving heterogeneous integration.
[0014] The interconnect gating network 210 formed by the aforementioned thin-film transistors (TFTs) can be used to realize communication between the control chip 300 and the target functional unit. Since the corresponding thin-film transistor circuit 200 is directly fabricated on the surface of the glass substrate 100, the interconnect gating network 210 and the control chip 300 can be connected through the wiring and via structure formed on the glass substrate 100. Thus, the glass substrate 100 (in conjunction with the aforementioned thin-film transistor circuit 200) actually undertakes the active guidance function (such as addressing, gating, state maintenance, etc.) based on the interconnect gating network 210. Compared with the case where only the glass substrate is used as a passive carrier, a large number of metal wirings can be saved, and the communication connection between the control chip 300 and the designated target functional unit can be established more flexibly and controllably.
[0015] Furthermore, the aforementioned target functional units can be used to execute target computing tasks under the control of the control chip 300. In some embodiments, the aforementioned functional unit array 220 may include one or more neuromorphic computing units, which may include thin-film transistor-based neuronal circuits and / or synaptic circuits. Based on this, the control chip 300 configures one or more neuromorphic computing units as target functional units through the aforementioned interconnect gating network 210, and can instruct the corresponding target functional units to execute neuromorphic computing tasks, thereby realizing a novel computing architecture suitable for tasks such as neuromorphic computing that require flexible interaction between a large number of units.
[0016] For example, the thin-film transistor circuit 200 described above may be a low-temperature polycrystalline silicon thin-film transistor or an oxide thin-film transistor, and no specific limitation is made in the embodiments of this application.
[0017] Please refer to further information. Figure 2 , Figure 2 This is a cross-sectional structural diagram of a heterogeneous integrated chip system based on an active glass substrate disclosed in an embodiment of this application. Figure 2 As shown, traces and via structures (represented by the blacked-out portions) can be formed on the glass substrate 100. The interconnect gating network 210, the functional unit array 220, and the control chip 300 (taking two control chips 310 and 320 as examples) can be connected through different traces and via structures.
[0018] It should be noted that, Figure 2 The wiring and via structure shown is only a hierarchical example. In actual production, the glass substrate 100 can be specifically designed according to the type and quantity of the functional unit array 220 and the control chip 300, as well as the topology between them and the interconnect gating network 210.
[0019] like Figure 2As shown, when the silicon interposer of the traditional packaging scheme is replaced by a glass substrate 100, the control chip 300 can be directly bonded to the surface of the glass substrate 100. The aforementioned wiring and via structures, and interconnect gate network 210 replace the metal wiring. It is understood that, based on actual production needs, some areas or lines of metal wiring may also be retained, and no specific limitations are made in the embodiments of this application.
[0020] To further explain, Figure 2 This paper only shows the necessary structures for connecting the interconnect gating network 210, the functional unit array 220, and the control chip 300 via the glass substrate 100 in this embodiment of the application. Other structures required to constitute a heterogeneous integrated chip system are not specifically shown. Optionally, the thin-film transistor circuit 200 (used to form the interconnect gating network 210 and the functional unit array 220) can be fabricated deeper in the glass substrate 100; the functional unit array 220, the control chip 300, and the interconnect gating network 210 can be in close contact or a certain distance can be maintained, which can be determined by the design requirements of the above-mentioned wiring and via structures.
[0021] In some embodiments, the control chip 300 described above may include multiple chips. For example... Figure 1 As shown, taking control chips 310, 320, and 330 as examples, multiple control chips 300 can be connected to the interconnection network 210 through the traces and vias formed by the glass substrate 100, and communication between the various control chips 300 can be achieved through the interconnection network 210.
[0022] Optionally, the aforementioned multiple control chips 300 can be silicon-based CMOS (Complementary Metal-Oxide-Semiconductor) chips, and are fixed in an array on the surface of the glass substrate 100 using a specific bonding method. Exemplarily, the bonding method can include flip chip bonding, direct bonding, adhesive bonding, etc., and is not specifically limited in this embodiment. It should be noted that the aforementioned control chips 300 can be packaged using a logic die and high-bandwidth memory (HBM) stacked structure to realize interconnect communication, computing control, and other functions.
[0023] In this embodiment, the interconnect gating network 210 may include a cross switch matrix. The aforementioned multiple control chips 300 can dynamically change the topology of the interconnect gating network 210 by configuring the on / off states of each thin-film transistor in the cross switch matrix.
[0024] Based on this, each control chip 300 can be electrically connected to the interconnection network 210 through the wiring and via structure on the glass substrate 100, and then electrically connected to one or more functional units (such as neuromorphic computing units, the configured and connected functional units can be referred to as target functional units) in the functional unit array 220. Each control chip 300 can be used to execute high-precision control algorithms, configure instructions, and complete external data interaction; each target functional unit can have independent input and output ports for executing target computing tasks under the control of the corresponding control chip 300.
[0025] Please refer to further information. Figure 3 , Figure 3 This is a schematic diagram of the overall framework of a heterogeneous integrated chip system based on an active glass substrate disclosed in an embodiment of this application. Figure 3 As shown, multiple control chips 300 (e.g., control chips 310, 320, 330...) can be interconnected via a gating network 210 ( Figure 3 (Not specifically shown) is connected to the functional unit array 220, and is specifically connected to one or more target functional units (e.g., target functional units 221, 222, 223, 224...) based on the configuration of the interconnect gating network 210.
[0026] As an optional implementation, the control chip 300 can dynamically configure the topology of the interconnect gating network 210 by controlling the conduction of each thin-film transistor corresponding to the functional unit array 220 in the above-mentioned cross switch matrix, and form a communication connection with each corresponding target functional unit.
[0027] For example, such as Figure 4A As shown, the control chip 310 can establish a communication connection with the target functional units 221 and 222 by configuring the thin-film transistors corresponding to the target functional units 221 and 222 to the on state; the control chip 320 can also establish a communication connection with the target functional units 223 and 224 by configuring the thin-film transistors corresponding to the target functional units 223 and 224 to the on state; if the control chip 330 does not configure the thin-film transistors corresponding to any target functional unit, it can temporarily disconnect from the functional unit array 220.
[0028] As another optional implementation, when the control chip 300 includes multiple chips, the first control chip can further dynamically configure the topology of the interconnect gating network 210 by controlling the conduction of the thin-film transistors corresponding to the second control chip in the cross-switch matrix, thereby forming a communication connection with the second control chip. It is understood that the first control chip and the second control chip can each be any one of the multiple control chips 300.
[0029] For example, such as Figure 4B As shown, with the control chip 310 as the first control chip and the control chip 320 as the second control chip, the first control chip 310 can establish a communication connection with the second control chip 320 by configuring the thin-film transistor corresponding to the second control chip 320 to be in a conducting state. During this process, the first control chip 310 and the second control chip 320 can maintain their communication connections with the configured target functional unit, or they can temporarily disconnect; this is not specifically limited in the embodiments of this application.
[0030] like Figure 4A , 4B As shown, unlike the COG (Chipon Glass) scheme in the display driver field, which has a fixed topology and unidirectional communication control, the heterogeneous integrated chip system in this application embodiment can dynamically and flexibly configure the interconnection topology between chips (including between each control chip 300, or between the control chip 300 and the target functional unit) based on the thin film transistor circuit 200 directly manufactured on the surface of the glass substrate 100, so as to achieve bidirectional reliable communication and effectively overcome the defects of traditional wiring schemes.
[0031] As can be seen, the heterogeneous integrated chip system based on an active glass substrate described in the above embodiments can form an active switching network by directly fabricating thin-film transistor circuits 200 on the glass substrate 100. The resulting active glass substrate does not require a large number of metal traces and can directly support the control chip 300, enabling controllable interconnection and flexible selection between the control chip 300 and the functional unit array 220. This transforms the glass substrate from a passive carrier into an active functional component, helping to overcome the shortcomings of traditional metal wiring, which is fixed and inflexible, and enabling dynamic configuration of the heterogeneous integrated chip system. Simultaneously, the functional unit array 220 formed based on the aforementioned thin-film transistor circuit 200 can flexibly adapt to the different task requirements of the control chip 300, achieving deep heterogeneous integration under its high-precision selection control. This design effectively reduces the system complexity of heterogeneous integration, reduces the overall integration area and material costs, while improving the flexibility and reconfigurability of inter-chip interconnection configurations, reducing the need for dedicated switching chips. This facilitates supporting new computing architectures with higher interactivity requirements while optimizing costs.
[0032] Please see Figure 5 , Figure 5 This is a schematic flowchart of a heterogeneous integrated chip system packaging method based on an active glass substrate disclosed in an embodiment of this application. Figure 5 As shown, the encapsulation method may include the following steps: S502, Form a glass substrate and form wiring and via structures on the glass substrate.
[0033] S504. A thin-film transistor circuit is fabricated on the surface of a glass substrate, forming an interconnect gating network and a functional unit array, such that the interconnect gating network and the functional unit array are connected through the aforementioned wiring and via structure.
[0034] S506. The control chip is bonded to the surface of the glass substrate so that the control chip is connected to the interconnect gating network and the functional unit array through the above-mentioned wiring and via structure; or, it is connected to the interconnect gating network and connected to the functional unit array through the interconnect gating network.
[0035] As can be seen, by implementing the packaging method described in the above embodiments, active gating, routing and other functions (implemented based on interconnect gating networks) can be integrated on the glass substrate, thereby reducing the need for dedicated switching chips, greatly simplifying the design requirements of heterogeneous integrated chip systems, helping to reduce overall area and material costs, and improving packaging fault tolerance.
[0036] Please see Figure 6 , Figure 6 This is a flowchart illustrating a control method for a heterogeneous integrated chip system based on an active glass substrate, as disclosed in an embodiment of this application. This control method can be applied to the aforementioned heterogeneous integrated chip system, which may include a glass substrate and a control chip. A thin-film transistor circuit is fabricated on the surface of the glass substrate, and this thin-film transistor circuit can respectively form an interconnect gating network and a functional unit array. The control chip is bonded to the surface of the glass substrate and can be connected to one or more target functional units in the functional unit array through the interconnect gating network. Figure 6 As shown, the control method may include the following steps: S602, The first control chip configures the on / off state of each thin-film transistor in the interconnect gating network by sending source signals, and forms a communication connection with the communication target; The communication target can be one of the target functional units of the second control chip or the functional unit array, and the first control chip and the second control chip can be any one of a plurality of control chips.
[0037] As can be seen, the control method described in the above embodiments can dynamically and flexibly configure the interconnection topology between chips, achieve bidirectional reliable communication, and dynamically configure heterogeneous integrated chip systems to flexibly adapt to different task requirements of the control chip. Based on this, by utilizing a large-area, low-cost thin-film transistor neuromorphic array (i.e., the aforementioned functional unit array), deep heterogeneous integration can be achieved under the high-precision control of the control chip, supporting a novel computing architecture that supports tasks requiring flexible interaction between a large number of units, such as neuromorphic computing.
[0038] In some embodiments, the control chip for which the above control method is applied may include: Memory containing executable program code; A processor coupled to memory; The processor can call the executable program code stored in the memory to execute all or part of the steps in the heterogeneous integrated chip system control method based on an active glass substrate described in the above embodiments.
[0039] Furthermore, embodiments of this application disclose a readable storage medium that stores an executable program for electronic data exchange, wherein the executable program enables a control chip to perform all or part of the steps in the heterogeneous integrated chip system control method based on an active glass substrate described in the above embodiments.
[0040] The above provides a detailed description of a heterogeneous integrated chip system, packaging, and control method based on an active glass substrate disclosed in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of the system structure and method in this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A heterogeneous integrated chip system based on an active glass substrate, characterized in that, include: A glass substrate on which thin-film transistor circuits are fabricated, wherein the thin-film transistor circuits form an interconnect gating network and a functional unit array, respectively. A control chip, which is bonded to the surface of the glass substrate and connected to one or more target functional units in the functional unit array via the interconnect gating network; The interconnection and gating network is used to enable communication between the control chip and the target functional unit. The target functional unit is used to execute the target calculation task under the control of the control chip.
2. The heterogeneous integrated chip system according to claim 1, characterized in that, The glass substrate has a wiring and via structure, and the interconnect gating network, the functional unit array and the control chip are connected through the wiring and via structure.
3. The heterogeneous integrated chip system according to claim 2, characterized in that, The control chip includes multiple chips, which are respectively connected to the interconnection gating network through the wiring and via structure, and the interconnection gating network enables communication between the control chips.
4. The heterogeneous integrated chip system according to any one of claims 1 to 3, characterized in that, The interconnect gating network includes a cross switch matrix, and the control chip dynamically changes the topology of the interconnect gating network by configuring the on / off state of each thin-film transistor in the cross switch matrix.
5. The heterogeneous integrated chip system according to claim 4, characterized in that, The control chip establishes a communication connection with each target functional unit by controlling the conduction of each thin-film transistor corresponding to the functional unit array in the cross switch matrix.
6. The heterogeneous integrated chip system according to claim 4, characterized in that, When there are multiple control chips, the first control chip forms a communication connection with the second control chip by controlling the conduction of the thin-film transistors in the cross switch matrix corresponding to the second control chip; The first control chip and the second control chip are each any one of the plurality of control chips.
7. The heterogeneous integrated chip system according to any one of claims 1 to 3, characterized in that, The functional unit array includes one or more neuromorphic computing units, each comprising thin-film transistor-based neuronal circuits and / or synaptic circuits, and is used to perform neuromorphic computing tasks under the configuration of the control chip.
8. The heterogeneous integrated chip system according to any one of claims 1 to 3, characterized in that, The thin-film transistor circuit uses low-temperature polycrystalline silicon thin-film transistors or oxide thin-film transistors.
9. A method for packaging a heterogeneous integrated chip system based on an active glass substrate, characterized in that, include: A glass substrate is formed, and wiring and via structures are formed on the glass substrate; Thin-film transistor circuits are fabricated on the surface of the glass substrate, forming interconnect gating networks and functional unit arrays, such that the interconnect gating networks and functional unit arrays are connected through the wiring and via structures. The control chip is bonded to the surface of the glass substrate so that the control chip is connected to the interconnect gating network and the functional unit array through the wiring and via structure, respectively. Alternatively, it can be connected to the interconnect gating network and connected to the functional unit array via the interconnect gating network.
10. A control method for a heterogeneous integrated chip system based on an active glass substrate, characterized in that, A method applicable to heterogeneous integrated chip systems, the heterogeneous integrated chip system comprising a glass substrate and a control chip, wherein thin-film transistor circuits are fabricated on the surface of the glass substrate, the thin-film transistor circuits respectively forming an interconnect gating network and a functional unit array, and the control chip is bonded to the surface of the glass substrate and connected to one or more target functional units in the functional unit array through the interconnect gating network, the method comprising: The first control chip configures the on / off state of each thin-film transistor in the interconnect gating network by sending source signals, and forms a communication connection with the communication target. The communication target is either the second control chip or one of the target functional units in the functional unit array, and the first control chip and the second control chip are any one of the plurality of control chips.