Array substrate, display panel and display device

Abstract

The application relates to the technical field of display, and particularly discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate, a driving circuit layer, a first planar layer, a bridge electrode layer, a second planar layer and pixel electrodes arranged in an array which are sequentially arranged on the substrate; the driving circuit layer comprises thin film transistors arranged in an array; the bridge electrode layer comprises bridge electrodes arranged in an array; the pixel electrodes are electrically connected to a bridge electrode through first through holes in the second planar layer; the bridge electrodes are electrically connected to the first poles of the thin film transistors through second through holes in the first planar layer; and the first through holes and the second through holes are arranged at intervals in a plane parallel to the substrate. The array substrate provided by the application can ensure yield on the basis of reducing parasitic capacitance.

Description

Technical Field

[0001] This invention relates to the field of display technology. More specifically, it relates to an array substrate, a display panel, and a display device. Background Technology

[0002] Currently, array substrates serve as the core driving substrates for display panels. Array substrates typically include thin-film transistors, pixel electrodes, and multiple passivation layers and planarization layers located between the thin-film transistors and pixel electrodes. The pixel electrodes are electrically connected to the thin-film transistors through vias in the multiple passivation layers and planarization layers to obtain the pixel voltage driving the display panel.

[0003] However, in related technologies, directly etching all the passivation and planarization layers between the thin-film transistor and the pixel electrode can cause the pixel electrode to be electrically connected to the thin-film transistor through a relatively deep via. The pixel electrode is prone to ramp breakage, which prevents the electrical signal of the thin-film transistor from being conducted to the pixel electrode, resulting in display abnormalities. At the same time, the large parasitic capacitance between the pixel electrode and the electrode of the thin-film transistor and other adjacent conductive structures can affect the charging rate and display effect.

[0004] Therefore, there is an urgent need to provide an array substrate that balances low parasitic capacitance and improves pixel electrode breakage. Summary of the Invention

[0005] The purpose of this invention is to provide an array substrate, a display panel, and a display device to solve at least one of the problems existing in the prior art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A first aspect of the present invention provides an array substrate, comprising: a substrate and a driving circuit layer, a first planarization layer, a bridging electrode layer, a second planarization layer, and an array of pixel electrodes sequentially stacked on the substrate; the driving circuit layer includes an array of thin-film transistors, and the bridging electrode layer includes an array of bridging electrodes; the pixel electrodes are electrically connected to a bridging electrode through a first via of the second planarization layer, and the bridging electrode is electrically connected to a first electrode of a thin-film transistor through a second via of the first planarization layer, wherein the first via and the second via are spaced apart in a plane parallel to the substrate.

[0007] Optionally, it further includes: a first passivation layer located between the bridging electrode layer and the second planarization layer, the first passivation layer including a third via communicating with the first via, and the pixel electrode being electrically connected to a bridging electrode through the first via and the third via.

[0008] Optionally, it further includes: a second passivation layer located between the bridging electrode layer and the first planarization layer, the second passivation layer including a fourth via communicating with the second via, the bridging electrode being electrically connected to the first electrode of the thin-film transistor through the fourth via and the second via.

[0009] Optionally, the driving circuit layer includes a third passivation layer located between the first electrode of the thin-film transistor and the first planarization layer. The third passivation layer includes a fifth via communicating with the second via. The bridging electrode is electrically connected to the first electrode of the thin-film transistor through the second via and the fifth via.

[0010] Optionally, it further includes: a fourth passivation layer located between the second planarization layer and the pixel electrode, the fourth passivation layer including a sixth via communicating with the first via, the pixel electrode being electrically connected to a bridging electrode through the sixth via and the first via.

[0011] Optionally, it further includes: a common electrode located between the second planarization layer and the fourth passivation layer, wherein the fourth passivation layer is located between the pixel electrode and the common electrode.

[0012] Optionally, it further includes: a touch line, wherein the bridging electrode is disposed on the same layer as the touch line and spaced apart.

[0013] The present invention also provides a method for fabricating an array substrate, comprising: sequentially forming a driving circuit layer, a first planarization layer, a bridging electrode layer, a second planarization layer, and an array of pixel electrodes on the substrate, wherein the driving circuit layer includes an array of thin-film transistors, and the bridging electrode layer includes an array of bridging electrodes; the pixel electrodes are electrically connected to a bridging electrode through a first via of the second planarization layer, and the bridging electrode is electrically connected to a first electrode of a thin-film transistor through a second via of the first planarization layer, wherein the first via and the second via are spaced apart in a plane parallel to the substrate.

[0014] The present invention also provides a display panel, including the array substrate described in the present invention.

[0015] The present invention also provides a display device, including the display panel described in the present invention.

[0016] The beneficial effects of this invention are as follows: The array substrate provided by this invention utilizes a double-layer planar structure composed of a first planarization layer and a second planarization layer. This increases the interlayer distance between the pixel electrode and the first electrode, and between the pixel electrode and other functional layers (e.g., touch lines), thereby reducing the parasitic capacitance between the pixel electrode and the first electrode, and between the pixel electrode and other functional layers (e.g., touch lines). Further research revealed that the double-layer planar structure is more prone to pixel failure than the single-layer planar structure. Analysis confirmed that pixel failure originates from the need to form a single, relatively deep via penetrating both the second and first planarization layers in the double-layer planar structure. Single, deep vias are prone to breakage when their sidewalls are ramped up. Therefore, this invention incorporates a bridging electrode layer between the driving circuit layer and the pixel electrode. The pixel electrode is electrically connected to a bridging electrode via a first via in the second planarization layer, and the bridging electrode is electrically connected to the first electrode of a thin-film transistor via a second via in the first planarization layer. The first and second vias are spaced apart in a plane parallel to the substrate. In other words, two independent, shallow vias that are layered and staggered replace a single, deep via that directly penetrates the second and first planarization layers. This significantly reduces the ramp height of the pixel electrode, effectively improving pixel electrode breakage. In summary, the array substrate provided by this invention can maintain high yield while reducing parasitic capacitance. Attached Figure Description

[0017] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0018] Figure 1 A plan view of an array substrate provided in an embodiment of the present invention is shown.

[0019] Figure 2 Show along Figure 1 A cross-sectional view obtained from section AA'; Figure 3 A flowchart illustrating a method for fabricating an array substrate according to another embodiment of the present invention is shown; Figures 4 to 12 This diagram shows cross-sectional schematics of each stage in the fabrication process of an array substrate provided in another embodiment of the present invention. Detailed Implementation

[0020] In this invention, "on," "formed on," and "set on" can mean that one layer is directly formed or set on another layer, or that one layer is indirectly formed or set on another layer, meaning that there are other layers between the two layers.

[0021] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or portions, these components, members, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or portion from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the invention.

[0022] Combination Figure 1 and Figure 2 , Figure 1 This is a plan view of the array substrate. Figure 2 For along Figure 1 A cross-sectional view obtained from section line AA'. An embodiment of the present invention provides an array substrate, comprising: a substrate 1 and a driving circuit layer 2, a first planarization layer 3, a bridging electrode layer 4, a second planarization layer 5, and an array of pixel electrodes 6 sequentially stacked on the substrate 1; the driving circuit layer 2 includes an array of thin-film transistors (TFTs), and the bridging electrode layer 4 includes an array of bridging electrodes 41; the pixel electrodes 6 are electrically connected to a bridging electrode 41 through a first via 51 of the second planarization layer 5, and the bridging electrode 41 is electrically connected to a first electrode 7 of a thin-film transistor (TFT) through a second via 31 of the first planarization layer 3; the first via 51 and the second via 31 are spaced apart in a plane parallel to the substrate 1.

[0023] In this embodiment, the double-layer planar structure formed by the first planarization layer 3 and the second planarization layer 5 increases the interlayer distance between the pixel electrode 6 and the first electrode 7, and between the pixel electrode 6 and other functional layers (such as the touch line 16), thereby reducing the parasitic capacitance between the pixel electrode 6 and the first electrode 7, and between the pixel electrode 6 and other functional layers (such as the touch line 16), and improving the pixel charging rate and refresh rate. Further research revealed that although the double-layer planar structure can solve the problem of large parasitic capacitance in the array substrate, it is more prone to pixel failure than the single-layer planar structure. Analysis confirmed that pixel failure is caused by the pixel electrode 6 being more prone to breakage. The reason why the pixel electrode 6 is prone to breakage is that the double-layer planar structure requires the formation of a single and relatively deep via that penetrates the second planarization layer 5 and the first planarization layer 3. The pixel electrode 6 is prone to breakage when the sidewall of the single and relatively deep via is covered. To address the issue of pixel electrode breakage, a bridging electrode layer is constructed between the driving circuit layer and the pixel electrode. The pixel electrode 6 is electrically connected to a bridging electrode 41 via a first via 51 of the second planarization layer 5. The bridging electrode 41 is electrically connected to the first electrode 7 of a thin-film transistor via a second via 31 of the first planarization layer 3. The first via 51 and the second via 31 are spaced apart in a plane parallel to the substrate 1. This means that two independent, shallow vias that are layered and staggered replace the single, deep via that directly penetrates the second planarization layer 5 and the first planarization layer 3. This allows the pixel electrode 6 to extend only through the first via 51, indirectly connecting to the first electrode 7 of the thin-film transistor (TFT) via the bridging electrode 41. The ramp height of the pixel electrode 6 is significantly reduced, effectively mitigating the problem of ramp breakage and ensuring the conductivity continuity of the pixel electrode 6. This allows the electrical signal from the first electrode 7 to be conducted to the pixel electrode, significantly improving the conduction reliability of the pixel electrode 6. In summary, the array substrate provided in this embodiment can simultaneously address the requirements of low parasitic capacitance and improved pixel electrode breakage.

[0024] Furthermore, the double-layer planarization structure formed by the first planarization layer 3 and the second planarization layer 5 can make the surface of the array substrate flatter, especially the surface of the effective display area in the array substrate, which is conducive to the stable positioning of the subsequent spacers (PS). It can effectively prevent the spacers (PS) from sliding into the effective display area under pressure under external force, thus preventing display abnormalities and improving the display effect.

[0025] The thin-film transistor (TFT) further includes: a gate 13 located on one side of the substrate 1 and a gate insulating layer 14 located on the side of the gate 13 facing away from the substrate 1; a semiconductor layer 15 located between the first electrode 7 and the gate insulating layer 14; and a second electrode (not shown) disposed on the same layer as the first electrode 7 and spaced apart. The semiconductor layer 15 includes a channel region and source and drain regions located on both sides of the channel region. The channel region and the gate 13 have overlapping areas when projected onto the substrate 1. The first electrode 7 is connected to the drain region, and the second electrode is connected to the source region. In this embodiment, the first electrode 7 is the drain electrode.

[0026] In a specific example, the driving circuit layer 2 includes multiple scan lines (or gate lines) extending along a first direction X (e.g., row direction) and multiple data lines 12 extending along a second direction Y (e.g., column direction) formed on the substrate 1. The gate 13 of the thin-film transistor (TFT) is connected to the scan lines, and the second electrode (e.g., source electrode) is connected to the data lines 12. When a potential is applied to the gate through the scan lines, the TFT is turned on, i.e., the channel region becomes conductive, and the first electrode 7 and the second electrode are connected. At this time, the data voltage provided by the data lines 12 passes sequentially through the second electrode and the first electrode 7 of the TFT. The voltage signal of the first electrode 7 is transmitted to the bridging electrode 41 through the second via 51 of the first planarization layer 5, and then the bridging electrode 41 transmits the voltage signal of the first electrode 7 to the pixel electrode 6, ultimately achieving electrical connection between the pixel electrode 6 and the first electrode 7.

[0027] In one embodiment, the pixel electrode 6 can be an indium tin oxide (ITO) electrode or an indium zinc oxide (IZO) electrode; the material of the bridging electrode layer 4 includes a metallic conductive material.

[0028] In one embodiment, the thickness of the pixel electrode 6 is 0.6 μm to 0.9 μm, for example, 0.6 μm, 0.7 μm, 0.8 μm, or 0.9 μm. The thickness of the pixel electrode 6 is not less than 0.6 μm to ensure that the pixel electrode 4 has good step coverage capability in the first via 51, enhancing its ability to prevent slope breakage and improving the conductivity of the pixel electrode 3; the thickness of the pixel electrode 6 is not more than 0.9 μm to avoid a decrease in light transmittance due to excessive thickness, ensuring display brightness.

[0029] In one embodiment, the thickness of the first planarization layer 3 is 2μm to 3μm, for example, 2μm, 2.5μm, or 3μm. The thickness of the first planarization layer 3 is not less than 2μm. The first planarization layer 3 can provide sufficient dielectric isolation distance between the bridging electrode 41 and the first electrode 7, reduce the parasitic capacitance between the bridging electrode 4 and the first electrode 7, thereby improving the charging capability of the pixel, and at the same time enhancing the effect of making the surface of the array substrate flatter. The thickness of the first planarization layer 3 is not higher than 3μm to avoid insufficient etching caused by excessive depth of the second via in the first planarization layer 3, and at the same time to avoid a large overall thickness of the array substrate.

[0030] In one embodiment, the thickness of the second planarization layer 5 is 2μm to 3μm, for example, 2μm, 2.5μm, or 3μm. The thickness of the second planarization layer 5 is not less than 2μm, which provides sufficient dielectric isolation distance between the bridging electrode 41 and the pixel electrode 6, reduces the parasitic capacitance between the bridging electrode 4 and the pixel electrode 6, and enhances the effect of making the surface of the array substrate flatter. The thickness of the second planarization layer 5 is not higher than 3μm, which avoids excessive depth of the first via 51 in the second planarization layer 5, enhances the effect of preventing the pixel electrode 6 from climbing and breaking, and also avoids a large overall thickness of the array substrate.

[0031] In one embodiment, the first planarization layer 3 includes a first organic resin layer, and the second planarization layer 5 includes a second organic resin layer.

[0032] In one embodiment, the array substrate further includes a touch line 16, and a bridging electrode 41 is disposed on the same layer as the touch line 16 and spaced apart. The bridging electrode 41 does not need to occupy a separate film layer, which can reduce the number of film layers of the array substrate, thereby reducing the thickness of the array substrate; at the same time, the touch line 16 does not need to occupy the layout space of the first electrode 7, the second electrode or the gate 13, which is beneficial to optimize the layout of the pixel circuit and facilitates the realization of high-density pixel design.

[0033] See Figure 1 In this embodiment, the orthographic projection of the data line 12 onto the substrate 1 and the orthographic projection of the touch line 16 onto the substrate 1 have overlapping areas.

[0034] In this embodiment, the bridging electrode 41 and the touch line 16 are made of the same material, such as a conductive metal. The bridging electrode 41 and the touch line 16 are manufactured using the same process, eliminating the need for a separate process for manufacturing the bridging electrode 41, thus reducing the manufacturing cost of the array substrate.

[0035] In other embodiments, the touch line 16 is made of a different material than the bridging electrode 41.

[0036] In one embodiment, the array substrate further includes a fourth passivation layer 10 located between the second planarization layer 5 and the pixel electrode 6. The fourth passivation layer 10 includes a sixth via 101 communicating with the first via 51. The pixel electrode 6 is electrically connected to a bridging electrode 41 through the sixth via 101 and the first via 51.

[0037] In one embodiment, the array substrate further includes a common electrode 11 located between the second planarization layer 5 and the fourth passivation layer 10, wherein the fourth passivation layer 10 is located between the pixel electrode 6 and the common electrode 11. The fourth passivation layer 10 is used to insulate the pixel electrode 6 and the common electrode 11 to prevent short circuits from causing pixel failure.

[0038] In one embodiment, the common electrode 11 can be an indium tin oxide (ITO) electrode or an indium zinc oxide (IZO) electrode.

[0039] It should be noted that some of the common electrodes 11 are reused as touch sensors by the touch electrodes. This is achieved by dividing the originally continuous common electrodes 11 into multiple independent touch electrode blocks. Since the second planarization layer 5 is usually a single layer, the portion of the common electrodes 11 reused by the touch electrodes is electrically connected to the touch lines 16 through contact holes in the second planarization layer 5. The contact holes and the first vias 51 are spaced apart. Thus, the second planarization layer 5, located between the common electrodes 11 and the touch lines 16, effectively increases the interlayer distance between them, reducing the parasitic capacitance and increasing the refresh rate of the display panel. This makes finger touch more sensitive and accurate, and the display panel responds more quickly.

[0040] As is known to those skilled in the art, the integration of the touch line 16 and the touch electrode into the array substrate in this application is an in-cell touch technology.

[0041] Based on the above analysis, the thicknesses of the pixel electrode 6, the first planarization layer 3, and the second planarization layer 5 are matched in this application. The thicknesses of the first planarization layer 3 and the second planarization layer 5 correspond to the dielectric thicknesses of the second via and the first via 51, respectively. Both vias are shallow vias. The orthogonal projections of the first via 51 and the second via on the substrate 1 are staggered to avoid forming a deep pit structure with overlapping depths. With the pixel electrode 6 having a thickness of 0.6μm to 0.9μm, the pixel electrode 6 can achieve good coverage at the step of the first via 51, fundamentally avoiding the defects of pixel electrode 6 climbing and breaking under the deep pit structure, and avoiding dark spots on the display panel that cause display abnormalities. Furthermore, the two organic planarization layers work together to achieve dual planarization, improving the surface morphology of the effective display area in the array substrate. This facilitates the stable positioning of subsequent spacers (PS), enhances the mechanical pressing reliability of the display panel, and prevents PS from slipping into the display area and affecting the display effect. Simultaneously, parasitic capacitance is reduced from both the driving circuit and touch circuit perspectives, improving pixel charging rate, supporting high refresh rate displays, and enhancing touch sensitivity. The array substrate described above can significantly improve competitiveness in the high-end product market and increase profits.

[0042] In one embodiment, the array substrate further includes a first passivation layer 17 located between the bridging electrode layer 4 and the second planarization layer 5. The first passivation layer 17 includes a third via 171 communicating with the first via 51. The pixel electrode 6 is electrically connected to a bridging electrode 41 through the first via 51 and the third via 171. By disposing the first passivation layer 17 between the bridging electrode layer 4 and the second planarization layer 5, the first passivation layer 17 can passivate and protect the bridging electrode layer 4, preventing it from being etched in subsequent processes.

[0043] It is known that the first passivation layer 17 is also located between the touch line 16 and the second planarization layer 5.

[0044] In one embodiment, the third via 171, the first via 51, and the sixth via 101 are interconnected, and the pixel electrode 6 is electrically connected to a bridging electrode 41 through the sixth via 10, the first via 51, and the third via 171 in sequence.

[0045] In one embodiment, the edges of the orthographic projection of the third via 171 on the substrate 1 and the orthographic projection of the sixth via 101 on the substrate 1 coincide. When forming the third via 171 and the sixth via 101, a first passivation layer 17 and a second planarization layer 5 are first formed, and the second planarization layer 5 is etched to form the first via 51. After depositing the sixth passivation layer 10, the same photomask is used to etch both the sixth passivation layer 10 and the first passivation layer 17 in one step to simultaneously form the sixth via 101 and the third via 171. This eliminates the need for additional photomasks, simplifying the process, saving costs, and improving process efficiency.

[0046] In other embodiments, the edges of the orthographic projection of the third via 171 on the substrate 1 and the orthographic projection of the sixth via 101 on the substrate 1 may not coincide.

[0047] In one embodiment, the array substrate further includes a second passivation layer 8 located between the bridging electrode layer 4 and the first planarization layer 3. The second passivation layer 8 includes a fourth via communicating with the second via. The bridging electrode 41 is electrically connected to the first electrode 7 of a thin-film transistor through the fourth via and the second via. The second passivation layer 8 can effectively protect the first planarization layer 3, preventing the first planarization layer 3 from being etched in subsequent processes and ensuring the planarization effect of the array substrate brought by the first planarization layer 3.

[0048] It is known that the second passivation layer 8 is also located between the touch line 16 and the first planarization layer 3.

[0049] In one embodiment, the driving circuit layer 2 includes a third passivation layer 9 located between the first electrode 7 of the thin-film transistor and the first planarization layer 3. The third passivation layer 9 includes a fifth via communicating with the second via. The bridging electrode 41 is electrically connected to the first electrode 7 of the thin-film transistor through the second via and the fifth via. The third passivation layer 9 effectively protects the first electrode 7 of the thin-film transistor, preventing it from being etched in subsequent processes, thus protecting the device performance of the thin-film transistor and improving the yield of the array substrate process.

[0050] In one embodiment, the second via, the fifth via, and the fourth via are interconnected, and the bridging electrode 41 is electrically connected to the first electrode 7 of a thin-film transistor through the fourth via, the second via, and the fifth via in sequence.

[0051] In one embodiment, the edges of the orthographic projections of the fourth via on substrate 1 and the fifth via on substrate 1 coincide. When forming the fourth and fifth vias, a stacked third passivation layer 9 and a first planarization layer 3 are first formed, and the first planarization layer 3 is etched to form the second via. After depositing the second passivation layer 8, the third passivation layer 9 and the second passivation layer 8 are etched in one step using the same mask to simultaneously form the fourth and fifth vias. This eliminates the need for additional photomasks, simplifying the process, saving costs, and improving process efficiency.

[0052] In other embodiments, the edges of the orthographic projection of the fourth via on substrate 1 and the orthographic projection of the fifth via on substrate 1 may not coincide.

[0053] Another embodiment of the present invention also provides a method for fabricating an array substrate, see reference. Figure 3 ,include: S1: A driving circuit layer, a first planarization layer, a bridging electrode layer, a second planarization layer, and an array of pixel electrodes are sequentially formed on the substrate. The driving circuit layer includes an array of thin-film transistors, and the bridging electrode layer includes an array of bridging electrodes. The pixel electrodes are electrically connected to a bridging electrode through a first via of the second planarization layer, and the bridging electrode is electrically connected to a first electrode of a thin-film transistor through a second via of the first planarization layer. The first via and the second via are spaced apart in a plane parallel to the substrate.

[0054] The following is for reference. Figures 4 to 12 This section details the fabrication process of the array substrate.

[0055] refer to Figure 4 A driving circuit layer 2 is formed on substrate 1.

[0056] In this embodiment, the step of forming the driving circuit layer 2 on the substrate 1 includes: forming a thin film transistor (TFT) on the substrate; and forming a third passivation layer 9 on the side of the thin film transistor (TFT) away from the substrate 1.

[0057] In one embodiment, the process of forming a third passivation layer 9 on the side of the thin-film transistor (TFT) away from the substrate 1 includes a deposition process, such as plasma-enhanced chemical vapor deposition.

[0058] In one embodiment, the step of forming a thin-film transistor on a substrate includes: sequentially forming a gate 13, a gate insulating layer 14, a semiconductor layer, and a first electrode 7 on the substrate. A third passivation layer 9 is located on the side of the first electrode 7 facing away from the substrate 1. The third passivation layer 9 is used to protect the first electrode 7 and prevent the first electrode 7 from being etched, which would affect the device performance of the thin-film transistor.

[0059] The thin-film transistor further includes a second electrode (not shown), which is disposed on the same layer as the first electrode 7 and spaced apart. The semiconductor layer includes a channel region and source and drain regions located on both sides of the channel region. The channel region and the gate 13 have overlapping areas when projected onto the substrate 1. The first electrode 7 is connected to the drain region, and the second electrode is connected to the source region.

[0060] In this embodiment, the first electrode 7 is the drain electrode, and the second electrode is the source electrode.

[0061] For a description of the drive circuit layer 2, including scan lines and data lines, please refer to the description in the foregoing embodiment.

[0062] refer to Figure 5 A first planarization layer 3 is formed on the side of the driving circuit layer 2 facing away from the substrate 1, and a second via 31 is formed in the first planarization layer 3. The second via 31 exposes a portion of the surface of the third passivation layer 9.

[0063] In one embodiment, the process of forming the first planarization layer 3 on the side of the driving circuit layer 2 away from the substrate 1 includes a spin coating process.

[0064] In one embodiment, the process of forming the second via 31 includes a dry etching process or a wet etching process.

[0065] For a description of the thickness and material of the first planarization layer 3, please refer to the description in the foregoing embodiments.

[0066] refer to Figure 6 A second passivation layer 8 is formed on the side of the first planarization layer 3 away from the substrate 1, and a fourth via 81 and a fifth via 91 are formed in the second passivation layer 8 and the third passivation layer 9, respectively.

[0067] The second passivation layer 8 is also located on the sidewall of the first planarization layer 3 and on the surface of the third passivation layer 9 away from the substrate layer.

[0068] In this embodiment, while forming the fourth via 81 in the second passivation layer 8, a fifth via 91 is formed in the third passivation layer 9. The third passivation layer 9 and the second passivation layer 8 are etched in one step using the same photomask, eliminating the need for additional photomasks, simplifying the process, saving costs, and improving process efficiency.

[0069] In other embodiments, a fifth via 91 may be formed first in the third passivation layer 9, and then a fourth via 81 may be formed in the second passivation layer 8.

[0070] In this embodiment, the edges of the orthographic projection of the fourth via 81 on the substrate 1 and the orthographic projection of the fifth via 91 on the substrate 1 coincide.

[0071] In one implementation, the process of forming the second passivation layer 8 on the side of the first planarization layer 3 facing away from the substrate 1 includes a deposition process, such as plasma-enhanced chemical vapor deposition.

[0072] refer to Figure 7 A bridging electrode layer 4 is formed on the side of the second passivation layer 8 that is away from the substrate 1.

[0073] The bridging electrode layer 4 includes an array of bridging electrodes 41. The bridging electrodes 41 are electrically connected to the first electrode 7 of a thin-film transistor via a fourth via 81, a second via 31, and a fifth via 91 in sequence. Specifically, the bridging electrodes 41 extend from the surface of the second passivation layer 8 away from the substrate 1 into the fourth via 81, the second via 31, and the fifth via 91.

[0074] In one specific embodiment, the bridging electrode 41 is located on the surface of the second passivation layer 8 facing away from the substrate 1, the sidewall of the second passivation layer 8, the sidewall of the third passivation layer 9, and a portion of the surface of the first electrode 7 facing away from the substrate 1. The bridging electrode 41 is electrically connected to the first electrode 7.

[0075] In this embodiment, while a bridging electrode layer 4 is formed on the side of the second passivation layer 8 away from the substrate 1, a touch line is formed on the side of the second passivation layer 8 away from the substrate 1, and the bridging electrode 41 and the touch line bridging electrode 41 are spaced apart.

[0076] In other embodiments, the order in which the touch lines and bridging electrodes 41 are formed may not be limited.

[0077] refer to Figure 8 A first passivation layer 17 is formed on the side of the bridging electrode layer 4 facing away from the substrate 1. The first passivation layer 17 can passivate and protect the bridging electrode layer 4, preventing the bridging electrode layer 4 from being etched in subsequent processes.

[0078] In one embodiment, the process of forming the first passivation layer 17 on the side of the bridging electrode layer 4 away from the substrate 1 includes a deposition process, such as plasma-enhanced chemical vapor deposition.

[0079] In this embodiment, the first passivation layer 17 is also located on the side of the touch line away from the substrate 1.

[0080] refer to Figure 9 A second planarization layer 5 is formed on the side of the first passivation layer 17 opposite to the substrate 1, and a first via 51 is formed in the second planarization layer 5. The first via 51 exposes a portion of the surface of the first passivation layer 17.

[0081] In one embodiment, the process of forming the second planarization layer 5 on the side of the first passivation layer 17 away from the substrate 1 includes a spin coating process.

[0082] In one embodiment, the process of forming the first via 51 includes a dry etching process or a wet etching process.

[0083] For a description of the thickness and material of the second planarization layer 5, please refer to the description in the foregoing embodiments.

[0084] refer to Figure 10 A common electrode 11 is formed on the side of the second planar layer 5 away from the substrate 1.

[0085] In one embodiment, the common electrode 11 can be an indium tin oxide (ITO) electrode or an indium zinc oxide (IZO) electrode.

[0086] In this embodiment, a portion of the common electrode 11 is reused by the touch electrode as a touch sensor, which divides the originally continuous common electrode 11 into multiple independent touch electrode blocks.

[0087] In one embodiment, a portion of the common electrode 11 is electrically connected to the touch line through a contact hole in the second planarization layer 5. The contact hole (not shown) and the first via 51 are spaced apart.

[0088] refer to Figure 11 A fourth passivation layer 10 is formed on the side of the common electrode 11 and the second planarization layer 5 away from the substrate 1, and a sixth via 101 and a third via 171 are formed in the fourth passivation layer 10 and the first passivation layer 17.

[0089] In this embodiment, while the sixth via 101 is formed in the fourth passivation layer 10, the third via 171 is formed in the first passivation layer 17. Using the same photomask to etch both the fourth passivation layer 10 and the first passivation layer 17 in one step eliminates the need for additional photomasks, simplifying the process, saving costs, and improving process efficiency.

[0090] In other embodiments, a third via 171 may be formed first in the first passivation layer 17, and then a sixth via 101 may be formed in the fourth passivation layer 10.

[0091] In this embodiment, the edges of the orthographic projection of the third via 171 on the substrate 1 and the orthographic projection of the sixth via 101 on the substrate 1 coincide.

[0092] In one embodiment, the process of forming a fourth passivation layer 10 on the side of the common electrode 11 and the second planarization layer 5 away from the substrate 1 includes a deposition process, such as a plasma-enhanced chemical vapor deposition process.

[0093] refer to Figure 12 A pixel electrode 6 is formed on the side of the fourth passivation layer 10 that is away from the substrate 1.

[0094] The pixel electrode 6 is electrically connected to a bridging electrode 41 through the sixth via 10, the first via 51, and the third via 171 in sequence. Specifically, the pixel electrode 6 extends from the surface of the fourth passivation layer 10 away from the substrate 1 into the sixth via 10, the first via 51, and the third via 171.

[0095] In one specific embodiment, the pixel electrode 6 is located on the surface of the fourth passivation layer 10 facing away from the substrate 1, the sidewall of the sixth via 10, the sidewall of the first via 51, the sidewall of the third via 171, and the surface of the bridging electrode 41 facing away from the substrate 1. The pixel electrode 6 is electrically connected to the bridging electrode 41.

[0096] For a description of the material and thickness of the pixel electrode 6, please refer to the description in the foregoing embodiments.

[0097] Another embodiment of the present invention provides a display panel including the array substrate described above.

[0098] In one embodiment, the display panel includes a liquid crystal display (LCD) panel. The LCD panel further includes a cell substrate disposed opposite to the array substrate, and a liquid crystal layer located between the cell substrate and the array substrate.

[0099] Another embodiment of the present invention provides a display device including the display panel described above. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this embodiment does not limit the scope of the application.

[0100] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. An array substrate, characterized in that, include: A substrate and a driving circuit layer, a first planarization layer, a bridging electrode layer, a second planarization layer and an array of pixel electrodes are sequentially stacked on the substrate; The driving circuit layer includes an array of thin-film transistors, and the bridging electrode layer includes an array of bridging electrodes. The pixel electrode is electrically connected to a bridging electrode through a first via of the second planarization layer, and the bridging electrode is electrically connected to a first electrode of the thin-film transistor through a second via of the first planarization layer. The first via and the second via are spaced apart in a plane parallel to the substrate.

2. The array substrate according to claim 1, characterized in that, Also includes: A first passivation layer is located between the bridging electrode layer and the second planarization layer. The first passivation layer includes a third via communicating with the first via. The pixel electrode is electrically connected to a bridging electrode through the first via and the third via.

3. The array substrate according to claim 1, characterized in that, Also includes: A second passivation layer is located between the bridging electrode layer and the first planarization layer. The second passivation layer includes a fourth via communicating with the second via. The bridging electrode is electrically connected to the first electrode of the thin-film transistor through the fourth via and the second via.

4. The array substrate according to claim 1, characterized in that, The driving circuit layer includes a third passivation layer located between the first electrode of the thin-film transistor and the first planarization layer. The third passivation layer includes a fifth via communicating with the second via. The bridging electrode is electrically connected to the first electrode of the thin-film transistor through the second via and the fifth via.

5. The array substrate according to claim 1, characterized in that, Also includes: A fourth passivation layer is located between the second planarization layer and the pixel electrode. The fourth passivation layer includes a sixth via that communicates with the first via. The pixel electrode is electrically connected to a bridging electrode through the sixth via and the first via.

6. The array substrate according to claim 5, characterized in that, Also includes: A common electrode is located between the second planarization layer and the fourth passivation layer, which is located between the pixel electrode and the common electrode.

7. The array substrate according to claim 1, characterized in that, Also includes: The touch line has bridging electrodes that are on the same layer as the touch line and spaced apart from it.

8. A method for fabricating an array substrate, characterized in that, include: A driving circuit layer, a first planarization layer, a bridging electrode layer, a second planarization layer, and an array of pixel electrodes are sequentially formed on the substrate. The driving circuit layer includes an array of thin-film transistors, and the bridging electrode layer includes an array of bridging electrodes. The pixel electrode is electrically connected to a bridging electrode through a first via of the second planarization layer, and the bridging electrode is electrically connected to a first electrode of the thin-film transistor through a second via of the first planarization layer. The first via and the second via are spaced apart in a plane parallel to the substrate.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 7.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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