Integrated circuit and method of operating the same

Abstract

An integrated circuit and an operating method thereof. The integrated circuit includes a reinforcement circuit coupled between a first bundle node and a second bundle node. A voltage on each bundle node is maintained with a bundle circuit. The reinforcement circuit includes a first type transistor in a first type active region structure and a second type transistor in a second type active region structure. The first type transistor has a source terminal connected to a first power line, a drain terminal connected to the first bundle node, and a gate terminal connected to the second bundle node. The second type transistor has a source terminal connected to a second power line, a drain terminal connected to the second bundle node, and a gate terminal connected to the first bundle node.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit and a method for operating the integrated circuit. Background Technology

[0002] The recent trend of miniaturization in integrated circuits (ICs) has resulted in smaller devices that consume less power but provide more functionality at higher speeds. Miniaturization also leads to more stringent design and manufacturing specifications, as well as reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout patterns for ICs, while ensuring compliance with standard cell layout design and manufacturing specifications. Summary of the Invention

[0003] This disclosure includes an integrated circuit comprising: a first power line for maintaining a first power supply voltage; a second power line for maintaining a second power supply voltage; a first-type bonding transistor having a source terminal connected to the first power line, wherein the first-type bonding transistor is maintained in an on state; a first bonding node connected to the drain terminal of the first-type bonding transistor; a second-type bonding transistor having a source terminal connected to the second power line, wherein the second-type bonding transistor is maintained in an on state; a second bonding node connected to the drain terminal of the second-type bonding transistor; a first-type active region structure extending in a first direction; a second-type active region structure extending in the first direction; and a plurality of enhancement circuits, wherein each of these enhancement circuits includes a first-type transistor in the first-type active region structure and a second-type transistor in the second-type active region structure, wherein the first-type transistor has a source terminal connected to the first power line, a drain terminal connected to the first bonding node, and a gate terminal connected to the second bonding node, and wherein the second-type transistor has a source terminal connected to the second power line, a drain terminal connected to the second bonding node, and a gate terminal connected to the first bonding node.

[0004] This disclosure includes a method of operating an integrated circuit, comprising: maintaining a channel of a first bonded transistor in an ON state while maintaining the source terminal of the first bonded transistor at a first power supply voltage; applying an output voltage from the drain terminal of the first bonded transistor to a first bonded node; maintaining a channel of a second bonded transistor in an ON state while maintaining the source terminal of the second bonded transistor at a second power supply voltage; applying an output voltage from the drain terminal of the second bonded transistor to a second bonded node; maintaining the source terminal of a first type transistor at the first power supply voltage; maintaining the source terminal of a second type transistor at the second power supply voltage; applying a first voltage at the first bonded node to the gate terminal of the second type transistor; applying an output voltage from the drain terminal of the second type transistor to the second bonded node; applying a second voltage at the second bonded node to the gate terminal of the first type transistor; and applying an output voltage from the drain terminal of the first type transistor to the first bonded node.

[0005] This disclosure includes an integrated circuit comprising: a first bundling node for maintaining a first voltage thereon at a first logic level; a second bundling node for maintaining a second voltage thereon at a second logic level different from the first logic level; a first type active region structure extending in a first direction, having a first isolation region and a second isolation region; a second type active region structure extending in the first direction, having a third isolation region and a fourth isolation region; a first type transistor in the first type active region structure between the first and second isolation regions, the first type transistor having a source terminal connected to a first power line for maintaining a first power supply voltage; a second type transistor in the second type active region structure between the third and fourth isolation regions, the second type transistor having a source terminal connected to a second power line for maintaining a second power supply voltage; a drain terminal of the first type transistor connected to the first bundling node; a gate terminal of the second type transistor also connected to the first bundling node; a drain terminal of the second type transistor connected to the second bundling node; and a gate terminal of the first type transistor also connected to the second bundling node. Attached Figure Description

[0006] When together with the accompanying Figure 1 The best understanding of the features disclosed herein can be obtained by reading the following detailed description. It should be noted that, according to standard industrial practice, the features are not drawn to scale. In fact, the dimensions of each feature may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figure 1 This is a schematic diagram of an integrated circuit according to some embodiments, the integrated circuit including reinforcement circuitry coupled to two bundled nodes maintained at different logic levels;

[0008] Figure 2This is a schematic diagram of an integrated circuit according to some embodiments, which has three bundled nodes coupled to various reinforcement circuits;

[0009] Figure 3 This is a schematic diagram of an integrated circuit according to some embodiments, which has a pull-up circuit coupled to two bundled nodes to set the voltage on each of the two bundled nodes to the corresponding logic HIGH voltage.

[0010] Figure 4 This is a schematic diagram of an integrated circuit according to some embodiments, which has a pull-up circuit coupled to two bundled nodes to set the voltage on each of the two bundled nodes to the corresponding logic HIGH voltage.

[0011] Figure 5 and Figures 6A to 6B These are schematic diagrams of integrated circuits according to some embodiments, which have three bundled nodes coupled to various reinforcement circuits;

[0012] Figures 7A to 7B and Figures 8A to 8B These are schematic diagrams of integrated circuits according to some embodiments, which have three bundled nodes coupled to various reinforcement circuits;

[0013] Figures 9A to 9D This is a flowchart of a method for operating an integrated circuit according to some embodiments;

[0014] Figure 10 This is a layout diagram of a circuit unit implemented using reinforcement circuitry 150 according to some embodiments;

[0015] Figures 11A to 11D According to some embodiments Figure 10 The cross-sectional view of the circuit unit along each cut plane;

[0016] Figure 12 This is a layout diagram of a circuit unit implemented using two enhancement circuits according to some embodiments;

[0017] Figure 13 This is a layout diagram of a circuit unit implemented using a reinforcement circuit 150 connected to three bundled nodes, according to some embodiments.

[0018] Figure 14 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments;

[0019] Figure 15 This is a block diagram of an electronic design automation (EDA) system according to some embodiments;

[0020] Figure 16This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments.

[0021] [Symbol Explanation]

[0022] 20: Power lines

[0023] 20M: Power line

[0024] 30: Substrate

[0025] 40: Power lines

[0026] 50n: NMOS active region structure

[0027] 50p: PMOS active region structure

[0028] 71: Driver

[0029] 75: Circuit Node

[0030] 82: Word line driver

[0031] 84: Memory Unit

[0032] 86: Control Circuit

[0033] 88: I / O circuits

[0034] 101: Vertical unit boundary

[0035] 102: Horizontal element boundary

[0036] 108: Horizontal element boundary

[0037] 109: Vertical unit boundary

[0038] 110: Pull-up circuit

[0039] 111: PMOS transistor

[0040] 112: NMOS transistor

[0041] 113: NMOS transistor

[0042] 118: Bound Node

[0043] 120: Pull-down circuit

[0044] 121: NMOS transistor

[0045] 122: PMOS transistor

[0046] 123: PMOS transistor

[0047] 128: Bound Nodes

[0048] 130: Pull-up circuit

[0049] 131: PMOS transistor

[0050] 132: NMOS transistor

[0051] 133: NMOS transistor

[0052] 138: Bound Node

[0053] 150: Enhanced Circuit

[0054] 150A: Enhanced Circuit

[0055] 150B: Enhanced Circuitry

[0056] 150C: Enhanced Circuitry

[0057] 150D: Enhanced Circuitry

[0058] 150Z: Enhanced Circuitry

[0059] 151: PMOS transistor

[0060] 152: NMOS transistor

[0061] 160: Enhanced Circuit

[0062] 160A: Enhanced Circuit

[0063] 160B: Enhanced Circuit

[0064] 160C: Enhanced Circuitry

[0065] 160D: Enhanced Circuitry

[0066] 160Z: Enhanced Circuitry

[0067] 161: PMOS transistor

[0068] 162: NMOS transistor

[0069] 311: PMOS transistor

[0070] 312: NMOS transistor

[0071] 322: NMOS transistor

[0072] 323: NMOS transistor

[0073] 331: PMOS transistor

[0074] 332: NMOS transistor

[0075] 340: Pull-up circuit

[0076] 340M: Combined bundled circuit

[0077] 550: Enhanced circuitry

[0078] 550A: Enhanced Circuitry

[0079] 550B: Enhanced Circuitry

[0080] 550C: Enhanced Circuitry

[0081] 550D: Enhanced Circuitry

[0082] 550Z: Enhanced Circuitry

[0083] 900A: Method

[0084] 900B: Method

[0085] 900C: Method

[0086] 900D: Method

[0087] 911: Operation

[0088] 912: Operation

[0089] 921: Operation

[0090] 922: Operation

[0091] 931: Operation

[0092] 932: Operation

[0093] 933: Operation

[0094] 941: Operation

[0095] 942: Operation

[0096] 943: Operation

[0097] 951B: Operation

[0098] 952B: Operation

[0099] 961B: Operation

[0100] 961D: Operation

[0101] 962B: Operation

[0102] 963B: Operation

[0103] 963D: Operation

[0104] 971C: Operation

[0105] 972C: Operation

[0106] 972D: Operation

[0107] 973C: Operation

[0108] 1000: Circuit unit

[0109] 1200: Circuit Unit

[0110] 1300: Circuit Unit

[0111] 1400: Method

[0112] 1410: Operation

[0113] 1420: Operation

[0114] 1430: Operation

[0115] 1442: Operation

[0116] 1444: Operation

[0117] 1452: Operation

[0118] 1454: Operation

[0119] 1462: Operation

[0120] 1464: Operation

[0121] 1500: Electronic Design Automation (EDA) System

[0122] 1502: Hardware Processor

[0123] 1504: Non-transitory computer-readable storage media

[0124] 1506: Computer program code

[0125] 1507: Library

[0126] 1508: Bus

[0127] 1509: Layout Diagram

[0128] 1510: I / O Interface

[0129] 1512: Network Interface

[0130] 1514: Network

[0131] 1542: UI

[0132] 1600: Manufacturing System

[0133] 1620: Design Studio

[0134] 1622: IC Design Layout Diagram

[0135] 1630: Shelter Room

[0136] 1632: Masking Data Preparation

[0137] 1644: Mask manufacturing

[0138] 1645: Mask

[0139] 1650: IC manufacturer / producer (wafer fab)

[0140] 1652: Manufacturing tools

[0141] 1653: Semiconductor wafer

[0142] 1660: IC device

[0143] AA': Cutting plane

[0144] BB': Cutting plane

[0145] CC': Cutting plane

[0146] DD': Cutting plane

[0147] d151: Terminal conductor

[0148] d151AB: Terminal conductor

[0149] d152: Terminal conductor

[0150] d152A: Terminal conductor

[0151] d152B: Terminal conductor

[0152] d162: Terminal conductor

[0153] g101: Dummy gate conductor

[0154] g109: Dummy gate conductor

[0155] g151: Gate conductor

[0156] g151A: Gate conductor

[0157] g151B: Gate conductor

[0158] g152: Gate conductor

[0159] g152B: Gate conductor

[0160] h118: Horizontal conductor

[0161] h128: Horizontal conductor

[0162] h138: Horizontal conductor

[0163] h148: Horizontal conductor

[0164] i101n: Border Segregation Zone

[0165] i101p: Border Segregation Zone

[0166] i109n: Border Segregation Zone

[0167] i109p: Border Segregation Zone

[0168] ILD0: Interlayer Dielectric

[0169] M0: Metal layer

[0170] s151: Terminal conductor

[0171] S151A: Terminal Conductor

[0172] S151B: Terminal Conductor

[0173] S152: Terminal conductor

[0174] s162: Terminal conductor

[0175] VD: Through-hole connector

[0176] VG: Through-hole connector Detailed Implementation

[0177] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of elements, values, operations, materials, arrangements, or the like are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Other elements, values, operations, materials, arrangements, or the like are contemplated. For example, the following description of forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Additionally, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0178] In addition, for ease of description, this document uses spatial relative terms (such as "below," "under," "lower part," "above," "upper part," and the like) to describe the relationship between one element or feature shown in the figures and another element or feature. Besides the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0179] In some embodiments, the integrated circuit includes a first bundled node maintained at a logic HIGH voltage using a pull-up circuit and a second bundled node maintained at a logic LOW voltage using a pull-down circuit. One or more reinforcement circuits are coupled between the first and second bundled nodes to reduce the impact of stray capacitive coupling from other circuit portions on the parasitic voltages on the first and second bundled nodes.

[0180] In some embodiments, the enhancement circuit coupled between the first and second bundled nodes includes a PMOS transistor and an NMOS transistor. The PMOS transistor has a source terminal connected to a first power line, a drain terminal connected to the first bundled node, and a gate terminal connected to the second bundled node. The NMOS transistor has a source terminal connected to a second power line, a drain terminal connected to the second bundled node, and a gate terminal connected to the first bundled node.

[0181] In some embodiments, one or more reinforcement circuits are implemented within reinforcement circuit cells. During the integrated circuit layout process, one or more reinforcement circuit cells are placed in unoccupied areas of the circuit layout. Therefore, the stability of the logic HIGH voltage on the first bundled node and the stability of the logic LOW voltage on the second bundled node are improved without increasing the area used by the integrated circuit.

[0182] Figure 1 This is a schematic diagram of an integrated circuit according to some embodiments, which includes reinforcement circuitry coupled to two bundled nodes maintained at different logic levels. Figure 1 In the circuit diagram, a voltage representing logic HIGH is applied to bundle node 118 by pull-up circuit 110, and bundle node 118 is maintained at logic HIGH. A voltage representing logic LOW is applied to bundle node 128 by pull-down circuit 120, and bundle node 128 is maintained at logic LOW. Exemplary embodiments of pull-up circuit 110 and pull-down circuit 120 are illustrated in the circuit diagram. Figure 1 The illustration is shown in the figure. In some embodiments, the binding node 118 is a first conductive rail that connects one or more nodes together. In some embodiments, the binding node 128 is a second conductive rail that connects one or more nodes together.

[0183] Both binding nodes 118 and 128 are connected to each of reinforcement circuits 150A, 150B, 150C, and 150D. An exemplary embodiment of reinforcement circuits 150A, 150B, 150C, or 150D serves as reinforcement circuit 150 in... Figure 1 The illustration shows that reinforcement circuits 150A, 150B, 150C, and 150D further facilitate maintaining the voltage representing logic HIGH at bundle node 118 and the voltage representing logic LOW at bundle node 128. Because bundle nodes 118 and 128 are coupled to reinforcement circuits 150A, 150B, 150C, and 150D, the voltages at bundle nodes 118 and 128 are less affected by voltage changes at other circuit nodes, such as circuit node 75 driven by driver 71, due to stray capacitive coupling.

[0184] exist Figure 1 In this circuit, pull-up circuit 110 includes a PMOS transistor 111 and an NMOS transistor 112. The source terminal of PMOS transistor 111 is connected to a high supply voltage VDD, while the source terminal of NMOS transistor 112 is connected to a low supply voltage VSS. The gate terminals of both PMOS transistor 111 and NMOS transistor 112 are connected to the drain terminal of NMOS transistor 112. PMOS transistor 111 acts as a tying transistor. During operation, PMOS transistor 111 remains in the ON state, and the voltage at the drain terminal of PMOS transistor 111 is maintained at a level close to the high supply voltage VDD. Therefore, the voltage representing logic HIGH is applied to the tying node 118 by pull-up circuit 110. NMOS transistor 112 acts as a holding transistor. During operation, the voltage at the drain terminal of NMOS transistor 112 is maintained at the voltage level that drives PMOS transistor 111 into the ON state.

[0185] In some embodiments, the pull-up circuit 110 may also include an NMOS transistor 113. Figure 1 In this circuit, the gate, source, and drain terminals of NMOS transistor 113 are all connected to the drain terminal of NMOS transistor 112. Due to NMOS transistor 113, an additional capacitive load is added to the drain terminal of NMOS transistor 112. In some alternative embodiments, pull-up circuit 110 does not include NMOS transistor 113.

[0186] exist Figure 1 In this circuit, pull-down circuit 120 includes an NMOS transistor 121 and a PMOS transistor 122. The source terminal of NMOS transistor 121 is connected to a low supply voltage VSS, while the source terminal of PMOS transistor 122 is connected to a high supply voltage VDD. The gate terminals of both NMOS transistor 121 and PMOS transistor 122 are connected to the drain terminal of PMOS transistor 122. NMOS transistor 121 acts as a tying transistor. During operation, NMOS transistor 121 remains in the ON state, and the voltage at the drain terminal of NMOS transistor 121 is maintained at a level close to the low supply voltage VSS. Therefore, the voltage representing logic LOW is applied to the tying node 128 by pull-down circuit 120. PMOS transistor 122 acts as a holding transistor. During operation, the voltage at the drain terminal of PMOS transistor 122 is maintained at the voltage level that drives NMOS transistor 121 into the ON state.

[0187] In some embodiments, the pull-down circuit 120 may also include a PMOS transistor 123, depending on the situation. Figure 1 In this configuration, the gate, source, and drain terminals of PMOS transistor 123 are all connected to the drain terminal of PMOS transistor 122. Due to PMOS transistor 123, an additional capacitive load is added at the drain terminal of PMOS transistor 122. In some alternative embodiments, PMOS transistor 123 is not included in the pull-down circuit 120.

[0188] exist Figure 1 In this circuit, the enhancement circuit 150 includes a PMOS transistor 151 and an NMOS transistor 152. The source terminal of the PMOS transistor 151 is connected to a high power supply voltage VDD, while the source terminal of the NMOS transistor 152 is connected to a low power supply voltage VSS. The drain terminal of the PMOS transistor 151 and the gate terminal of the NMOS transistor 152 are connected to a bonding node 118. The gate terminal of the PMOS transistor 151 and the drain terminal of the NMOS transistor 152 are connected to a bonding node 128.

[0189] During operation, each of the PMOS transistor 151 and NMOS transistor 152 is maintained in the ON state by a voltage applied to its corresponding gate. Specifically, a voltage at the bundle node 128, representing logic LOW, is applied to the gate of the PMOS transistor 151, driving it into the ON state. Because the PMOS transistor 151 is ON, its channel maintains high conductivity, which further drives the voltage at the bundle node 118 toward the high supply voltage VDD, and further maintains the voltage at the bundle node 118 to represent logic HIGH. Similarly, a voltage at the bundle node 118, representing logic HIGH, is applied to the gate of the NMOS transistor 152, driving it into the ON state. Because the NMOS transistor 152 is ON, its channel maintains high conductivity, which further drives the voltage at the bundle node 128 toward the low supply voltage VSS, and further maintains the voltage at the bundle node 128 to represent logic LOW.

[0190] exist Figure 1 In the integrated circuit, the logic HIGH voltage level and the logic LOW voltage level are respectively provided on the bundled node 118 and the bundled node 128. Figure 1 The exemplary integrated circuit includes an array of memory cells 84 (such as SRAM cells) and word line drivers 82. In some embodiments, the array of memory cells 84 is arranged in a two-dimensional matrix. A column of memory cells in the two-dimensional matrix is ​​selected for reading or writing using one or more selection signals generated from one of the word line drivers 82. The array of memory cells 84 and the word line drivers 82 are implemented in the same power domain powered by a high supply voltage VDD and a low supply voltage VSS. In the array of memory cells 84 and the word line drivers 82, each circuit node conductively connected to the bundle node 118 is set to a logic HIGH voltage level, and each circuit node conductively connected to the bundle node 128 is set to a logic LOW voltage level.

[0191] In some alternative embodiments, some circuit elements in the integrated circuit are powered in a first power domain, while some other circuit elements in the integrated circuit are powered in a second power domain. For example, in... Figure 2 In the integrated circuit shown, the first power domain is powered by a high supply voltage VDDM and a low supply voltage VSS, while the second power domain is powered by a high supply voltage VDDP and a low supply voltage VSS. The high supply voltage VDDM and the high supply voltage VDDP are maintained at different voltage levels.

[0192] Figure 2This is a schematic diagram of an integrated circuit according to some embodiments, which has three bundled nodes coupled to various reinforcement circuits. Figure 2 In the circuit diagram, when the voltage on bundled node 118 is driven high by pull-up circuit 110 towards a high supply voltage VDDM, bundled node 118 maintains a voltage representing logic HIGH in the first power domain. When the voltage on bundled node 128 is driven low by pull-down circuit 120 towards a low supply voltage VSS, bundled node 128 maintains a voltage representing logic LOW in both the first and second power domains. When the voltage on bundled node 138 is driven high by pull-up circuit 130 towards a high supply voltage VDDP, bundled node 138 maintains a voltage representing logic HIGH in the second power domain. Exemplary embodiments of pull-up circuit 110 and pull-up circuit 130 are illustrated in the circuit diagram. Figure 2 The illustration is shown in the figure. An exemplary embodiment of the pull-low circuit 120 has been shown in the figure. Figure 1 The illustration shows that the circuit diagram for pull-down circuit 120 is not shown in the figure. Figure 2 Reproduced in the middle. In some embodiments, the binding node 138 is a third conductive rail that connects one or more nodes together.

[0193] exist Figure 2 In this configuration, each of reinforcement circuits 150A-150D and 150Z is connected to bundled nodes 118 and 128, and each of reinforcement circuits 160A-160D and 160Z is connected to bundled nodes 138 and 128. Each of reinforcement circuits 150A-150D and 150Z facilitates maintaining the voltage on bundled node 118 (for representing HIGH logic in the first power domain) and maintaining the voltage on bundled node 128 (for representing LOW logic in the first power domain). Each of reinforcement circuits 160A-160D and 160Z facilitates maintaining the voltage on bundled node 138 (for representing HIGH logic in the second power domain) and maintaining the voltage on bundled node 128 (for representing LOW logic in the second power domain). An exemplary embodiment of one of reinforcement circuits 150A-150D and 150Z is described below. Figure 2 The illustration shows a reinforcement circuit 150, and an exemplary embodiment of one of the reinforcement circuits 160A-160D and 160Z is shown in the figure. Figure 2 The illustration shows the reinforcement circuit 160.

[0194] Figure 2The exemplary integrated circuit includes an array of memory cells 84 (such as SRAM cells) and a word line driver 82. In some embodiments, the array of memory cells 84 is arranged in a two-dimensional matrix. The array of memory cells 84 and the word line driver 82 are implemented in a first power domain powered by a high supply voltage VDDM and a low supply voltage VSS. In the array of memory cells 84 and the word line driver 82, each circuit node conductively connected to the bundle node 118 is set to a logic HIGH voltage level in the first power domain, and each circuit node conductively connected to the bundle node 128 is set to a logic LOW voltage level in the first power domain.

[0195] Figure 2 The exemplary integrated circuit also includes an array of I / O circuitry 88 and control circuitry 86. The I / O circuitry in the array of I / O circuitry 88 is configured to read bit signals on bit lines or write bit signals to bit lines, and the bit lines are connected to memory cells. In some embodiments, control circuitry 86 provides column addresses, row addresses, clock signals, and other signals to facilitate writing data to or reading data from the array of memory cells 84. The array of I / O circuitry 88 and control circuitry 86 are implemented in a second power domain powered by a high supply voltage VDDP and a low supply voltage VSS. In the array of I / O circuitry 88 and control circuitry 86, each circuit node conductively connected to bundle node 138 is set to a logic HIGH voltage level in the second power domain, and each circuit node conductively connected to bundle node 128 is set to a logic LOW voltage level in the second power domain.

[0196] exist Figure 2In this circuit, pull-up circuit 110 includes a PMOS transistor 111 and an NMOS transistor 112. The source terminal of PMOS transistor 111 is connected to a high supply voltage VDDM, while the source terminal of NMOS transistor 112 is connected to a low supply voltage VSS. The gate terminals of both PMOS transistor 111 and NMOS transistor 112 are connected to the drain terminal of NMOS transistor 112. PMOS transistor 111 acts as a tying transistor. During operation, PMOS transistor 111 remains in the ON state, and the voltage at the drain terminal of PMOS transistor 111 is maintained at a level close to the high supply voltage VDDM. Therefore, the voltage representing logic HIGH in the first power domain is applied to the tying node 118 by pull-up circuit 110. NMOS transistor 112 acts as a holding transistor. During operation, the voltage at the drain terminal of NMOS transistor 112 is maintained at the voltage level that drives PMOS transistor 111 into the ON state. In some embodiments, the pull-up circuit 110 may also include an NMOS transistor 113 (that is, in some alternative embodiments, the pull-up circuit 110 does not include an NMOS transistor 113).

[0197] exist Figure 2 In this circuit, pull-up circuit 130 includes a PMOS transistor 131 and an NMOS transistor 132. The source terminal of PMOS transistor 131 is connected to a high supply voltage VDDP, while the source terminal of NMOS transistor 132 is connected to a low supply voltage VSS. The gate terminals of both PMOS transistor 131 and NMOS transistor 132 are connected to the drain terminal of NMOS transistor 132. PMOS transistor 131 functions as a tying transistor. During operation, PMOS transistor 131 remains in the ON state, and the voltage at the drain terminal of PMOS transistor 131 is maintained at a level close to the high supply voltage VDDP. Therefore, the voltage representing logic HIGH in the second power domain is applied to the tying node 138 by pull-up circuit 130. NMOS transistor 132 functions as a holding transistor. During operation, the voltage at the drain terminal of NMOS transistor 132 is maintained at the voltage level that drives PMOS transistor 131 into the ON state. In some embodiments, the pull-up circuit 130 may also include an NMOS transistor 133 (that is, in some alternative embodiments, the pull-up circuit 130 does not include an NMOS transistor 133).

[0198] exist Figure 2In this circuit, the enhancement circuit 150 includes a PMOS transistor 151 and an NMOS transistor 152. The source terminal of the PMOS transistor 151 is connected to a high supply voltage VDDM, while the source terminal of the NMOS transistor 152 is connected to a low supply voltage VSS. The drain terminal of the PMOS transistor 151 and the gate terminal of the NMOS transistor 152 are connected to a bonding node 118. The gate terminal of the PMOS transistor 151 and the drain terminal of the NMOS transistor 152 are connected to a bonding node 128.

[0199] During operation, each of the PMOS transistor 151 and NMOS transistor 152 is maintained in the ON state by a voltage applied to its corresponding gate. Specifically, a voltage is applied to the gate of the PMOS transistor 151 at the bundle node 128, representing logic LOW, thus driving the PMOS transistor 151 into the ON state. Because the PMOS transistor 151 is in the ON state, the channel of the PMOS transistor 151 maintains high conductivity, which further drives the voltage at the bundle node 118 toward the high supply voltage VDDM, and further maintains the voltage at the bundle node 118 at logic HIGH, representing the first power domain. Similarly, a voltage is applied to the gate of the NMOS transistor 152 at the bundle node 118, representing logic HIGH, thus driving the NMOS transistor 152 into the ON state. Because NMOS transistor 152 is in the ON state, the channel of NMOS transistor 152 is maintained at high conductivity, which further drives the voltage on the bundle node 128 toward the low supply voltage VSS, and further maintains the voltage on the bundle node 128 at logic LOW representing the first power domain.

[0200] exist Figure 2 In this circuit, the enhancement circuit 160 includes a PMOS transistor 161 and an NMOS transistor 162. The source terminal of the PMOS transistor 161 is connected to a high supply voltage VDDP, while the source terminal of the NMOS transistor 162 is connected to a low supply voltage VSS. The drain terminal of the PMOS transistor 161 and the gate terminal of the NMOS transistor 162 are connected to a bonding node 138. The gate terminal of the PMOS transistor 161 and the drain terminal of the NMOS transistor 162 are connected to a bonding node 128.

[0201] During operation, each of the PMOS transistor 161 and NMOS transistor 162 is maintained in the ON state by a voltage applied to its corresponding gate. Specifically, a voltage is applied to the gate of the PMOS transistor 161 at the bundle node 128, which represents logic LOW, driving the PMOS transistor 161 into the ON state. Because the PMOS transistor 161 is in the ON state, the channel of the PMOS transistor 161 maintains high conductivity, which further drives the voltage at the bundle node 138 toward the high supply voltage VDDP, and further maintains the voltage at the bundle node 138 at logic HIGH, representing the second power domain. Similarly, a voltage is applied to the gate of the NMOS transistor 162 at the bundle node 138, which represents logic HIGH, driving the NMOS transistor 162 into the ON state. Because NMOS transistor 162 is in the ON state, the channel of NMOS transistor 162 is maintained at high conductivity, which further drives the voltage on the bundle node 128 toward the low supply voltage VSS, and further maintains the voltage on the bundle node 128 at logic LOW representing the second power domain.

[0202] exist Figure 2 In this configuration, pull-up circuits 110 and 130 are correspondingly coupled to bundled nodes 118 and 138, whereby each of bundled nodes 118 and 138 maintains a corresponding logic HIGH voltage in one of the power domains. In some alternative embodiments (such as...) Figures 3 to 5 In the embodiment, a pull-up circuit is coupled to both bundled nodes 118 and 138 to maintain the corresponding logic HIGH voltage on each of bundled nodes 118 and 138.

[0203] Figure 3 This is a schematic diagram of an integrated circuit according to some embodiments, having a pull-up circuit coupled to two bundled nodes to set the voltage on each of the two bundled nodes to a corresponding logic HIGH voltage. Figure 3 In the process, when the pull-down circuit 120 sets the bundled node 128 to a logic LOW voltage, the pull-up circuit 340 sets each of the bundled nodes 118 and 138 to the corresponding logic HIGH voltage. Figure 3 The integrated circuit in the middle is obtained by using a pull-up circuit 340 instead of pull-up circuits 110 and 130. Figure 2 It is derived from the integrated circuits in the original.

[0204] exist Figure 3In this circuit, pull-up circuit 340 includes PMOS transistor 311, PMOS transistor 331, and NMOS transistor 322. In some embodiments, pull-up circuit 340 may also include NMOS transistor 323. The source terminal of PMOS transistor 311 is connected to a high power supply voltage VDDM, the source terminal of PMOS transistor 331 is connected to a high power supply voltage VDDP, and the source terminal of NMOS transistor 322 is connected to a low power supply voltage VSS. The gate terminals of PMOS transistors 311 and 331, and the gate terminal of NMOS transistor 322, are all connected to the drain terminal of NMOS transistor 322.

[0205] The drain of PMOS transistor 311 is connected to bundle node 118, and the drain of PMOS transistor 331 is connected to bundle node 138. During operation, each of PMOS transistors 311 and 331, which serve as bundle transistors, remains in the ON state. The voltage at the drain of PMOS transistor 311 is maintained at a voltage level close to the high supply voltage VDDM, and the voltage at the drain of PMOS transistor 331 is maintained at a voltage level close to the high supply voltage VDDP. Therefore, a voltage representing logic HIGH in the first power domain is applied to bundle node 118, and a voltage representing logic HIGH in the second power domain is applied to bundle node 138.

[0206] Furthermore, during operation, NMOS transistor 322 acts as a holding transistor, and the voltage at the drain terminal of NMOS transistor 322 is maintained at the voltage level that drives PMOS transistors 311 and 331 into the on state. In some embodiments, pull-up circuit 340 may also include NMOS transistor 323. That is, in some alternative embodiments, pull-up circuit 340 does not include NMOS transistor 323. In some alternative embodiments (such as in... Figure 4 In the illustrated embodiment, the pull-up circuit 340 also includes one or more additional NMOS transistors used as enhancement transistors.

[0207] Figure 4 This is a schematic diagram of an integrated circuit according to some embodiments, which has a pull-up circuit coupled to two bundled nodes to set the voltage on each of the two bundled nodes to the corresponding logic HIGH voltage. Figure 4 Integrated circuits in Figure 3This is a modification of the integrated circuit in the original circuit. The modification includes adding NMOS transistors 312 and 332 to the pull-up circuit 340. The source terminals of NMOS transistors 312 and 332 are connected to the low supply voltage VSS. The drain terminals of NMOS transistors 312 and 332 are connected to the drain terminal of NMOS 321 (which is used as a holding transistor). The gate terminal of NMOS transistor 312 is connected to the drain terminal of PMOS transistor 311, and the gate terminal of NMOS transistor 332 is connected to the drain terminal of PMOS transistor 331.

[0208] exist Figure 4 In this configuration, each of NMOS transistors 312 and 332 serves as a power-up transistor. Because the gate of NMOS transistor 312 is connected to the drain of PMOS transistor 311 and maintains a voltage level close to the high supply voltage VDDM at the bonded node 118 (also designated TIEHM), NMOS transistor 312 remains in the on-state. When NMOS transistor 312 remains in the on-state, the conductive connection from the drain of NMOS transistor 312 to the low supply voltage VSS is enhanced, and the conductive connection from the gate of PMOS transistor 311 to the low supply voltage VSS is also enhanced. With the enhanced connectivity between the gate of PMOS transistor 311 and the low supply voltage VSS, the connectivity between the drain of PMOS transistor 311 and the high supply voltage VDDM is improved. Therefore, bonded node 118 becomes less susceptible to parasitic voltages attributable to stray capacitive coupling, and the logic HIGH voltage at bonded node 118 becomes more stable.

[0209] Similarly, because the gate of NMOS transistor 332 is connected to the drain of PMOS transistor 331 and maintains a voltage level close to the high supply voltage VDDP at the bundled node 138 (also labeled TIEHP), NMOS transistor 332 remains in the ON state. When NMOS transistor 332 remains in the ON state, the conductivity from the drain of NMOS transistor 332 to the low supply voltage VSS is enhanced, and the conductivity from the gate of PMOS transistor 331 to the low supply voltage VSS is also enhanced. With the enhanced connectivity between the gate of PMOS transistor 331 and the low supply voltage VSS, the connectivity between the drain of PMOS transistor 331 and the high supply voltage VDDM is improved. Therefore, bundled node 138 becomes less susceptible to parasitic voltages attributable to stray capacitive coupling, and the logic HIGH voltage at bundled node 138 becomes more stable.

[0210] exist Figures 2 to 4In this configuration, each of reinforcement circuits 150A-150D and 150Z is connected to binding nodes 118 and 128, and each of reinforcement circuits 160A-160D and 160Z is connected to binding nodes 138 and 128. In some alternative embodiments (such as in...), Figure 5 and Figures 6A to 6B In the illustrated embodiment, each of the reinforcement circuits is connected to three binding nodes.

[0211] Figure 5 and Figures 6A to 6B These are schematic diagrams of integrated circuits according to some embodiments, these integrated circuits having three bundled nodes coupled to various reinforcement circuits. Figure 5 and Figures 6A to 6B In this circuit, each of the reinforcement circuits 550A to 550D and 550Z is connected to the binding node 118, binding node 128, and binding node 138. Figure 5 and Figures 6A to 6B The integrated circuits in the corresponding section are from Figure 2 and Figures 3 to 4 It is derived from the integrated circuits in [the original text]. Specifically, in [the context of]... Figure 2 and Figures 3 to 4 In the middle, two enhancement circuits (such as 150A and 160A) utilize corresponding ground Figure 5 and Figures 6A to 6B One of the enhanced circuits, 550A, is replaced.

[0212] exist Figure 5 and Figures 6A to 6B In this embodiment, each of the enhancement circuits 550A-550D and 550Z promotes the maintenance of the voltage on the bundled node 118 (for representing HIGH logic in the first power domain), the maintenance of the voltage on the bundled node 128 (for representing LOW logic in both the first and second power domains), and the maintenance of the voltage on the bundled node 138 (for representing HIGH logic in the second power domain). An exemplary embodiment of one of the enhancement circuits 550A-550D and 550Z serves as the enhancement circuit 550 in... Figure 5 and Figures 6A to 6B The illustration is shown in the illustration.

[0213] exist Figure 5 and Figures 6A to 6BIn this circuit, enhancement circuit 550 includes PMOS transistor 151, PMOS transistor 161, and NMOS transistor 152. The source terminal of PMOS transistor 151 is connected to a high supply voltage VDDM, the source terminal of PMOS transistor 161 is connected to a high supply voltage VDDP, and the source terminal of NMOS transistor 152 is connected to a low supply voltage VSS. The drain terminal of PMOS transistor 151 and the gate terminal of NMOS transistor 152 are connected to bonded node 118. The drain terminal of PMOS transistor 161 is connected to bonded node 138. The gate terminals of PMOS transistors 151 and 161 and the drain terminal of NMOS transistor 152 are connected to bonded node 128.

[0214] During operation, each of PMOS transistors 151 and 161 and NMOS transistor 152 is maintained in the ON state by a voltage applied to its corresponding gate. Specifically, a voltage is applied to the gate of PMOS transistor 151 at the bundle node 128, which represents logic LOW, thereby driving PMOS transistor 151 into the ON state. A voltage is also applied to the gate of PMOS transistor 161 at the bundle node 128, which represents logic HIGH in the first power domain, at the bundle node 118, thereby driving NMOS transistor 152 into the ON state.

[0215] Because PMOS transistor 151 is in the ON state, the channel of PMOS transistor 151 is maintained at high conductivity, which drives the voltage on the bundle node 118 toward the high supply voltage VDDM, and further maintains the voltage on the bundle node 118 at logic HIGH representing the first power domain.

[0216] Because PMOS transistor 161 is in the ON state, the channel of PMOS transistor 161 is maintained at high conductivity, which drives the voltage on the bundle node 138 toward the high supply voltage VDDP, and further maintains the voltage on the bundle node 138 at logic HIGH representing the second power domain.

[0217] Because NMOS transistor 152 remains in the ON state, the voltage at the gate of PMOS transistor 151 and the voltage at the gate of PMOS transistor 161 decrease towards the low power supply voltage VSS, which further drives each of PMOS transistors 151 and 161 into the ON state.

[0218] In such Figures 3 to 4 and Figures 6A to 6BIn the integrated circuit shown, each of bundled nodes 118 and 138 is set to a corresponding logic HIGH voltage using a pull-up circuit 340, but bundled node 128 is set to a logic LOW voltage using a pull-down circuit 120. In some alternative embodiments, such as Figures 7A to 7B and Figures 8A to 8B As shown, the logic HIGH voltage on bundled nodes 118 and 138 and the logic LOW voltage on bundled node 128 are maintained using a combined bundled circuit modified from pull-up circuit 340.

[0219] Figures 7A to 7B and Figures 8A to 8B These are schematic diagrams of integrated circuits according to some embodiments, which have three bundled nodes coupled to various reinforcement circuits. Figures 7A to 7B and Figures 8A to 8B The integrated circuits in the corresponding section are from Figures 3 to 4 and Figures 6A to 6B The integrated circuit in the pull-up circuit 340 is modified. The modification includes connecting the drain terminal of the NMOS transistor 322 in the pull-up circuit 340 to the bundled node 128. The modification also includes removing the pull-down circuit 120. With this modification, the pull-up circuit 340 becomes a combined bundled circuit 340M. In addition to setting the logic HIGH voltage on bundled nodes 118 and 138, the combined bundled circuit 340M is also used to set the logic LOW voltage on bundled node 128. That is, the combined bundled circuit 340M is used to perform the functions previously performed by… Figures 3 to 4 The pull-down circuit 120 and Figures 6A to 6B The pull-up circuit 340 in the middle performs the function.

[0220] Figures 9A to 9D These are corresponding flowcharts of methods 900A to 900D for operating integrated circuits according to some embodiments. Figures 9A to 9D The sequence of operations described in methods 900A to 900D is for illustrative purposes only; the operation of each of methods 900A to 900D can be performed in a different manner. Figures 9A to 9D The sequence of actions described herein will be executed. It will be understood that additional operations may be available... Figures 9A to 9D The methods described herein are performed before, during, and / or after 900A–900D, and some other processes may be described only briefly in this document.

[0221] like Figure 9A As shown, method 900A includes operations 911-912, 921-922, 931, 941-943, and 932-933.

[0222] In operation 911 of method 900A, the channel of the first bonded transistor remains in the ON state, while the source terminal of the first bonded transistor is maintained at the first supply voltage. In operation 912 of method 900A, the output voltage from the drain terminal of the first bonded transistor is applied to the first bonded node. Figure 1 and Figure 5 In an exemplary embodiment, the source terminal of PMOS transistor 111 is connected to a high power supply voltage VDD, and a voltage at the drain terminal of PMOS transistor 111 is applied to the bundled node 118, while PMOS transistor 111 remains in the on state. Figure 3 and Figures 7A to 7B In an exemplary embodiment, the source terminal of the PMOS transistor 311 is connected to a high power supply voltage VDD, and the voltage at the drain terminal of the PMOS transistor 311 is applied to the bundle node 118 while the PMOS transistor 311 remains in the on state.

[0223] In operation 921 of method 900A, the channel of the second bonded transistor remains in the ON state, while the source terminal of the second bonded transistor is maintained at the second supply voltage. In operation 922 of method 900A, the output voltage from the drain terminal of the second bonded transistor is applied to the second bonded node. Figure 1 In an exemplary embodiment, the source terminal of NMOS transistor 121 is connected to a low supply voltage VSS, and a voltage at the drain terminal of NMOS transistor 121 is applied to the bundled node 128 while NMOS transistor 121 remains in the on state. Figures 7A to 7B In an exemplary embodiment, the source terminal of the NMOS transistor 322 is connected to a low power supply voltage VSS, and the voltage at the drain terminal of the NMOS transistor 322 is applied to the bundle node 128 while the NMOS transistor 322 remains in the on state.

[0224] In operation 931 of method 900A, the source terminal of the first type of transistor is maintained at the first power supply voltage. In operation 941 of method 900A, the source terminal of the second type of transistor is maintained at the second power supply voltage. Figure 1 , Figure 3 ,and Figure 5 In an exemplary embodiment, the source terminal of PMOS transistor 151 is connected to a high power supply voltage VDD or VDDM, and the source terminal of NMOS transistor 152 is connected to a low power supply voltage VSS.

[0225] In operation 942 of method 900A, a first voltage on the first bundled node is applied to the gate terminal of the second type transistor. In operation 943 of method 900A, an output voltage from the drain terminal of the second type transistor is applied to the second bundled node. Figure 1 , Figure 3 ,and Figure 5 In an exemplary embodiment, a voltage on the bundled node 118 is applied to the gate terminal of the NMOS transistor 152, and an output voltage from the drain terminal of the NMOS transistor 152 is applied to the bundled node 128.

[0226] In operation 932 of method 900A, a second voltage on the second bundled node is applied to the gate terminal of the first type transistor. In operation 933 of method 900A, an output voltage from the drain terminal of the first type transistor is applied to the first bundled node. Figure 1 , Figure 3 ,and Figure 5 In an exemplary embodiment, a voltage on the bundled node 128 is applied to the gate terminal of the PMOS transistor 151, and an output voltage from the drain terminal of the PMOS transistor 151 is applied to the bundled node 118.

[0227] exist Figure 9B In this method, method 900B includes all operations of method 900A (i.e., operations 911-912, 921-922, 931, 941-943, and 932-933), and also includes operations 951B-952B and 961B-963B.

[0228] In operation 951B of method 900B, the channel of the third bonded transistor is maintained in the ON state, while the source terminal of the third bonded transistor is maintained at the third supply voltage. In operation 952B of method 900B, the output voltage from the drain terminal of the third bonded transistor is applied to the third bonded node. Figure 3 and Figures 7A to 7B In an exemplary embodiment, the source terminal of the PMOS transistor 331 is connected to a high power supply voltage VDDP, and the voltage at the drain terminal of the PMOS transistor 331 is applied to the bundle node 138 while the PMOS transistor 331 remains in the on state.

[0229] In operation 961B of method 900B, the source terminal of the second first-type transistor is maintained at the third supply voltage. In operation 962B of method 900B, a second voltage on the second bundled node is applied to the gate terminal of the second first-type transistor. In operation 963B of method 900B, an output voltage from the drain terminal of the second first-type transistor is applied to the third bundled node. Figure 3 , Figures 7A to 7B ,and Figures 8A to 8BIn an exemplary embodiment, the source terminal of PMOS transistor 161 is connected to a high power supply voltage VDDP, the voltage on the bundle node 128 is applied to the gate terminal of PMOS transistor 161, and the output voltage from the drain terminal of PMOS transistor 161 is applied to the bundle node 138.

[0230] exist Figure 9C In this method, method 900C includes all operations of method 900B (i.e., operations 911-912, 921-922, 931, 941-943, 932-933, 951B-952B, and 961B-963B), and also includes operations 971C-973C.

[0231] In operation 971C of method 900C, the source terminal of the second type-two transistor is maintained at the second supply voltage. In operation 972C of method 900C, a third voltage on the third bundle node is applied to the gate terminal of the second type-two transistor. In operation 973C of method 900C, the output voltage from the drain terminal of the second type-two transistor is applied to the second bundle node. Figure 3 and Figures 7A to 7B In an exemplary embodiment, the source terminal of NMOS transistor 162 is connected to a low supply voltage VSS, the voltage on the bundle node 138 is applied to the gate terminal of NMOS transistor 162, and the output voltage from the drain terminal of NMOS transistor 162 is applied to the bundle node 128.

[0232] exist Figure 9D In this method, method 900D includes all the operations of method 900A (i.e., operations 911-912, 921-922, 931, 941-943, and 932-933), and also includes operations 961D, 962B, 963D, 971C, 972D, and 973C. Operation 962B in method 900D is the same as operation 962B in methods 900B and 900C. Operation 971C in method 900D is the same as operation 971C in method 900C. Operation 973C in method 900D is the same as operation 973C in method 900C. Operations 961D and 963D in method 900D are correspondingly modified from operations 961B and 963B in method 900B. Operation 972D in method 900D is a modification of operation 972C in method 900C.

[0233] In operation 961D of method 900D, the source terminal of the second first-type transistor is maintained at the first supply voltage. In operation 962B of method 900D, a second voltage on the second bundled node is applied to the gate terminal of the second first-type transistor. In operation 963D of method 900D, an output voltage from the drain terminal of the second first-type transistor is applied to the first bundled node. Figure 1 and Figure 3 In an exemplary embodiment, in operations 931, 932, and 933, the PMOS transistor 151 in the enhancement circuit 150A is a first type transistor, and in operations 961D, 962B, and 963D, the PMOS transistor 151 in the enhancement circuit 150B is a second first type transistor.

[0234] In operation 971C of method 900D, the source terminal of the second type-two transistor is maintained at the second supply voltage. In operation 972D of method 900D, a first voltage on the first bundled node is applied to the gate terminal of the second type-two transistor. In operation 973C of method 900D, an output voltage from the drain terminal of the second type-two transistor is applied to the second bundled node. Figure 1 and Figure 3 In an exemplary embodiment, in operations 941, 942, and 943, the NMOS transistor 152 in the enhancement circuit 150A is a second type transistor, and in operations 971C, 972D, and 973C, the NMOS transistor 152 in the enhancement circuit 150B is a second second type transistor.

[0235] Figure 10 This is a layout diagram of a circuit unit 1000 implemented using a reinforcement circuit 150 according to some embodiments. The circuit diagram of the reinforcement circuit 150 in the circuit unit 1000 is shown in... Figures 1 to 4 The illustration shows an integrated circuit with enhancement circuitry 150. This integrated circuit includes a PMOS active region structure 50p and an NMOS active region structure 50n. Each of the PMOS active region structure 50p and the NMOS active region structure 50n extends in the X direction. The integrated circuit with enhancement circuitry 150 also includes gate conductors g151 and g152 extending in the Y direction, and end conductors s151-s152 and d151-d152 extending in the Y direction. The integrated circuit also includes dummy gate conductors g101 and g109 at the vertical cell boundaries 101 and 109 of the circuit cells. Gate conductors g151 and g152 are separated from each of the dummy gate conductors g101 and g109 by a contact polysilicon pitch (“CPP”). Here, the Y direction is perpendicular to the X direction.

[0236] The enhancement circuit 150 includes a PMOS transistor 151 in the PMOS active region structure 50p and an NMOS transistor 152 in the NMOS active region structure 50n. The gate, source, and drain terminals of the PMOS transistor 151 are respectively formed with gate conductor g151, terminal conductor s151, and terminal conductor d151, all of which intersect with the PMOS active region structure 50p. The gate, source, and drain terminals of the NMOS transistor 152 are respectively formed with gate conductor g152, terminal conductor s152, and terminal conductor d152, all of which intersect with the NMOS active region structure 50n.

[0237] In some embodiments, each of the PMOS active region structure 50p and the NMOS active region structure 50n includes one or more fin structures, and therefore, each of the PMOS transistor 151 and the NMOS transistor 152 is a finFET transistor. In some embodiments, each of the PMOS active region structure 50p and the NMOS active region structure 50n includes one or more nanosheets, and therefore, each of the PMOS transistor 151 and the NMOS transistor 152 is a nanosheet transistor. In some embodiments, each of the PMOS active region structure 50p and the NMOS active region structure 50n includes one or more nanowires, and therefore, each of the PMOS transistor 151 and the NMOS transistor 152 is a nanowire transistor.

[0238] Figure 11A According to some embodiments, circuit unit 1000 is along such... Figure 10 The cross-sectional view of the cutting plane AA' shown. Figure 11B According to some embodiments, circuit unit 1000 is along such... Figure 10 The cross-sectional view of the cutting plane BB' shown. Figure 11C According to some embodiments, circuit unit 1000 is along such... Figure 10 The cross-sectional view of the cutting plane CC' shown. Figure 11D According to some embodiments, circuit unit 1000 is along such... Figure 10 The cross-sectional view of the cutting plane DD' shown.

[0239] like Figure 10 and Figures 11A to 11DAs shown, the integrated circuit with reinforcement circuitry 150 also includes power lines 20 and 40 extending in the X direction and horizontal conductors h118 and h128 extending in the X direction. Each of the power lines and horizontal conductors is formed in a first metal layer (e.g., metal layer M0) covering a first interlayer dielectric ILD0, which covers the PMOS active region structure 50p, the NMOS active region structure 50n, and various gate conductors and terminal conductors. Power line 20 is used to maintain a high supply voltage VDD, and power line 40 is used to maintain a low supply voltage VSS. Horizontal conductor h118 is configured to maintain a pin at a bundle node 118 at a logic HIGH voltage, and horizontal conductor h128 is configured to maintain a pin at a bundle node 128 at a logic LOW voltage.

[0240] exist Figure 10 and Figures 11A to 11D In the circuit, terminal conductor s151 is connected to power line 20 via through-hole connector VD, terminal conductor d151 is connected to horizontal conductor h118 via through-hole connector VD, and gate conductor g151 is connected to horizontal conductor h128 via through-hole connector VG. Terminal conductor s152 is connected to power line 40 via through-hole connector VD, terminal conductor d152 is connected to horizontal conductor h128 via through-hole connector VD, and gate conductor g152 is connected to horizontal conductor h118 via through-hole connector VG.

[0241] Will Figure 10 The circuit unit 1000 is defined between vertical unit boundaries 101 and 109 extending in the Y direction and horizontal unit boundaries 102 and 108 extending in the X direction. Figures 11A to 11B In the cross-sectional view, the PMOS active region structure 50p and the NMOS active region structure 50n are formed on the substrate 30. The active regions in the PMOS active region structure 50p (such as the source region, channel region, or drain region of the PMOS transistor 151) are isolated from the active regions in adjacent cells by boundary isolation regions i101p below the dummy gate conductor g101 and i109p below the dummy gate conductor g109. The active regions in the NMOS active region structure 50n (such as the source region, channel region, or drain region of the NMOS transistor 152) are isolated from the active regions in adjacent cells by boundary isolation regions i101n below the dummy gate conductor g101 and i109n below the dummy gate conductor g109. Boundary isolation regions i101p and i101n are aligned along the Y direction at the vertical cell boundary 101. Boundary isolation zones i109p and i109n are aligned along the Y direction at the vertical unit boundary 109.

[0242] Figure 12This is a layout diagram of a circuit unit 1200 implemented using two reinforcement circuits 150A and 150B according to some embodiments. Each of the reinforcement circuits 150A and 150B has, as shown in the diagram... Figures 1 to 4 The circuit is the same as the enhancement circuit 150 illustrated in the illustration. The integrated circuit having circuit cell 1200 includes a PMOS active region structure 50p and an NMOS active region structure 50n. Each of the PMOS active region structure 50p and the NMOS active region structure 50n extends in the X direction. The circuit cell 1200 is defined between dummy gate conductors g101 and g109 at the vertical cell boundaries 101 and 109 of the circuit cell. The active region in the PMOS active region structure 50p is isolated from the active region in the adjacent cell by a boundary isolation region below the dummy gate conductors g101 and g109. The active region in the NMOS active region structure 50n is isolated from the active region in the adjacent cell by a boundary isolation region below the dummy gate conductors g101 and g109.

[0243] Each of the enhancement circuits 150A and 150B includes a PMOS transistor in the PMOS active region structure 50p and an NMOS transistor in the NMOS active region structure 50n. The gate, source, and drain terminals of the PMOS transistor in enhancement circuit 150A are formed using gate conductor g151A, terminal conductor s151A, and terminal conductor d151AB, respectively. The gate, source, and drain terminals of the PMOS transistor in enhancement circuit 150B are formed using gate conductor g151B, terminal conductor s151B, and terminal conductor d151AB, respectively. The gate, source, and drain terminals of the NMOS transistor in enhancement circuit 150A are formed using gate conductor g152A, terminal conductor s152AB, and terminal conductor d152A, respectively. The gate, source, and drain terminals of the NMOS transistor in enhancement circuit 150B are formed using gate conductor g152B, terminal conductor s152AB, and terminal conductor d152B, respectively.

[0244] The integrated circuit having circuit unit 1200 also includes power lines 20 and 40 extending in the X direction and horizontal conductors h118 and h128 extending in the X direction. Each of the power lines and horizontal conductors is formed in a first metal layer (e.g., metal layer M0) covering a first interlayer dielectric ILD0, which covers the PMOS active region structure 50p, the NMOS active region structure 50n, and various gate conductors and terminal conductors. Power line 20 is used to maintain a high supply voltage VDD, and power line 40 is used to maintain a low supply voltage VSS. Horizontal conductor h118 is configured to maintain a pin at a bundle node 118 at a logic HIGH voltage, and horizontal conductor h128 is configured to maintain a pin at a bundle node 128 at a logic LOW voltage.

[0245] exist Figure 12 In this configuration, each of end conductors s151A and s151B is connected to power line 20 via through-hole connector VD, and end conductor s152AB is connected to power line 40 via through-hole connector VD. End conductor d151AB is connected to horizontal conductor h118 via through-hole connector VD, and each of gate conductors g152A and g152B is also connected to horizontal conductor h118 via through-hole connector VG. Each of end conductors d152A and d152B is connected to horizontal conductor h128 via through-hole connector VD, and each of gate conductors g151A and g151B is also connected to horizontal conductor h128 via through-hole connector VG.

[0246] Figure 12 The circuit unit 1200 has a unit width of three CPPs. The unit width is measured as the distance along the X direction between the dummy gate conductors g101 and g109. For comparison, Figure 10 The circuit unit 1000 has a cell width of two CPPs. Depending on how the circuit unit 1200 is connected to other circuits in the integrated circuit, the circuit unit 1200 may be considered to have two separate reinforcement circuits or only one combined reinforcement circuit. Specifically, in some embodiments, each of the two reinforcement circuits in the circuit unit 1200 serves as... Figures 1 to 4 One of the enhancement circuits (e.g., 150A, 150B, 150C, or 150D) in the circuit is connected. In some embodiments, the two enhancement circuits in circuit unit 1200 are used as one enhancement circuit 150, and the enhancement circuit (combined) includes two PMOS transistors connected in parallel and two NMOS transistors connected in parallel.

[0247] Additionally, in Figure 10 Circuit unit 1000 and Figure 12In circuit unit 1200, the PMOS and NMOS transistors are configured as static transistors. The channel states of the static transistors are fixed over time. For example, Figure 10 The channel state of each of the PMOS transistors 151 and NMOS transistors 152 remains conductive and does not change over time. In some embodiments, the circuit unit implemented using the enhancement circuit includes more than two PMOS transistors and / or more than two NMOS transistors, and all PMOS transistors and NMOS transistors in the circuit unit are configured as static transistors.

[0248] Figure 13 This is a layout diagram of a circuit cell 1300 implemented using reinforcement circuitry 550 connected to three bundled nodes according to some embodiments. The integrated circuit having the circuit cell 1300 includes PMOS active region structures 50p and 52p extending in the X direction and NMOS active region structures 50n and 52n extending in the X direction. The circuit cell 1300 is defined between dummy gate conductors g101 and g109 at the vertical cell boundaries 101 and 109 of the circuit cell. The active regions in the PMOS and NMOS active region structures are isolated from the active regions in adjacent cells by corresponding boundary isolation regions below the dummy gate conductors g101 and g109.

[0249] The enhancement circuit 550 in circuit unit 1300 includes a PMOS transistor in PMOS active region structure 50p, a PMOS transistor in PMOS active region structure 52p, and an NMOS transistor in NMOS active region structure 50n. In some embodiments, the enhancement circuit 550 also includes an NMOS transistor in NMOS active region structure 52n. The gate, source, and drain terminals of the PMOS transistor in PMOS active region structure 50p are formed using gate conductor g151, terminal conductor s151, and terminal conductor d151, respectively. The gate, source, and drain terminals of the PMOS transistor in PMOS active region structure 52p are formed using gate conductor g161, terminal conductor s161, and terminal conductor d161, respectively. The gate, source, and drain terminals of the NMOS transistor in NMOS active region structure 50n are formed using gate conductor g152, terminal conductor s152, and terminal conductor d152, respectively.

[0250] The integrated circuit having circuit unit 1300 also includes power lines 20M, 20P, and 40 extending in the X direction, and horizontal conductors h118, h128, h138, and h148 extending in the X direction. Each of the power lines and horizontal conductors is formed in a first metal layer (e.g., metal layer M0) covering a first interlayer dielectric ILD0, which covers both the PMOS and NMOS active region structures. Power line 20M is used to maintain a high supply voltage VDDM in the first power domain, power line 20P is used to maintain a high supply voltage VDDP in the second power domain, and power line 40 is used to maintain a low supply voltage VSS. Horizontal conductor h118 is configured as an access pin for maintaining a logic HIGH voltage in a first power domain, horizontal conductor h138 is configured as an access pin for maintaining a logic HIGH voltage in a second power domain, and horizontal conductor h128 is configured as an access pin for maintaining a logic LOW voltage in a bundle node 128.

[0251] exist Figure 13 In the circuit, terminal conductor s151 is connected to power line 20M via through-hole connector VD, terminal conductor s161 is connected to power line 20P via through-hole connector VD, and terminal conductor s152 is connected to power line 40 via through-hole connector VD. Terminal conductor d151 is connected to horizontal conductor h118 via through-hole connector VD, terminal conductor d152 is connected to horizontal conductor h128 via through-hole connector VD, and terminal conductor d161 is connected to horizontal conductor h138 via through-hole connector VD. Gate conductor g151 is connected to horizontal conductor h128 via through-hole connector VG. Gate conductor g161 is connected to horizontal conductor h148 via through-hole connector VG, and horizontal conductor h148 is connected to terminal conductor d152 via through-hole connector VD.

[0252] In some alternative embodiments, the enhancement circuit 550 in circuit unit 1300 also includes an NMOS transistor in the NMOS active region structure 52n. In some embodiments, the gate, source, and drain terminals of the NMOS transistor in the NMOS active region structure 52n are respectively formed using gate conductor g162, terminal conductor s162, and terminal conductor d162. Terminal conductor s162 is connected to the power line 40 via a through-hole connector VD, and terminal conductor d152 is connected to the horizontal wire h148 via a through-hole connector VD. Furthermore, terminal conductors d152 and d151 are merged and directly connected to each other.

[0253] Figure 14 This is a flowchart of a method 1400 for manufacturing an integrated circuit according to some embodiments. Figure 14The sequence of operations depicted in Method 1400 is for illustrative purposes only; the operations of Method 1400 can be performed in different ways. Figure 14 The sequence of operations described herein shall be executed. It should be understood that additional operations may be performed... Figure 14 The methods described herein are performed before, during, and / or after 1400, and some other processes may be described only briefly in this document.

[0254] In operation 1410 of method 1400, a first type active region structure and a second type active region structure extending in the X direction are fabricated on a substrate. The channel region, source region, and drain region of at least one first type transistor are formed using the first type active region structure. The channel region, source region, and drain region of at least one second type transistor are formed using the second type active region structure. In some embodiments, the first type active region structure is a PMOS active region structure, and the second type active region structure is an NMOS active region structure. In some embodiments, the first type active region structure is an NMOS active region structure, and the second type active region structure is a PMOS active region structure. Figure 10 and Figures 11A to 11D In an exemplary embodiment, a PMOS active region structure 50p and an NMOS active region structure 50n are fabricated on a substrate 30.

[0255] In operation 1420 of method 1400, a first isolation region and a second isolation region are manufactured in a first-type active region structure, and a third isolation region and a fourth isolation region are manufactured in a second-type active region structure. The first and third isolation regions are aligned at the first vertical cell boundary. The second and fourth isolation regions are aligned at the second vertical cell boundary. Figure 10 and Figures 11A to 11D In an exemplary embodiment, boundary isolation regions i101p and i109p are fabricated in the PMOS active region structure 50p, and boundary isolation regions i101n and i109n are fabricated in the NMOS active region structure 50n.

[0256] In operation 1430 of method 1400, a first gate conductor and a second gate conductor extending in the Y direction are fabricated. The first gate conductor intersects with a first-type active region structure at the channel region of a first-type transistor. The second gate conductor intersects with a second-type active region structure at the channel region of a second-type transistor. Figure 10 and Figures 11A to 11D In an exemplary embodiment, a gate conductor g151 intersecting with the PMOS active region structure 50p and a gate conductor g152 intersecting with the NMOS active region structure 50n are manufactured.

[0257] In operation 1442 of method 1400, a first terminal conductor and a second terminal conductor intersecting with the first type active region structure are manufactured. In operation 1444 of method 1400, a third terminal conductor and a fourth terminal conductor intersecting with the second type active region structure are manufactured. The first terminal conductor and the second terminal conductor intersect with the first type active region structure correspondingly as the source and drain terminals of the first type transistor. The third terminal conductor and the fourth terminal conductor intersect with the second type active region structure correspondingly as the source and drain terminals of the second type transistor. Figure 10 and Figures 11A to 11D In an exemplary embodiment, end conductors s151 and d151 intersecting with the PMOS active region structure 50p and end conductors s152 and d152 intersecting with the NMOS active region structure 50n are manufactured.

[0258] In operation 1452 of method 1400, a first through-hole connector and a second through-hole connector are formed. The first through-hole connector is directly connected to a first terminal conductor, and the second through-hole connector is directly connected to a third terminal conductor. In operation 1454 of method 1400, a third through-hole connector, a fourth through-hole connector, a fifth through-hole connector, and a sixth through-hole connector are formed. The third through-hole connector is directly connected to a second terminal conductor, the fourth through-hole connector is directly connected to a second gate conductor, the fifth through-hole connector is directly connected to a fourth terminal conductor, and the sixth through-hole connector is directly connected to a first gate conductor. In some embodiments, at least one of the first, second, third, fourth, fifth, or sixth through-hole connectors is formed simultaneously with another of the first, second, third, fourth, fifth, or sixth through-hole connectors. In operation 1462 of method 1400, a first power line and a second power line are manufactured. The first power line is directly connected to the first through-hole connector, and the second power line is directly connected to the second through-hole connector. Figure 10 and Figures 11A to 11D In an exemplary embodiment, power lines 20 and 40 extending in the X direction are fabricated in a first metal layer (e.g., metal layer M0) above the active region structure. End conductors s151 are connected to power line 20 via through-hole connector VD, and end conductors s152 are connected to power line 40 via through-hole connector VD.

[0259] In operation 1464 of method 1400, a first wire and a second wire are manufactured. The first wire is directly connected to both the third and fourth through-hole connectors. The second wire is directly connected to both the fifth and sixth through-hole connectors. Figure 10 and Figures 11A to 11DIn an exemplary embodiment, horizontal conductors h118 and h128 extending in the X direction are fabricated in a first metal layer (e.g., metal layer M0) above the active region structure. Horizontal conductor h118 is connected to end conductor d151 via via connector VD and to gate conductor g152 via via connector VG.

[0260] Figure 15 This is a block diagram of an electronic design automation (EDA) system 1500 according to some embodiments.

[0261] In some embodiments, the EDA system 1500 includes an automatic placement and routing (APR) system. According to one or more embodiments, the method described herein for representing a layout diagram of wiring arrangements may be implemented, for example, using the EDA system 1500 according to some embodiments.

[0262] In some embodiments, the EDA system 1500 is a general-purpose computing device including a hardware processor 1502 and a non-transitory computer-readable storage medium 1504. The storage medium 1504 is encoded (i.e., stored computer code 1506) in particular using computer program code 1506 (i.e., an executable instruction set). The instructions 1506, executed by the hardware processor 1502, represent (at least partially) an EDA tool that implements part or all of the methods described herein according to one or more embodiments (hereinafter referred to as the processes and / or methods).

[0263] Processor 1502 is electrically coupled to computer-readable storage medium 1504 via bus 1508. Processor 1502 is also electrically coupled to I / O interface 1510 via bus 1508. Network interface 1512 is also electrically connected to processor 1502 via bus 1508. Network interface 1512 is connected to network 1514, enabling processor 1502 and computer-readable storage medium 1504 to be connected to external components via network 1514. Processor 1502 is used to execute computer program code 1506 encoded in computer-readable storage medium 1504 so that system 1500 can be used to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 1502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0264] In one or more embodiments, the computer-readable storage medium 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1504 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0265] In one or more embodiments, storage medium 1504 stores computer program code 1506 that enables system 1500 (where such execution represents (at least partially) EDA tools) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1504 also stores information facilitating the performance of part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1504 stores a library 1507 of standard units (including such standard units as disclosed herein). In one or more embodiments, storage medium 1504 stores one or more layout diagrams 1509 corresponding to one or more layouts disclosed herein.

[0266] EDA system 1500 includes an I / O interface 1510. The I / O interface 1510 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1510 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor keys for communicating information and commands to processor 1502.

[0267] EDA system 1500 also includes a network interface 1512 coupled to processor 1502. Network interface 1512 allows system 1500 to communicate with network 1514, through which one or more other computer systems are connected. Network interface 1512 includes: a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 1500.

[0268] System 1500 receives information through I / O interface 1510. The information received through I / O interface 1510 includes one or more of the following: instructions, data, design rules, standard unit libraries, and / or other parameters for processing by processor 1502. The information is transferred to processor 1502 via bus 1508. EDA system 1500 receives information about the user interface (UI) through I / O interface 1510. The information is stored as UI 1542 in computer-readable media 1504.

[0269] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a stand-alone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application that is used by an EDA system 1500. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO® from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

[0270] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical discs (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROMs, RAMs, memory cards), and the like.

[0271] Figure 16 This is a block diagram of an integrated circuit (IC) manufacturing system 1600 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1600 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one element in a semiconductor integrated circuit layer.

[0272] exist Figure 16In this IC manufacturing system 1600, entities such as design room 1620, mask room 1630, and IC manufacturer / producer (wafer fab) 1650 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 1660. The entities in system 1600 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as intranets and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1620, mask room 1630, and IC wafer fab 1650 are owned by a single, larger company. In some embodiments, two or more of design room 1620, mask room 1630, and IC wafer fab 1650 coexist in shared facilities and use shared resources.

[0273] Design studio (or design team) 1620 produces IC design layout 1622. IC design layout 1622 includes various geometric patterns designed for IC device 1660. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1660 to be manufactured. The layers are combined to form various IC features. For example, a portion of IC design layout 1622 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, as well as various material layers disposed on the semiconductor substrate. Design studio 1620 performs appropriate design procedures to form IC design layout 1622. Design procedures include one or more of the following: logic design, physical design, or place and route. IC design layout 1622 exists in one or more data files containing information about the geometric patterns. For example, IC design layout 1622 may be expressed in GDSII file format or DFII file format.

[0274] Masking chamber 1630 includes data preparation 1632 and mask fabrication 1644. Masking chamber 1630 uses an IC design layout 1622 to fabricate one or more masks 1645, which will be used to fabricate various layers of an IC device 1660 according to the IC design layout 1622. Masking chamber 1630 performs mask data preparation 1632, in which the IC design layout 1622 is converted into a representative data file (RDF). Mask data preparation 1632 provides the RDF to mask fabrication 1644. Mask fabrication 1644 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 1645 or a semiconductor wafer 1653. The design layout 1622 is manipulated by mask data preparation 1632 to conform to the specific characteristics of the mask writer and / or the requirements of the IC wafer fab 1650. Figure 16 In this diagram, mask data preparation 1632 and mask manufacturing 1644 are shown as separate elements. In some embodiments, mask data preparation 1632 and mask manufacturing 1644 may be collectively referred to as mask data preparation.

[0275] In some embodiments, mask data preparation 1632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that can be caused by diffraction, interference, other process effects, and the like. OPC adjustment IC design layout diagram 1622. In some embodiments, mask data preparation 1632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masking, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0276] In some embodiments, mask data preparation 1632 includes a mask rule checker (MRC) that checks an IC design layout 1622 that has undergone a process in an OPC with a set of mask generation rules, which contain certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout 1622 to compensate for photolithography effects during mask fabrication 1644, which may offset some modifications performed by the OPC to satisfy the mask generation rules.

[0277] In some embodiments, mask data preparation 1632 includes lithography process checking (LPC) of a simulation process, which is performed by IC wafer fab 1650 to manufacture IC device 1660. LPC simulates this process based on IC design layout 1622 to produce a simulated manufacturing device, such as IC device 1660. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after the simulated manufacturing device has been generated by LPC, if the simulated device shape is not sufficiently compact to meet design rules, OPC and / or MRC will be repeated to further refine the IC design layout 1622.

[0278] It should be understood that the above description of mask data preparation 1632 has been simplified for clarity. In some embodiments, data preparation 1632 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1622 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1622 during data preparation 1632 can be performed in various different sequences.

[0279] Following mask data preparation 1632 and during mask manufacturing 1644, a mask 1645 or a group of masks 1645 is manufactured based on a modified IC design layout 1622. In some embodiments, mask manufacturing 1644 includes performing one or more lithography exposures based on the IC design layout 1622. In some embodiments, a mechanism of electron beams (e-beams) or multiple electron beams is used to form a pattern on the mask (photomask or master photomask) 1645 based on the modified IC design layout 1622. The mask 1645 can be formed in various techniques. In some embodiments, the mask 1645 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams (such as ultraviolet (UV) beams) intended to expose image-sensitive material layers (e.g., photoresist) already coated on the wafer are blocked by the opaque areas and penetrate the transparent areas. In one example, the binary mask version of mask 1645 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 1645 is formed using a phase shift mask (PSM) technique. In the phase shift mask (PSM) version of mask 1645, various features in the pattern formed on the phase shift mask are used to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask produced by mask fabrication 1644 is used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1653, in etching processes to form various etched regions in semiconductor wafer 1653, and / or in other suitable processes.

[0280] IC wafer fab 1650 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC wafer fab 1650 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end-of-line, FEOL) of various IC products, a second manufacturing facility that provides back-end manufacturing (back-end-of-line, BEOL) for interconnecting and packaging IC products, and a third manufacturing facility that provides other services for the foundry company.

[0281] IC wafer fab 1650 includes manufacturing tools 1652 for performing various manufacturing operations on semiconductor wafers 1653, such that IC device 1660 is manufactured according to a mask (e.g., mask 1645). In various embodiments, manufacturing tools 1652 include one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0282] IC wafer fab 1650 uses a mask 1645, manufactured by mask chamber 1630, to manufacture IC device 1660. Therefore, IC wafer fab 1650 uses IC design layout 1622 at least indirectly to manufacture IC device 1660. In some embodiments, semiconductor wafer 1653 is manufactured by IC wafer fab 1650 using mask 1645 to form IC device 1660. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1622. Semiconductor wafer 1653 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1653 further includes one or more of the following: various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent manufacturing steps).

[0283] This disclosure relates to an integrated circuit. The integrated circuit includes a first power line for maintaining a first power supply voltage. The circuit also includes a second power line for maintaining a second power supply voltage. The circuit also includes a first-type bonding transistor having a source terminal connected to the first power line, wherein the first-type bonding transistor is maintained in an on state. The circuit also includes a first bonding node connected to the drain terminal of the first-type bonding transistor. The circuit also includes a second-type bonding transistor whose source terminal is connected to the second power line, wherein the second-type bonding transistor is maintained in an on state. The circuit also includes a second bonding node connected to the drain terminal of the second-type bonding transistor; a first-type active region structure extending in a first direction; and a second-type active region structure extending in the first direction. The circuit also includes a plurality of enhancement circuits, wherein each of the plurality of enhancement circuits includes a first-type transistor in the first-type active region structure and a second-type transistor in the second-type active region structure, wherein the first-type transistor has a source terminal connected to the first power line, a drain terminal connected to the first bonding node, and a gate terminal connected to the second bonding node, and wherein the second-type transistor has a source terminal connected to the second power line, a drain terminal connected to the second bonding node, and a gate terminal connected to the first bonding node.

[0284] In some embodiments, a gate terminal of the first bonded transistor is maintained at a voltage that drives the first bonded transistor into the on state, and a gate terminal of the second bonded transistor is maintained at a voltage that drives the second bonded transistor into the on state. In some embodiments, the integrated circuit further includes: a first holding transistor of a second type having a source terminal connected to a second power line, the first holding transistor having a drain terminal connected to the gate terminal of the first bonded transistor; and a second holding transistor of a first type having a source terminal connected to the first power line, the second holding transistor having a drain terminal connected to the gate terminal of the second bonded transistor. In some embodiments, the integrated circuit further includes: a third power line for maintaining at a third power supply voltage; a third bonded transistor of a first type having a source terminal connected to the third power line, wherein the third bonded transistor is maintained in the on state; and a third bonding node connected to the drain terminal of the third bonded transistor. In some embodiments, the integrated circuit further includes: a third holding transistor of a second type having a source terminal connected to the second power line, the third holding transistor having a drain terminal connected to the gate terminal of the third bonded transistor. In some embodiments, each reinforcement circuit in the reinforcement circuit further includes: a second first-type transistor having a source terminal connected to a third power line, a drain terminal connected to a third bundling node, and a gate terminal connected to a second bundling node. In some embodiments, each reinforcement circuit in the reinforcement circuit further includes: a second second-type transistor having a source terminal connected to a second power line, a drain terminal connected to a second bundling node, and a gate terminal connected to a third bundling node.

[0285] Another aspect disclosed herein relates to a method. This method includes maintaining the channel of a first bonded transistor in an ON state while the source terminal of the first bonded transistor is maintained at a first power supply voltage. This method also includes applying an output voltage from the drain terminal of the first bonded transistor to a first bonded node. This method also includes maintaining the channel of a second bonded transistor in an ON state while the source terminal of the second bonded transistor is maintained at a second power supply voltage. This method also includes applying an output voltage from the drain terminal of the second bonded transistor to a second bonded node. This method also includes maintaining the source terminal of a first type transistor at the first power supply voltage. This method also includes maintaining the source terminal of a second type transistor at the second power supply voltage. This method also includes applying a first voltage at the first bonded node to the gate terminal of the second type transistor. This method also includes applying an output voltage from the drain terminal of the second type transistor to the second bonded node. This method also includes applying a second voltage at the second bonded node to the gate terminal of the first type transistor. This method also includes applying an output voltage from the drain terminal of the first type transistor to the first bonded node.

[0286] In some embodiments, the method further includes: maintaining the channel of the third bonded transistor in an ON state while maintaining the source terminal of the third bonded transistor at a third power supply voltage; applying an output voltage from the drain terminal of the third bonded transistor to a third bonded node; maintaining the source terminal of the second first-type transistor at the third power supply voltage; applying a second voltage on the second bonded node to the gate terminal of the second first-type transistor; and applying an output voltage from the drain terminal of the second first-type transistor to the third bonded node. In some embodiments, the method further includes: maintaining the source terminal of the second second-type transistor at a second power supply voltage; applying a third voltage on the third bonded node to the gate terminal of the second second-type transistor; and applying an output voltage from the drain terminal of the second second-type transistor to the second bonded node. In some embodiments, the method further includes: maintaining the source terminal of the second first type transistor at a first power supply voltage; maintaining the source terminal of the second second type transistor at a second power supply voltage; applying a first voltage at a first bundling node to the gate terminal of the second second type transistor; applying an output voltage from the drain terminal of the second second type transistor to a second bundling node; applying a second voltage at the second bundling node to the gate terminal of the second first type transistor; and applying an output voltage from the drain terminal of the second first type transistor to the first bundling node.

[0287] Another aspect of this disclosure also relates to an integrated circuit. This integrated circuit includes: a first bundled node for maintaining a first voltage thereon at a first logic level; a second bundled node for maintaining a second voltage thereon at a second logic level different from the first logic level; a first type active region structure extending in a first direction, having a first isolation region and a second isolation region; and a second type active region structure extending in the first direction, having a third isolation region and a fourth isolation region. This circuit also includes a first type transistor in the first type active region structure between the first and second isolation regions, the first type transistor having a source terminal connected to a first power line for maintaining a first power supply voltage. This circuit also includes a second type transistor in the second type active region structure between the third and fourth isolation regions, the second type transistor having a source terminal connected to a second power line for maintaining a second power supply voltage. This circuit also includes a drain terminal of the first type transistor connected to the first bundled node. This circuit also includes a gate terminal of the second type transistor also connected to the first bundled node. This circuit also includes a drain terminal of the second type transistor connected to the second bundled node. This circuit also includes a gate terminal of the first type transistor also connected to the second bundled node.

[0288] In some embodiments, the integrated circuit further includes: a first type of bonding transistor for maintaining in an on state, the bonding transistor having a source terminal connected to a first power line and a drain terminal connected to a first bonding node. In some embodiments, the integrated circuit further includes: a second type of bonding transistor for maintaining in an on state, the bonding transistor having a source terminal connected to a second power line and a drain terminal connected to a second bonding node. In some embodiments, the integrated circuit further includes: a third bonding node for maintaining a third voltage on it at a third logic level; a second first type transistor, in a first type active region structure between a first isolation region and a second isolation region, the second first type transistor having a source terminal connected to a third power line for maintaining at a third power supply voltage; a drain terminal of the second first type transistor connected to the third bonding node; and a gate terminal of the second first type transistor connected to the second bonding node. In some embodiments, the integrated circuit further includes: a second second type transistor, in a second type active region structure between a third isolation region and a fourth isolation region, the second second type transistor having a source terminal connected to a second power line; a gate terminal of the second second type transistor connected to the third bonding node; and a drain terminal of the second second type transistor connected to the second bonding node. In some embodiments, the first and third isolation regions are aligned along a second direction at the first vertical cell boundary, and the second and fourth isolation regions are aligned along a second direction at the second vertical cell boundary, the second direction being perpendicular to the first direction. In some embodiments, the first and second isolation regions are separated by a distance of two CPPs (“contact polysilicon pitch”), and the third and fourth isolation regions are separated by a distance of two CPPs. In some embodiments, the first and second isolation regions are separated by a distance of three CPPs (“contact polysilicon pitch”), and the third and fourth isolation regions are separated by a distance of three CPPs. In some embodiments, all transistors in the first type of active region structure between the first and second isolation regions are configured as static transistors, and all transistors in the second type of active region structure between the third and fourth isolation regions are configured as static transistors.

[0289] Those skilled in the art will readily recognize that the disclosed one or more embodiments achieve one or more advantages described above. After reading the above specification, those skilled in the art will be able to implement various modifications, equivalent substitutions, and various other embodiments as broadly disclosed herein. Therefore, the intent to protect this disclosure is limited only to the definitions contained in the appended claims and their equivalents.

Claims

1. An integrated circuit, characterized in that, Include: A first electric field line is used to maintain a first power supply voltage; A second power line is used to maintain a second power supply voltage; A first-type first-bonded transistor has a source terminal connected to the first power line, wherein the first-bonded transistor is used to maintain a conducting state; A first binding node is connected to a drain terminal of the first binding transistor; A second type of second-bonded transistor has a source terminal connected to the second power line, wherein the second-bonded transistor is used to maintain a conducting state; A second bonding node is connected to a drain terminal of the second bonding transistor; A first type of active region structure, extending in a first direction; A second type of active region structure extends in the first direction; as well as A plurality of enhancement circuits, wherein each of the plurality of enhancement circuits includes a first type transistor in the first type active region structure and a second type transistor in the second type active region structure, wherein the first type transistor has a source terminal connected to the first power line, a drain terminal connected to the first bundling node, and a gate terminal connected to the second bundling node, and wherein the second type transistor has a source terminal connected to the second power line, a drain terminal connected to the second bundling node, and a gate terminal connected to the first bundling node.

2. The integrated circuit as described in claim 1, characterized in that, Further includes: A first holding transistor of the second type has a source terminal connected to the second power line and a drain terminal connected to a gate terminal of the first bonded transistor. as well as A second holding transistor of the first type has a source terminal connected to the first power line and a drain terminal connected to a gate terminal of the second holding transistor.

3. The integrated circuit as described in claim 1, characterized in that, Further includes: A third power line is used to maintain a third power supply voltage; A third-bonded transistor of the first type has a source terminal connected to the third power line, wherein the third-bonded transistor is used to maintain a conducting state; as well as A third binding node is connected to a drain terminal of the third binding transistor.

4. A method for operating an integrated circuit, characterized in that, Include: One channel of a first bonded transistor is kept in an on state, while one source terminal of the first bonded transistor is maintained at a first supply voltage; An output voltage from the drain terminal of the first bonded transistor is applied to a first bonded node; One channel of a second bonded transistor is kept in an on state, while one source terminal of the second bonded transistor is maintained at a second power supply voltage; An output voltage from a drain terminal of the second bonded transistor is applied to a second bonded node; One source terminal of a first type transistor is maintained at the first power supply voltage; One source terminal of a second type transistor is maintained at the second power supply voltage; A first voltage is applied to a gate terminal of the second type transistor at the first bundle node; An output voltage from a drain terminal of the second type of transistor is applied to the second bundle node; A second voltage is applied to a gate terminal of the first type transistor at the second bundle node; as well as An output voltage from one drain terminal of the first type of transistor is applied to the first bundle node.

5. The method as described in claim 4, characterized in that, Further includes: One channel of a third-bonded transistor is kept in an on state, while one source terminal of the third-bonded transistor is maintained at a third power supply voltage; An output voltage from the drain terminal of the third bonded transistor is applied to a third bonded node; One source terminal of a second type-1 transistor is maintained at the third power supply voltage; The second voltage on the second bundle node is applied to a gate terminal of the second first-type transistor; as well as An output voltage from one drain terminal of the second type-1 transistor is applied to the third bundle node.

6. The method as described in claim 4, characterized in that, Further includes: One source terminal of a second type-1 transistor is maintained at the first power supply voltage; One source terminal of a second type transistor is maintained at the second power supply voltage; The first voltage on the first bundle node is applied to a gate terminal of the second type transistor. An output voltage from a drain terminal of the second type-two transistor is applied to the second bundle node; The second voltage on the second bundle node is applied to a gate terminal of the second first-type transistor; as well as An output voltage from one drain terminal of the second type-1 transistor is applied to the first bundle node.

7. An integrated circuit, characterized in that, Include: A first bundled node is used to maintain a first voltage on it at a first logic level; A second binding node is used to maintain a second voltage on it at a second logic level different from the first logic level; A first type of active region structure extends in a first direction, wherein it has a first isolation region and a second isolation region; A second type of active region structure extends in the first direction, wherein it has a third isolation region and a fourth isolation region; A first type transistor, in the first type active region structure between the first isolation region and the second isolation region, the first type transistor has a source terminal connected to a first power line for maintaining a first power supply voltage; A second type transistor, in the second type active region structure between the third isolation region and the fourth isolation region, the second type transistor has a source terminal connected to a second power line for maintaining a second power supply voltage; A drain terminal of the first type of transistor connected to the first bundle node; It is also connected to a gate terminal of the second type of transistor at the first bundle node; A drain terminal of the second type of transistor connected to the second bundle node; as well as It is also connected to a gate terminal of the first type of transistor in the second bundle node.

8. The integrated circuit as described in claim 7, characterized in that, Further includes: A third binding node is used to maintain a third voltage on it at a third logic level; A second first-type transistor, in the first-type active region structure between the first isolation region and the second isolation region, the second first-type transistor has a source terminal connected to a third power line for maintaining a third power supply voltage; A drain terminal of the second first-type transistor connected to the third bundle node; as well as A gate terminal of the second first-type transistor connected to the second bundle node.

9. The integrated circuit as described in claim 8, characterized in that, Further includes: A second type transistor, in the second type active region structure between the third isolation region and the fourth isolation region, the second type transistor has a source terminal connected to the second power line; A gate terminal of the second type transistor is connected to the third bundle node; as well as One drain terminal of the second type transistor is connected to the second bundle node.

10. The integrated circuit as claimed in claim 7, characterized in that, The first isolation zone and the third isolation zone are aligned along a second direction at the boundary of a first vertical unit, and the second isolation zone and the fourth isolation zone are aligned along the second direction at the boundary of a second vertical unit, the second direction being perpendicular to the first direction.

Images