Smart glass package carrier system with built-in stress sensing and method of manufacturing the same

Abstract

The application discloses a smart glass packaging board system with built-in stress sensing and a preparation method thereof, and belongs to the technical field of semiconductor advanced packaging substrates. The system adopts a symmetric three-layer composite structure, and from top to bottom, the structure is an upper composite buffer layer, a glass core layer and a lower composite buffer layer. The composite buffer layer is respectively embedded with a thin film piezoelectric sensing array. The sensing units are vertically one-to-one corresponding, and can collect dynamic thermal shear stress of a multi-layer interface in a package in real time. The preparation method comprises seven procedures of glass substrate pretreatment marking, lower sensing array sputtering etching, lower buffer layer slot coating, upper mirror image array preparation, upper buffer layer coating, segmented nitrogen high-temperature curing and automatic electrical property needle measurement sorting. The application realizes in-situ online monitoring of internal stress of a package, the sensing structure has strong interface bonding force and high long-term reliability, can support positive optimization of packaging reliability, and is suitable for high-end packaging scenes such as 2.5D / 3D IC, silicon photonics and CPO optical communication.

Description

Technical Field

[0001] This invention belongs to the field of advanced semiconductor packaging substrate technology, specifically relating to a glass-based packaging substrate system and its fabrication process that integrates a thin-film piezoelectric sensing array and can collect dynamic thermal shear stress inside the package in real time. Background Technology

[0002] As advanced semiconductor packaging technologies rapidly advance towards high-density integration, large-size ultra-thin substrates, and high-power chip stacking, traditional organic substrates suffer from limitations such as high dielectric loss, large coefficient of thermal expansion, and insufficient flatness. Silicon interposers, on the other hand, face challenges related to high cost and difficulty in large-size fabrication. Glass substrates, with their advantages of low dielectric loss, high surface flatness, low coefficient of thermal expansion, and controllable manufacturing costs, are gradually becoming the core carrier in high-end packaging fields and are widely used in packaging scenarios such as 2.5D / 3D IC, silicon photonics, and CPO optical communication.

[0003] During actual chip operation, active devices continuously generate Joule heat, causing the packaging system's temperature to fluctuate periodically. Due to significant differences in the coefficients of thermal expansion between the glass core layer, buffer layer, solder layer, and chip, temperature cycling generates continuous dynamic thermal shear stress at various interfaces within the package. When stress distribution is uneven or localized stress overload occurs, it can easily lead to reliability defects such as microcrack initiation in the glass substrate, interlayer delamination, internal circuit breakage, and BGA solder joint fatigue failure, severely limiting the long-term service life of high-end packaged devices.

[0004] Currently, the industry's stress detection and control for packaging substrates mainly suffers from the following technical deficiencies: 1. Stress testing relies on offline destructive methods: Existing solutions mostly employ methods such as cross-section metallographic analysis, indirect estimation via infrared thermography, and external strain gauge attachment. These methods can only perform offline sampling inspections of finished products and cannot achieve online, real-time internal stress monitoring while the chip is in operation. Furthermore, external strain gauges can only collect stress from the substrate surface and cannot capture the internal shear stress at the interface between the glass core layer and the buffer layer. This results in large errors in the detection data and fails to reflect the true stress state inside the package.

[0005] 2. Traditional glass substrates do not have stress self-sensing capabilities: Conventional glass substrates only bear physical load and electrical wiring functions, without built-in sensing structures. After a failure occurs in the packaging, it is impossible to trace the entire process of stress evolution, making it difficult to locate the root cause of the failure and support positive optimization of packaging reliability.

[0006] 3. Low integration between the sensing structure and the substrate: Existing piezoelectric / piezoresistive sensing films are mostly bonded to the substrate by external mounting. The bonding force with the buffer layer interface is weak, and delamination and peeling are prone to occur under long-term thermal cycling conditions. They cannot synchronously follow the deformation of the substrate, resulting in lag in stress measurement response and data distortion. Moreover, external sensors will increase the overall thickness of the package, which is not conducive to the development of ultra-thin and miniaturized devices.

[0007] 4. Poor mass production compatibility of built-in sensing solutions: The few existing substrate solutions with built-in sensors have problems with fragmented process steps and complex processes, which cannot be compatible with the standard coating, sputtering and curing mass production lines of glass substrates. This results in low production yield, high manufacturing costs, and difficulty in achieving large-scale industrial mass production. Summary of the Invention

[0008] The purpose of this invention is to provide a smart glass encapsulation substrate system with built-in stress sensing and its preparation method, which solves the technical problems of traditional glass encapsulation substrates that cannot monitor internal dynamic thermal shear stress in real time and in situ, have poor bonding force at the interface of the sensing structure, and lack compatibility with mass production processes.

[0009] The objective of this invention is achieved through the following technical solution: A smart glass packaging substrate system with built-in stress sensing and its preparation method are disclosed. The system adopts a symmetrical three-layer composite substrate architecture, consisting of an upper composite buffer layer, a glass core layer, and a lower composite buffer layer from top to bottom. The upper and lower composite buffer layers each have a thin-film piezoelectric sensing array embedded inside. The thin-film piezoelectric sensing array is completely embedded inside the corresponding buffer layer and is used to collect dynamic thermal shear stress generated at the multi-layer interface inside the substrate during the packaging process in real time.

[0010] As a further improvement of the present invention, the glass core layer is made of borosilicate glass or high aluminosilicate glass substrate, with a thickness of 0.15~0.5mm, a coefficient of thermal expansion of 0.3~0.8ppm / ℃, a dielectric constant Dk≤4.0, and a dielectric loss Df≤0.001; the upper and lower surfaces of the glass core layer are both subjected to plasma activation treatment, and a high-density RDL redistribution channel and a blind via structure are reserved inside.

[0011] As a further improvement of the present invention, the upper composite buffer layer and the lower composite buffer layer are prepared using the same epoxy-modified buffer resin, with a single layer thickness of 10~30μm and a coefficient of thermal expansion between that of the glass core layer and the chip solder; the epoxy-modified buffer resin has a temperature resistance range of -55℃ to 180℃ after curing and an insulation resistance ≥10 Ω·cm. 14 Ω・cm, breakdown voltage ≥5kV.

[0012] As a further improvement of the present invention, the thin-film piezoelectric sensing array is first prepared by magnetron sputtering of a ZnO or AlN piezoelectric thin film with a thickness of 0.8~2.5μm and a sputtering thickness uniformity deviation ≤±0.05μm; then, the piezoelectric thin film is etched by a stepwise wet etching process to form the thin-film piezoelectric sensing array; the sensing array of the thin-film piezoelectric sensing array is arranged in a matrix uniform arrangement, and the metal electrodes of all sensing units are led out to the test pad area at the edge of the carrier board.

[0013] As a further improvement of the present invention, the upper thin-film piezoelectric sensing array in the upper composite buffer layer and the lower thin-film piezoelectric sensing array in the lower composite buffer layer are arranged in a mirror symmetrical manner along the glass core layer, and the sensing units of the upper and lower layers are vertically corresponding one-to-one, which can synchronously collect the bidirectional thermal shear stress at the upper and lower interfaces of the substrate and restore the complete stress gradient in the thickness direction of the substrate.

[0014] A method for fabricating a smart glass encapsulation substrate system with built-in stress sensing, completed entirely in a Class 1000 cleanroom, includes the following steps: Step 1: Pre-treatment and alignment mark making of glass core layer: Cut, chamfer, wet clean, pre-bake at low temperature, and activate double-sided oxygen plasma treatment of the glass core layer substrate, and make optical positioning mark points at the four corners of the substrate. Step 2: Fabrication of the lower thin-film piezoelectric sensing array: The bottom metal electrode and the piezoelectric thin film are sputtered sequentially on the lower surface of the glass core layer. The lower thin-film piezoelectric sensing array and the first metal circuit are formed by photolithography and etching, and the first metal electrode is led out to the edge of the substrate. Step 3: Slit coating and pre-baking of the lower composite buffer layer: The lower epoxy-modified buffer resin is prepared by slit coating process, which completely covers the lower thin film piezoelectric sensing array, and the lower composite buffer layer is formed by segmented pre-baking. Step 4: Fabrication of the upper mirror-symmetric piezoelectric sensing array: Flip the glass core layer, and fabricate an upper thin-film piezoelectric sensing array and a second metal circuit that are mirror-symmetric to the lower thin-film piezoelectric sensing array, referring to the lower layer process parameters, and lead the second metal electrode to the edge of the carrier plate; Step 5: Coating and pre-baking of the upper composite buffer layer: The upper epoxy-modified buffer resin is prepared by slit coating process to completely cover the upper thin film piezoelectric sensing array, and the upper composite buffer layer is formed by segmented pre-baking. Step 6: Segmented high-temperature integral thermosetting: The upper and lower composite buffer layers are integrally thermoset and molded under a nitrogen atmosphere using a stepped heating process.

[0015] As a further improvement of the present invention, in step 1, the oxygen plasma activation treatment controls the oxygen flow rate to 50 sccm, the bombardment power to 300 W, and the single-sided treatment time to 120 s, and the surface water contact angle is reduced to below 10° after treatment; the size of the optical positioning Mark point is 100 μm × 100 μm, and the etching depth is 0.05 μm.

[0016] As a further improvement of the present invention, in step 6, the segmented high-temperature curing is carried out in a nitrogen atmosphere, and the oxygen content in the cavity is ≤100ppm; the heating rate is 1℃ / min, and the temperature is successively maintained at 120℃ for 60min, 140℃ for 90min, and 160℃ for 120min; after curing, the temperature is gradually reduced to room temperature at a rate of 0.8℃ / min.

[0017] As a further improvement of the present invention, it also includes step 7: automatic electrical probe testing and finished product sorting: detecting the conductivity and piezoelectric response sensitivity of all thin-film piezoelectric sensing arrays, rejecting defective products and completing finished product classification and data traceability.

[0018] As a further improvement of the present invention, in step 7, the detection and judgment criteria are: single-channel on-resistance ≤ 50Ω, piezoelectric output voltage in the range of 10~50mV under standard deformation of 0.02%, and piezoelectric response voltage fluctuation range ≤ ±5mV.

[0019] The above technical solution has the following beneficial effects: 1. By embedding a thin-film piezoelectric sensing array inside the buffer layer, dynamic thermal shear stress at the internal interface of the package can be acquired online while the chip is in operation. This overcomes the limitations of traditional offline destructive testing and surface strain gauges, which cannot sense internal stress. The stress evolution process can be traced, greatly reducing the difficulty of locating the root cause of the fault.

[0020] 2. The vertically aligned, mirror-symmetrical double-layer thin-film piezoelectric sensing array synchronously acquires bidirectional shear stress, which can restore the complete stress gradient in the thickness direction of the substrate, eliminate data offset of single-sided detection, and achieve a stress detection resolution of up to 0.01MPa. The positioning accuracy of stress concentration areas is ≤50μm.

[0021] 3. Thin-film piezoelectric sensing arrays are integrated with the substrate through sputtering and coating processes. The film adhesion is ≥6N / mm², and there is no risk of delamination under long-term thermal cycling. It does not increase the packaging thickness, which meets the development needs of ultra-thin and miniaturized adapter devices. Attached Figure Description

[0022] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0023] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0024] Figure 1 This is a schematic diagram of the process provided by the present invention.

[0025] Figure 2 This is a schematic diagram of the structure provided in step 1 of the present invention.

[0026] Figure 3 This is a schematic diagram of the structure during the preparation process in step 2 of the present invention.

[0027] Figure 4 This is a schematic diagram of the structure provided for step 2 of the present invention.

[0028] Figure 5 This is a schematic diagram of the slit coating process provided in step 3 of the present invention.

[0029] Figure 6 This is a schematic diagram of the structure provided in step 3 of the present invention.

[0030] Figure 7 This is a structural schematic diagram provided for step 4 of the present invention.

[0031] Figure 8 This is a structural schematic diagram provided for step 5 of the present invention.

[0032] In the picture: 1. Glass core layer; 11. Mark point; 2. Lower Ti / Au composite conductive layer; 3. Piezoelectric thin film; 4. Lower thin film piezoelectric sensing array; 5. First metal line; 51. Second metal line; 6. First metal electrode; 7. Lower composite buffer layer; 8. Upper thin film piezoelectric sensing array; 9. Second metal electrode; 10. Upper composite buffer layer; 21. Slurry supply station; 22. Precision coating nozzle; 23. Slit mechanism; 24. Film cutter; 25. Coating machine platform. Detailed Implementation

[0033] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0034] like Figure 1 As shown, a method for fabricating a smart glass encapsulation substrate system with built-in stress sensing is completed entirely in a Class 1000 cleanroom, and includes the following steps: Step 1: Pre-treatment of glass core layer and fabrication of alignment marks The core of this step is to complete the cleaning, surface activation, and positioning mark production of the glass core layer, eliminating surface impurities and improving interface adhesion.

[0035] First, incoming material inspection is conducted. Borosilicate glass or high-alumina silica glass is selected as the substrate for the glass core layer 1. The thickness, dimensions, and warpage are checked, and defective wafers with chipped edges, scratches, or holes are rejected. Requirements: The initial warpage of the substrate must be ≤5μm / 100mm. After processing, the surface must be free of particles, oil stains, water stains, and visible scratches, and free of chipped edges, missing corners, and microcracks. The glass core layer 1 has pre-reserved high-density RDL redistribution channels and blind / buried via structures to meet the high-density wiring requirements of 2.5D / 3D chip stacking.

[0036] Then, an ultra-thin glass slicer is used to cut the substrate to the standard size of the carrier board, and the four sides of the substrate are chamfered to remove sharp burrs. During the cutting process, the internal RDL redistribution channel and blind buried via structure are not damaged.

[0037] The process then proceeds to the wet cleaning step, which involves alkaline washing, pure water spraying, ultrasonic rinsing, and isopropanol dehydration. The ultrasonic cleaning power is set to 200W, and the cleaning time for a single batch is 5 minutes. After cleaning, the product is sent to a dust-free oven for low-temperature pre-drying. The temperature is set to 80℃ and held for 10 minutes to remove surface moisture. After removal, the product is allowed to cool naturally to room temperature.

[0038] Next, oxygen plasma activation treatment is performed on both sides of the substrate. Plasma bombardment is performed alternately on the front and back sides, with the oxygen flow rate controlled at 50 sccm and the bombardment power at 300W. The treatment time for each side is 120s. After treatment, the surface water contact angle needs to be reduced to below 10°.

[0039] Finally, through exposure, development, and etching processes using an optical alignment exposure machine, square optical positioning Mark points 11 are fabricated at the four corners of the substrate. The size of a single Mark point 11 is 100μm×100μm, and the etching depth is 0.05μm. Requirements: the Mark point 11 pattern is complete, the edges are free of jagged edges, and there is no offset in optical recognition.

[0040] The marked substrate is sealed in a cleanroom container and temporarily stored under vacuum to avoid secondary contamination, and must be transferred to the next sputtering process within 1 hour.

[0041] The glass core layer 1 prepared in this step is as follows: Figure 2 As shown, its thickness is 0.15~0.5mm, its thermal expansion coefficient is 0.3~0.8ppm / ℃, its dielectric constant Dk≤4.0, and its dielectric loss Df≤0.001; it has reserved high-density RDL rewiring channels and blind via structures inside to meet the high-density wiring requirements of 2.5D / 3D chip stacking.

[0042] Step 2: Fabrication of the lower thin-film piezoelectric sensing array This step involves sputtering and photolithography on the lower surface of the glass core layer 1 to form a lower matrix-type thin-film piezoelectric sensing array and metal electrodes.

[0043] During operation, the glass core layer 1 is first flipped over and vacuum-adsorbed and fixed onto the magnetron sputtering stage. Automatic optical alignment is achieved through the four corner Mark points 11. First, a bottom metal electrode is sputtered to deposit the Ti / Au composite conductive layer 2, with a Ti layer thickness of 0.1 μm and an Au layer thickness of 0.05 μm. The vacuum level of the sputtering chamber is controlled to be ≤5 × 10⁻⁶ throughout the sputtering process. -4 Pa. Subsequently, piezoelectric thin films 3 made of ZnO (zinc oxide) or AlN (aluminum nitride) were continuously sputtered, controlling the thickness of the piezoelectric thin film 3 within the range of 0.8~2.5 μm, with a sputtering thickness uniformity deviation ≤ ±0.05 μm. The prepared products are as follows... Figure 3 As shown.

[0044] After the piezoelectric thin film 3 was deposited, a 1.2 μm thick photoresist was spin-coated onto the surface and pre-baked at 90°C for 8 min to cure the photoresist layer. The pattern was then exposed according to the sensor array layout, with the exposure energy set to 120 mJ / cm². After developing and removing the unexposed photoresist layer, the area to be etched was exposed.

[0045] A step-by-step wet etching process was employed. First, the piezoelectric thin film 3 was etched to form the lower thin-film piezoelectric sensing array 4. Then, the lower Ti / Au composite conductive layer 2 was etched to form the first metal circuit 5. The etching temperature was controlled at 30℃ and the etching rate at 0.03 μm / s. After etching, the remaining photoresist was stripped off, and the array was rinsed with pure water, dried, and then sent to an AOI optical inspection instrument for a full inspection of the pattern integrity of the lower thin-film piezoelectric sensing array 4. The first metal electrode 6 of the lower thin-film piezoelectric sensing array 4 was then led out to the test pad area at the edge of the glass core layer 1. The resulting product is shown below. Figure 4 As shown.

[0046] In this step, the lower thin-film piezoelectric sensing array 4 has a single sensing unit size of 50μm×50μm, a unit spacing of 100μm, an array pattern alignment deviation of ≤±3μm, a film adhesion of ≥6N / mm², and no tape detachment. The first metal line 5 is free of open circuits, short circuits, gaps, and burrs, and the first metal electrode 6 is completely connected to the electrode pad area at the edge of the glass core layer 1. Before production, the target material must be cleaned and the cavity degassed. The etching waste liquid must be replaced regularly to prevent over-etching of the lines. The piezoelectric film should not be exposed to the environment for more than 30 minutes to avoid moisture affecting the piezoelectric performance.

[0047] Step 3: Slit coating and pre-baking of the lower composite buffer layer This step uses a slot coating process to prepare the lower epoxy-modified buffer resin, which completely covers the lower thin-film piezoelectric sensing array 4. After pre-baking to remove the solvent, the lower composite buffer layer 7 is formed.

[0048] like Figure 5 As shown, during operation, the substrate is first vacuum-fixed onto the coating machine stage 25, and the automatic identification of the Mark points completes the coating alignment; the epoxy modified buffer resin is stirred and degassed for 30 minutes in advance to eliminate internal air bubbles. After curing, the resin has a temperature resistance range of -55℃ to 180℃ and a volume insulation resistance ≥10 Ω·cm. 14 Ω・cm.

[0049] The slurry supply station 21 delivers epoxy-modified buffer resin slurry to the precision coating nozzle 22. The slurry is output through the slit mechanism 23 to the coating die head for uniform resin coating. This fully covers the lower thin-film piezoelectric sensing array 4 and forms a lower composite buffer layer 7 on the lower surface of the glass core layer 1. The coating speed is controlled at 20 mm / s, the slit gap at 20 μm, and the target thickness of a single layer is controlled at 10~30 μm. After coating, the film is cut by the film cutter 24 to complete the coating operation. The structure of the prepared product is as follows: Figure 6 As shown.

[0050] After coating, the coating is placed in a dust-free hot air pre-drying oven. A segmented hot air pre-drying process is used to slowly evaporate the organic solvent. The temperature is first held at 90℃ for 15 minutes, then increased to 110℃ and held for 10 minutes. The pre-drying heating rate is ≤2℃ / min to avoid rapid heating that could cause coating blistering. After pre-drying, the coating is cooled to room temperature, and the coating thickness is measured using a film thickness gauge. The surface condition is checked using a visual CCD to confirm that the buffer layer completely covers all piezoelectric sensing units on the lower layer, with no exposed film, film thickness uniformity deviation ≤±1μm, no bubbles, pinholes, shrinkage marks, or flow marks on the coating surface, no delamination at the interface between the coating and the glass / piezoelectric film, and the edge adhesive overflow width ≤0.2mm before being transferred to the upper layer process.

[0051] The humidity in the workshop for this process needs to be controlled between 40% and 60% to prevent the resin from absorbing moisture. Once opened, the resin must be used within 24 hours. Hard objects are prohibited from touching the surface of the resin that is not completely dry.

[0052] Step 4: Fabrication of the upper-layer mirror-symmetric piezoelectric sensing array This step involves flipping the glass core layer 1 to fabricate an upper thin-film piezoelectric sensing array 8, which is mirror-symmetrical to the lower thin-film piezoelectric sensing array 4, achieving a vertical one-to-one correspondence between the upper and lower sensing units. Specifically: The glass core layer 1 is flipped using an automatic flipping machine so that the upper surface of the glass core layer 1 faces upward. During the flipping process, the vacuum pen only contacts the blank area of ​​the glass core layer and does not touch the lower composite buffer layer 7. After the flipping is completed, secondary alignment is performed using optical mark points to calibrate the sputtering stage coordinates.

[0053] Subsequently, referencing the same process parameters as the lower thin-film piezoelectric sensing array 4, Cu / Au bottom conductive electrodes were sputtered sequentially, followed by the deposition of ZnO (zinc oxide) or AlN (aluminum nitride) piezoelectric thin films of the same specifications. Then, through spin-coating photoresist, pre-baking, pattern exposure, development, etching, and desizing and drying processes, the fabrication of the second metal line 51 and the upper thin-film piezoelectric sensing array 8 was completed. During the process, the vertical alignment of the upper and lower arrays was strictly controlled, with a deviation ≤ ±4μm, ensuring a one-to-one vertical correspondence between the two sensing units, and that the array unit size and spacing were perfectly mirror-matched with the lower layer. Then, the second metal electrode 9 of the upper thin-film piezoelectric sensing array 8 was led out to the electrode pad area at the edge of the glass core layer 1. The fabricated product structure is as follows: Figure 7 As shown.

[0054] In this case, the upper thin-film piezoelectric sensing array 8 and the lower thin-film piezoelectric sensing array 4 are distributed in a mirror-symmetric manner and are collectively referred to as thin-film piezoelectric sensing arrays; the first metal electrode 6 and the second metal electrode 9 are distributed in a mirror-symmetric manner and are collectively referred to as metal electrodes; the second metal line 51 and the first metal line are distributed in a mirror-symmetric manner and are collectively referred to as metal lines.

[0055] After preparation, the pattern of the upper thin film piezoelectric sensing array 8 is detected by AOI and mirror symmetry verification is performed with the lower thin film piezoelectric sensing array 4 to confirm that there are no open circuits, short circuits and missing patterns in the upper circuit, and that the piezoelectric film is free of scratches and contamination. Products that fail to meet the alignment requirements are isolated separately and are prohibited from flowing into the next coating process. Before sputtering, it must be confirmed that there is no dust and resin debris contamination on the upper surface of the glass core layer 1.

[0056] Step 5: Coating and pre-baking of the composite buffer layer This step uses a slot coating process to prepare the upper epoxy-modified buffer resin, which completely covers the upper thin-film piezoelectric sensing array 8. After pre-baking to remove the solvent, the upper composite buffer layer 10 is formed.

[0057] During the process, the substrate is positioned and fixed. A standard coating pattern consistent with the lower composite buffer layer 7 is retrieved. Epoxy-modified buffer resin of the same batch and parameters as the lower composite buffer layer 7 is used. After thorough stirring and degassing, the upper thin-film piezoelectric sensing array 8 is fully covered using a slot coater. The coating direction is consistent with that of the lower composite buffer layer 7 to reduce internal curing stress. After coating, a segmented pre-baking process identical to that of the lower composite buffer layer 7 is used to remove the internal solvent of the resin, resulting in the prepared material as shown in the image. Figure 8 The product structure shown.

[0058] After cooling, the thickness and surface appearance of the upper composite buffer layer 10 are inspected. The thickness range of the upper composite buffer layer 10 is controlled to be consistent with that of the lower composite buffer layer 7, which is 10~30μm. The thickness difference between the upper composite buffer layer 10 and the lower composite buffer layer 7 is ≤2μm, and the overall flatness of the coating is ≤3μm.

[0059] In terms of quality requirements, the composite buffer layer 10 completely encapsulates the upper thin-film piezoelectric sensing array, with no exposed sensing structure. The coating is free of bubbles, scratches, and particulate impurities, and the resin and piezoelectric film interface are tightly bonded with no risk of delamination. The pre-baked semi-finished products must be stored individually to avoid coating adhesion. If large areas of bubbles appear, the entire piece must be scrapped and cannot be reworked or repaired.

[0060] Step 6: Segmented high-temperature integral thermosetting This step involves segmented, stepped heating to cure the lower composite buffer layer 7 and the upper composite buffer layer 10, releasing the coating internal stress and forming an integrated three-layer intelligent glass encapsulation carrier plate (hereinafter referred to as: carrier plate).

[0061] First, the semi-finished wafers are placed on a high-temperature resistant graphite carrier, ensuring that the wafers are isolated and do not contact each other. Then, they are placed in a segmented high-temperature nitrogen oven. Nitrogen purging is performed first, with nitrogen continuously introduced at a flow rate of 20 L / min until the oxygen content in the chamber drops to ≤100 ppm to prevent oxidation and blackening of the metal electrodes at high temperatures. Next, a stepped temperature-curing process is executed, with the heating rate controlled at 1℃ / min throughout. The substrate is held at 120℃ for 60 min, 140℃ for 90 min, and 160℃ for 120 min in three separate stages. After curing, the substrate is slowly cooled in steps at a rate of 0.8℃ / min until it is completely cooled to room temperature before being removed. After curing, the overall warpage and interface condition of the carrier are tested. The buffer resin must be completely cured, with no stickiness on the surface. The overall warpage of the carrier should be ≤8μm / 100mm. There should be no delamination, bubbles, or peeling at the interface between the glass core layer 1 and the upper composite buffer layer 10 and lower composite buffer layer 7. The insulation resistance of the cured carrier should be ≥10 Ω. 14 Ω・cm, breakdown voltage ≥5kV.

[0062] Rapid heating and cooling are strictly prohibited in this process to avoid excessive curing stress caused by large temperature differences, which can lead to microcracks in the glass. The oven needs to be calibrated regularly to ensure that the temperature difference inside the cavity is ≤±3℃. After curing, allow it to cool naturally and avoid sudden cooling by air.

[0063] Step 7: Automated electrical probe testing and finished product sorting This step automatically detects the conductivity and piezoelectric response sensitivity of all thin-film piezoelectric sensing arrays, eliminates defective products, and completes finished product classification and full-process data traceability.

[0064] The cured substrate is fed into a fully automated pin-doping machine. A CCD automatically identifies and positions the mark points, controlling the probe module to precisely align with the electrode pads on the substrate edge. The probe diameter is 25μm, and the probe pressure is set to 0.15N. Subsequently, all thin-film piezoelectric sensing arrays are scanned row by row and cell by cell. First, the continuity resistance of each channel is detected, then a standard micro-deformation is applied to the substrate, and the piezoelectric output voltage is collected. The test environment is controlled at a constant temperature of 25℃ and humidity of 45%. The judgment criteria are: single-channel continuity resistance ≤50Ω, piezoelectric output voltage within the 10~50mV range under a standard deformation of 0.02%, and piezoelectric response voltage fluctuation range ≤±5mV.

[0065] After inspection, the system automatically distinguishes between good and defective products, marking the defective products with their location. Good products are then automatically sorted and barcoded before being stored, while defective products are stored in separate areas to prevent mixing with good products. All inspection data is automatically stored, enabling full-process traceability. Qualified finished products must have no probe punctures or metal detachment on their electrode pads. Probes must be cleaned and replaced regularly during this process to prevent oxidation and misjudgments. The equipment must be preheated for 30 minutes before inspection to ensure stable signal acquisition.

[0066] like Figure 8 As shown, a smart glass packaging substrate system with built-in stress sensing is fabricated using the above method. It employs a symmetrical three-layer composite substrate architecture, consisting of an upper composite buffer layer 10, a glass core layer 1, and a lower composite buffer layer 7, arranged from top to bottom. Both the upper composite buffer layer 10 and the lower composite buffer layer 7 embed thin-film piezoelectric sensing arrays. These thin-film piezoelectric sensing arrays are completely embedded within the corresponding upper composite buffer layer 10 and lower composite buffer layer 7, and are used to collect dynamic thermal shear stress generated at the multi-layer interfaces within the substrate during the entire packaging process.

[0067] Furthermore, the glass core layer 1 is made of borosilicate glass or high aluminosilicate glass substrate with a thickness of 0.15~0.5mm, a coefficient of thermal expansion of 0.3~0.8ppm / ℃, a dielectric constant Dk≤4.0, and a dielectric loss Df≤0.001. The upper and lower surfaces of the glass core layer 1 are plasma activated. The glass core layer 1 has reserved high-density RDL redistribution channels and blind / buried via structures to meet the high-density wiring requirements of 2.5D / 3D chip stacking.

[0068] Furthermore, the upper composite buffer layer 10 and the lower composite buffer layer 7 are prepared using the same epoxy-modified buffer resin, with a single-layer thickness of 10~30μm. Their coefficient of thermal expansion is between that of the glass core layer 1 and the chip solder. The epoxy-modified buffer resin has a temperature resistance range of -55℃ to 180℃, and its insulation resistance after curing is ≥10¹⁰. 4 Ω・cm, breakdown voltage ≥5kV; the thin-film piezoelectric sensing array is completely encapsulated and embedded inside the epoxy-modified buffer resin through a coating process.

[0069] Furthermore, the thin-film piezoelectric sensing array uses a ZnO (zinc oxide) or AlN (aluminum nitride) piezoelectric thin film prepared by magnetron sputtering, with a film thickness of 0.8~2.5μm and a sputtering thickness uniformity deviation of ≤±0.05μm. The sensing array is arranged in a matrix uniformly, with a single sensing unit size of 50μm×50μm and a unit spacing of 100μm. The metal electrodes of all sensing units are led out to the test pad area at the edge of the substrate. The piezoelectric thin film relies on the piezoelectric effect to convert substrate deformation into a voltage signal output that is linearly related to thermal shear stress.

[0070] Furthermore, the upper thin-film piezoelectric sensing array 8 in the upper composite buffer layer 10 and the lower thin-film piezoelectric sensing array 4 in the lower composite buffer layer 7 are arranged in a mirror symmetrical manner along the glass core layer 1. The sensing units of the upper and lower layers are vertically corresponding one-to-one, which can synchronously collect the bidirectional thermal shear stress of the upper and lower interfaces of the substrate, restore the complete stress gradient in the thickness direction of the substrate, and eliminate the data offset caused by unilateral detection. Example 1

[0071] This embodiment provides a standard-specification intelligent glass packaging carrier system with built-in stress sensing, suitable for high-end stacked packaging scenarios such as 3D memory chips. Its specific structure and fabrication process are as follows: 1. Structural Composition Glass core layer: made of borosilicate glass substrate with a thickness of 0.3mm and a coefficient of thermal expansion CTE=0.5ppm / ℃. Both the upper and lower surfaces are treated with oxygen plasma activation. The glass core layer has reserved RDL redistribution and blind buried hole channels.

[0072] Thin-film piezoelectric sensing array: The piezoelectric thin film is made of AlN (aluminum nitride) material with a sputtering thickness of 1.2μm; the upper and lower piezoelectric arrays are arranged in a mirror symmetrical manner, with an array unit size of 50μm×50μm and a unit spacing of 100μm; the metal electrodes adopt a Ti / Au composite conductive layer, and all electrodes are uniformly led out to the edge test pad of the long side of the carrier board.

[0073] Upper and lower composite buffer layers: both are made of epoxy-modified buffer resin, with a single layer thickness of 20μm and a temperature resistance range of -55℃ to 160℃ after curing, completely covering the upper and lower thin film piezoelectric sensing arrays.

[0074] 2. Preparation process Prepared strictly according to the following 7 standardized procedures: ① Glass substrate cleaning and activation: Incoming borosilicate glass substrates are inspected to remove defective products with chipped edges and scratches; they are then precisely cut to standard dimensions and chamfered on all four sides, followed by wet cleaning with alkaline washing, pure water spraying, ultrasonic rinsing, and isopropanol dehydration. They are then pre-baked at 80℃ for 10 minutes to remove moisture; subsequently, double-sided oxygen plasma activation is performed with an oxygen flow rate of 50 sccm, a power of 300W, and a single-sided treatment time of 120 seconds; finally, 100μm × 100μm optical positioning mark points are created at the four corners through exposure, development, and etching, and then temporarily stored in a vacuum.

[0075] ② Fabrication of the lower thin-film piezoelectric sensing array: The glass core layer is vacuum-adsorbed onto the sputtering stage with the lower surface facing upwards, and optically aligned using Mark points; Ti (0.1μm) / Au (0.05μm) bottom conductive electrodes are sputtered first, followed by continuous sputtering of a 1.2μm thick AlN piezoelectric film; a 1.2μm thick photoresist is spin-coated, pre-baked at 90℃ for 8 min, and the array pattern is exposed at an energy of 120mJ / cm²; after development, the piezoelectric film and the underlying metal lines are etched stepwise, the remaining photoresist is stripped off, and the image is cleaned and dried, and the integrity of the pattern is fully inspected by AOI.

[0076] ③ Coating of the lower composite buffer layer: Stir the epoxy modified buffer resin to degas for 30 minutes, and then coat it evenly on the surface of the lower sensor array at a speed of 20 mm / s using a slot coater, with a coating thickness of 20 μm; adopt a segmented pre-baking process: keep at 90℃ for 15 minutes and at 110℃ for 10 minutes to slowly evaporate the solvent; after cooling, check the film thickness and appearance, and transfer the film after confirming that there are no bubbles or pinholes.

[0077] ④ Fabrication of the upper thin-film piezoelectric sensing array: The substrate is flipped using an automatic flipping mechanism so that the upper surface of the glass core layer faces upward; the coordinates are calibrated by secondary optical alignment, and the sputtering, photolithography, and etching parameters are exactly the same as in step ② to fabricate an upper thin-film piezoelectric sensing array that is mirror-symmetrical to the lower thin-film piezoelectric sensing array, ensuring that the vertical alignment deviation of the upper and lower units is ≤ ±4μm.

[0078] ⑤ Coating of the upper composite buffer layer: Using the same coating and pre-baking parameters as in step ③, coat the upper 20μm thick epoxy buffer resin to completely cover the upper thin film piezoelectric sensing array; control the thickness difference between the upper and lower composite buffer layers to ≤2μm.

[0079] ⑥ Segmented high-temperature curing: Place the semi-finished product sheet on a high-temperature resistant graphite carrier and send it into a segmented high-temperature nitrogen oven; first, replace the nitrogen with oxygen until the oxygen content is ≤100ppm, and then cure by step temperature increase: 120℃ for 60min, 140℃ for 90min, and 160℃ for 120min, with a heating rate of 1℃ / min; after curing, cool down step by step at a rate of 0.8℃ / min, and after cooling to room temperature, take it out and test the warpage of the substrate.

[0080] ⑦ Automatic Electrical Needle Test: The carrier board is fed into the fully automatic needle dotting machine. After the CCD identifies and positions the mark, the probe module connects to the edge test pads. The continuity resistance and piezoelectric response voltage of the circuit are tested unit by unit. The continuity resistance threshold is ≤50Ω / single channel. The output voltage range is 10~50mV under the standard deformation of 0.02%. The system automatically determines good products and defective products. Good products are labeled with barcodes and put into storage. Defective products are marked with the defect location and stored in isolation.

[0081] 3. Performance Testing After the substrate prepared in this embodiment is packaged, it exhibits stable performance in thermal shock cycle tests from -40℃ to 150℃: the piezoelectric array signal output is continuous and uninterrupted, and the dynamic thermal shear stress at the interface between the glass core layer and the upper and lower composite buffer layers can be collected in real time, with a stress detection resolution of up to 0.01MPa; after 1000 consecutive thermal cycles, there is no delamination or open circuit phenomenon of the sensing unit, and the substrate is free from delamination and microcrack initiation, and the reliability meets the packaging requirements of high-end 3D memory chips. Example 2

[0082] This embodiment provides an ultra-thin smart glass packaging substrate system with built-in stress sensing, suitable for lightweight packaging scenarios of micro high-frequency photonic devices and radio frequency chips. Its specific structure and fabrication process are as follows: 1. Structural Composition Glass core layer: Made of ultra-thin borosilicate glass substrate with a thickness of 0.18mm and a coefficient of thermal expansion CTE=0.35ppm / ℃.

[0083] Thin-film piezoelectric sensing array: The piezoelectric thin film is made of ZnO (zinc oxide) material with a sputtering thickness of 0.9μm; the upper and lower layers are arranged in a symmetrical matrix, and the electrodes are led out to the test pads on the short side of the carrier board.

[0084] Upper and lower composite buffer layers: Low-modulus epoxy buffer resin is used, with a single layer thickness of 12μm, further reducing the overall thickness of the carrier plate.

[0085] 2. Preparation process The mass production process is as follows: glass substrate activation → sputtering of the lower ZnO thin film → coating of the lower composite buffer layer → fabrication of the upper thin film piezoelectric sensing array → coating of the upper composite buffer layer → low-temperature segmented curing at 125℃ → automated needle detection and sorting; the core operation logic of each process is the same as in Example 1. The sputtering power, coating rate and curing temperature parameters have been adjusted to adapt to the thin substrate to ensure that the thin glass is free from warping and microcracks.

[0086] 3. Performance Testing The ultrathin substrate prepared in this embodiment has an overall thickness of only 0.204 mm, which can meet the packaging requirements of micro high-frequency photonic devices; the piezoelectric array can capture the small shear stress generated by the temperature rise of the high-frequency chip in real time, and the positioning accuracy of the stress concentration area is ≤50μm; after batch process verification, the mass production yield of this product can reach 96.3%, and it can be applied on a large scale to micro radio frequency photonic packaging products.

[0087] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0088] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0089] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A smart glass encapsulation substrate system with built-in stress sensing and its fabrication method, characterized in that, A symmetrical three-layer composite substrate architecture is adopted, consisting of an upper composite buffer layer (10), a glass core layer (1), and a lower composite buffer layer (7) from top to bottom. The upper composite buffer layer (10) and the lower composite buffer layer (7) are both embedded with thin-film piezoelectric sensing arrays. The thin-film piezoelectric sensing arrays are completely buried inside the corresponding buffer layers and are used to collect dynamic thermal shear stress generated by the multi-layer interface inside the substrate during the packaging process in real time.

2. The intelligent glass encapsulation substrate system with built-in stress sensing according to claim 1, characterized in that, The glass core layer (1) is made of borosilicate glass or high aluminosilicate glass substrate with a thickness of 0.15~0.5mm, a thermal expansion coefficient of 0.3~0.8ppm / ℃, a dielectric constant Dk≤4.0, and a dielectric loss Df≤0.

001. The upper and lower surfaces of the glass core layer (1) are plasma activated and have high-density RDL redistribution channels and blind via structures reserved inside.

3. The intelligent glass encapsulation carrier system with built-in stress sensing according to claim 1, characterized in that, The upper composite buffer layer (10) and the lower composite buffer layer (7) are prepared using the same epoxy-modified buffer resin, with a single layer thickness of 10~30μm. Their coefficient of thermal expansion is between that of the glass core layer (1) and the chip solder. The epoxy-modified buffer resin has a temperature resistance range of -55℃ to 180℃ after curing, and an insulation resistance ≥10 Ω·cm. 14 Ω・cm, breakdown voltage ≥5kV.

4. The intelligent glass encapsulation substrate system with built-in stress sensing according to claim 1, characterized in that, The thin-film piezoelectric sensing array is first prepared by magnetron sputtering of ZnO or AlN material piezoelectric thin film (3) with a film thickness of 0.8~2.5μm and sputtering thickness uniformity deviation ≤±0.05μm; then the piezoelectric thin film is etched by step wet etching process to form thin-film piezoelectric sensing array; the sensing array of the thin-film piezoelectric sensing array is arranged in a matrix uniform arrangement, and the metal electrodes of all sensing units are led out to the test pad area at the edge of the carrier board.

5. The intelligent glass encapsulation carrier system with built-in stress sensing according to claim 1, characterized in that, The upper thin-film piezoelectric sensing array (8) in the upper composite buffer layer (10) and the lower thin-film piezoelectric sensing array (4) in the lower composite buffer layer (7) are arranged in a mirror symmetry along the glass core layer (1). The sensing units of the upper and lower layers are vertically corresponding one-to-one, and can synchronously collect the bidirectional thermal shear stress of the upper and lower interfaces of the substrate to restore the complete stress gradient in the thickness direction of the substrate.

6. A method for manufacturing a smart glass encapsulation substrate system with built-in stress sensing as described in any one of claims 1-5, characterized in that, The entire process is completed in a Class 1000 cleanroom and includes the following steps: Step 1: Pre-treatment of glass core layer and preparation of alignment marks: Cut, chamfer, wet clean, low temperature pre-bake, and double-sided oxygen plasma activation treatment are performed on the substrate of glass core layer (1). Optical positioning mark points (11) are made at the four corners of the substrate. Step 2: Fabrication of the lower thin film piezoelectric sensing array: The bottom metal electrode and the piezoelectric thin film (3) are sputtered sequentially on the lower surface of the glass core layer (1), and the lower thin film piezoelectric sensing array (4) and the first metal line (5) are formed by photolithography and etching, and the first metal electrode (6) is led out to the edge of the carrier plate; Step 3: Slit coating and pre-baking of the lower composite buffer layer: The lower epoxy modified buffer resin is prepared by slit coating process, which completely covers the lower thin film piezoelectric sensing array (4), and the lower composite buffer layer (7) is formed by segmented pre-baking. Step 4: Fabrication of upper layer mirror-symmetric piezoelectric sensing array: Flip the glass core layer (1), and fabricate an upper layer thin film piezoelectric sensing array (8) and a second metal line (51) that are mirror-symmetric to the lower layer thin film piezoelectric sensing array (4) with reference to the lower layer process parameters, and lead out the second metal electrode (9) to the edge of the carrier plate; Step 5: Coating and pre-baking of the upper composite buffer layer: The upper epoxy modified buffer resin is prepared by slit coating process to completely cover the upper thin film piezoelectric sensing array (8), and the upper composite buffer layer (10) is formed by segmented pre-baking. Step 6: Segmented high-temperature integral thermosetting: The upper composite buffer layer (10) and the lower composite buffer layer (7) are integrally thermoset and molded under a nitrogen atmosphere using a stepped heating process.

7. The preparation method according to claim 6, characterized in that, In step 1, the oxygen plasma activation treatment controls the oxygen flow rate to 50 sccm, the bombardment power to 300 W, and the single-sided treatment time to 120 s. After the treatment, the surface water contact angle is reduced to below 10°. The size of the optical positioning Mark point (11) is 100 μm × 100 μm, and the etching depth is 0.05 μm.

8. The preparation method according to claim 6, characterized in that, In step 6, the segmented high-temperature curing is carried out in a nitrogen atmosphere with an oxygen content of ≤100ppm in the chamber; the heating rate is 1℃ / min, and the temperature is successively maintained at 120℃ for 60min, 140℃ for 90min, and 160℃ for 120min; after curing, the temperature is gradually reduced to room temperature at a rate of 0.8℃ / min.

9. The preparation method according to claim 6, characterized in that, It also includes step 7: automatic electrical probe testing and finished product sorting: testing the conductivity and piezoelectric response sensitivity of all thin-film piezoelectric sensing arrays, rejecting defective products and completing finished product classification and data traceability.

10. The preparation method according to claim 9, characterized in that, In step 7, the detection criteria are: single-channel on-resistance ≤ 50Ω, piezoelectric output voltage within the range of 10~50mV under standard deformation of 0.02%, and piezoelectric response voltage fluctuation range ≤ ±5mV.

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