High-purity quartz boat for semiconductor vertical furnace and preparation method thereof

Abstract

The application discloses a high-purity quartz boat for a semiconductor vertical furnace and a preparation method thereof. The axial temperature distribution of a target semiconductor vertical furnace is obtained, and a bearing skeleton area, a wafer contact area and an axial heat compensation area are divided according to the axial temperature distribution, so that different quartz materials correspond to the requirements of high-temperature bearing, wafer contact and local heat response adjustment, respectively, and the performance is limited due to the fact that a single material simultaneously bears the functions of deformation resistance and low pollution. The transition connection section of the high-purity transparent quartz and the composite heat setting under the vertical full-load state further promote the connection transition and the thermal history matching between the functional areas, reduce the interface stress concentration caused by the direct connection of different quartz materials, and make the quartz boat form a stable material partition, connection state and axial heat response relationship under the high-temperature full-load working condition of the semiconductor vertical furnace, so as to take into account low pollution, low warping and low slot distance drift.

Description

Technical Field

[0001] This invention relates to the field of quartz process fixtures for semiconductor heat treatment, and particularly to a high-purity quartz carrier boat for a semiconductor vertical furnace and its preparation method. Background Technology

[0002] Semiconductor vertical furnaces are key pieces of equipment commonly used in heat treatment processes such as wafer oxidation, diffusion, annealing, and low-pressure chemical vapor deposition. Vertical furnaces typically have vertically arranged furnace tubes and heating zones distributed along the furnace tube axis. During heat treatment, wafers are usually supported by quartz boats and enter the reaction zone of the furnace tubes via a lifting mechanism. The quartz boats within the furnace not only serve to position and support the wafer array but also directly affect the spatial position of the wafers in the high-temperature atmosphere, inter-wafer spacing, heating uniformity, and cleanliness.

[0003] Quartz boats are generally made from high-purity quartz material, primarily because quartz offers high temperature resistance, low metal contamination, and good compatibility with semiconductor heat treatment processes. Existing quartz boats typically use high-purity quartz tubes, rods, or plates as raw materials, and are manufactured through steps such as cutting, grinding, grooving, drilling, flame welding, annealing, acid washing, ultrapure water cleaning, and clean packaging. While this method meets the basic forming requirements of ordinary quartz boats, its technical focus is largely on the geometric processing, welding, and surface cleaning of quartz components, with insufficient consideration given to the actual service conditions of quartz boats in semiconductor vertical furnaces.

[0004] In semiconductor vertical furnaces, the quartz boat is not in a typical static load-bearing environment, but rather operates under conditions of vertical placement, full wafer loading, axial temperature gradients, repeated heating and cooling, and an ultra-clean reaction atmosphere. The heating rates, holding temperatures, cooling responses, and radiative heat transfer conditions experienced by the upper, middle, and lower parts of the quartz boat are not entirely consistent, and the functions of the wafer slots, boat pillars, bottom support, and top connection also differ significantly. Specifically, the boat pillars and end frames primarily provide high-temperature support and creep resistance, while the wafer slots and support teeth primarily ensure low-contamination contact with the wafers. Furthermore, areas near the furnace with significant axial temperature differences require consideration of thermal response compensation.

[0005] In existing technologies, using a single high-purity quartz material to fabricate a monolithic quartz carrier typically makes it difficult to simultaneously meet both the requirements of high-temperature deformation resistance and low-contamination contact. Low-hydroxyl, high-temperature, high-viscosity quartz is beneficial for maintaining structural stability of the load-bearing framework at high temperatures, but it is not necessarily suitable as a direct wafer contact area. Ultra-high-purity synthetic quartz is beneficial for reducing the risk of metal contamination in the wafer contact area, but when used as a monolithic load-bearing framework, its high-temperature viscosity, hydroxyl content, and thermal response may not meet the deformation resistance requirements under long-term full-load thermal cycling. Therefore, a single-material approach easily creates a process contradiction between low contamination and deformation resistance.

[0006] Furthermore, existing technologies may consider using multiple quartz materials in different areas, but directly splicing or welding multiple quartz materials presents new problems. Although the main component of quartz materials from different sources and of different types is silicon dioxide, their hydroxyl content, high-temperature viscosity, bubble structure, radiation absorption characteristics, and thermal response behavior are not entirely consistent. If simply combined based on material names, residual stress concentration can easily occur at the joint interface, leading to microcracks, local warping, or particle release in the welded area during repeated temperature rises and falls. If opaque quartz is randomly placed at the end of the carrier boat or in non-contact areas, it may also disrupt the local thermal field inside the vertical furnace, causing asynchronous thermal deformation at different heights (upper, middle, and lower), thereby causing slot drift and abnormal automatic loading and unloading.

[0007] Therefore, there is an urgent need to provide a new method for preparing high-purity quartz carriers for semiconductor vertical furnaces. This method is not simply a matter of splicing together various quartz materials, but rather involves dividing the materials into functional zones based on the axial temperature distribution of the semiconductor vertical furnace and the service functional areas of the quartz carrier. It also incorporates axial thermal compensation and composite thermal shaping to adapt to the high-temperature full-load thermal cycling conditions of the semiconductor vertical furnace. Summary of the Invention

[0008] This invention overcomes the shortcomings of the prior art and provides a high-purity quartz carrier boat for semiconductor vertical furnaces and its preparation method. By functionally partitioning low-hydroxyl high-purity quartz, ultra-high-purity synthetic quartz, and high-purity opaque quartz, as well as using a high-purity transparent quartz transition connection section and composite heat setting under an axial gradient temperature field, the material configuration, connection position, and heat treatment state of the quartz carrier boat are matched with the axial temperature distribution of the target semiconductor vertical furnace.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a method for preparing a high-purity quartz boat for a semiconductor vertical furnace, comprising the following steps:

[0010] S1. Obtain the axial temperature distribution of the target semiconductor vertical furnace and divide the quartz boat into a load-bearing frame area, a wafer contact area, and an axial thermal compensation area.

[0011] S2. The load-bearing skeleton area components are prepared using low-hydroxyl high-purity quartz, the wafer contact area components are prepared using ultra-high purity synthetic quartz, and the axial thermal compensation area components are prepared using high-purity opaque quartz.

[0012] S3. Connect the wafer contact area component to the load-bearing frame area component through a high-purity transparent quartz transition connection section, and connect the axial thermal compensation area component to the upper end, lower end or axial temperature deviation area of ​​the load-bearing frame area component to obtain a pre-assembled quartz carrier.

[0013] S4. The pre-assembled quartz carrier is placed vertically and a simulated wafer or equivalent load is loaded into it. Composite thermal shaping is then performed in an axial gradient temperature field.

[0014] S5. The composite heat-set quartz carrier is sequentially acid-washed, ultrapure water-washed, dried, and cleanly packaged to obtain the high-purity quartz carrier for semiconductor vertical furnace.

[0015] In a preferred embodiment of the present invention, in step S1, the axial temperature distribution includes the upper end temperature, middle temperature and lower end temperature of the quartz boat loading area in the target semiconductor vertical furnace. The measurement temperature range of the axial temperature distribution is 600-1250℃, the measurement interval is 20-150mm and the measurement time is 10-120min.

[0016] In a preferred embodiment of the present invention, in step S2, the low-hydroxyl high-purity quartz has an OH content of 0.1-20 ppm, a SiO2 content of ≥99.99%, a Na content of ≤0.5 ppm, a K content of ≤0.5 ppm, a Fe content of ≤0.5 ppm, and an Al content of ≤20 ppm.

[0017] In a preferred embodiment of the present invention, in step S2, the ultra-high purity synthetic quartz has a SiO2 content ≥99.995%, a Na content ≤0.1ppm, a K content ≤0.1ppm, a Fe content ≤0.1ppm, an Al content ≤5ppm, and an OH content of 50-1200ppm.

[0018] In a preferred embodiment of the present invention, in step S2, the high-purity opaque quartz has a SiO2 content ≥99.99%, a bubble volume fraction of 1-15%, an average bubble diameter of 5-80 μm, and a thickness of 1-8 mm.

[0019] In a preferred embodiment of the present invention, in step S3, the SiO2 content of the high-purity transparent quartz transition connection section is ≥99.99%, the length is 3-30mm, and the diameter or width is 2-15mm. The distance between the connection point of the high-purity transparent quartz transition connection section and the wafer contact area component is 5-40mm from the bottom of the wafer groove.

[0020] In a preferred embodiment of the present invention, in step S3, the wafer contact area component includes wafer grooves or wafer support teeth, wherein the groove spacing of the wafer grooves or wafer support teeth is 2-8mm, the groove width is 0.4-2.5mm, the groove depth is 0.5-5mm, and the groove opening radius is 0.05-0.5mm.

[0021] In a preferred embodiment of the present invention, in step S4, the mass of a single simulated wafer or equivalent load is 5-250g, the number of wafers loaded is 25-200, the composite heat setting temperature is 800-1250℃, the holding time is 20-240min, the heating rate is 1-10℃ / min, and the cooling rate is 0.5-8℃ / min.

[0022] In a preferred embodiment of the present invention, in step S5, the pickling uses one or more of HF, HNO3, and HCl, with HF mass concentration of 0.1-10%, HNO3 mass concentration of 5-40%, and HCl mass concentration of 5-30%. The pickling temperature is 20-80℃, and the pickling time is 5-120 min. The ultrapure water used for cleaning has a resistivity ≥15 MΩ·cm, and the cleaning time is 10-180 min. The drying temperature is 60-180℃, and the drying time is 20-240 min.

[0023] The present invention also provides a high-purity quartz carrier boat for a semiconductor vertical furnace, which is prepared by any of the above-described preparation methods and includes a load-bearing frame region, a wafer contact region, and an axial thermal compensation region. The load-bearing frame region includes a boat column, a bottom support portion, and a top connecting portion. The wafer contact region includes wafer grooves or wafer support teeth. The axial thermal compensation region includes a high-purity opaque quartz ring, a high-purity opaque quartz sheet, or a high-purity opaque quartz segment.

[0024] This invention addresses the shortcomings of the prior art and has the following beneficial effects:

[0025] (1) This invention provides a method for preparing a high-purity quartz carrier for a semiconductor vertical furnace. By obtaining the axial temperature distribution of the target semiconductor vertical furnace and dividing it into a load-bearing skeleton area, a wafer contact area and an axial thermal compensation area, different quartz materials are respectively assigned to the high-temperature load-bearing, wafer contact and local thermal response adjustment requirements, avoiding the limitation of performance caused by a single material simultaneously undertaking the functions of anti-deformation and low pollution. The high-purity transparent quartz transition connection section and the composite thermal shaping under vertical full load further promote the connection transition and thermal history matching between the functional areas, reduce the interface stress concentration caused by the direct connection of different quartz materials, and enable the quartz carrier to form a stable material partition, connection state and axial thermal response relationship under the high temperature full load condition of the semiconductor vertical furnace, thereby taking into account low pollution, low warpage and low slot drift.

[0026] (2) In this invention, when the bubble volume fraction of high-purity opaque quartz is within the appropriate range, its internal bubble structure can change the radiation absorption, scattering and heat transfer state of the axial thermal compensation zone, thereby reducing the difference in heating and cooling response between the lower end and the middle of the carrier boat; the acquisition of the axial temperature distribution of the target vertical furnace further promotes the matching of the bubble structure with the specific thermal field deviation position, avoiding insufficient compensation due to excessively low bubble volume fraction or excessive local thermal response due to excessively high bubble volume fraction, so that the axial thermal compensation zone can adjust the local thermal drift without damaging the cleanliness of the wafer contact area, thereby reducing warpage under high temperature full load and slot drift after thermal cycling.

[0027] (3) In this invention, when the length of the high-purity transparent quartz transition connection section is within the appropriate range, a continuous geometric connection and thermal response transition can be formed between the low-hydroxyl high-purity quartz load-bearing skeleton area and the ultra-high-purity synthetic quartz wafer contact area, reducing the interface stress concentration caused by the direct connection of different quartz materials; the length of the connection section is matched with the wafer slot position, the boat column connection position and the composite heat-setting state, further promoting the welding area to move away from the direct contact path of the wafer and maintaining the stable positioning of the slot, so that the functional partitioning of various quartz materials is transformed from simple splicing into a stable connection structure, thereby reducing particle release, pollution migration and slot pitch drift. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a flowchart of a method for preparing a high-purity quartz boat for a semiconductor vertical furnace according to an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein. Therefore, the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0032] Several specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways than those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0033] This invention provides a high-purity quartz boat for semiconductor vertical furnaces and its preparation method. This method is applicable to quartz boats used in semiconductor vertical furnaces to support silicon wafers, wafers, or equivalent sheet-like substrates, and is particularly suitable for vertically loaded quartz boats used in high-temperature heat treatment processes such as oxidation, diffusion, annealing, and low-pressure chemical vapor deposition. The quartz boat can be used in semiconductor vertical furnaces corresponding to 4-inch, 6-inch, 8-inch, or 12-inch wafers, and its number of boat columns, number of slots, and end support structure can be adjusted according to the furnace tube size, number of wafers, and loading method.

[0034] Existing quartz carriers are typically manufactured from a single high-purity quartz material through cutting, grinding, grooving, welding, annealing, and cleaning. While this method is technologically mature, its material configuration prioritizes overall carrier uniformity, failing to adequately differentiate the functional requirements of load-bearing areas, wafer contact areas, and axial thermal response areas within a semiconductor vertical furnace. In practical applications, the quartz carrier is vertically fully loaded, with wafers arranged axially. Differences in thermal response exist at the upper, middle, and lower ends of the furnace. The carrier's load-bearing framework needs to resist high-temperature creep, the wafer contact area needs to control metal ion contamination and particle release, and the axial temperature deviation area needs to avoid localized thermal drift. Therefore, a single quartz material cannot simultaneously achieve high-temperature load-bearing capacity, low-contamination contact, and thermal response compensation.

[0035] This invention solves the aforementioned problems by combining material functional zoning with axial thermal compensation. Specifically, low-hydroxyl high-purity quartz is used in the load-bearing framework area, ultra-high-purity synthetic quartz in the wafer contact area, and high-purity opaque quartz in the axial thermal compensation area. Low-hydroxyl high-purity quartz is used to form the boat pillars, bottom support, and top connection; ultra-high-purity synthetic quartz is used to form the wafer grooves or wafer support teeth; and high-purity opaque quartz is used to form the thermal compensation components located at the upper end, lower end, or axial temperature deviation area. Through this zoning method, the load-bearing structure, contact structure, and thermal compensation structure are each formed from quartz materials adapted to their respective functions.

[0036] Furthermore, this invention does not directly splice together multiple quartz materials. Instead, it sets up a high-purity transparent quartz transition connection section between the wafer contact area components and the load-bearing frame area components, and sets the main connection area away from the direct contact path of the wafer. This transition connection section makes the geometric connection and thermal response transition between different quartz components more continuous. After assembly, the pre-assembled quartz carrier is placed vertically according to its actual working direction in the semiconductor vertical furnace, and a simulated wafer or equivalent load component is loaded. Composite thermal shaping is then performed in an axial gradient temperature field, allowing each functional area to complete thermal history matching under conditions close to actual service conditions.

[0037] Unless otherwise specified, all raw materials used in the following examples are commercially available or prepared using conventional methods in the art.

[0038] In some embodiments, the low-hydroxyl high-purity quartz can be fused high-purity quartz, low-hydroxyl transparent quartz, or high-purity quartz that has undergone dehydroxylation treatment. The OH content of the low-hydroxyl high-purity quartz can be 0.1-20 ppm, the SiO2 content can be ≥99.99%, the Na content can be ≤0.5 ppm, the K content can be ≤0.5 ppm, the Fe content can be ≤0.5 ppm, and the Al content can be ≤20 ppm. This material is mainly used to prepare boat columns, bottom supports, and top connectors.

[0039] In some embodiments, the ultra-high purity synthetic quartz can be fumed silica, silicon tetrachloride hydrolyzed synthetic quartz, or other semiconductor-grade synthetic quartz. The ultra-high purity synthetic quartz has a SiO2 content ≥99.995%, a Na content ≤0.1ppm, a K content ≤0.1ppm, a Fe content ≤0.1ppm, an Al content ≤5ppm, and an OH content of 50-1200ppm. This material is mainly used to prepare wafer grooves or wafer support teeth.

[0040] In some embodiments, the high-purity opaque quartz can be opaque quartz containing closed bubbles, milky white quartz, or semiconductor-grade opaque quartz. The SiO2 content of the high-purity opaque quartz can be ≥99.99%, the bubble volume fraction can be 1-15%, the average bubble diameter can be 5-80 μm, and the thickness can be 1-8 mm. This material is mainly used to prepare high-purity opaque quartz rings, high-purity opaque quartz sheets, or high-purity opaque quartz segments.

[0041] In some embodiments, the high-purity transparent quartz transition connection section can be a transparent high-purity quartz rod, a transparent high-purity quartz sheet, a transparent high-purity quartz short beam, or a transparent high-purity quartz connecting block. The SiO2 content of the high-purity transparent quartz transition connection section can be ≥99.99%, the length can be 3-30 mm, and the diameter or width can be 2-15 mm. The distance between the connection point of the high-purity transparent quartz transition connection section and the wafer contact area component and the bottom of the wafer trench can be 5-40 mm.

[0042] like Figure 1 As shown, a method for preparing a high-purity quartz boat for a semiconductor vertical furnace includes the following steps:

[0043] S1. Obtain the axial temperature distribution of the target semiconductor vertical furnace and divide the quartz boat into a load-bearing frame area, a wafer contact area, and an axial thermal compensation area.

[0044] S2. The load-bearing skeleton area components are prepared using low-hydroxyl high-purity quartz, the wafer contact area components are prepared using ultra-high purity synthetic quartz, and the axial thermal compensation area components are prepared using high-purity opaque quartz.

[0045] S3. Connect the wafer contact area component to the load-bearing frame area component through a high-purity transparent quartz transition connection section, and connect the axial thermal compensation area component to the upper end, lower end or axial temperature deviation area of ​​the load-bearing frame area component to obtain a pre-assembled quartz carrier.

[0046] S4. Place the pre-assembled quartz carrier vertically and load it with a simulated wafer or equivalent load, and perform composite thermal shaping in an axial gradient temperature field.

[0047] S5. The composite heat-set quartz carrier is sequentially acid-washed, ultrapure water-washed, dried, and cleanly packaged to obtain a high-purity quartz carrier for semiconductor vertical furnaces.

[0048] The above steps will be described in detail below.

[0049] Step S1 involves acquiring the axial temperature distribution of the target semiconductor vertical furnace and dividing the functional areas of the quartz boat. In this paper, the axial temperature distribution refers to the temperature distribution formed along the axial direction of the furnace tube within the corresponding loading height range of the quartz boat in the target semiconductor vertical furnace. The axial temperature distribution may include the upper, middle, and lower temperatures of the quartz boat loading area, or it may include temperature data corresponding to multiple temperature measurement points spaced at intervals along the loading height.

[0050] Specifically, after the target semiconductor vertical furnace reaches the set process temperature, temperature measuring points can be set at the upper, middle, and lower ends of the quartz boat loading area to obtain the temperature at different heights. The measurement temperature range for axial temperature distribution can be 600-1250℃, the measurement interval can be 20-150mm, and the measurement time can be 10-120min. The measurement time can be one or more stages of the vertical furnace heating stage, isothermal stage, or cooling stage. For cases requiring more precise thermal compensation, more temperature measuring positions can be set along the height direction of the quartz boat to determine the axial temperature deviation area.

[0051] In the context of this invention, the axial temperature deviation region refers to an area where the temperature is higher, lower, or experiences lag in heating or cooling compared to the center of the quartz boat or the target uniform temperature region. The axial temperature deviation region can be located at the upper end of the quartz boat, the lower end of the quartz boat, or a local height position near the center of the quartz boat. It is understood that the axial temperature deviation region is not a fixed structural location, but is determined based on the actual temperature distribution of the target semiconductor vertical furnace.

[0052] Furthermore, based on the function of the quartz boat in the target semiconductor vertical furnace, the quartz boat is divided into a load-bearing frame area, a wafer contact area, and an axial thermal compensation area. The load-bearing frame area refers to the region used to form the main load-bearing structure of the quartz boat, and may include boat pillars, bottom supports, top connectors, crossbeams, or connecting beams. The wafer contact area refers to the region used to support, limit, or approach the wafer edge, and may include wafer slots, wafer support teeth, slot bottom supports, or wafer positioning parts. The axial thermal compensation area refers to the region where high-purity opaque quartz components are arranged according to the axial temperature distribution, and may include an upper thermal compensation area, a lower thermal compensation area, or a localized thermal compensation area.

[0053] Step S2 involves the preparation of components for different functional regions. Based on the functional region division determined in step S1, this step involves preparing quartz components for the corresponding regions using low-hydroxyl high-purity quartz, ultra-high-purity synthetic quartz, and high-purity opaque quartz, respectively.

[0054] Specifically, the load-bearing framework components are prepared using low-hydroxyl high-purity quartz. These components may include a boat column, a bottom support, and a top connection. The boat column can be a quartz rod, quartz tube, or quartz plate-like support extending along the height of the quartz boat; the bottom support can be a bottom ring, bottom plate, base, or bottom connecting beam; and the top connection can be a top ring, top plate, or top connecting beam. The low-hydroxyl high-purity quartz can be processed into load-bearing framework components of predetermined dimensions through steps such as cutting, grinding, drilling, chamfering, and cleaning.

[0055] Specifically, ultra-high purity synthetic quartz is used to fabricate wafer contact area components. These components may include wafer slots or wafer support teeth. Wafer slots can be elongated quartz pieces with multiple wafer slot positions, and wafer support teeth can be toothed support structures spaced apart along the wafer alignment direction. The slot pitch of the wafer slots or wafer support teeth can be 2-8 mm, the slot width can be 0.4-2.5 mm, the slot depth can be 0.5-5 mm, and the slot opening radius can be 0.05-0.5 mm. The slot positions can be formed through grinding, cutting, finishing, and chamfering.

[0056] Specifically, high-purity opaque quartz is used to fabricate the axial thermal compensation zone component. The axial thermal compensation zone component can be a high-purity opaque quartz ring, a high-purity opaque quartz sheet, or a high-purity opaque quartz segment. The high-purity opaque quartz ring can be a ring-shaped component surrounding the upper or lower end of a quartz carrier; the high-purity opaque quartz sheet can be a sheet-shaped component located in a localized axial temperature deviation area; the high-purity opaque quartz segment can be a segment-shaped component connected to the carrier column, end support, or local support. The thickness of the high-purity opaque quartz component can be 1-8 mm.

[0057] Step S3 is the connection and forming of the pre-assembled quartz carrier. In this step, the wafer contact area component is connected to the load-bearing frame area component through a high-purity transparent quartz transition connecting section, and the axial thermal compensation area component is connected to the upper end, lower end, or axial temperature deviation area of ​​the load-bearing frame area component.

[0058] Specifically, the high-purity transparent quartz transition connection section is located between the wafer contact area component and the load-bearing frame area component. The high-purity transparent quartz transition connection section can be connected to the wafer contact area component first, and then to the load-bearing frame area component; alternatively, it can be connected to the load-bearing frame area component first, and then to the wafer contact area component. The connection method can be flame welding, partial thermal fusion, or other thermal connection methods suitable for high-purity quartz components. During the connection process, a high-purity gas environment or a clean environment can be used to reduce external contamination in the connection area.

[0059] More specifically, the distance between the connection point of the wafer contact area component and the high-purity transparent quartz transition connection section and the bottom of the wafer trench can be 5-40 mm. In this article, the bottom of the wafer trench refers to the trench bottom area near the lowest support position of the wafer edge after wafer loading. Maintaining the above-mentioned distance between the connection point and the bottom of the wafer trench helps to ensure that the connection area avoids the direct contact path with the wafer. It should be understood that the distance can be determined along the trench depth direction, the trench width direction, or the shortest distance of the wafer contact path, as long as the spatial relationship between the connection point and the wafer contact position can be clearly defined.

[0060] Furthermore, the axial thermal compensation zone component is connected to the load-bearing frame component. If step S1 determines that there is a temperature deviation area at the upper end, a high-purity opaque quartz ring, a high-purity opaque quartz sheet, or a high-purity opaque quartz segment can be placed at the upper end of the quartz carrier; if step S1 determines that there is a temperature deviation area at the lower end, a high-purity opaque quartz ring, a high-purity opaque quartz sheet, or a high-purity opaque quartz segment can be placed at the lower end of the quartz carrier; if step S1 determines that there is a temperature deviation area at the middle or local height position, a high-purity opaque quartz sheet or a high-purity opaque quartz segment can be placed at the corresponding height position.

[0061] Step S4 is composite heat setting. In this step, the pre-assembled quartz carrier is placed vertically and a simulated wafer or equivalent load is loaded into it, and heat treatment is performed in an axial gradient temperature field.

[0062] In the context of this invention, a simulated wafer refers to a sheet-like load cell whose size, thickness, or mass matches that of a target wafer. This load cell can be a high-purity quartz sheet, a silicon wafer, or other sheet-like material that can withstand complex heat setting temperatures. An equivalent load cell refers to a component capable of forming a load corresponding to the wafer loading at a slot or support position on a quartz carrier. This component can be a sheet-like material, a ring-like material, or a combined counterweight. The mass of a single simulated wafer or equivalent load cell can be 5-250g, and the loading quantity can be 25-200 wafers.

[0063] Specifically, the pre-assembled quartz carrier is placed vertically according to its actual working direction in the target semiconductor vertical furnace. Vertical placement means that the height direction of the quartz carrier is basically consistent with the direction of gravity. The simulated wafer or equivalent load component is installed into the wafer slot or wafer support teeth, so that the load-bearing skeleton area, wafer contact area and axial thermal compensation area undergo heat treatment together under load.

[0064] Furthermore, the composite heat setting temperature can be 800-1250℃, the holding time can be 20-240 min, the heating rate can be 1-10℃ / min, and the cooling rate can be 0.5-8℃ / min. The axial gradient temperature field can be set according to the axial temperature distribution of the target semiconductor vertical furnace obtained in step S1, or it can be formed by a multi-zone heating device. During the composite heat setting process, the upper, middle, and lower ends of the pre-assembled quartz boat can be placed in different temperature ranges, or it can have an axial temperature difference corresponding to that of the target semiconductor vertical furnace during the isothermal stage.

[0065] Step S5 involves cleaning, drying, and packaging the composite heat-set quartz carrier. This step sequentially performs acid washing, ultrapure water rinsing, drying, and clean packaging on the composite heat-set quartz carrier.

[0066] Specifically, pickling can use one or more of HF, HNO3, and HCl. The mass concentration of HF can be 0.1-10%, the mass concentration of HNO3 can be 5-40%, and the mass concentration of HCl can be 5-30%. The pickling temperature can be 20-80℃, and the pickling time can be 5-120 minutes. Pickling can be done using a single pickling method or a multi-stage pickling method. In multi-stage pickling, HNO3 or HCl can be used first to remove surface metal ions, followed by treatment of the surface processed layer with a low concentration of HF.

[0067] Furthermore, the resistivity of the ultrapure water used for cleaning can be ≥15 MΩ·cm, and the cleaning time can be 10-180 min. Ultrapure water cleaning can be performed using overflow cleaning, circulating cleaning, spray cleaning, or immersion cleaning. The drying temperature can be 60-180℃, and the drying time can be 20-240 min. After drying, the quartz boat is packaged in a clean environment, which can be a cleanroom, a clean working area, or a clean packaging area.

[0068] The high-purity quartz carrier boat for semiconductor vertical furnaces prepared by the above steps includes a load-bearing frame region, a wafer contact region, and an axial thermal compensation region. The load-bearing frame region includes a boat column, a bottom support, and a top connection; the wafer contact region includes wafer slots or wafer support teeth; and the axial thermal compensation region includes a high-purity opaque quartz ring, a high-purity opaque quartz sheet, or a high-purity opaque quartz segment.

[0069] The quartz carrier of the present invention can be functionally divided into a load-bearing frame area, a wafer contact area, and an axial thermal compensation area. The load-bearing frame area forms the main support structure of the quartz carrier, the wafer contact area is located inside the load-bearing frame area and is used to form wafer slots, and the axial thermal compensation area is located in the axial temperature deviation area of ​​the quartz carrier. It should be noted that the functional area division does not require completely independent physical boundaries between the areas, but is based on material configuration, component function, and the service location of the vertical furnace.

[0070] In some embodiments, the load-bearing frame area may include three or four boat pillars. The boat pillars extend along the height direction of the quartz boat and are maintained in relative position by a bottom support and a top connection. The boat pillars may be solid quartz rods, hollow quartz tubes, or plate-shaped quartz pillars. Specifically, the outer diameter of the boat pillar may be 5-30 mm, and the wall thickness may be 1-8 mm; when the boat pillar is a solid quartz rod, its diameter may be 4-25 mm; when the boat pillar is a plate-shaped quartz pillar, its thickness may be 2-15 mm, and its width may be 5-40 mm. These dimensions can be selected according to the wafer size, boat height, and number of slots.

[0071] In some embodiments, the bottom support may include a bottom ring, a bottom plate, a bottom crossbeam, or a bottom positioning seat. The top connection may include a top ring, a top plate, or a top crossbeam. Both the bottom support and the top connection may be made of low-hydroxyl high-purity quartz and connected to the boat column by flame welding. Specifically, the thickness of the bottom support and the top connection may be 2-20 mm, and the outer diameter or maximum width may be 40-350 mm. For a quartz boat corresponding to a 12-inch wafer, the outer diameter or maximum width of the bottom support and the top connection may be 250-350 mm; for a quartz boat corresponding to an 8-inch wafer, the outer diameter or maximum width of the bottom support and the top connection may be 180-260 mm.

[0072] In some embodiments, the wafer contact area may include two, three, or four sets of wafer slots. The wafer slots are arranged along the height direction of the quartz boat and are parallel or substantially parallel to the boat pillars. Multiple slots for placing wafer edges are formed on the wafer slots. The slots can be formed by cutting, grinding, or precision grooving. The slot spacing can be 2-8 mm, the slot width can be 0.4-2.5 mm, the slot depth can be 0.5-5 mm, and the slot opening radius can be 0.05-0.5 mm. For high-wafer-count boats with small spacing, a slot spacing of 2-4 mm can be used; for larger diameter or thicker wafers, a slot spacing of 4-8 mm can be used.

[0073] It is important to emphasize that the use of ultra-high purity synthetic quartz in the wafer contact area does not mean that the entire carrier boat needs to be made of ultra-high purity synthetic quartz. The main function of the wafer contact area is to support the wafer edge or restrict its position. Being close to the wafer surface and edge, it is sensitive to residual metal ions and particle release. The load-bearing framework area, on the other hand, primarily provides axial support and thermal cycling resistance, placing greater emphasis on high-temperature viscosity and creep resistance. Therefore, this invention uses different quartz materials to prepare these two types of areas.

[0074] The wafer contact area components are connected to the load-bearing frame components via high-purity transparent quartz transition connectors. These transition connectors can be short beams, connecting blocks, connecting pillars, or connecting plates. One end connects to the wafer slot, and the other end connects to a boat pillar or load-bearing beam. The transition connectors can be a single segment or multiple spaced-apart connections. Multiple transition connectors can be spaced along the height of the wafer slot, with a spacing of 20-150 mm between adjacent transition connectors.

[0075] Specifically, the length of the transition connection section is 3-30 mm, and the diameter or width is 2-15 mm. When the length of the transition connection section is less than 3 mm, the connection area is too short, which is not conducive to processing positioning and connection forming; when the length of the transition connection section is greater than 30 mm, it may increase the local structural complexity of the carrier boat. It is understood that the above size range is mainly used to define the size of the connection components suitable for the quartz carrier boat of the semiconductor vertical furnace, and those skilled in the art can select within this range according to the carrier boat specifications.

[0076] The connection point between the high-purity transparent quartz transition connector and the wafer contact area component is 5-40mm from the bottom of the wafer trench. This distance is not simply a geometric clearance dimension, but rather creates a spatial separation between the connection point and the direct contact area of ​​the wafer. Specifically, after the wafer is placed in the trench, its edge is usually located at or near the bottom of the trench. If the welded connection point is directly close to the bottom of the trench, the surface condition, stress state, and particle release risk of the welded area are more likely to affect the wafer contact path. By setting the connection point at a certain distance from the bottom of the trench, the direct wafer support location and the component connection location can be structurally distinguished.

[0077] The axial thermal compensation zone can be located at the upper or lower end of the quartz carrier, or in the axial temperature deviation area. The axial thermal compensation zone is made of high-purity opaque quartz. Compared to transparent quartz, the internal bubble structure of high-purity opaque quartz alters radiation transmission and scattering behavior, thus allowing it to be used as a localized thermal response adjustment component. It should be noted that the high-purity opaque quartz in this invention is not an arbitrarily placed decorative component on the carrier, nor is it a simple heat insulation component; rather, its placement is determined based on the axial temperature distribution of the target semiconductor vertical furnace.

[0078] In some embodiments, when the lower region of the target semiconductor vertical furnace experiences sluggish heating, a high-purity opaque quartz ring or segment can be placed at the lower end of the quartz carrier; when the upper region of the target semiconductor vertical furnace cools too quickly, a high-purity opaque quartz ring or sheet can be placed at the upper end of the quartz carrier; when the local temperature in the middle of the target semiconductor vertical furnace is too high, a local high-purity opaque quartz sheet or segment can be placed at the corresponding height. Therefore, the position of the axial thermal compensation zone is not fixed at a specific end, but is determined according to the axial temperature distribution of the target vertical furnace.

[0079] In some embodiments, the high-purity opaque quartz ring may have an annular body with a thickness of 1-8 mm and a width of 3-30 mm; the high-purity opaque quartz sheet may have a sheet-like body with a thickness of 1-8 mm, a width of 3-40 mm, and a height of 5-80 mm; the high-purity opaque quartz segment may have a columnar, strip-like, or arc-shaped structure, with a length of 5-100 mm. The aforementioned thermal compensation components can be connected to the load-bearing frame components by flame welding, or they can be integrally formed with the top connecting part or the bottom support part and then connected to the boat column.

[0080] The pre-assembled quartz carrier is kept vertical during the composite heat setting process and a simulated wafer or equivalent load-bearing component is loaded inside. This step is used to subject the load-bearing frame area, wafer contact area, and axial thermal compensation area to heat treatment under load conditions consistent with the actual service direction. It should be distinguished that conventional quartz annealing typically emphasizes the elimination of residual stress after welding, while the composite heat setting of this invention simultaneously includes three conditions: vertical orientation, simulated wafer load, and axial gradient temperature field.

[0081] Specifically, the composite heat setting can be performed in a multi-zone heating furnace. The multi-zone furnace has multiple heating zones along its height, so that the upper, middle, and lower ends of the pre-assembled quartz boat correspond to different temperatures. The composite heat setting temperature is 800-1250℃, the holding time is 20-240 min, the heating rate is 1-10℃ / min, and the cooling rate is 0.5-8℃ / min. In one embodiment, the temperature difference between the upper, middle, and lower ends can be 5-80℃. In another embodiment, the temperature difference can correspond to the axial temperature difference of the target semiconductor vertical furnace obtained in step S1.

[0082] Understandably, composite heat setting does not require completely replicating all process conditions of the target semiconductor vertical furnace, but rather at least replicating the main conditions related to the thermal deformation of the quartz boat, including vertical placement, loading status, and axial gradient temperature field. For different furnace types, the composite heat setting conditions can be adjusted according to their furnace tube height, number of heating zones, and temperature distribution.

[0083] Furthermore, after the composite heat setting is completed, the quartz boat undergoes acid pickling, ultrapure water rinsing, drying, and clean packaging. Acid pickling removes surface residues from the processing and joining process; ultrapure water rinsing removes acid residues and migratable ions; drying removes residual moisture from the surface and tank of the quartz boat; and clean packaging reduces the adhesion of exogenous particles during transportation and storage.

[0084] In this invention, clean packaging can employ double-layer clean bags, vacuum packaging, or sealed packaging filled with high-purity N2. The packaging environment can be an ISO 5, ISO 6, or ISO 7 clean environment. The purity of the high-purity N2 can be ≥99.999%. It should be understood that the packaging method does not limit the scope of protection of this invention, as long as it meets the clean transfer requirements of semiconductor quartz components.

[0085] In some embodiments, pickling can be performed in two stages. The first stage pickling uses one or both of HNO3 and HCl, with an HNO3 mass concentration of 5-40% and an HCl mass concentration of 5-30%, at a pickling temperature of 20-80°C and a pickling time of 5-60 min. The second stage pickling uses HF, with an HF mass concentration of 0.1-10%, at a pickling temperature of 20-60°C and a pickling time of 2-30 min. After pickling, the sample is rinsed with ultrapure water with a resistivity ≥15 MΩ·cm for 10-180 min.

[0086] In some embodiments, drying can be performed using clean hot air drying, vacuum drying, or high-purity N2 purging drying. The drying temperature can be 60-180℃, and the drying time can be 20-240 min. When using high-purity N2 purging drying, the high-purity N2 flow rate can be 5-100 L / min, and the purging time can be 10-120 min.

[0087] The following provides further explanation of several terms used in this invention.

[0088] In this article, low-hydroxyl high-purity quartz refers to quartz materials with low OH content and metallic impurity content that meet the requirements for use in semiconductor quartz components. It can be obtained through electrofusion, gas refining, dehydroxylation treatment, or other conventional quartz material preparation methods.

[0089] In this article, ultra-high purity synthetic quartz refers to high-purity SiO2 material obtained through synthesis methods. Its metal ion content is lower than that of ordinary natural high-purity quartz, and it is suitable for use in contact area components close to the wafer.

[0090] In this article, high-purity opaque quartz refers to quartz materials that possess an internal scattering structure while maintaining a high SiO2 content. The scattering structure can be formed by closed bubbles, with a bubble volume fraction of 1-15% and an average bubble diameter of 5-80 μm.

[0091] In this article, the high-purity transparent quartz transition connection section refers to a transparent high-purity quartz connector placed between a low-hydroxyl high-purity quartz component and an ultra-high-purity synthetic quartz component to form a geometric connection and material transition. It can be a separately machined connector or a connection area formed by a short transparent high-purity quartz component during the connection process.

[0092] It should be noted that the specific structure of the high-purity quartz carrier in this invention can be adjusted according to the target semiconductor vertical furnace. For example, the quartz carrier can be a three-column, four-column, or multi-column carrier; the wafer contact area can be configured as a groove structure or a toothed support structure; the axial thermal compensation area can be annular, sheet-like, segmental, or a combination of the above structures. All the above modifications do not depart from the technical concept of the coordinated control of material functional zoning and axial thermal compensation in this invention.

[0093] Example

[0094] The following embodiments are used to further illustrate the technical solutions of the present invention, but do not constitute a limitation on the scope of protection of the present invention. In each embodiment, unless otherwise specified, the quartz boat is prepared according to the specifications of an 8-inch semiconductor vertical furnace wafer boat, and the number of wafer slots is 100.

[0095] Example 1:

[0096] A method for preparing a high-purity quartz carrier boat for a semiconductor vertical furnace includes the following steps:

[0097] S1. Obtain the axial temperature distribution of the target semiconductor vertical furnace under full load. The measurement temperature is 1050℃, the measurement interval is 80mm, and the measurement time is 60min. Based on the axial temperature distribution, the quartz boat is divided into a load-bearing skeleton area, a wafer contact area, and an axial thermal compensation area, with the axial thermal compensation area located at the lower end of the quartz boat.

[0098] S2. The boat column, bottom support, and top connector are prepared using low-hydroxyl high-purity quartz. The low-hydroxyl high-purity quartz has an OH content of 8 ppm, a SiO2 content of 99.996%, a Na content of 0.3 ppm, a K content of 0.3 ppm, a Fe content of 0.2 ppm, and an Al content of 12 ppm. The wafer groove is prepared using ultra-high purity synthetic quartz. The ultra-high purity synthetic quartz has a SiO2 content of 99.999%, a Na content of 0.05 ppm, a K content of 0.05 ppm, a Fe content of 0.05 ppm, an Al content of 3 ppm, and an OH content of 500 ppm. The lower heat compensation ring is prepared using high-purity opaque quartz. The high-purity opaque quartz has a SiO2 content of 99.996%, a bubble volume fraction of 4%, an average bubble diameter of 35 μm, and a thickness of 4 mm.

[0099] S3. The wafer slot strips are processed into a structure with a slot pitch of 4.76 mm, a slot width of 1.0 mm, a slot depth of 2.0 mm, and a slot opening radius of 0.20 mm. A high-purity transparent quartz transition connecting section is used to connect the wafer slot strips to the boat column. The high-purity transparent quartz transition connecting section has a SiO2 content of 99.996%, a length of 12 mm, a width of 6 mm, and the connection point is 20 mm away from the bottom of the wafer slot. The lower end thermal compensation ring is connected to the bottom support part to obtain the pre-assembled quartz boat.

[0100] S4. Place the pre-assembled quartz carrier vertically and load 100 simulated wafers, each weighing 55g, into it. Perform composite heat setting in an axial gradient temperature field. The composite heat setting temperature is 1080℃, the holding time is 120min, the heating rate is 4℃ / min, and the cooling rate is 2℃ / min.

[0101] S5. The composite heat-set quartz carrier is subjected to acid washing, ultrapure water cleaning, drying, and clean packaging. The acid washing process uses three stages: HCl, HNO3, and HF. The HCl mass concentration is 10%, the acid washing temperature is 35℃, and the acid washing time is 20 min. The HNO3 mass concentration is 25%, the acid washing temperature is 40℃, and the acid washing time is 30 min. The HF mass concentration is 1.5%, the acid washing temperature is 25℃, and the acid washing time is 8 min. The ultrapure water resistivity is 18 MΩ·cm, and the cleaning time is 90 min. The drying temperature is 130℃, and the drying time is 100 min.

[0102] Example 2:

[0103] This embodiment is basically the same as embodiment 1, except that in step S2, the volume fraction of bubbles in the high-purity opaque quartz is 7%.

[0104] The remaining steps and parameters are the same as in Example 1.

[0105] Example 3:

[0106] This embodiment is basically the same as embodiment 1, except that in step S2, the volume fraction of bubbles in the high-purity opaque quartz is 10%.

[0107] The remaining steps and parameters are the same as in Example 1.

[0108] Example 4:

[0109] This embodiment is basically the same as embodiment 2, except that in step S3, the length of the high-purity transparent quartz transition connection section is 15mm.

[0110] The remaining steps and parameters are the same as in Example 2.

[0111] Example 5:

[0112] This embodiment is basically the same as embodiment 2, except that in step S3, the length of the high-purity transparent quartz transition connection section is 18mm.

[0113] The remaining steps and parameters are the same as in Example 2.

[0114] Comparative Example 1:

[0115] This comparative example is basically the same as Example 1, except that in step S2, the volume fraction of bubbles in the high-purity opaque quartz is 3%.

[0116] The remaining steps and parameters are the same as in Example 1.

[0117] Comparative Example 2:

[0118] This comparative example is basically the same as Example 1, except that in step S2, the volume fraction of bubbles in the high-purity opaque quartz is 11%.

[0119] The remaining steps and parameters are the same as in Example 1.

[0120] Comparative Example 3:

[0121] This comparative example is basically the same as Example 2, except that in step S3, the length of the high-purity transparent quartz transition connection section is 11 mm.

[0122] The remaining steps and parameters are the same as in Example 2.

[0123] Comparative Example 4:

[0124] This comparative example is basically the same as Example 2, except that in step S3, the length of the high-purity transparent quartz transition connection section is 19mm.

[0125] The remaining steps and parameters are the same as in Example 2.

[0126] Comparative Example 5:

[0127] This comparative example is basically the same as Example 2, except that in step S3, the high-purity opaque quartz axial thermal compensation zone component is not set.

[0128] The remaining steps and parameters are the same as in Example 2.

[0129] Comparative Example 6:

[0130] This comparative example is basically the same as Example 2, except that in step S2, the wafer contact area component is made of low-hydroxyl high-purity quartz.

[0131] The remaining steps and parameters are the same as in Example 2.

[0132] To verify the technical effectiveness of the high-purity quartz carrier for semiconductor vertical furnaces prepared by the method of the present invention, the quartz carriers obtained in Examples 1-5 and Comparative Examples 1-6 were tested for full-load high-temperature warpage, slot pitch drift after thermal cycling, particle release from the wafer contact area, and metal contamination on the wafer surface. All tests were conducted using 8-inch wafers of the same specifications under simulated operating conditions.

[0133] Full-load high-temperature warpage test:

[0134] The quartz boat to be tested was placed vertically in a high-temperature testing furnace, and 100 simulated wafers, each weighing 55g, were loaded into its wafer slots. The testing furnace was heated to 1050℃ and held for 120 minutes. After the holding period, the maximum radial offset of the top center of the quartz boat relative to the bottom center was measured under high temperature conditions. This maximum radial offset was taken as the full-load high-temperature warpage.

[0135] For Examples 4 and 5, since their composite heat setting temperature is 1080-1100℃, the test still uniformly uses 1050℃ as the comparison temperature to ensure that the data of each group are comparable.

[0136] Test of slot pitch drift after thermal cycling:

[0137] One hundred simulated wafers were loaded into a quartz carrier boat and subjected to 100 thermal cycles in a test furnace. Each thermal cycle consisted of heating from room temperature to 1050°C, holding at that temperature for 60 minutes, and then cooling to below 200°C. After completing 100 thermal cycles, the pitch of each wafer was measured at room temperature and compared with the pitch before thermal cycling. The maximum pitch change was recorded as the pitch drift after thermal cycling.

[0138] The slot spacing was measured using a non-contact three-dimensional dimensional measurement method. The measurement locations were the middle height region, the upper height region, and the lower height region of the wafer slot strip, with no fewer than 10 slots selected for measurement in each region.

[0139] Wafer contact area particle release test:

[0140] After cleaning and drying, 8-inch silicon wafers were loaded into a quartz carrier boat for testing and subjected to 50 consecutive loading and unloading cycles. After each loading and unloading, a wafer surface particle detection device was used to detect the number of particles with a diameter ≥ 0.2 μm on the silicon wafer surface. Five silicon wafers were selected for each test group, and the average value was taken as the particle release amount in the wafer contact area.

[0141] Wafer surface metal contamination test:

[0142] An 8-inch silicon wafer, after being cleaned and dried, was placed into a quartz boat for testing and held at 1050℃ for 60 minutes. After cooling, the silicon wafer was removed, and the surface metal contamination levels of Na, K, Fe, and Al were measured using a surface metal contamination detection method. The sum of the contamination levels of the four metal elements was then used as the total surface metal contamination level of the wafer.

[0143] Table 1 Test results of the examples and comparative examples

[0144] Group Full load high temperature warpage / mm Spacing drift after thermal cycling / mm <![CDATA[Particle release amount / particle·tablet -1 > <![CDATA[Wafer surface metal contamination amount / 10 10 atoms·cm -2 > Example 1 0.31 0.039 39 1.52 Example 2 0.19 0.022 27 1.18 Example 3 0.25 0.031 33 1.36 Example 4 0.16 0.018 21 1.04 Example 5 0.21 0.026 28 1.21 Comparative Example 1 0.43 0.058 51 1.84 Comparative Example 2 0.51 0.071 64 2.13 Comparative Example 3 0.40 0.054 72 2.26 Comparative Example 4 0.47 0.066 58 1.95 Comparative Example 5 0.59 0.087 47 1.69 Comparative Example 6 0.64 0.093 96 3.12

[0145] As can be seen from Table 1, the full-load high-temperature warpage, slot pitch drift after thermal cycling, particle release, and wafer surface metal contamination of Examples 1-5 are all lower than those of Comparative Examples 1-6. This indicates that the present invention, through the combination of material functional zoning, axial thermal compensation zone setting, high-purity transparent quartz transition connection section, and composite thermal setting, enables the quartz carrier boat to obtain better dimensional stability and cleanliness under the high-temperature full-load conditions of semiconductor vertical furnace.

[0146] Examples 1, 2, 3, Comparative Example 1, and Comparative Example 2 were used to investigate the effect of the bubble volume fraction of high-purity opaque quartz on axial thermal compensation. In each group, only the bubble volume fraction of the high-purity opaque quartz was changed, while other process parameters remained constant. The results showed that the overall effect, from best to worst, was as follows: Example 2, Example 3, Example 1, Comparative Example 1, and Comparative Example 2. In Example 2, the bubble volume fraction was 7%, resulting in the lowest full-load high-temperature warpage and the lowest groove drift after thermal cycling. In Example 3, the bubble volume fraction was 10%, showing the second best effect. In Example 1, the bubble volume fraction was 4%, still superior to the Comparative Example. In Comparative Example 1, the bubble volume fraction was 3%, indicating insufficient thermal compensation. In Comparative Example 2, the bubble volume fraction was 11%, indicating excessive local radiation regulation, which increased the difference in thermal response. Therefore, the bubble volume fraction of high-purity opaque quartz is not necessarily better the lower or higher it is, but rather should be matched with the axial temperature distribution of the target vertical furnace within a specific range.

[0147] Examples 2, 4, 5, Comparative Example 3, and Comparative Example 4 were used to investigate the effect of the length of the transition connection section of high-purity transparent quartz on the connection stability of various quartz materials. In each group, only the length of the transition connection section of the high-purity transparent quartz was changed, while other process parameters remained the same. The results showed that the overall effect, from best to worst, was as follows: Example 4, Example 5, Example 3, Comparative Example 3, and Comparative Example 4. Specifically, the transition connection section length of Example 4 was 15 mm, resulting in a relatively stable connection transition; the transition connection section length of Example 5 was 18 mm, with a slightly lower effect than Example 4; the overall effect of Example 3 was still better than Comparative Example 3 and Comparative Example 4. In Comparative Example 3, the transition connection section length was 11 mm, resulting in insufficient connection transition distance and concentrated changes in interface thermal response; in Comparative Example 4, the transition connection section length was 19 mm, which was too long, increasing the impact of the local connection structure on the stability of the slot position. Therefore, the length of the transition connection section needs to be matched with the wafer slot, boat pillar, and welding position, rather than simply being extended or shortened.

[0148] Compared with Example 2, Comparative Example 5 eliminated the high-purity opaque quartz axial thermal compensation zone component. The results showed that the amount of metal contamination on the wafer surface of Comparative Example 5 was lower than that of Comparative Example 6, but its full-load high-temperature warpage and trench pitch drift after thermal cycling were significantly higher than all examples. This indicates that material functional zoning alone can improve contamination control in the wafer contact area, but it is difficult to solve the local thermal drift caused by the axial temperature difference of the vertical furnace.

[0149] Compared to Example 2, Comparative Example 6 replaced the wafer contact area components with low-hydroxyl high-purity quartz. The results showed that the particle release and wafer surface metal contamination of Comparative Example 6 were significantly increased. At the same time, the full-load high-temperature warpage and the groove pitch drift after thermal cycling were also higher than all examples, indicating that although low-hydroxyl high-purity quartz alone can be used for load-bearing skeletons, it is not suitable to replace ultra-high purity synthetic quartz in forming the wafer contact area.

[0150] In summary, the technical effect of this invention is not generated by a single parameter change, nor by the direct splicing of multiple ordinary quartz materials. Rather, it is formed by the combined effects of a low-hydroxyl, high-purity quartz load-bearing framework region, an ultra-high-purity synthetic quartz wafer contact region, a high-purity opaque quartz axial thermal compensation region, a high-purity transparent quartz transition connection section, and composite heat setting under vertical full load conditions. The material functional zoning addresses the conflict between contamination control and high-temperature deformation resistance; the high-purity opaque quartz axial thermal compensation region reduces localized thermal drift caused by axial temperature differences in the vertical furnace; and the high-purity transparent quartz transition connection section mitigates abrupt changes in connection between different quartz components. These factors work together to enable the quartz carrier boat to simultaneously achieve low contamination, low warpage, and low slot pitch drift under high-temperature full load conditions in a semiconductor vertical furnace.

[0151] Based on the preferred embodiments of the present invention described above, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A method for preparing a high-purity quartz boat for a semiconductor vertical furnace, characterized in that, Includes the following steps: S1. Obtain the axial temperature distribution of the target semiconductor vertical furnace and divide the quartz boat into a load-bearing frame area, a wafer contact area, and an axial thermal compensation area. S2. The load-bearing skeleton area components are prepared using low-hydroxyl high-purity quartz, the wafer contact area components are prepared using ultra-high purity synthetic quartz, and the axial thermal compensation area components are prepared using high-purity opaque quartz. S3. Connect the wafer contact area component to the load-bearing frame area component through a high-purity transparent quartz transition connection section, and connect the axial thermal compensation area component to the upper end, lower end or axial temperature deviation area of ​​the load-bearing frame area component to obtain a pre-assembled quartz carrier. S4. The pre-assembled quartz carrier is placed vertically and a simulated wafer or equivalent load is loaded into it. Composite thermal shaping is then performed in an axial gradient temperature field. S5. The composite heat-set quartz carrier is sequentially acid-washed, ultrapure water-washed, dried, and cleanly packaged to obtain the high-purity quartz carrier for semiconductor vertical furnace.

2. The method for preparing a high-purity quartz boat for a semiconductor vertical furnace according to claim 1, characterized in that: In step S1, the axial temperature distribution includes the upper, middle and lower temperatures of the quartz boat loading area in the target semiconductor vertical furnace. The measurement temperature range of the axial temperature distribution is 600-1250℃, the measurement interval is 20-150mm, and the measurement time is 10-120min.

3. The method for preparing a high-purity quartz boat for a semiconductor vertical furnace according to claim 1, characterized in that: In step S2, the low-hydroxyl high-purity quartz has an OH content of 0.1-20 ppm, a SiO2 content of ≥99.99%, a Na content of ≤0.5 ppm, a K content of ≤0.5 ppm, a Fe content of ≤0.5 ppm, and an Al content of ≤20 ppm.

4. The method for preparing a high-purity quartz boat for a semiconductor vertical furnace according to claim 1, characterized in that: In step S2, the ultra-high purity synthetic quartz has a SiO2 content ≥99.995%, a Na content ≤0.1ppm, a K content ≤0.1ppm, a Fe content ≤0.1ppm, an Al content ≤5ppm, and an OH content of 50-1200ppm.

5. The method for preparing a high-purity quartz boat for a semiconductor vertical furnace according to claim 1, characterized in that: In step S2, the high-purity opaque quartz has a SiO2 content of ≥99.99%, a bubble volume fraction of 1-15%, an average bubble diameter of 5-80 μm, and a thickness of 1-8 mm.

6. The method for preparing a high-purity quartz boat for a semiconductor vertical furnace according to claim 1, characterized in that: In step S3, the SiO2 content of the high-purity transparent quartz transition connection section is ≥99.99%, the length is 3-30mm, and the diameter or width is 2-15mm. The distance between the connection point of the high-purity transparent quartz transition connection section and the wafer contact area component is 5-40mm from the bottom of the wafer groove.

7. The method for preparing a high-purity quartz boat for a semiconductor vertical furnace according to claim 1, characterized in that: In step S3, the wafer contact area component includes wafer slots or wafer support teeth. The slot spacing of the wafer slots or wafer support teeth is 2-8mm, the slot width is 0.4-2.5mm, the slot depth is 0.5-5mm, and the slot opening radius is 0.05-0.5mm.

8. The method for preparing a high-purity quartz boat for a semiconductor vertical furnace according to claim 1, characterized in that: In step S4, the mass of a single simulated wafer or equivalent load is 5-250g, the number of wafers loaded is 25-200, the composite heat setting temperature is 800-1250℃, the holding time is 20-240min, the heating rate is 1-10℃ / min, and the cooling rate is 0.5-8℃ / min.

9. The method for preparing a high-purity quartz boat for a semiconductor vertical furnace according to claim 1, characterized in that: In step S5, the pickling uses one or more of HF, HNO3, and HCl, with HF mass concentration of 0.1-10%, HNO3 mass concentration of 5-40%, and HCl mass concentration of 5-30%. The pickling temperature is 20-80℃, and the pickling time is 5-120 min. The ultrapure water used for cleaning has a resistivity ≥15 MΩ·cm, and the cleaning time is 10-180 min. The drying temperature is 60-180℃, and the drying time is 20-240 min.

10. A high-purity quartz carrier boat for a semiconductor vertical furnace, characterized in that: The wafer is prepared by any one of claims 1-9 and includes a load-bearing skeleton region, a wafer contact region, and an axial thermal compensation region. The load-bearing skeleton region includes a boat column, a bottom support portion, and a top connecting portion. The wafer contact region includes a wafer groove or a wafer support tooth. The axial thermal compensation region includes a high-purity opaque quartz ring, a high-purity opaque quartz sheet, or a high-purity opaque quartz segment.

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