Managing impedance matching in chip packages

Abstract

Systems, devices, and methods for chip packaging are provided. In one aspect, a chip package includes a substrate and a pad at a surface of the substrate. The substrate includes a transmission line coupled to the pad. The transmission line includes a loop structure positioned adjacent to the pad, and the loop structure includes a multi-turn curve wrapped around a center axis.

Description

Technical Field

[0001] This disclosure relates to chip packaging and impedance matching for chip packaging. Background Technology

[0002] Semiconductor devices can be classified into non-volatile memory devices (such as flash memory devices) and volatile memory devices (such as dynamic random access memory (DRAM)). Semiconductor memory devices can have different structures, with memory cells and lines of varying densities on the chip. Memory devices typically include a memory array of memory cells and a control circuitry system. The control circuitry system facilitates the operation of the memory array.

[0003] Universal Flash Memory (UFS) packages can be used to integrate memory devices with other devices. Ball Grid Array (BGA) balls can be used as the electrical interface between the UFS chip and the printed circuit board (PCB). Solder balls can be arranged in a grid pattern on the underside of the UFS package, providing high-density interconnects for efficient signal transmission, power delivery, and grounding. Summary of the Invention

[0004] This disclosure describes methods, apparatus, systems, and techniques for managing impedance matching in chip packages.

[0005] One aspect of this disclosure is a chip package including a substrate; and pads located on the surface of the substrate, wherein the substrate includes transmission lines coupled to the pads, the transmission lines including coil structures positioned adjacent to the pads, and the coil structures including multi-turn curves wound around a central axis.

[0006] In some embodiments, the coil structure of the transmission line at least partially overlaps with the pads.

[0007] In some embodiments, the coil structure includes a planar helical coil.

[0008] In some embodiments, the planar helical coil includes at least one of a planar square helical coil, a planar rectangular helical coil, a planar hexagonal helical coil, or a planar octagonal helical coil.

[0009] In some embodiments, the transmission line includes a wiring structure extending from the coil structure, and the impedance of the combination of the coil structure and the pads is substantially equal to the impedance of the wiring structure.

[0010] In some embodiments, the pad has a capacitance C, the coil structure has an inductance L, and the capacitance C of the pad is related to the inductance L of the coil structure, satisfying the following conditions: Where Z0 is the target impedance.

[0011] In some embodiments, the coil structure has a uniform spacing between adjacent turns in the multi-turn curve.

[0012] In some implementations, each curve in the multi-turn curve has a different perimeter.

[0013] In some implementations, the transmission line is configured to transmit serializer-deserializer (SERDES) signals.

[0014] In some embodiments, the transmission line is a first transmission line, the substrate includes a second transmission line positioned adjacent to the first wiring structure, and wherein the first transmission line is configured to transmit a positive signal, and the second transmission line is configured to transmit a negative signal.

[0015] In some embodiments, the chip package includes a ball grid array (BGA) package, which includes a substrate and the pads are connected to solder balls.

[0016] Another aspect of this disclosure is a memory device comprising: a substrate; pads located on the substrate, wherein the substrate includes: a transmission line coupled to the pads, the transmission line including a coil structure positioned adjacent to the pads, and the coil structure including a multi-turn curve wound around a central axis; and conductive lines; a memory structure including a plurality of memory cells and located on the substrate; and a control structure including control circuitry and located on the substrate, wherein the memory structure is coupled to the control structure via the conductive lines of the substrate.

[0017] In some embodiments, the transmission line has a first end coupled to the control structure and a second end coupled to the pad, the second end including the coil structure.

[0018] In some embodiments, the memory device includes a molding encapsulant configured to encapsulate at least the memory structure and the control structure on the substrate.

[0019] In some embodiments, the coil structure of the transmission line at least partially overlaps with the pads.

[0020] In some embodiments, the transmission line includes a wiring structure extending from the coil structure, and the impedance of the combination of the coil structure and the pads is substantially equal to the impedance of the wiring structure.

[0021] In some embodiments, the pad has a capacitance C, the coil structure has an inductance L, and the capacitance C of the pad is related to the inductance L of the coil structure, satisfying the following conditions: Where Z0 is the target impedance.

[0022] Another aspect of this disclosure is a method comprising: providing a substrate; and forming pads on the surface of the substrate, wherein providing the substrate comprises: forming a transmission line, the transmission line comprising a coil structure adjacent to the pads, and the coil structure comprising a multi-turn curve wound around a central axis.

[0023] In some embodiments, the method includes determining at least one of the length of the coil structure or the number of turns of the multi-turn curve of the coil structure, based at least on the target impedance and capacitance of the pads.

[0024] In some embodiments, the transmission line includes a wiring structure extending from the coil structure. Forming the transmission line includes forming the transmission line such that the impedance of the combination of the coil structure and the pads is substantially equal to the impedance of the wiring structure.

[0025] In some embodiments, the coil structure of the transmission line at least partially overlaps with the pads.

[0026] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of this subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0027] The accompanying drawings, which are incorporated herein and form part of this disclosure, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0028] Figure 1A A side view of an example chip package is shown.

[0029] Figure 1B A side view of an example of a substrate and solder balls is shown.

[0030] Figure 1C It shows Figure 1B An enlarged view of the substrate area.

[0031] Figure 2A A plan view of an example chip package is shown.

[0032] Figure 2B It shows Figure 2AAn enlarged view of a pair of pads in a chip package.

[0033] Figure 3A A plan view showing an example of a coil structure for paired transmission lines in a chip package.

[0034] Figure 3B The chip package edge is shown Figure 3A A cross-sectional view of the A-A' axis.

[0035] Figure 3C An additional example of a coil structure for a transmission line is shown.

[0036] Figure 4A An example of an equivalent circuit for a transmission line is shown.

[0037] Figure 4B This is a table of examples of dimensionless coefficients for different coil shapes used in coil structures.

[0038] Figure 5A Examples of time-domain reflectometer (TDR) plots associated with various configurations of the transmission line are shown.

[0039] Figure 5B It shows the relationship with Figure 5A An example of an insertion loss diagram corresponding to a transmission line in the diagram.

[0040] Figure 6A An example of the simulation results of the impedance along a reference transmission line without a coil structure is shown.

[0041] Figure 6B An example of the simulation results for the impedance along an example transmission line with a coil structure is shown.

[0042] Figure 7 A flowchart illustrating an example method for forming a chip package is shown.

[0043] Figure 8 A block diagram of a system having one or more semiconductor devices is shown.

[0044] It should be understood that the various exemplary embodiments shown in the accompanying drawings are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0045] In semiconductor manufacturing, chip packaging is a step in semiconductor device fabrication that encapsulates one or more semiconductor dies of an integrated circuit within a support housing to protect them from physical damage, corrosion, etc. The support housing containing the encapsulated semiconductor die(s) can be referred to as a chip package. Impedance matching within a chip package can be critical for ensuring good signal integrity and reliable data transmission. In high-speed (e.g., greater than 1 Gbps) electronic systems, impedance mismatch between components can cause signal reflections, leading to data loss, increased error rates, and degraded performance. In some examples, chip packages may have ball grid array (BGA) packages, where solder balls are attached to corresponding pads on the BGA package. The pads can have large capacitances that can affect the impedance near the pads. Furthermore, as the transmission speeds of chip packages increase in the future, the capacitive effect of the pads on impedance matching may become more severe. This makes impedance matching near the pads even more challenging.

[0046] Embodiments of this disclosure provide chip packages and / or memory devices, and methods for forming such chip packages. In some embodiments, the chip package includes a substrate and pads located on the surface of the substrate. The substrate includes transmission lines coupled to the pads. The transmission lines include coil structures positioned adjacent to the pads, and the coil structures include multi-turn curves wound around a central axis.

[0047] Embodiments of this disclosure can provide one or more of the following technical advantages and / or benefits. First, the techniques described in this disclosure can improve impedance matching near pads. For example, in some embodiments, a transmission line in a chip package includes a coil structure at one end, and the coil structure is positioned adjacent to a pad. The coil structure can provide high inductance to offset the effect of the high capacitance of the pad on impedance. Therefore, the total impedance of the combined structure of the coil structure and the pad can be adjusted to match other segments of the transmission line, thereby improving impedance matching. Additionally, the techniques can provide flexibility in determining the geometric parameters of the coil structure (e.g., the inner diameter, outer diameter, width, number of turns, and / or fill ratio of the coil structure) to match characteristic impedance. Characteristic impedance can be the impedance of another segment of the transmission line (e.g., wiring structure), source / load impedance, or any other relevant impedance. The geometric parameters of the coil structure can be configured to ensure substantially uniform impedance along the transmission line. Improved impedance matching can reduce signal reflections and insertion losses along the transmission line, thereby enhancing signal integrity.

[0048] The technology can be applied to various types of semiconductor devices, volatile memory devices (such as DRAM memory devices), or non-volatile memory (NVM) devices (such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (such as PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc.). The technology can also be applied to charge-trapping based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating-gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory cell types, such as SLC (single-level cell), MLC (multi-level cell) (such as two-level cell), TLC (three-level cell), QLC (four-level cell), or PLC (five-level cell). Alternatively or concurrently, the technology can be applied to various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC), solid-state drives (SSDs) or universal flash memory (UFS), embedded systems, etc.

[0049] Figure 1A A side view of an example of a chip package 100 according to one or more embodiments of the present disclosure is shown. Figure 1B A side view of an example of a substrate and solder balls according to one or more embodiments of this disclosure is shown. Figure 1C It shows Figure 1B An enlarged view of region 122 of the substrate. For ease of description, reference will be made when describing the structure of the chip package 100. Figures 1A to 1C In this disclosure, chip package 100 may also be referred to as a memory device. Chip package 100 may be... Figure 8 The memory system 802.

[0050] Chip package 100 may include a substrate 110, and a memory structure 120 and a control structure 130 located on the substrate 110. In some embodiments, the chip package is a ball grid array (BGA) package based on universal flash memory (UFS) technology. It should be noted that the techniques described in this disclosure are also applicable to other types of BGA packages. For example, the techniques described in this disclosure can be applied to a package in which multiple chips are vertically stacked, and the multiple chips can be coupled to each other through through-silicon vias (TSVs). In another example, the techniques can be applied to a package in which multiple chips are vertically stacked but offset from each other in a lateral direction to expose edge portions of the lower chips, and the exposed edge portions of the lower chips can be used to form conductive lines for coupling to other chips.

[0051] Memory structure 120 and control structure 130 can be any suitable chip. Memory structure 120 and control structure 130 can include various components for providing storage, computing, and / or processing functions. In some examples, memory structure 120 can be a high-bandwidth memory (HBM) device. Control structure 130 can be a processor, logic die, or controller. In some embodiments, memory structure 120 can include one or more memory dies stacked vertically on top of each other. Each memory die can include a memory substructure and a control substructure. The memory substructure can include at least one memory array, and each memory array can include multiple memory cells. Memory cells can be DRAM memory cells, NAND memory cells, ferroelectric memory cells, or any other suitable memory cells.

[0052] The control substructure may include peripheral circuitry for the memory substructure. Peripheral circuitry (e.g., control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory array. For example, peripheral circuitry may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry in control structure 130 may be implemented using CMOS technology, for example, utilizing logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, etc.).

[0053] Chip package 100 may include a molding encapsulant 140 configured to encapsulate at least memory structure 120 and control structure 130 on substrate 110. The molding encapsulant 140 may be made of any suitable material, such as silica filler, resin, etc. In some embodiments, the molding encapsulant 140 includes an epoxy molding compound (EMC). The molding encapsulant 140 may cover and protect the memory structure 120 and control structure 130, enhance the mechanical strength of chip package 100, and protect against environmental factors (e.g., moisture or dust). Figure 1A The molding encapsulant 140 is depicted as covering the top surfaces of the memory structure 120 and the control structure 130, but in some examples, the molding encapsulant 140 may at least partially expose the top surfaces of the memory structure 120 and / or the control structure 130.

[0054] The substrate 110 can be made of a suitable insulating material (e.g., a dielectric material), such as an epoxy resin-based substrate, a resin-based bismaleimide triazine (BT) substrate, etc. The substrate 110 can be relatively rigid to provide mechanical support to the memory structure 120 and the control structure 130. The substrate 110 has a first surface 111 and a second surface 112 opposite to the first surface 111 along a vertical direction (e.g., the Z direction). The memory structure 120 and the control structure 130 can be disposed on the second surface 112 of the substrate 110, such as... Figure 1A As shown.

[0055] The substrate 110 may also provide electrical support for the memory structure 120 and the control structure 130. In some embodiments, the substrate 110 includes one or more layers of conductive lines, such as copper wires, with insulating material between them. Conductive lines 106 on different layers can be connected via vias 108. The conductive lines 106 can provide interconnections from the inputs / outputs of the memory structure 120 and the control structure 130 to contact structures 162 (e.g., solder balls) formed on the first surface 111 of the chip package 100. The memory structure 120 and the control structure 130 may include input / output (I / O) pads (not shown) electrically connected to the internal memory array and / or circuitry of the memory structure 120 and the control structure 130.

[0056] Furthermore, the chip package 100 may include pads 102 on a first surface 111 of the chip package 100 to couple to contact structure 162. The pads may include one or more conductive materials, such as copper (Cu), nickel (Ni), gold (Au), or any other suitable material. In some embodiments, the chip package 100 is a BGA package (e.g., as shown in the image). Figure 1B and Figure 2A (As shown), and each of the contact structures 162 may be a solder ball formed on the corresponding pad 102. It should be noted that in some examples, the contact structure 162 may not be a solder ball. In one example, the chip package 100 is a Pad Grid Array (LGA) package, and each of the contact structures 162 may include a pad 102 (e.g., a flat contact pad). In another example, the chip package 100 is a Pin Grid Array (PGA) package, and each of the contact structures 162 includes a pin.

[0057] The substrate 110 may also include a transmission line 104 coupled to the pads 102 and the conductive lines 106, such as Figure 1A and Figure 1CAs shown. Transmission line 104 may comprise one or more conductive materials, such as Cu or any other suitable material. A first end 104a of transmission line 104 may be positioned adjacent to pad 102. A second end (not shown) of transmission line 104 may extend away from pad 102 (e.g., along the Y direction). For example, as... Figure 1A As shown, the first end 104a of the transmission line 104 can be located directly above the pad 102. As used herein, when the pads on the first surface of the substrate face down and the memory and control structures on the second surface of the substrate face up, whether a component (e.g., a layer, structure, or device) is “on,” “above,” or “below” another component (e.g., a layer, structure, or device) of a chip package (e.g., chip package 100) is determined in the z-direction (i.e., the vertical direction) relative to the first surface of the chip package substrate (e.g., the first surface 111 of substrate 110).

[0058] In some examples, such as Figure 1C As shown, the first end 104a of the transmission line 104 may at least partially overlap with the pad 102. See below for reference. Figures 2A to 3B In more detail, the first end 104a of the transmission line 104 includes a coil structure.

[0059] In some embodiments, the transmission line 104 is connected to the pad 102 via a vertical protrusion 105. In some embodiments, the vertical protrusion 105 is part of the transmission line 104. In some embodiments, the vertical protrusion 105 is a via.

[0060] Transmission line 104, pad 102, and contact structure 162 can be configured to electrically interface memory structure 120 and / or control structure 130 within chip package 100 to components outside chip package 100. In some embodiments, a first end 104a of transmission line 104 is coupled to pad 102, and a second end of transmission line (e.g., Figure 6B The second end 600b) of transmission line 600 is coupled to control structure 130. Transmission line 104 can be coupled to control structure 130 through corresponding vias and / or conductive lines 106. In some embodiments, transmission line 104 is configured to transmit high-speed signals (e.g., between 1Gbps and 50Gbps). For example, transmission line 104 can be configured to transmit serializer-deserializer (SERDES) signals based on the Mobile Industry Processor Interface (MIPI) M-PHY protocol.

[0061] Figure 2A A plan view of an example chip package 200 is shown. Chip package 200 may be a BGA package. Chip package 200 may be... Figure 8The memory system 802. In the chip package 200, pads 202 may be arranged in a two-dimensional grid pattern 201 across a first surface 211 of the substrate 210 of the chip package 200. The grid pattern 201 may include fine-pitch pads and / or coarse-pitch pads. Fine-pitch pads may have smaller distances between them (e.g., 0.8 mm, 0.5 mm, or even finer), thereby allowing for higher component density, while coarse-pitch pads may have larger distances between them (e.g., 13 mm or more). In some examples, the grid pattern 201 may include fine-pitch pads and coarse-pitch pads based on a specific package design, such as Figure 2A As shown. In some examples, the grid pattern 201 can be symmetrical to distribute mechanical force evenly during the welding process.

[0062] In some examples, the pads 202 in the chip package 200 can be arranged in pairs. Each pair of pads 202 includes two pads 202 positioned adjacent to each other. Figure 2B It shows Figure 2A An enlarged view of a pair of pads 202 in the chip package 200. Differential signaling technology can be used with the chip package 200 to ensure signal integrity and reduce issues such as interference, crosstalk, and / or reflections. The pair of pads 202 can be used for two complementary signals in the differential signaling (e.g., P-channel and N-channel). The paired pads 202 (and corresponding contact structures) can be positioned adjacent to each other to help maintain consistent impedance and reduce noise.

[0063] Chip package 200 may also include one or more transmission lines ( Figure 2A (Not shown in the diagram), which is configured to be routed to the corresponding pad 202 according to the signal path. Corresponding to the pairs of pads 202, the transmission lines can also be arranged in pairs, wherein each transmission line is coupled to its corresponding pad 202. In some embodiments, see the following reference. Figures 3A to 3C As described in further detail, the first end of the transmission line adjacent to pad 202 may have a coil structure to improve impedance matching.

[0064] Figure 3A A plan view showing an example of a coil structure 303 for a pair of transmission lines 304 in a chip package 300. Figure 3B It shows along Figure 3A A cross-sectional view of the chip package 300 along the A-A' axis. For ease of description, reference will be made when describing the structures of the coil structure 303 and the chip package 300. Figure 3A and Figure 3B Both.

[0065] like Figure 3AAs shown, the paired transmission lines 304 may include a first transmission line 304A and a second transmission line 304B. The paired transmission lines 304 may be coupled to paired pads for transmitting differential signals (e.g., Figure 2B (paired pads 202). In some embodiments, the first transmission line 304A is configured to transmit a positive signal, and the second transmission line 304B is configured to transmit a negative signal.

[0066] In some embodiments, each of the first transmission line 304A and the second transmission line 304B includes a coil structure 303 and a wiring structure 305. Transmission lines 304A and 304B may have the same or substantially similar layout, and the coil structures 303 of the transmission lines 304 may be positioned adjacent to each other in a symmetrical manner, such as... Figure 3A As shown. In some embodiments, transmission line 304 is made of copper. It should be understood that transmission line 304 is not necessarily drawn to scale. Wiring structure 305 may be larger than... Figure 3A The wiring structure depicted in the image is longer.

[0067] In some implementations, the coil structure 303 is connected to the pads (e.g., Figure 3B The pads 302 are positioned adjacent to each other, and the coil structure 303 includes a multi-turn curve 314 wound around a central axis. The central axis may be an axis extending perpendicular to its plane through the center of the coil structure 303. For example, the central axis may be... Figure 3B The axis B-B'. Figure 3A The example embodiment shown has two curves 314 for each coil structure 303. Each curve 314 of the coil structure 303 can be a thin, narrow conductive trace. Each curve 314 can include multiple straight segments connected in series, such as... Figure 3A As shown. Curve 314 can also have a circular shape (e.g., as shown). Figure 3C (As shown). In some embodiments, the coil structure 303 includes a conductive material, such as copper.

[0068] In some embodiments, the coil structure 303 has a uniform spacing between adjacent turns in the multi-turn curve 314. In some embodiments, each curve in the multi-turn curve 314 has a different perimeter. For example, the inner turns may have a smaller perimeter, while the outer turns may have a larger perimeter. The geometric parameters of the coil structure 303 (e.g., the inner diameter, outer diameter, width, number of turns, and / or fill ratio of the coil structure 303) can be determined based on a target impedance (e.g., characteristic impedance) to improve impedance matching along the transmission line 304, as referenced below. Figures 4A to 4B A more detailed description.

[0069] In some embodiments, the coil structure 303 includes a planar helical coil. For example, the multi-turn curve 314 may be formed on a single plane or in a single layer, such as... Figure 3A As shown. In some embodiments, the coil structure 303 is a multilayer structure with vias connecting different layers. Each layer in the multilayer coil structure may include one or more turns of curve 314.

[0070] One end 303-1 of the coil structure 303 may be terminated at or adjacent to the central axis, while the other end 303-2 of the coil structure 303 may be connected to a corresponding wiring structure 305. In some embodiments, the wiring structure 305 may be an elongated structure extending away from the coil structure 303. The wiring structure 305 may be a microstrip, stripline, or coplanar waveguide. The wiring structure 305 may be a thin, narrow conductive trace within the substrate 310. The width and thickness of the wiring structure 305 may be configured to match the characteristic impedance of the signal and / or ensure impedance matching along the transmission line 304. In some examples, the wiring structure 305 is about a few micrometers to tens of micrometers wide. In some embodiments, one end of the wiring structure 305 is connected to the coil structure 303, while the other end of the wiring structure 305 is coupled to a control structure (e.g., Figure 1A (130). In some embodiments, the wiring structure 305 is via conductive lines (e.g., Figure 1A 106) and vias (e.g., Figure 1A 108) is coupled to the control structure (e.g., Figure 1A (130). In some embodiments, wiring structure 305 comprises the same material as coil structure 303.

[0071] refer to Figure 3B The coil structures 303A and 303B of the transmission line 304 can be positioned adjacent to the pads 302A and 302B, respectively (e.g., directly above the pads 302A and 302B). In some embodiments, the coil structure 303 of the transmission line 304 is in direct contact with the corresponding pad 302. For example, as... Figure 3B As shown, coil structure 303A can directly contact pad 302A, while coil structure 303B can directly contact pad 302B. In some embodiments, the coil structure 303 of transmission line 304 is coupled to pad 302 via a via. For example, briefly turning... Figure 1C The coil structure (e.g., in the first end 104a of the transmission line 104) is coupled to the pad 102 through a vertical protrusion 105 (e.g., a via).

[0072] It should be understood that Figure 3B It may not be drawn to scale. Although Figure 3BThe diagram shows that the coil structure 303 and its corresponding pad 302 have similar thicknesses or lateral dimensions, but the coil structure 303 and pad 302 can have different thicknesses (e.g., along the Z direction) and / or lateral dimensions (e.g., along the X and Y directions). Additionally, although in Figure 3B The coil structure 303 is depicted as a solid block, but the coil structure 303 may have a fill ratio of less than 100% (e.g., the proportion of the coil structure occupied by conductive material), such as... Figure 3A As shown.

[0073] Figure 3C Additional examples of the coil structure for transmission line 304 are shown. In some embodiments, the coil structure includes at least one of a planar square helical coil 324, a planar rectangular helical coil, a planar hexagonal helical coil 322, a planar octagonal helical coil 320, or a planar circular helical coil 326. Without being limited to any particular theory, the planar hexagonal or octagonal helical coils 320, 322 can provide better space utilization compared to a circular design, the planar square or rectangular helical coil 324 can provide a simple manufacturing process, and the planar circular helical coil 326 can provide better performance by reducing resistance and losses due to sharp corners. It should be understood that... Figure 3A and Figure 3C The examples in the text are for illustrative purposes and are not intended to be construed as limiting. Other coil shapes may also be used in the coil structure.

[0074] Figure 4A An example of an equivalent circuit 400 for a transmission line is shown. The transmission line can be any implementation of the transmission line included in this disclosure, for example, Figures 1A to 1C Transmission line 104 and / or Figures 3A to 3C Transmission line 304. For illustrative purposes and for simplicity, it will be referred to in the following discussion as... Figures 3A to 3B Transmission line 304 and Figures 3A to 3B Pad 302 is used as an example. It should be understood that... Figure 4A The equivalent circuit 400 in the diagram can be simplified and is not intended to be limiting. Other equivalent circuits are also possible for transmission line 304.

[0075] Without being limited to any specific theory, when transmitting high-speed signals through transmission line 304, a section of transmission line 304 can be approximated as an LC series-parallel circuit, such as... Figure 4A As shown. The impedance of a section of transmission line 304 can be approximately calculated using the following formula:

[0076]

[0077] Where C is the capacitance per unit length (or unit area), L is the inductance per unit length (or unit area), and Z0 is the impedance.

[0078] Because pad 302 is coupled to coil structure 303 of transmission line 304, the combined structure of pad 302 and coil structure 303 can be considered a segment of transmission line 304. In some examples, it is associated with other segments of transmission line 304 (e.g., Figure 3A Compared to the wiring structure 305, the pad 302 can have a larger capacitance C. Without the coil structure 303 to enhance the inductance L, the total impedance of the combined structure can be less than other sections of the transmission line 304, resulting in impedance mismatch. Impedance mismatch can cause signal reflection, thereby reducing the integrity of high-speed signals and causing high signal loss and power dissipation. In contrast, by utilizing the coil structure 303 to increase the inductance L of the combined structure, the total impedance of the combined structure can be adjusted to match the impedance of other sections of the transmission line 304, thereby reducing signal loss and improving signal integrity.

[0079] In some implementations, the combined impedance of coil structure 303 and pad 302 is substantially equal to the impedance of wiring structure 305. In some examples, coil structure 303 can be designed based on a target impedance of the combined structure. The target impedance for the combined structure can be the characteristic impedance of wiring structure 305, source / load impedance, or any other impedance used for impedance matching purposes. Examples of target impedances include 50 ohms, 75 ohms, 100 ohms, or any other suitable value. Based on the target impedance, the geometric parameters of coil structure 303 (e.g., inner diameter, outer diameter, width, number of turns, and / or fill ratio of coil structure 303) can be determined by the following steps:

[0080] Step 1: Capacitor C based on pad 302 S The target impedance Z of the combined structure used for pad 302 and coil structure 303 T Equation 1 is used to determine the required inductance L of coil structure 303. C ;as well as

[0081] Step 2: Based at least on the required inductance L of the coil structure 303 obtained from Step 1 C To determine the geometric parameters of coil structure 303. Different coil shapes may have different correlations between inductance and geometric parameters. In some examples, a single-layer circular helical coil structure (e.g., Figure 3C The inductance of 326 can be based on a modified Harold A. Wheeler formula related to its geometric parameters:

[0082]

[0083] Where L is the inductance in Henry, μ0 is the permeability of free space (H / m), and a is the average radius in meters. Where d in It is the inner diameter, d out It is the outer diameter, and c is the width of the coil in meters. And n is the number of turns.

[0084] In some examples, single-layer square, hexagonal, and octagonal spiral coils (e.g., Figure 3C The inductances of 324, 322, and 320 can be derived from their geometric parameters based on a modified Wheeler formula:

[0085]

[0086] Where L is the inductance in Henry, μ0 is the permeability of free space (H / m), n is the number of turns, and d... avg The average diameter is expressed in meters, and K1 and K2 are empirical dimensionless coefficients that can depend on the coil shape, and ρ is the coil fill ratio, which is defined as... Where d in It is the inner diameter, d out It is the outer diameter. Figure 4B A table is shown showing example dimensionless coefficients for different shapes of coil structures used in Equation 3. For example, for a single-layer octagonal helical coil, K1 can be 2.25 and K2 can be 3.55.

[0087] It should be noted that Equations 2 and 3 are not intended to be interpreted in a limited sense; other formulas can be used to determine the required inductance L based on coil structure 303. C The geometric parameters of the coil structure 303 are calculated for impedance matching along the transmission line 304.

[0088] Figure 5A Examples of time-domain reflectometer (TDR) plots associated with various configurations of the transmission line are shown. Figure 5B It shows the relationship with Figure 5AExamples of insertion loss diagrams corresponding to transmission lines are provided. Specifically, curves 502 and 512 correspond to reference transmission line #1, which has a wiring structure with a length of 5300 μm but no coil structure. According to one or more embodiments of this disclosure, curves 504 and 514 correspond to transmission line #2, which has a coil structure 303 adjacent to pad 302 and a wiring structure 305 with a length of 7000 μm. Curves 506 and 516 correspond to reference transmission line #3, which has a wiring structure with a length of 5300 μm but no coil structure. The difference between reference transmission line #3 and reference transmission line #1 is that the space below the pad is empty in reference transmission line #3. According to one or more embodiments of this disclosure, curves 508 and 518 correspond to transmission line #4, which has a coil structure 303 adjacent to pad 302 and a wiring structure 305 with a length of 5300 μm. Transmission line #4 differs from transmission line #2 in the length of its wiring structure.

[0089] refer to Figure 5A In the coordinate system, the horizontal axis represents time in nanoseconds (ns), while the vertical axis represents impedance in ohms. Time on the horizontal axis can correspond to the travel time of a signal propagating along transmission lines #1, #2, #3, and #4 at a specific speed. Therefore, the horizontal axis can indirectly represent different positions along transmission lines #1, #2, #3, and #4, and the vertical axis can thus represent the impedance along the longitudinal length of transmission lines #1, #2, #3, and #4. For example, for transmission lines #2 and #4 according to one or more embodiments of this disclosure, region 510 of curves 504 and 508 can indicate the impedance of the combined structure of coil structure 303 and pad 302. For a reference transmission line #1 without a coil structure, region 510 of curve 502 can indicate the impedance of the pad 302 and the end section of the reference transmission line (e.g., the end section 612 without a coil shape, such as...). Figure 6A (As shown). For reference transmission line #3 without a coil structure, region 510 of curve 506 can indicate only the impedance of pad 302. For all four transmission lines, region 520 can indicate the impedance of other segments along the transmission line. For example, regions 520 of transmission lines #2 and #4 can correspond to... Figures 3A to 3B The impedance of the wiring structure 305 of the transmission line 304, and / or Figure 6B The impedance of the wiring structure 605 of transmission line 604. Region 520 of reference transmission line #1 can be... Figure 6A The wiring structure is 622.

[0090] Continue to refer to Figure 5AWithout a coil structure to compensate for the inductance in region 510, reference transmission lines #1 and #3 (corresponding to curves 502 and 506) have low impedance, which is mismatched with other sections of the corresponding transmission lines (e.g., region 520). In contrast, according to one or more embodiments of this disclosure, by utilizing coil structure 303 to compensate for the inductance in region 510, the impedance in region 510 can be increased, thereby effectively reducing the impedance mismatch with other sections of the transmission line (e.g., region 520). Figure 5A As shown, the impedance difference between regions 510 and 520 of transmission lines #2 and #4 (corresponding to curves 504 and 508) is significantly smaller than the impedance difference of reference transmission lines #1 and #3 (corresponding to curves 502 and 506). This improved impedance mismatch reduces signal reflections along transmission lines #2 and #4 and improves signal quality.

[0091] Now for reference Figure 5B ,exist Figure 5B In the coordinate system depicted, the horizontal axis represents the frequency of the signal transmitted through the transmission line, while the vertical axis represents the insertion loss of the signal. For example... Figure 5B As shown, insertion loss may increase with increasing frequency due to factors including resistive loss and skin effect. As mentioned above, the four insertion loss curves 512, 514, 516, and 518 correspond to four different transmission line configurations. For each insertion loss curve 512, 514, 516, and 518, the corresponding dashed lines 512a, 514a, 516a, and 518a connect the first and second resonant points of the insertion loss, and the slope of the dashed line corresponds to the rate of change of the insertion loss. A steeper slope of the dashed line indicates a faster insertion loss, while a gentler slope indicates a smoother change. Figure 5B As shown, the dashed lines 512a and 516a (corresponding to...) Figure 5A Compared to the slopes of reference transmission lines #1 and #3 (excluding coil structures), dashed lines 514a and 518a (corresponding to...) Figure 5A The slopes of the transmission lines #2 and #4, each including a coil structure, are much gentler. This indicates that embodiments of this disclosure can have lower insertion loss. Additionally, as Figure 5B As shown, the improvement in insertion loss can be more significant at higher frequencies. Lower insertion loss can mean less signal attenuation, thus providing improved transmission range and high-frequency performance.

[0092] Figure 6A An example of simulation results for the impedance along a reference transmission line without a coil structure is shown. The reference transmission line can be the one mentioned above. Figure 5A and Figure 5B The reference transmission line #1 is described. Figure 6BAn example of simulation results for the impedance along a transmission line 604 having a coil structure 603 according to one or more embodiments of this disclosure is shown. The transmission line 604 having the coil structure 603 can be any embodiment of the transmission line included in this disclosure, for example, Figures 1B to 1C Transmission line 104 Figures 3A to 3B Transmission line 304, or refer to the above. Figure 5A and Figure 5B The transmission lines #2 and #4 are described. Figure 6B The coil structure 603 in the middle can have the same as Figure 3A The coil structure 303 has the same or similar coil shape. Figure 6A and Figure 6B Different shades in the diagram can represent different impedances, with lighter shades indicating lower impedances.

[0093] like Figure 6A As shown, the impedance of the reference assembly structure 620 (which includes the end section 612 of the reference transmission line #1 (without coil structure) and the pads) may be lower than the impedance of other sections of the reference transmission line #1, indicating a significant impedance mismatch. As mentioned above, the lower impedance of the reference assembly structure 620 may be attributed to the larger capacitance of the pads.

[0094] In comparison, such as Figure 6B As shown, in the case of using coil structure 603 to compensate for inductance, it includes coil structure 603 and pads (e.g., Figure 3B The impedance of the combined structure 610 (302) can be substantially equal to the impedance of the wiring structure 605. Therefore, with Figure 6A Compared to reference transmission line #1, the impedance along transmission line 604 can be more uniform. Therefore, embodiments of this disclosure can significantly improve impedance mismatch, thereby providing better signal integrity during transmission.

[0095] Figure 7 A flowchart illustrating the process of an example method 700 for forming a chip package is shown. The chip package can be, for example... Figures 1A to 1C Chip package 100, Figures 2A to 2B Chip package 200 or Figures 3A to 3C The chip is packaged in 300.

[0096] At step 702, a substrate is provided. The substrate may be, for example... Figures 1A to 1C substrate 110, Figures 2A to 2B substrate 210, or Figures 3A to 3B The substrate 310.

[0097] At step 704, pads are formed on the surface of the substrate. Providing the substrate includes forming a transmission line, the transmission line including a coil structure adjacent to the pads, and the coil structure including a multi-turn curve wound around a central axis. The pads may be, for example... Figures 1A to 1C pad 102, Figures 2A to 2B pad 202, or Figures 3A to 3B The pad 302. The transmission line can be, for example... Figures 1A to 1C Transmission line 104 Figures 3A to 3C Transmission line 304, reference Figures 5A to 5B The described transmission lines #2, #4, or Figure 6B The transmission line 604. The coil structure can be, for example... Figure 3A and Figure 3B coil structure 303, Figure 3C Any of the spiral coils 320, 322, 324, and 326, reference Figures 5A to 5B The described coil structure of transmission lines #2 and #4, or Figure 6B The coil structure 603.

[0098] In some implementations, the method includes determining at least one of the length of the coil structure or the number of turns of a multi-turn curve of the coil structure, based at least on the target impedance and capacitance of the pads, as referenced above. Figures 4A to 4B As stated above.

[0099] In some implementations, the transmission line includes a wiring structure extending from the coil structure. Forming the transmission line includes forming the transmission line such that the impedance of the combination of the coil structure and the pads is substantially equal to the impedance of the wiring structure, as referenced above. Figures 4A to 6B The wiring structure can be, for example... Figure 3A Wiring structure 305 or Figure 6B The wiring structure is 605.

[0100] In some implementations, the coil structure of the transmission line at least partially overlaps with the pads, for example, as... Figures 1A to 3B As shown.

[0101] Figure 8 A block diagram of a system 800 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of this disclosure is shown. System 800 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 8As shown, system 800 may include a host device 808 and a memory system 802 having one or more 3D memory devices 804 and a memory controller 806. The host device 808 may include a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). The host device 808 may be configured to send data to or receive data from one or more 3D memory devices 804.

[0102] In some implementations, the 3D memory device 804 may be Figures 1A to 1C The memory structure 120 in the memory device or chip package 100 Figures 2A to 2B The memory structure in the chip package 200, or Figures 3A to 3C The memory structure in the chip package 300.

[0103] In some implementations, the memory system 802 can be any 3D memory device disclosed herein, such as Figures 1A to 1C Memory devices or chip packages 100 Figures 2A to 2B Chip package 200, or Figures 3A to 3C The chip package is 300. As mentioned above, the memory system 802 can be UFS.

[0104] In some embodiments, the 3D memory device 804 includes NAND flash memory. A memory controller 806 (also referred to as controller circuitry) is coupled to the 3D memory device 804 and the host device 808. Consistent with embodiments of this disclosure, the 3D memory device 804 may include a plurality of conductive interconnects through a cover layer that contact conductive pads in a conductive pad layer, and the memory controller 806 may be coupled to the 3D memory device 804 through at least one of the plurality of conductive interconnects. The memory controller 806 is configured to control the 3D memory device 804. For example, the memory controller 806 may be configured to operate a plurality of channel structures via word lines. The memory controller 806 may manage data stored in the 3D memory device 804 and communicate with the host device 808.

[0105] In some embodiments, the memory controller 806 is designed / configured to operate in low duty cycle environments (e.g., Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 806 is designed / configured to operate in high duty cycle environments such as SSDs or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 806 can be configured to control the operation of the 3D memory device 804, such as read, erase, and program (or write) operations. The memory controller 806 can also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 804, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 806 is also configured to process error correction codes (ECC) regarding data read from or written to the 3D memory device 804. The memory controller 806 may also perform any other suitable function, such as formatting the 3D memory device 804.

[0106] The memory controller 806 can communicate with external devices (e.g., host device 808) according to a specific communication protocol. For example, the memory controller 806 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, FireWire protocol, etc.

[0107] The memory controller 806 and one or more 3D memory devices 804 can be integrated into various types of memory devices, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 802 can be implemented and packaged into different types of end electronic products. Figure 8In one example shown, the memory controller 806 and a single 3D memory device 804 can be integrated into the memory card 802. The memory card 802 may include PC cards (PCMCIA (Personal Computer Memory Card International Association)), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0108] The subject matter and embodiments of action and operation described in this disclosure can be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or in combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs encoded on a computer program carrier, such as one or more modules of computer program instructions, for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagated signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by a data processing apparatus. The computer storage medium can be one or more of the following: a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof. The computer storage medium is not a propagated signal.

[0109] Note that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," "an implementation," "an implementation," "an example implementation," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, its effect in conjunction with other implementations (whether explicitly described or not) on such feature, structure, or characteristic will be within the knowledge of those skilled in the art.

[0110] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can be understood to express either a singular or a plural usage, depending at least partly on the context. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but can also allow for the presence of additional factors that are not necessarily explicitly described, again depending at least partly on the context.

[0111] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on” something, but also includes the meaning of “on” when there is an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above” or “on top of” something, but can also include the meaning of “above” or “on top of” something (i.e., directly on) when there is no intermediate feature or layer between them.

[0112] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship of one element or feature relative to another element(s) or feature(s) as shown in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of the equipment in use or process steps. The equipment may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0113] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0114] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (in which contacts, interconnects, and / or vertical interconnect channels (vias)) and one or more dielectric layers.

[0115] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10%–30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0116] As used in this disclosure, the terms “substantially” or “basically” mean the majority or most, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0117] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.

[0118] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0119] As used in this article, the term "surrounded by" means being at least partially surrounded by. For example, "A is surrounded by B" can mean that A is at least partially surrounded by B.

[0120] As used herein, the term “and / or” means and covers any and all possible combinations of one or more of the associated listed items. For example, the term “A and / or B” means that option A, option B, or both options A and B are possible, where A and B can be singular or plural.

[0121] This disclosure provides numerous different implementations or examples for carrying out various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include implementations in which the first and second features can be in direct contact, and may also include implementations in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, in various examples, reference numerals and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity and does not, in itself, prescribe a relationship between the various implementations and / or configurations discussed.

[0122] The foregoing description of specific embodiments can be readily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance given herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0123] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims (which are defined by the claims themselves), but rather as descriptions of features specific to particular embodiments of a particular invention. Certain features described in this disclosure in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, in some cases, one or more features from the claimed combination may be removed from the combination, and the claims may be for sub-combinations or variations thereof.

[0124] Similarly, although operations are shown in the accompanying drawings and recited in the claims in a specific order, this should not be construed as requiring such operations to be performed in the specific or sequential order shown, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0125] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the processes shown in the figures do not necessarily require the specific or sequential order shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0126] The scope and extent of this disclosure should not be limited by any of the embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A chip package, comprising: substrate; as well as A pad located on the surface of the substrate, wherein the substrate includes a transmission line coupled to the pad, the transmission line including a coil structure positioned adjacent to the pad, and the coil structure including a multi-turn curve wound around a central axis.

2. The chip package according to claim 1, wherein, The coil structure of the transmission line at least partially overlaps with the pad.

3. The chip package according to claim 1 or 2, wherein, The coil structure includes a planar helical coil.

4. The chip package according to claim 3, wherein, The planar spiral coil includes at least one of a planar square spiral coil, a planar rectangular spiral coil, a planar hexagonal spiral coil, or a planar octagonal spiral coil.

5. The chip package according to any one of claims 1 to 4, wherein, The transmission line includes a wiring structure extending from the coil structure, and the impedance of the combination of the coil structure and the pads is substantially equal to the impedance of the wiring structure.

6. The chip package according to any one of claims 1 to 5, wherein, The pad has a capacitance C, the coil structure has an inductance L, and the capacitance C of the pad is related to the inductance L of the coil structure, satisfying the following condition: Where Z0 is the target impedance.

7. The chip package according to any one of claims 1 to 6, wherein, The coil structure has a uniform spacing between adjacent turns in the multi-turn curve.

8. The chip package according to any one of claims 1 to 7, wherein, Each curve in the multi-turn curve has a different perimeter.

9. The chip package according to any one of claims 1 to 8, wherein, The transmission line is configured to transmit serializer-deserializer (SERDES) signals.

10. The chip package according to any one of claims 1 to 9, wherein, The chip package includes a ball grid array (BGA) package, which includes the substrate and the pads are connected to solder balls.

11. A memory device, comprising: substrate; solder pads, which are located on the substrate. The substrate includes: A transmission line coupled to the pad, the transmission line including a coil structure positioned adjacent to the pad, and the coil structure including a multi-turn curve wound around a central axis; and Conductive wire; A memory structure comprising a plurality of memory cells and located on the substrate; and A control structure, comprising a control circuit and located on the substrate. The memory structure is coupled to the control structure via the conductive lines on the substrate.

12. The memory device according to claim 11, wherein, The transmission line has a first end coupled to the control structure and a second end coupled to the pad, the second end including the coil structure.

13. The memory device according to claim 11 or 12, comprising: A molding encapsulant configured to encapsulate at least the memory structure and the control structure on the substrate.

14. The memory device according to any one of claims 11 to 13, wherein, The coil structure of the transmission line at least partially overlaps with the pad.

15. The memory device according to any one of claims 11 to 14, wherein, The transmission line includes a wiring structure extending from the coil structure, and the impedance of the combination of the coil structure and the pads is substantially equal to the impedance of the wiring structure.

16. The memory device according to any one of claims 11 to 15, wherein, The pad has a capacitance C, the coil structure has an inductance L, and the capacitance C of the pad is related to the inductance L of the coil structure, satisfying the following condition: Where Z0 is the target impedance.

17. A method comprising: Provide substrate; as well as Pads are formed on the surface of the substrate. The provision of the substrate includes: forming a transmission line, the transmission line including a coil structure adjacent to the pad, and the coil structure including a multi-turn curve wound around a central axis.

18. The method of claim 17, comprising: The length of the coil structure or the number of turns of the multi-turn curve of the coil structure is determined based at least on the target impedance and capacitance of the pads.

19. The method according to claim 17 or 18, in, The transmission line includes a wiring structure extending from the coil structure, and The formation of the transmission line includes forming the transmission line such that the impedance of the combination of the coil structure and the pad is substantially equal to the impedance of the wiring structure.

20. The method according to any one of claims 17 to 19, wherein, The coil structure of the transmission line at least partially overlaps with the pad.

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