Systems and methods for encoding and decoding in accordance with a communication protocol

Abstract

A system for encoding and decoding in accordance with a communication protocol is provided and can include a transmitter having a transmit data buffer to store data, an encoding circuit operatively coupled to the transmit data buffer to receive the data from the transmit data buffer and encode the data based on a selected encoding method, and a transmit shift register operatively coupled to the encoding circuit to receive the encoded data and transmit the encoded data in a bit-by-bit manner. The system can include a receiver having a receive shift register to receive the encoded data, a decoding circuit operatively coupled to the receive shift register to receive the encoded data from the receive shift register in a parallel manner and decode the encoded data based on a selected decoding method, and a receive data buffer operatively coupled to the decoding circuit to receive the decoded data.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Nonprovisional Patent Application No. 19 / 093,416, filed March 28, 2025, and U.S. Provisional Patent Application No. 63 / 570,900, filed March 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates in general to data communication, and more specifically to systems and methods for encoding and decoding data in accordance with communication protocols. Background Technology

[0003] Communication with secure integrated circuits can be achieved through proprietary interfaces or by relying on internal integrated circuit (I2C) buses. Some single-wire solution protocols are based on communication protocols such as Serial Peripheral Interface (SPI) or Universal Asynchronous Receiver / Transmitter (UART / Universal Synchronous Receiver / Transmitter (USRT), which use one frame per bit. For example, a mating addressable LED can be based on SPI, where the amount of time a signal is high or low determines whether the frame is 0 or 1. These communication protocols introduce increased software overhead when encoding and decoding individual data bits due to significant computational requirements. Furthermore, these protocols have limited data transfer efficiency and limit the overall communication speed by transmitting data bit by bit. Proprietary solutions often limit compatibility with specific ICs, thus hindering broader applicability. Therefore, there is a need for improved systems and methods for encoding and decoding data according to communication protocols. Summary of the Invention

[0004] According to one aspect of one or more examples, a system for encoding and decoding data according to a communication protocol is provided. The system may include a transmitter and a receiver. The transmitter may include: a transmit data buffer for storing data; encoding circuitry operatively coupled to the transmit data buffer; and a transmit shift register operatively coupled to the encoding circuitry. The encoding circuitry may receive data bit-by-bit from the transmit data buffer, select an encoding method based on a first control signal received from a first control register, and encode the data based on the selected encoding method and a first plurality of reference data values. The transmit shift register may receive the encoded data and transmit the encoded data bit-by-bit. The receiver may include: a receive shift register for receiving the encoded data bit-by-bit; decoding circuitry operatively coupled to the receive shift register; and a receive data buffer operatively coupled to the decoding circuitry. The decoding circuitry may receive the encoded data from the receive shift register, which shifts the bit-by-bit data into complete bytes before transmitting the bytes to the decoding circuitry in parallel. The decoding circuit can select a decoding method based on a second control signal received from a second control register, and decode the encoded data based on the selected decoding method and a plurality of reference data values. A receive data buffer can receive the decoded data.

[0005] The first plurality of reference data values ​​used for encoding may include a first encoded data value stored in a first reference register of the encoding circuit and a second encoded data value stored in a second reference register of the encoding circuit. The second plurality of reference data values ​​used for decoding may include a first decoded data value stored in a first reference register of the decoding circuit, a second decoded data value stored in a second reference register of the decoding circuit, and a third decoded data value stored in a third reference register of the decoding circuit. The system may include a baud rate generator for generating a baud rate for the system.

[0006] According to one aspect of one or more examples, a method for encoding and decoding according to a communication protocol is provided. The method may include: receiving data bit-by-bit from a transmit data buffer of a transmitter; selecting an encoding method based on a first control signal received from a first control register of an encoding circuit of the transmitter; encoding the data based on the selected encoding method and a first plurality of reference data values; receiving the encoded data in parallel from a receive shift register of a receiver; selecting a decoding method based on a second control signal received from a second control register of a decoding circuit of the receiver; and decoding the encoded data based on the selected decoding method and the plurality of reference data values.

[0007] The first plurality of reference data values ​​used for encoding may include a first encoded data value stored in a first reference register of the encoding circuit and a second encoded data value stored in a second reference register of the encoding circuit. The second plurality of reference data values ​​used for decoding may include a first decoded data value stored in a first reference register of the decoding circuit, a second decoded data value stored in a second reference register of the decoding circuit, and a third decoded data value stored in a third reference register of the decoding circuit. The method may include generating a baud rate. Attached Figure Description

[0008] Figure 1 A block diagram illustrating a system for encoding and decoding data according to a communication protocol, based on one or more examples, is shown.

[0009] Figure 2 A block diagram of a transmitter of a system coded according to a communication protocol, exemplifying one or more examples, is shown.

[0010] Figure 3 A block diagram of a receiver is shown, illustrating a system that decodes according to a communication protocol based on one or more examples.

[0011] Figure 4 A flowchart illustrating a method for encoding and decoding according to a communication protocol, based on one or more examples, is shown. Detailed Implementation

[0012] Reference will now be made to the various examples illustrated in the accompanying drawings, in which the same reference numerals always denote the same elements. These examples may be presented in various forms, and are not limited to those described herein.

[0013] Figure 1 A block diagram illustrating a system 100 for encoding and decoding according to a communication protocol, exemplified according to various examples, is shown. System 100 can utilize a combination of hardware components and control logic within a communication protocol (such as, but not limited to, serial communication protocols) to encode and decode data transmitted bit by bit. According to various examples, encoding and decoding can be built into UART / USRT or SPI, thereby reducing CPU overhead. For example, instead of the CPU writing one byte for each bit to be transmitted, an 8-bit byte can be written. According to various examples, as the byte is written, the system can encode each bit in the byte and transmit each bit according to the selected encoding method. According to various examples, software overhead can be reduced to one-eighth of the original, allowing one or more single-wire protocols to be handled like SPI or UART / USRT.

[0014] refer to Figure 1System 100 can configure multiple settings for the serial communication protocol on its serial communication interface. These settings may include setting the baud rate value, setting the number of communication pins, setting it to bidirectional (full-duplex) or unidirectional (half-duplex) communication, specifying transmit or receive buffers, or selecting synchronous or asynchronous communication mode.

[0015] System 100 may include three functional blocks: a clock generator 102, a transmitter 118, and a receiver 134. Transmitter 118 and receiver 134 may be arranged to handle the serial transmission of data sent from system 100 and the reception of data sent to system 100, respectively. Clock generator 102 may generate a regular stream of electrical pulses at a specific frequency to manage the timing of data transmission and reception. Clock generator 102 may include a baud rate register 104 and a baud rate generator 106.

[0016] Baud rate register 104 stores baud rate values. Baud rate generator 106 can use the baud rate values ​​to calculate the baud rate. According to one or more examples, baud rate register 104 can be set when one of multiple settings is selected. According to one or more examples, system 100 can receive baud rate values ​​from an external source and store the baud rate values ​​in baud rate register 104. Baud rate generator 106 can receive the internal clock of clock generator 102 and can calculate the baud rate based on the frequency of the received internal clock and the baud rate value in baud rate register 104. According to one or more examples, baud rate generator 106 can receive a clock external to clock generator 102 and can calculate the baud rate based on the frequency of the received external clock XCK and the baud rate value in baud rate register 104. Baud rate generator 106 can provide the baud rate to transmitter 118 and receiver 134. Baud rate generator 106 can also provide the baud rate to first pad 110, which can receive an external clock (XCK) signal that can be used to generate a baud rate according to one or more examples.

[0017] Transmitter 118 may include: a transmit data buffer 120 for storing data 122 (TX data 122); encoding circuitry 124 operatively coupled to the transmit data buffer 120; and a transmit shift register 126 operatively coupled to the encoding circuitry 124 for shifting the encoded data bit-by-bit. Each bit-by-bit operation corresponds to one bit. The encoded data may be sent to transmit pad 128 (TXD 128), which is operatively coupled to the transmit shift register 126.

[0018] Transmit pad 128 (TXD) can be used as the output path for encoded data. Transmit pad 128 (TXD) can transmit encoded data bit by bit, synchronized with the baud rate provided by baud rate generator 106.

[0019] Receiver 134 can receive received data frames from receive pad 130 (RXD) via third selection circuit 132 in a serial communication protocol. Receiver 134 can receive encoded data via third selection circuit 132. Receiver 134 may include: a receive shift register 136 operatively coupled to third selection circuit 132 to receive encoded data; a decoding circuit 138 operatively coupled to receive shift register 136; and a receive data buffer 140 operatively coupled to decoding circuit 138 to receive and store decoded data 142 (RX data 142).

[0020] The third selection circuit 132 can be used as a multiplexer. The third selection circuit 132 can receive encoded data from the transmit shift register 126 of the transmitter 118 and receive received data frames from the receive pad 130 (RXD). The receive pad 130 (RXD) can be used as the input path for the received data frames. The third selection circuit 132 can transmit the encoded data bit by bit, synchronized with the baud rate provided by the baud rate generator 106. The receive pad 130 (RXD) can be operatively coupled to the third selection circuit 132. The third selection circuit 132 can allow the same transmit pad (TxD) 128 to be used for both transmitting and receiving data, or the use of separate transmit pad (TxD) 128 and receive pad (RXD) 130. According to various examples, the third selection circuit can be used to detect data collisions, since data sent to the transmit pad 128 is also received by the receiver 134 via the third selection circuit 132. A CPU (not shown) can compare the transmitted data with the received data to confirm that they are identical.

[0021] Figure 2 A block diagram of a transmitter 118 of a system 100 exemplifying encoding according to a communication protocol according to one or more examples is shown. A transmit data buffer 120 of the transmitter 118 provides data 122 (TX data 122) for transmission. Data 122 can be sent to a multiplexer 202 of the transmitter 118. Data 122 can be fed into an encoding circuit 124 of the transmitter 118. The encoding circuit 124 may include an encoder 204, a first reference register 206, a second reference register 208, and a first control register 210. The encoding circuit 124 can receive data 122 bit-by-bit from the transmit data buffer 120. The encoding circuit 124 can select an encoding method based on a first control signal received from the first control register 210. The encoding circuit 124 can encode the data 122 based on the selected encoding method and at least one of a first plurality of reference data values. The transmit shift register 126 can receive encoded data one byte at a time for multiple bytes (e.g., 8 bytes of an 8-bit frame) and transmit the encoded data bit by bit.

[0022] The first plurality of reference data values ​​used for encoding may include a first encoded data value and a second encoded data value. In one or more examples, the first encoded data value is 0. The first encoded data value may be stored in the first reference register 206 of the encoding circuit 124. In one or more examples, the second encoded data value is 1. The second encoded data value may be stored in the second reference register 208 of the encoding circuit 124. The encoding method may be determined by a plurality of control bits within the first control register 210. The first control register 210 may include information regarding the use of the first reference register 206 and the second reference register 208. The encoder 204 may encode the data 122 and send the encoded data to the multiplexer 202. For example, if the encoder 204 receives an 8-bit string of alternating 0s and 1s in the data 122 (i.e., 01010101), the encoder will alternately send frames from the first reference register 206 (which stores the first encoded data value 0) and the second reference register 208 (which stores the second encoded data value 1). However, other encoding modes may be used. If the first control signal from the first control register 210 enables the encoding circuit 124, the multiplexer 202 can send the encoded data to the transmit shift register 126. If the first control signal disables the encoder, the multiplexer 202 will output the unencoded data 122 received from the transmit data buffer 120 to the transmit shift register 126.

[0023] Figure 3A block diagram of a receiver 134 of a system 100 for decoding data according to a communication protocol, exemplified according to one or more examples, is shown. A receive shift register 136 of the receiver 134 provides encoded data. The encoded data can be sent to a receive data buffer 140. The encoded data can be fed into a decoding circuit 138 of the receiver 134. The decoding circuit 138 may include a decoder 302, a first reference register 304, a second reference register 306, a third reference register 308, and a second control register 310. The decoding circuit 138 can receive the encoded data from the receive shift register 136 in parallel. For example, the receive shift register 136 can shift bit-by-bit data into complete bytes before transmitting bytes to the decoding circuit 138 in parallel. The decoding circuit 138 can select a decoding method based on a second control signal received from the second control register 310. The decoding circuit 138 can decode the encoded data based on the selected decoding method and a second plurality of reference data values. Decoder 302 can output decoded data to multiplexer 312 of receiver 134. Multiplexer can also receive encoded data from receive shift register 136 and receive a second control signal from second control register 310. Multiplexer 312 can selectively output encoded or decoded data to receive data buffer for storage as received data 142 based on the second control signal.

[0024] The second plurality of reference data values ​​used for decoding may include a first decoded data value, a second decoded data value, and a third decoded data value. In one or more examples, the first decoded data value is 0. The first decoded data value may be stored in the first reference register 304 of the decoding circuit 138. In one or more examples, the second decoded data value is 1. The second decoded data value may be stored in the second reference register 306 of the decoding circuit 138. In one or more examples, the third decoded data value may be a mask value. The third decoded data value may be stored in the third reference register 308 of the decoding circuit 138. The mask value may be used during the mask decoding method. The mask decoding method may be used for, but is not limited to, error correction, data filtering, and protocol adaptation. The decoding method may be determined by a plurality of control bits within the second control register 310. The second control register 310 may include information regarding the use of the first reference register 304, the second reference register 306, and the third reference register 308. The decoder 302 may decode the encoded data and send the decoded data 142 (RX data 142) to the receive data buffer 140. For example, the decoding circuit 138 can receive multiple bytes, decode the multiple bytes, and transmit the corresponding bits to the receive data buffer 140. As used herein according to various examples, a “byte” of data refers to the data payload (i.e., excluding the start bit, stop bit, and parity bit), which may include 8 bits, but may use more or fewer bits.

[0025] Various decoding modes can be used according to one or more examples. For example, each received frame may correspond to one of a first reference register 304 and a second reference register 306 of a decoding circuit 138, which determines whether the frame is 1 or 0. According to various examples, a masking mode can be used, in which the frame is decoded as 1 if the following condition is met: (DATA & REFDATA2) = (REFDATA 1 & REFDATA2), where DATA is the encoded data, REFDATA1 is the first decoded data value stored in the first reference register 304, and REFDATA2 is the second decoded data value stored in the second reference register 306. In an exemplary masking mode, if the frame is not decoded as 1, it is decoded as 0. The encoding and decoding modes provided herein are examples and not limiting.

[0026] Figure 4 A flowchart 400 illustrating a method for encoding and decoding data according to a communication protocol, based on one or more examples, is shown. It should be noted that, in order to explain the method operation of flowchart 200, reference will be made to... Figure 1 , Figure 2 and Figure 3 The components explained in the text.

[0027] Flowchart 400 begins at operation 402. At operation 404, the method may include receiving data 122 bit-by-bit from transmit data buffer 120 of transmitter 118. At operation 406, the method may include selecting an encoding method based on a first control signal received from a first control register 210 of encoding circuitry 124 of transmitter 118. At operation 408, the method may include encoding data 122 based on the selected encoding method and a first plurality of reference data values. At operation 410, the method may include receiving encoded data in parallel from receive shift register 136 of receiver 134. At operation 412, the method may include selecting a decoding method based on a second control signal received from a second control register 310 of decoding circuitry 138 of receiver 134. At operation 414, the method may include decoding the encoded data based on the selected decoding method and a second plurality of reference data values.

[0028] Flowchart 400 terminates at operation 416. It should be noted that flowchart 400 is to be interpreted as having the above-described process operations; however, those skilled in the art will understand that flowchart 400 may have more or fewer process operations that implement all the above-described embodiments of this disclosure.

[0029] Various examples have been disclosed herein in conjunction with the foregoing description and accompanying drawings. It should be understood that describing and illustrating each combination and sub-combination of these examples literally would be an undue repetition. Therefore, all examples can be combined in any manner and / or combination, and this specification (including the accompanying drawings) should be construed as constituting a complete written description of all combinations and sub-combinations of these examples herein, as well as the ways and processes of preparing and using them, and should support the claims for any such combinations or sub-combinations.

[0030] Those skilled in the art will understand that the examples described herein are not limited to those specifically shown and described above. Furthermore, unless the contrary is mentioned above, it should be noted that all figures are not drawn to scale. Various modifications and variations are possible in accordance with the above teachings.

Claims

1. A system for encoding and decoding according to a communication protocol, the system comprising: A transmitter, the transmitter comprising: A data transmission buffer, which is used to store data; An encoding circuit, operatively coupled to the transmit data buffer, wherein the encoding circuit is used for: Receive the data from the transmit data buffer; and The data is encoded based on the selected encoding method; and A transmit shift register, operatively coupled to the encoding circuitry, wherein the transmit shift register is used to receive the encoded data and transmit the encoded data bit by bit; and Receiver, the receiver comprising: A receive shift register, the receive shift register being used to receive the encoded data; Decoding circuitry, operatively coupled to the receive shift register, wherein the decoding circuitry is configured to: The encoded data is received from the receive shift register in parallel; and The encoded data is decoded based on the selected decoding method; and A receive data buffer is operatively coupled to the decoding circuit, wherein the receive data buffer is used to receive the decoded data.

2. The system of claim 1, wherein the encoding circuit includes a first control register for providing a first control signal; and The selected encoding method is chosen based on the first control signal from the first control register.

3. The system of claim 2, wherein the transmitter includes a multiplexer for selectively outputting the data or the encoded data to the transmit shift register based on the first control signal.

4. The system according to claim 2, wherein the encoding circuit comprises: A first reference register, the first reference register being used to store first encoded data; and The second reference register is used to store the second encoded data; The encoding circuit is used to encode the data based on at least one of the first encoded data and the second encoded data.

5. The system of claim 4, wherein the decoding circuit includes a second control register for providing a second control signal; and The selected decoding method is chosen based on the second control signal from the second control register.

6. The system of claim 5, wherein the receiver includes a multiplexer for selectively outputting the encoded data or the decoded data to the receive data buffer based on the first control signal.

7. The system according to claim 5, wherein the decoding circuit comprises: A first reference register, which is used to store first decoded data; The second reference register is used to store the second decoded data; and A third reference register, which is used to store third decoded data; The decoding circuit is used to decode the encoded data based on at least one of the first decoded data, the second decoded data, and the third decoded data.

8. The system of claim 1, the system comprising a baud rate generator for generating a baud rate for the system, wherein the transmit shift register is used to transmit the encoded data bit-by-bit based on the baud rate.

9. The system of claim 8, wherein the receive shift register is used to send encoded data to the decoding circuit bit by bit based on the baud rate.

10. The system of claim 8, wherein the baud rate generator generates the baud rate based on an external clock signal.

11. A method for transmitting and receiving encoded and decoded data according to a communication protocol, the method comprising: Receive data from the transmitter's transmit data buffer; The data is encoded based on the selected encoding method; The encoded data is transmitted bit by bit; The encoded data is received from the receiver's receive shift register in parallel. as well as The encoded data is decoded based on the selected decoding method.

12. The method of claim 11, the method comprising selecting a selected encoding method based on a first control signal received from a first control register of the encoding circuit of the transmitter.

13. The method of claim 12, wherein the method includes selectively transmitting the data or the encoded data based on the first control signal.

14. The method of claim 12, wherein the encoding includes encoding the data based on a first plurality of reference data values ​​stored in one or more reference registers of the encoding circuit.

15. The method of claim 14, the method comprising selecting a selected decoding method based on a second control signal received from a second control register of the decoding circuitry of the receiver.

16. The method of claim 15, the method comprising selectively storing the encoded data or the decoded data based on the second control signal.

17. The method of claim 15, wherein the decoding includes decoding the encoded data based on a second plurality of reference data values ​​stored in one or more reference registers of the decoding circuit.

18. The method according to claim 11, wherein the method comprises: Generate baud rate; The encoded data is transmitted bit by bit based on the baud rate.

19. The method of claim 18, wherein the encoded data is received bit-by-bit based on the baud rate.

20. The method of claim 18, wherein the baud rate is generated based on an external clock signal.

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