Shift register unit, display device, and detection method

Abstract

The application discloses a shift register unit, a display device and a detection method, which comprises a plurality of shift register units and at least one detection unit; the detection unit is electrically connected with the shift register unit and is configured to provide a signal of an initialization signal end to a first node in the shift register unit and detect a voltage value of a signal on the first node; and a threshold voltage of a transistor in the shift register unit is obtained according to a voltage value of a signal of a control signal end in the shift register unit and the voltage value of the signal on the first node. Through the cooperation of the shift register unit and the detection unit, the threshold voltage of the transistor in the shift register unit can be detected, and the threshold voltage of the transistor in the shift register unit can be better adjusted, thereby improving the display quality.

Description

Shift register unit, display device and detection method Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to shift register units, display devices, and detection methods. Background Technology

[0002] With the rapid development of display technology, display panels are showing a trend towards high integration and low cost. Among them, Gate Driver on Array (GOA) technology integrates the drive control circuitry onto the array substrate of the display panel to form a scanning drive for the display panel. Currently, the drive control circuitry typically consists of multiple cascaded shift register units. Summary of the Invention

[0003] The shift register unit provided in this embodiment includes:

[0004] A first control circuit, electrically connected to a first node, is configured to provide a reference signal to the first node in response to a signal at a control signal terminal.

[0005] The output circuit, electrically connected to the first node, is configured to provide a clock signal to the output signal and the cascaded signal in response to a signal on the first node.

[0006] A reset circuit, electrically connected to the output circuit, is configured to provide a signal from the first reference voltage signal terminal to the output signal terminal in response to a signal from the reset signal terminal.

[0007] The second control circuit, electrically connected to the second node, is configured to control the signal on the second node in response to the input signal terminal, the first power supply terminal, and the signal on the first node.

[0008] The third control circuit, electrically connected to the third node, is configured to control the signal on the third node in response to the input signal terminal, the second power supply terminal, and the signal on the first node.

[0009] A fourth control circuit, electrically connected to the first node, the second node, and the third node, is configured to provide a signal from the second reference voltage signal terminal to the first node in response to signals on the second node and the third node.

[0010] The fifth control circuit, electrically connected to the second node and the third node, is configured to, in response to signals on the second node and the third node, provide a signal from the first reference voltage signal terminal to the output signal terminal and a signal from the second reference voltage signal terminal to the cascaded signal terminal.

[0011] In some possible implementations, the first control circuit includes: an input transistor; the control signal terminal includes an input control signal terminal; and the reference signal terminal includes a first reference signal terminal.

[0012] The gate of the input transistor is electrically connected to the input control signal terminal, the first terminal of the input transistor is electrically connected to the first reference signal terminal, and the second terminal of the input transistor is electrically connected to the first node.

[0013] In some possible implementations, the first control circuit further includes: a first reset transistor; the control signal terminal further includes a first reset control signal terminal; and the reference signal terminal further includes a second reference signal terminal.

[0014] The gate of the first reset transistor is electrically connected to the first reset control signal terminal, the first terminal of the first reset transistor is electrically connected to the second reference signal terminal, and the second terminal of the first reset transistor is electrically connected to the first node.

[0015] In some possible implementations, the first control circuit further includes: a second reset transistor; the control signal terminal further includes a second reset control signal terminal; and the reference signal terminal further includes a third reference signal terminal.

[0016] The gate of the second reset transistor is electrically connected to the second reset control signal terminal, the first terminal of the second reset transistor is electrically connected to the third reference signal terminal, and the second terminal of the second reset transistor is electrically connected to the first node.

[0017] In some possible implementations, the fourth control circuit includes: a first control transistor and a second control transistor;

[0018] The gate of the first control transistor is electrically connected to the second node, the first terminal of the first control transistor is electrically connected to the first node, and the second terminal of the first control transistor is electrically connected to the second reference voltage signal terminal.

[0019] The gate of the second control transistor is electrically connected to the third node, the first terminal of the second control transistor is electrically connected to the first node, and the second terminal of the second control transistor is electrically connected to the second reference voltage signal terminal.

[0020] In some possible implementations, the gates of the first control transistor, the second control transistor, the input transistor, the first reset transistor, and the second reset transistor each have a first gate and a second gate.

[0021] The first control transistor, the second control transistor, the input transistor, the first reset transistor, and the second reset transistor are all electrically connected to the same fixed voltage signal terminal.

[0022] Alternatively, the second gates of the first control transistor, the second control transistor, the input transistor, the first reset transistor, and the second reset transistor are electrically connected to different fixed voltage signal terminals.

[0023] In some possible implementations, the output circuit includes: a first output transistor, a second output transistor, and a first capacitor;

[0024] The gate of the first output transistor is electrically connected to the first node, the first terminal of the first output transistor is electrically connected to the clock signal terminal, and the second terminal of the first output transistor is electrically connected to the output signal terminal.

[0025] The gate of the second output transistor is electrically connected to the first node, the first terminal of the second output transistor is electrically connected to the clock signal terminal, and the second terminal of the second output transistor is electrically connected to the cascaded signal terminal.

[0026] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the output signal terminal.

[0027] In some possible implementations, the reset circuit includes a third reset transistor;

[0028] The gate of the third reset transistor is electrically connected to the reset signal terminal, the first terminal of the third reset transistor is electrically connected to the first reference voltage signal terminal, and the second terminal of the third reset transistor is electrically connected to the output signal terminal.

[0029] In some possible implementations, the second control circuit includes: a third control transistor, a fourth control transistor, and a fifth control transistor;

[0030] The gate of the third control transistor is electrically connected to the first power supply terminal, the first electrode of the third control transistor is electrically connected to the first power supply terminal, and the second electrode of the third control transistor is electrically connected to the second node.

[0031] The gate of the fourth control transistor is electrically connected to the first node, the first terminal of the fourth control transistor is electrically connected to the second node, and the second terminal of the fourth control transistor is electrically connected to the third reference voltage signal terminal.

[0032] The gate of the fifth control transistor is electrically connected to the input signal terminal, the first terminal of the fifth control transistor is electrically connected to the second node, and the second terminal of the fifth control transistor is electrically connected to the third reference voltage signal terminal.

[0033] In some possible implementations, the third control circuit includes: a sixth control transistor, a seventh control transistor, and an eighth control transistor;

[0034] The gate of the sixth control transistor is electrically connected to the second power supply terminal, the first terminal of the sixth control transistor is electrically connected to the second power supply terminal, and the second terminal of the sixth control transistor is electrically connected to the third node.

[0035] The gate of the seventh control transistor is electrically connected to the first node, the first terminal of the seventh control transistor is electrically connected to the third node, and the second terminal of the seventh control transistor is electrically connected to the third reference voltage signal terminal.

[0036] The gate of the eighth control transistor is electrically connected to the input signal terminal, the first terminal of the eighth control transistor is electrically connected to the third node, and the second terminal of the eighth control transistor is electrically connected to the third reference voltage signal terminal.

[0037] In some possible implementations, the fifth control circuit includes: a ninth control transistor, a tenth control transistor, an eleventh control transistor, and a twelfth control transistor;

[0038] The gate of the ninth control transistor is electrically connected to the second node, the first terminal of the ninth control transistor is electrically connected to the cascaded signal terminal, and the second terminal of the ninth control transistor is electrically connected to the second reference voltage signal terminal.

[0039] The gate of the tenth control transistor is electrically connected to the third node, the first terminal of the tenth control transistor is electrically connected to the cascaded signal terminal, and the second terminal of the tenth control transistor is electrically connected to the second reference voltage signal terminal.

[0040] The gate of the eleventh control transistor is electrically connected to the second node, the first terminal of the eleventh control transistor is electrically connected to the output signal terminal, and the second terminal of the eleventh control transistor is electrically connected to the first reference voltage signal terminal.

[0041] The gate of the twelfth control transistor is electrically connected to the third node, the first terminal of the twelfth control transistor is electrically connected to the output signal terminal, and the second terminal of the twelfth control transistor is electrically connected to the first reference voltage signal terminal.

[0042] In some possible implementations, the transistors in the shift register unit include metal-oxide transistors.

[0043] The display device provided in this disclosure includes: the shift register unit described above and at least one detection unit;

[0044] The detection unit is electrically connected to the shift register unit and is configured to provide the initialization signal terminal to the first node in the shift register unit, and to detect the voltage value of the signal on the first node. Based on the voltage value of the control signal terminal in the shift register unit and the voltage value of the signal on the first node, the threshold voltage of the transistor in the shift register unit is obtained.

[0045] In some possible implementations, the detection unit includes: a first switch, a second switch, and an analog-to-digital converter;

[0046] The first end of the first switch is electrically connected to the first node, and the second end of the first switch is electrically connected to the initialization signal terminal;

[0047] The first end of the second switch is electrically connected to the first node, and the second end of the second switch is electrically connected to the analog-to-digital converter.

[0048] In some possible implementations, the detection unit includes: a first detection unit electrically connected to a first terminal of the input transistor, configured to connect the first terminal of the input transistor to a first reference signal terminal, or to connect the first terminal of the input transistor to the initialization signal terminal.

[0049] In some possible implementations, the first detection unit includes: a third switch, a fourth switch, a fifth switch, and a first analog-to-digital converter;

[0050] The first terminal of the third switch is electrically connected to the first electrode of the input transistor, and the second terminal of the third switch is electrically connected to the first reference signal terminal.

[0051] The first terminal of the fourth switch is electrically connected to the first electrode of the input transistor, and the second terminal of the fourth switch is electrically connected to the initialization signal terminal.

[0052] The first terminal of the fifth switch is electrically connected to the first electrode of the input transistor, and the second terminal of the fifth switch is electrically connected to the first analog-to-digital converter.

[0053] In some possible implementations, the detection unit further includes: a second detection unit electrically connected to the first terminal of the first reset transistor, configured to connect the first terminal of the first reset transistor to the second reference signal terminal, or connect the first terminal of the first reset transistor to the initialization signal terminal, or connect the first terminal of the first reset transistor to the first reference signal terminal.

[0054] In some possible implementations, the second detection unit includes: a sixth switch, a seventh switch, an eighth switch, a ninth switch, and a second analog-to-digital converter;

[0055] The first terminal of the sixth switch is electrically connected to the first electrode of the first reset transistor, and the second terminal of the sixth switch is electrically connected to the second reference signal terminal.

[0056] The first terminal of the seventh switch is electrically connected to the first electrode of the first reset transistor, and the second terminal of the seventh switch is electrically connected to the initialization signal terminal.

[0057] The first terminal of the eighth switch is electrically connected to the first electrode of the first reset transistor, and the second terminal of the eighth switch is electrically connected to the second analog-to-digital converter.

[0058] The first terminal of the ninth switch is electrically connected to the first electrode of the first reset transistor, and the second terminal of the ninth switch is electrically connected to the first reference signal terminal.

[0059] In some possible implementations, the detection unit further includes: a third detection unit electrically connected to the first terminal of the second reset transistor, configured to connect the first terminal of the second reset transistor to the third reference signal terminal, or connect the first terminal of the second reset transistor to the initialization signal terminal, or connect the first terminal of the second reset transistor to the first reference signal terminal.

[0060] In some possible implementations, the third detection unit includes: a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a third analog-to-digital converter;

[0061] The first terminal of the tenth switch is electrically connected to the first electrode of the second reset transistor, and the second terminal of the tenth switch is electrically connected to the third reference signal terminal.

[0062] The first terminal of the eleventh switch is electrically connected to the first electrode of the second reset transistor, and the second terminal of the eleventh switch is electrically connected to the initialization signal terminal.

[0063] The first terminal of the twelfth switch is electrically connected to the first electrode of the second reset transistor, and the second terminal of the twelfth switch is electrically connected to the third analog-to-digital converter;

[0064] The first terminal of the thirteenth switch is electrically connected to the first electrode of the second reset transistor, and the second terminal of the thirteenth switch is electrically connected to the first reference signal terminal.

[0065] The detection method for the above-mentioned display device provided in this disclosure includes:

[0066] In the first stage, the detection unit provides the initialization signal to the first node in the shift register unit;

[0067] In the second stage, the first control circuit in the shift register responds to the signal at the control signal terminal and provides the signal at the reference signal terminal to the first node.

[0068] In the third stage, the detection unit detects the voltage value of the signal on the first node, and obtains the threshold voltage of the transistor in the shift register unit based on the voltage value of the signal at the control signal terminal in the shift register unit and the voltage value of the signal on the first node. Attached Figure Description

[0069] Figure 1 is a schematic diagram of some structures of the display device provided in the embodiments of this disclosure;

[0070] Figure 2 is a schematic diagram of some structures of the shift register unit provided in the embodiments of this disclosure;

[0071] Figure 3 shows some other structural schematic diagrams of the shift register unit provided in the embodiments of this disclosure;

[0072] Figure 4 is a schematic diagram of some other structures of the display device provided in the embodiments of this disclosure;

[0073] Figure 5 is a schematic diagram of some of the structures of the display device provided in the embodiments of this disclosure;

[0074] Figure 6 is a schematic diagram of some more structures of the display device provided in the embodiments of this disclosure;

[0075] Figure 7 is a flowchart of the detection method provided in an embodiment of this disclosure;

[0076] Figure 8 is a simulation curve diagram provided in the embodiments of this disclosure;

[0077] Figure 9 is a schematic diagram of some of the structures of the display device provided in the embodiments of this disclosure;

[0078] Figure 10 is a schematic diagram of some of the structures of the display device provided in the embodiments of this disclosure;

[0079] Figure 11 is a schematic diagram of some of the structures of the display device provided in the embodiments of this disclosure;

[0080] Figure 12 is a schematic diagram of some of the structures of the display device provided in the embodiments of this disclosure;

[0081] Figure 13 is a schematic diagram of some more structures of the display device provided in the embodiments of this disclosure;

[0082] Figure 14 is a schematic diagram of some more structures of the display device provided in the embodiments of this disclosure;

[0083] Figure 15 is a schematic diagram of some of the structures of the display device provided in the embodiments of this disclosure;

[0084] Figure 16 is a schematic diagram of some of the structures of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0085] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0086] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0087] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0088] In this embodiment of the disclosure, as shown in FIG1, the display device may include a display panel 100 and a timing controller 200. The display panel 100 may include a plurality of pixel units arranged in an array; exemplarily, each pixel unit includes multiple sub-pixels of different colors. Each sub-pixel may include a transistor and a pixel electrode. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, allowing for color mixing of red, green, and blue to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, allowing for color mixing of red, green, blue, and white to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0089] In some embodiments of this disclosure, as shown in FIG1, the display panel 100 further includes: multiple gate lines GA, multiple data lines DA, a gate driving circuit 101, and a source driving circuit 102; wherein, the gate driving circuit 101 is coupled to the gate lines GA, and the source driving circuit 102 is coupled to the data lines DA. The timing controller 200 can input control signals to the gate driving circuit 101, thereby causing the gate driving circuit 101 to input signals to the gate lines GA to drive the scanning gate lines GA. Furthermore, the timing controller 200 can acquire the original display data of the image to be displayed in the current display frame and send the required display data to the source driving circuit 102, enabling the source driving circuit 102 to apply data voltage to the data lines DA in the display panel according to the display data, thereby charging the sub-pixels and enabling the image display function.

[0090] For example, multiple source driver circuits 102 can be configured, with different source driver circuits coupled to different data lines. For instance, as shown in Figure 1, two source driver circuits 110 can be configured, with one source driver circuit 102 coupled to half of the data lines and the other source driver circuit 102 coupled to the other half of the data lines. Of course, three, four, or more source driver circuits 110 can also be configured, which can be designed and determined according to the actual application requirements, and are not limited here.

[0091] It should be noted that the gate driving circuit can be configured as shown in Figure 1, located on both sides of the display panel. The gate driving circuits on both sides of the display panel can drive the same gate line, or a gate driving circuit can be located on only one side of the display panel, or the gate driving circuits on both sides of the display panel can drive gate lines corresponding to different rows of sub-pixels respectively. In this embodiment, the number of gate driving circuits in the display panel is not further limited and can be determined according to the needs of the actual application.

[0092] In existing technologies, gate drive circuits typically consist of multiple cascaded shift register units. Each shift register unit is electrically connected to at least one gate line. Each shift register unit can apply a valid level signal to its corresponding gate line, thereby controlling multiple gate lines in the display panel to sequentially open for line-by-line scanning. However, each shift register unit generally consists of multiple transistors. Due to manufacturing processes and device aging, the threshold voltage of the transistors in the shift register unit can become uneven, meaning the threshold voltage can drift. This can easily lead to leakage current in the shift register unit, affecting the output signal and consequently the display quality.

[0093] The shift register unit SR provided in this embodiment of the present disclosure, as shown in Figure 2, includes:

[0094] The first control circuit 10 is electrically connected to the first node N1 and is configured to provide the reference signal terminal VREF to the first node N1 in response to the signal of the control signal terminal CS.

[0095] Output circuit 20, electrically connected to the first node N1, is configured to provide the clock signal terminal CLK to the output signal terminal OUT and the cascaded signal terminal OUTC in response to the signal on the first node N1.

[0096] The reset circuit 30, which is electrically connected to the output circuit 20, is configured to provide the signal of the first reference voltage signal terminal V1 to the output signal terminal OUT in response to the signal of the reset signal terminal RST.

[0097] The second control circuit 40 is electrically connected to the second node N2 and is configured to control the signal on the second node N2 in response to the input signal terminal IN, the first power supply terminal VDD1 and the signal on the first node N1.

[0098] The third control circuit 50 is electrically connected to the third node N3 and is configured to control the signal on the third node N3 in response to the input signal terminal IN, the second power supply terminal VDD2 and the signal on the first node N1.

[0099] The fourth control circuit 60 is electrically connected to the first node N1, the second node N2 and the third node N3, and is configured to provide the signal of the second reference voltage signal terminal V2 to the first node N1 in response to the signals on the second node N2 and the third node N3.

[0100] The fifth control circuit 70, electrically connected to the second node N2 and the third node N3, is configured to provide the signal of the first reference voltage signal terminal V1 to the output signal terminal OUT and the signal of the second reference voltage signal terminal V2 to the cascaded signal terminal OT in response to the signals on the second node N2 and the third node N3.

[0101] In some embodiments of this disclosure, as shown in FIG2, the first control circuit 10 includes: an input transistor M1; a control signal terminal CS including an input control signal terminal INC; and a reference signal terminal VREF including a first reference signal terminal VREF1.

[0102] The gate of the input transistor M1 is electrically connected to the input control signal terminal INC, the first terminal of the input transistor M1 is electrically connected to the first reference signal terminal VREF1, and the second terminal of the input transistor M1 is electrically connected to the first node N1.

[0103] For example, the input transistor M1 can be turned on under the control of the valid level of the input control signal transmitted at the input control signal terminal INC, and can be turned off under the control of the invalid level of the input control signal. For example, if the input transistor M1 is set to an N-type transistor, the valid level of the input control signal is a high level, and the invalid level of the input control signal is a low level. Alternatively, if the input transistor M1 is set to a P-type transistor, the valid level of the input control signal is a low level, and the invalid level of the input control signal is a high level.

[0104] In some embodiments of this disclosure, as shown in FIG2, the first control circuit 10 further includes: a first reset transistor M2; the control signal terminal CS further includes a first reset control signal terminal RSTC1; and the reference signal terminal VREF further includes a second reference signal terminal VREF2.

[0105] The gate of the first reset transistor M2 is electrically connected to the first reset control signal terminal RSTC1, the first terminal of the first reset transistor M2 is electrically connected to the second reference signal terminal VREF2, and the second terminal of the first reset transistor M2 is electrically connected to the first node N1.

[0106] For example, the first reset transistor M2 can be turned on under the control of the effective level of the first reset control signal transmitted at the first reset control signal terminal RSTC1, and can be turned off under the control of the ineffective level of the first reset control signal. For example, if the first reset transistor M2 is set as an N-type transistor, then the effective level of the first reset control signal is high, and the ineffective level of the first reset control signal is low. Alternatively, if the first reset transistor M2 is set as a P-type transistor, then the effective level of the first reset control signal is low, and the ineffective level of the first reset control signal is high.

[0107] In some embodiments of this disclosure, as shown in FIG2, the first control circuit 10 further includes: a second reset transistor M3; the control signal terminal CS further includes a second reset control signal terminal RSTC2; and the reference signal terminal VREF further includes a third reference signal terminal VREF3.

[0108] The gate of the second reset transistor M3 is electrically connected to the second reset control signal terminal RSTC2, the first terminal of the second reset transistor M3 is electrically connected to the third reference signal terminal VREF3, and the second terminal of the second reset transistor M3 is electrically connected to the first node N1.

[0109] For example, the second reset transistor M3 can be turned on under the control of the effective level of the second reset control signal transmitted at the second reset control signal terminal RSTC2, and can be turned off under the control of the ineffective level of the second reset control signal. For example, if the second reset transistor M3 is set as an N-type transistor, then the effective level of the second reset control signal is high, and the ineffective level of the second reset control signal is low. Alternatively, if the second reset transistor M3 is set as a P-type transistor, then the effective level of the second reset control signal is low, and the ineffective level of the second reset control signal is high.

[0110] As shown in FIG2, in some embodiments of this disclosure, the fourth control circuit 60 includes: a first control transistor M4 and a second control transistor M5;

[0111] The gate of the first control transistor M4 is electrically connected to the second node N2, the first terminal of the first control transistor M4 is electrically connected to the first node N1, and the second terminal of the first control transistor M4 is electrically connected to the second reference voltage signal terminal V2.

[0112] The gate of the second control transistor M5 is electrically connected to the third node N3, the first terminal of the second control transistor M5 is electrically connected to the first node N1, and the second terminal of the second control transistor M5 is electrically connected to the second reference voltage signal terminal V2.

[0113] For example, the first control transistor M4 can be turned on under the control of the effective level of the signal transmitted on the second node N2, and can be turned off under the control of the ineffective level of the signal transmitted on the second node N2. For example, if the first control transistor M4 is set as an N-type transistor, then the effective level of the signal transmitted on the second node N2 is a high level, and the ineffective level of the signal transmitted on the second node N2 is a low level. Alternatively, if the first control transistor M4 is set as a P-type transistor, then the effective level of the signal transmitted on the second node N2 is a low level, and the ineffective level of the signal transmitted on the second node N2 is a high level.

[0114] For example, the second control transistor M5 can be turned on under the control of the effective level of the signal transmitted on the third node N3, and can be turned off under the control of the ineffective level of the signal transmitted on the third node N3. For example, if the second control transistor M5 is set to an N-type transistor, then the effective level of the signal transmitted on the third node N3 is a high level, and the ineffective level of the signal transmitted on the third node N3 is a low level. Alternatively, if the second control transistor M5 is set to a P-type transistor, then the effective level of the signal transmitted on the third node N3 is a low level, and the ineffective level of the signal transmitted on the third node N3 is a high level.

[0115] In some embodiments of this disclosure, as shown in FIG2, the output circuit 20 includes: a first output transistor M6, a second output transistor M7, and a first capacitor C1;

[0116] The gate of the first output transistor M6 is electrically connected to the first node N1, the first terminal of the first output transistor M6 is electrically connected to the clock signal terminal CLK, and the second terminal of the first output transistor M6 is electrically connected to the output signal terminal OUT.

[0117] The gate of the second output transistor M7 is electrically connected to the first node N1, the first terminal of the second output transistor M7 is electrically connected to the clock signal terminal CLK, and the second terminal of the second output transistor M7 is electrically connected to the cascaded signal terminal OUTC.

[0118] The first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate of the first capacitor C1 is electrically connected to the output signal terminal OUT.

[0119] For example, the first output transistor M6 and the second output transistor M7 can be turned on under the control of the effective level of the signal transmitted on the first node N1, and can be turned off under the control of the ineffective level of the signal transmitted on the first node N1. For example, if the first output transistor M6 and the second output transistor M7 are configured as N-type transistors, then the effective level of the signal transmitted on the first node N1 is a high level, and the ineffective level of the signal transmitted on the first node N1 is a low level. Alternatively, if the first output transistor M6 and the second output transistor M7 are configured as P-type transistors, then the effective level of the signal transmitted on the first node N1 is a low level, and the ineffective level of the signal transmitted on the first node N1 is a high level.

[0120] In some embodiments of this disclosure, as shown in FIG2, the reset circuit 30 includes: a third reset transistor M8;

[0121] The gate of the third reset transistor M8 is electrically connected to the reset signal terminal RST, the first terminal of the third reset transistor M8 is electrically connected to the first reference voltage signal terminal V1, and the second terminal of the third reset transistor M8 is electrically connected to the output signal terminal OUT.

[0122] For example, the third reset transistor M8 can be turned on under the control of the effective level of the reset signal transmitted at the reset signal terminal RST, and can be turned off under the control of the ineffective level of the reset signal. For example, if the third reset transistor M8 is set as an N-type transistor, then the effective level of the reset signal is high and the ineffective level of the reset signal is low. Alternatively, if the third reset transistor M8 is set as a P-type transistor, then the effective level of the reset signal is low and the ineffective level of the reset signal is high.

[0123] As shown in FIG2, in some embodiments of this disclosure, the second control circuit includes: a third control transistor M9, a fourth control transistor M10, and a fifth control transistor M11;

[0124] The gate of the third control transistor M9 is electrically connected to the first power supply terminal VDD1, the first terminal of the third control transistor M9 is electrically connected to the first power supply terminal VDD1, and the second terminal of the third control transistor M9 is electrically connected to the second node N2.

[0125] The gate of the fourth control transistor M10 is electrically connected to the first node N1, the first terminal of the fourth control transistor M10 is electrically connected to the second node N2, and the second terminal of the fourth control transistor M10 is electrically connected to the third reference voltage signal terminal V3.

[0126] The gate of the fifth control transistor M11 is electrically connected to the input signal terminal IN, the first terminal of the fifth control transistor M11 is electrically connected to the second node N2, and the second terminal of the fifth control transistor M11 is electrically connected to the third reference voltage signal terminal V3.

[0127] For example, the fourth control transistor M10 can be turned on under the control of the effective level of the signal transmitted on the first node N1, and can be turned off under the control of the ineffective level of the signal transmitted on the first node N1. For example, if the fourth control transistor M10 is set as an N-type transistor, then the effective level of the signal transmitted on the first node N1 is a high level, and the ineffective level of the signal transmitted on the first node N1 is a low level. Alternatively, if the fourth control transistor M10 is set as a P-type transistor, then the effective level of the signal transmitted on the first node N1 is a low level, and the ineffective level of the signal transmitted on the first node N1 is a high level.

[0128] For example, the fifth control transistor M11 can be turned on under the control of the valid level of the input signal at the input signal terminal IN, and can be turned off under the control of the invalid level of the input signal. For example, if the fifth control transistor M11 is set as an N-type transistor, then the valid level of the input signal is a high level, and the invalid level of the input signal is a low level. Alternatively, if the fifth control transistor M11 is set as a P-type transistor, then the valid level of the input signal is a low level, and the invalid level of the input signal is a high level.

[0129] In some embodiments of this disclosure, as shown in FIG2, the third control circuit 50 includes: a sixth control transistor M12, a seventh control transistor M13 and an eighth control transistor M14;

[0130] The gate of the sixth control transistor M12 is electrically connected to the second power supply terminal VDD2, the first terminal of the sixth control transistor M12 is electrically connected to the second power supply terminal VDD2, and the second terminal of the sixth control transistor M12 is electrically connected to the third node N3.

[0131] The gate of the seventh control transistor M13 is electrically connected to the first node N1, the first terminal of the seventh control transistor M13 is electrically connected to the third node N3, and the second terminal of the seventh control transistor M13 is electrically connected to the third reference voltage signal terminal V3.

[0132] The gate of the eighth control transistor M14 is electrically connected to the input signal terminal IN, the first terminal of the eighth control transistor M14 is electrically connected to the third node N3, and the second terminal of the eighth control transistor M14 is electrically connected to the third reference voltage signal terminal V3.

[0133] For example, the seventh control transistor M13 can be turned on under the control of the effective level of the signal transmitted on the first node N1, and can be turned off under the control of the ineffective level of the signal transmitted on the first node N1. For example, if the seventh control transistor M13 is set as an N-type transistor, then the effective level of the signal transmitted on the first node N1 is a high level, and the ineffective level of the signal transmitted on the first node N1 is a low level. Alternatively, if the seventh control transistor M13 is set as a P-type transistor, then the effective level of the signal transmitted on the first node N1 is a low level, and the ineffective level of the signal transmitted on the first node N1 is a high level.

[0134] For example, the eighth control transistor M14 can be turned on under the control of the valid level of the input signal at the input signal terminal IN, and can be turned off under the control of the invalid level of the input signal. For example, if the eighth control transistor M14 is set to an N-type transistor, the valid level of the input signal is high and the invalid level of the input signal is low. Alternatively, if the eighth control transistor M14 is set to a P-type transistor, the valid level of the input signal is low and the invalid level of the input signal is high.

[0135] In some embodiments of this disclosure, as shown in FIG2, the fifth control circuit 70 includes: a ninth control transistor M15, a tenth control transistor M16, an eleventh control transistor M17, and a twelfth control transistor M18.

[0136] The gate of the ninth control transistor M15 is electrically connected to the second node N2, the first terminal of the ninth control transistor M15 is electrically connected to the cascaded signal terminal OUTC, and the second terminal of the ninth control transistor M15 is electrically connected to the second reference voltage signal terminal V2.

[0137] The gate of the tenth control transistor M16 is electrically connected to the third node N3, the first terminal of the tenth control transistor M16 is electrically connected to the cascaded signal terminal OUTC, and the second terminal of the tenth control transistor M16 is electrically connected to the second reference voltage signal terminal V2.

[0138] The gate of the eleventh control transistor M17 is electrically connected to the second node N2, the first terminal of the eleventh control transistor M17 is electrically connected to the output signal terminal OUT, and the second terminal of the eleventh control transistor M17 is electrically connected to the first reference voltage signal terminal V1.

[0139] The gate of the twelfth control transistor M18 is electrically connected to the third node N3, the first terminal of the twelfth control transistor M18 is electrically connected to the output signal terminal OUT, and the second terminal of the twelfth control transistor M18 is electrically connected to the first reference voltage signal terminal V1.

[0140] For example, the ninth control transistor M15 and the eleventh control transistor M17 can be turned on under the control of the effective level of the signal transmitted on the second node N2, and can be turned off under the control of the ineffective level of the signal transmitted on the second node N2. For example, if the ninth control transistor M15 and the eleventh control transistor M17 are configured as N-type transistors, then the effective level of the signal transmitted on the second node N2 is a high level, and the ineffective level of the signal transmitted on the second node N2 is a low level. Alternatively, if the ninth control transistor M15 and the eleventh control transistor M17 are configured as P-type transistors, then the effective level of the signal transmitted on the second node N2 is a low level, and the ineffective level of the signal transmitted on the second node N2 is a high level.

[0141] For example, the tenth control transistor M16 and the twelfth control transistor M18 can be turned on under the control of the effective level of the signal transmitted on the third node N3, and can be turned off under the control of the ineffective level of the signal transmitted on the third node N3. For example, if the tenth control transistor M16 and the twelfth control transistor M18 are configured as N-type transistors, then the effective level of the signal transmitted on the third node N3 is a high level, and the ineffective level of the signal transmitted on the third node N3 is a low level. Alternatively, if the tenth control transistor M16 and the twelfth control transistor M18 are configured as P-type transistors, then the effective level of the signal transmitted on the third node N3 is a low level, and the ineffective level of the signal transmitted on the third node N3 is a high level.

[0142] For example, the input control signal terminal INC and the input signal terminal IN are loaded with the same signal, that is, the input control signal terminal INC and the input signal terminal IN can be the same signal terminal; the reset signal terminal RST and the first reset control signal terminal RSTC1 are loaded with the same signal, that is, the reset signal terminal RST and the first reset control signal terminal RSTC1 can be the same signal terminal.

[0143] In some embodiments of this disclosure, as shown in FIG2, the transistors in the shift register unit SR include metal-oxide-semiconductor (MOD) transistors. For example, the input transistor M1, the first reset transistor M2, the second reset transistor M3, the first control transistor M4, the second control transistor M5, the first output transistor M6, the second output transistor M7, the third reset transistor M8, the third control transistor M9, the fourth control transistor M10, the fifth control transistor M11, the sixth control transistor M12, the seventh control transistor M13, the eighth control transistor M14, the ninth control transistor M15, the tenth control transistor M16, the eleventh control transistor M17, and the twelfth control transistor M18 in the shift register unit SR can all be configured as MOD transistors. Alternatively, some of the transistors in the shift register unit can be configured as oxide transistors.

[0144] For example, the active layer material of the transistor in the shift register unit can be any one or more of metal oxide, amorphous silicon (a-Si), polycrystalline silicon (p-Si), and low temperature polycrystalline silicon (LTPS), wherein the active layer material is preferably a metal oxide transistor.

[0145] For example, the active layer material of the transistor in the shift register unit may include: metal oxide materials and / or metal oxide nitride materials. Metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. Metal oxide nitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. The active layer material can be amorphous, partially crystalline, single-crystal or polycrystalline, and can also be a single-layer or multi-layer structure.

[0146] In some embodiments of this disclosure, as shown in FIG2, the gates of the first control transistor M4, the second control transistor M5, the input transistor M1, the first reset transistor M2, and the second reset transistor M3 each have a first gate and a second gate; for example, the first gate is a top gate and the second gate is a bottom gate; wherein, the second gates of the first control transistor M4, the second control transistor M5, the input transistor M1, the first reset transistor M2, and the second reset transistor M3 are electrically connected to the same fixed voltage signal terminal VTC.

[0147] In some embodiments of this disclosure, as shown in FIG3, the second gates of the first control transistor M4, the second control transistor M5, the input transistor M1, the first reset transistor M2, and the second reset transistor M3 are electrically connected to different fixed voltage signal terminals (e.g., VTC1, VTC2, VTC3, and VTC4 in FIG3). Specifically, the second gate of the input transistor M1 is electrically connected to the fixed voltage signal terminal VTC1, the second gate of the first reset transistor M2 is electrically connected to the fixed voltage signal terminal VTC2, the second gate of the second reset transistor M3 is electrically connected to the fixed voltage signal terminal VTC3, and the second gates of the first control transistor M4 and the second control transistor M5 are electrically connected to the fixed voltage signal terminal VTC4. The voltages applied to the fixed voltage signal terminals VTC1, VTC2, VTC3, and VTC4 may be partially the same, partially different, or all different; this is not specifically limited here. The voltage applied to the fixed voltage signal terminals VTC1, VTC2, VTC3, and VTC4 can be adjusted according to the threshold voltage requirements of the first control transistor M4, the second control transistor M5, the input transistor M1, the first reset transistor M2, and the second reset transistor M3.

[0148] In this embodiment, through the cooperation of the first control circuit, output circuit, reset circuit, second control circuit, third control circuit, fourth control circuit, and fifth control circuit, an effective level signal can be applied to the gate line electrically connected to the shift register unit, thereby controlling the scanning drive of the display panel. However, due to process technology and component aging issues, the threshold voltage of the transistors in the first and fourth control circuits may shift, causing leakage current in the first node of the shift register unit. This leads to abnormal signal output from the shift register unit, resulting in display abnormalities and affecting display quality.

[0149] By using dual-gate transistors (e.g., first control transistor M4, second control transistor M5, input transistor M1, first reset transistor M2, and second reset transistor M3) in the first and fourth control circuits, the threshold voltages of the transistors (e.g., first control transistor M4, second control transistor M5, input transistor M1, first reset transistor M2, and second reset transistor M3) in the first and fourth control circuits can be adjusted by adjusting the voltage at the fixed voltage signal terminal electrically connected to the second gate of the transistor. This prevents the first node in the shift register unit from forming a leakage current path through the transistors in the first and fourth control circuits, thus avoiding leakage problems at the first node and improving display quality.

[0150] It should be noted that due to the large fluctuations in the manufacturing process, the threshold voltages of the transistors in the shift register units produced in different batches vary significantly. Furthermore, the threshold voltages of the transistors in the shift register units may shift after prolonged operation, making it impossible to determine the specific value of the threshold voltage of the transistors in the shift register units. This makes it impossible to determine the appropriate voltage setting for the fixed voltage signal terminal. Consequently, even if the voltage of the fixed voltage signal terminal electrically connected to the second gate of the transistor is adjusted, it may not prevent the first node in the shift register unit from forming a leakage current path through the transistors in the first and fourth control circuits. Therefore, it is necessary to determine the specific value of the threshold voltage of the transistors in the shift register units.

[0151] Based on the above problems, the display device provided in this disclosure embodiment, as shown in FIG4, includes: a plurality of shift register units (e.g., SR1, SR2, SR3 in FIG4) and at least one detection unit 300;

[0152] The detection unit 300 is electrically connected to the shift register unit SR2 and is configured to provide the initialization signal terminal Vinit to the first node N1 in the shift register unit SR2, and to detect the voltage value of the signal on the first node N1. Based on the voltage value of the control signal terminal CS (e.g., the input control signal terminal INC, the first reset control signal terminal RSTC1, and the second reset control signal terminal RSTC2) in the shift register unit SR2 and the voltage value of the signal on the first node N1, the threshold voltage of the transistor in the shift register unit SR2 is obtained.

[0153] This embodiment of the present disclosure sets up a detection unit electrically connected to a shift register unit, configured to provide an initialization signal to a first node in the shift register unit and detect the voltage value of the signal on the first node. Based on the voltage value of the control signal in the shift register unit and the voltage value of the signal on the first node, the threshold voltage of the transistor in the shift register unit is obtained. That is, the threshold voltage of the transistor in the shift register unit can be detected and calculated. Based on the threshold voltage of the transistor in the shift register unit, the voltage setting value of the fixed voltage signal terminal electrically connected to the second gate of the transistor can be further determined. That is, a suitable voltage can be applied to the fixed voltage signal terminal, thereby preventing the first node in the shift register unit from forming a leakage current path through the transistor in the first control circuit and the fourth control circuit, thus avoiding leakage problems in the first node and improving display quality.

[0154] For example, for an N-type dual-gate transistor, the smaller the voltage value of the fixed voltage signal terminal electrically connected to the second gate of the N-type dual-gate transistor, the larger the threshold voltage Vth of the N-type dual-gate transistor; for a P-type dual-gate transistor, the larger the voltage value of the fixed voltage signal terminal electrically connected to the second gate of the P-type dual-gate transistor, the smaller the threshold voltage Vth of the N-type dual-gate transistor. If the detected threshold voltage of the N-type dual-gate transistor is small, the voltage value of the fixed voltage signal terminal electrically connected to the second gate of the N-type dual-gate transistor can be considered for reduction; if the detected threshold voltage of the N-type dual-gate transistor is large, the voltage value of the fixed voltage signal terminal electrically connected to the second gate of the N-type dual-gate transistor can be considered for increase; if the detected threshold voltage of the P-type dual-gate transistor is small, the voltage value of the fixed voltage signal terminal electrically connected to the second gate of the P-type dual-gate transistor can be considered for reduction; if the detected threshold voltage of the P-type dual-gate transistor is large, the voltage value of the fixed voltage signal terminal electrically connected to the second gate of the P-type dual-gate transistor can be considered for increase.

[0155] For example, as shown in Figure 4, multiple shift register units (such as SR1, SR2, and SR3 in Figure 4) are cascaded. The IN terminal of the first shift register unit SR1 needs to be electrically connected to the start-of-frame signal terminal STV. The cascade signal terminal OUTC in shift register unit SR1 is electrically connected to the input signal terminal IN in shift register unit SR1. The reset signal terminal RST in shift register unit SR1 is electrically connected to the cascade signal terminal OUTC in shift register unit SR2. The reset signal terminal RST in shift register unit SR1 is electrically connected to the input signal terminal IN in shift register unit SR3. The reset signal terminal RST in shift register unit SR2 is electrically connected to the cascade signal terminal OUTC in shift register unit SR3.

[0156] For example, as shown in Figures 5 and 6, if it is necessary to detect the threshold voltage of the transistor in the shift register unit SR2, the first node N1 in the shift register unit SR needs to be led to an external detection unit 300 via a signal trace.

[0157] In some embodiments of this disclosure, as shown in Figures 5 and 6, the detection unit 300 includes: a first switch SW1, a second switch SW2, and an analog-to-digital converter (ADC);

[0158] The first terminal of the first switch SW1 is electrically connected to the first node N1, and the second terminal of the first switch SW1 is electrically connected to the initialization signal terminal Vinit.

[0159] The first terminal of the second switch SW2 is electrically connected to the first node N1, and the second terminal of the second switch SW2 is electrically connected to the analog-to-digital converter (ADC).

[0160] The detection method for the display device provided in this disclosure embodiment, as shown in FIG7, includes the following steps:

[0161] S100, First stage: The detection unit provides the initialization signal terminal to the first node in the shift register unit;

[0162] S200, Second stage: The first control circuit in the shift register responds to the signal at the control signal terminal and provides the signal at the reference signal terminal to the first node;

[0163] S300, Third stage: The detection unit detects the voltage value of the signal on the first node, and obtains the threshold voltage of the transistor in the shift register unit based on the voltage value of the signal at the control signal terminal in the shift register unit and the voltage value of the signal on the first node.

[0164] The following explanation will use the structures shown in Figures 5 and 6 as examples, along with the simulation curve shown in Figure 8, to further illustrate the detection process of the threshold voltage of the second reset transistor M3 in the shift register.

[0165] As shown in Figure 8, sw1 represents the signal loaded on the first switch SW1, sw2 represents the signal loaded on the second switch SW2, rstc2 represents the signal loaded on the second reset control signal terminal, n1 represents the signal on the first node N1, and Vsensing represents the simulated voltage of the signal detected on the first node N1.

[0166] In the first stage, the voltage value of the third reference signal terminal VREF3 is controlled to be vgh, and the voltage values ​​of the input control signal terminal INC, the first reference signal terminal VREF1, the first reset control signal terminal RSTC1, the second reference signal terminal VREF2, the second reset control signal terminal RSTC2, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the clock signal terminal CLK, the reset signal terminal RST, the first reference voltage signal terminal V1, the second reference voltage signal terminal V2, and the third reference voltage signal terminal V3 are controlled to be vgl. Then all transistors in the shift register SR remain in the off state. At the same time, the second switch SW2 is controlled to open; the first switch SW1 is controlled to close. The first switch SW1 connects the first node N1 with the initialization signal terminal Vinit. The first switch SW1 provides the signal of the initialization signal terminal Vinit to the first node N1 in the shift register unit SR. Then the voltage value of the first node N1 is VN1 = Vini, where Vini represents the voltage value of the signal of the initialization signal terminal Vinit.

[0167] In the second stage, the voltage value of the third reference signal terminal VREF3 is controlled to be vgh, the voltage value of the second reset control signal terminal RSTC2 is controlled to be Vsen, and the voltage values ​​of the input control signal terminal INC, the first reference signal terminal VREF1, the first reset control signal terminal RSTC1, the second reference signal terminal VREF2, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the clock signal terminal CLK, the reset signal terminal RST, the first reference voltage signal terminal V1, the second reference voltage signal terminal V2, and the third reference voltage signal terminal V3 are controlled to be vgl. Then, the second reset transistor M3 in the shift register SR turns on under the control of the high level of the second reset control signal terminal RSTC2, and provides the signal of the third reference signal terminal VREF3 to the first node N1, thus charging the first node N1. The voltage value of the first node N1 is VN1 = Vsen - Vth_M3. In addition, the first switch SW1 and the second switch SW2 are controlled to turn on. Here, Vsen represents the voltage value of the signal of the second reset control signal terminal RSTC2, and Vth_M3 represents the threshold voltage of the second reset transistor M3.

[0168] In the third stage, the voltage value of the third reference signal terminal VREF3 is controlled to be vgh, the voltage value of the second reset control signal terminal RSTC2 is controlled to be Vsen, and the voltage values ​​of the input control signal terminal INC, the first reference signal terminal VREF1, the first reset control signal terminal RSTC1, the second reference signal terminal VREF2, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the clock signal terminal CLK, the reset signal terminal RST, the first reference voltage signal terminal V1, the second reference voltage signal terminal V2, and the third reference voltage signal terminal V3 are controlled to be vgl. Furthermore, the first switch SW1 is controlled to open. When switch SW2 is closed, it connects the analog-to-digital converter (ADC) to the first node N1. The ADC can then detect the voltage value VN1 of the first node N1, which is Vsensing. Since VN1 = Vsen - Vth_M3 = Vsensing, and based on the known voltage value Vsen applied to the second reset control signal terminal RSTC2 and the detected voltage value VN1 = Vsensing of the first node N1, the threshold voltage Vth_M3 of the second reset transistor M3 can be calculated as Vsen - VN1 = Vsen - Vsensing.

[0169] Examples are shown in Table 1:

[0170] Table 1

[0171] For example, the preset voltage value Vsen of the second reset control signal terminal RSTC2 is 7V, and the initial threshold voltage of the second reset transistor M3 is 1.5V.

[0172] In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1 as VN1 = Vsensing = 10.49628, VN1 = Vsen - Vth_M3 ≈ 10.5. Therefore, the threshold voltage of the second reset transistor M3 is Vth_M3 = 7 - 10.5 = -3.5, and the change in the threshold voltage of the second reset transistor M3 is ΔVth_M3 = -5. In the third stage, the ADC detects the voltage value of the first node N1 as VN1 = Vsensing = 9.50787, VN1 = Vsen - Vth_M3 ≈ 9.5. Therefore, the threshold voltage of the second reset transistor M3 is Vth_M3 = 7 - 9.5 = -2.5, and the change in the threshold voltage of the second reset transistor M3 is ΔVth_M3 = -5. The value ΔVth_M3 = -4; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 8.51484, VN1 = Vsen - Vth_M3 ≈ 8.5, then the threshold voltage of the second reset transistor M3, Vth_M3 = 7 - 8.5 = -1.5, and the change in the threshold voltage of the second reset transistor M3, ΔVth_M3 = -3; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 7.5253, VN1 = Vsen - Vth_M3 ≈ 7.5, then the threshold voltage of the second reset transistor M3, Vth_M3 = 7 - 7.5 = -0.5, and the change in the threshold voltage of the second reset transistor M3, ΔVth_M3 = -3. The threshold voltage change ΔVth_M3 = -1; in the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 6.53633, VN1 = Vsen - Vth_M3 ≈ 6.5, then the threshold voltage of the second reset transistor M3, Vth_M3 = 7 - 6.5 = 0.5, the threshold voltage change ΔVth_M3 of the second reset transistor M3, ΔVth_M3 = -1; in the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 5.54524, VN1 = Vsen - Vth_M3 ≈ 5.5, then the threshold voltage of the second reset transistor M3, Vth_M3 = 7 - 5.5 = 1.5, the second The threshold voltage change of the reset transistor M3, ΔVth_M3 = 0; in the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 4.55501, VN1 = Vsen - Vth_M3 ≈ 4.5, then the threshold voltage of the second reset transistor M3, Vth_M3 = 7 - 4.5 = 2.5, and the threshold voltage change of the second reset transistor M3, ΔVth_M3 = 1; in the third stage, the ADC detects the voltage value of the first node N1, VN1 = Vsensing = 3.56661, VN1 = Vsen - Vth_M3 ≈ 3.5, then the threshold voltage of the second reset transistor M3, Vth_M3 = 7 - 3.5 = 3.5. The change in the threshold voltage of the second reset transistor M3, ΔVth_M3 = 2; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 2.57491, VN1 = Vsen - Vth_M3 ≈ 2.5, then the threshold voltage of the second reset transistor M3, Vth_M3 = 7 - 2.5 = 4.5, and the change in the threshold voltage of the second reset transistor M3, ΔVth_M3 = 3; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 1.58439, V... Since N1 = Vsen - Vth_M3 ≈ 1.5, the threshold voltage of the second reset transistor M3, Vth_M3 = 7 - 1.5 = 5.5, and the change in the threshold voltage of the second reset transistor M3, ΔVth_M3 = 4. In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 0.5959, VN1 = Vsen - Vth_M3 ≈ 0.5. Therefore, the threshold voltage of the second reset transistor M3, Vth_M3 = 7 - 0.5 = 6.5, and the change in the threshold voltage of the second reset transistor M3, ΔVth_M3 = 5.

[0173] It should be noted that the above only considers the threshold voltage shift of the second reset transistor M3 in the shift register. When the threshold voltages of other transistors in the shift register are normal, the threshold voltage of the second reset transistor M3 can be accurately detected. When the threshold voltages of all transistors in the shift register are positively shifted, the threshold voltage of the second reset transistor M3 can still be accurately detected. When the threshold voltages of all transistors in the shift register are negatively shifted, the detection of the threshold voltage of the second reset transistor M3 is distorted.

[0174] For example, as shown in Table 2:

[0175] Table 2

[0176] As can be seen from Table 2, the data for the threshold voltage Vth_M3 of the second reset transistor M3, which should have been detected as -3.5, -2.5, -1.5, and -0.5, correspond to the voltage values ​​VN1 = Vsensing of the first node N1 detected by the analog-to-digital converter (ADC) in the third stage as 4.23617, 5.02585, 5.78499, and 6.51039, respectively. It is evident that the detected voltage value VN1 = Vsensing of the first node N1 is significantly distorted. According to the analysis, this is because when the threshold voltages of all transistors in the shift register are negatively offset, the first node N1 can form a leakage current path through the first control transistor M4, the second control transistor M5, the input transistor M1, and the first reset transistor M2, thereby affecting the voltage value of the first node N1 detected by the ADC. Therefore, in this embodiment, by adjusting the voltage, the first node N1 can be completely turned off through the first control transistor M4, the second control transistor M5, the input transistor M1, and the first reset transistor M2, thus avoiding the formation of a leakage current path.

[0177] The specific testing methods are as follows:

[0178] In the first stage, the voltage values ​​of the third reference signal terminal VREF3 and the first reference signal terminal VREF1 are controlled to be vgh. The voltage values ​​of the input control signal terminal INC, the clock signal terminal CLK, the first reset control signal terminal RSTC1, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl. The voltage values ​​of the second reference signal terminal VREF2, the second reset control signal terminal RSTC2, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl. Then all transistors in the shift register SR remain in the off state. In addition, the second switch SW2 is controlled to open. The first switch SW1 is controlled to close. The first switch SW1 connects the first node N1 with the initialization signal terminal Vinit. The first switch SW1 provides the signal of the initialization signal terminal Vinit to the first node N1 in the shift register unit SR. Then the voltage value of the first node N1 is VN1 = Vini, where Vini represents the voltage value of the signal of the initialization signal terminal Vinit.

[0179] In the second stage, the voltage values ​​of the third reference signal terminal VREF3 and the first reference signal terminal VREF1 are controlled to be vgh, the voltage value of the second reset control signal terminal RSTC2 is controlled to be Vsen, and the voltage values ​​of the input control signal terminal INC, the clock signal terminal CLK, the first reset control signal terminal RSTC1, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl. The voltage values ​​of the second reference signal terminal VREF2, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V... The voltage value of 2 is vgl; then the second reset transistor M3 in the shift register SR is turned on under the control of the high level of the second reset control signal terminal RSTC2, and the signal of the third reference signal terminal VREF3 is provided to the first node N1, so the first node N1 is charged, and the voltage value of the first node N1 is VN1 = Vsen - Vth_M3; and the first switch SW1 is turned on; the second switch SW2 is turned on; where Vsen represents the voltage value of the signal of the second reset control signal terminal RSTC2, and Vth_M3 represents the threshold voltage of the second reset transistor M3;

[0180] In the third stage, the voltage values ​​of the third reference signal terminal VREF3 and the first reference signal terminal VREF1 are controlled to be vgh; the voltage value of the second reset control signal terminal RSTC2 is controlled to be Vsen; the voltage values ​​of the input control signal terminal INC, the clock signal terminal CLK, the first reset control signal terminal RSTC1, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl; the voltage values ​​of the second reference signal terminal VREF2, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl; and the first switch SW1 is controlled to be turned on. Open; control the second switch SW2 to close, the second switch SW2 connects the analog-to-digital converter (ADC) to the first node N1, then the ADC can detect the voltage value VN1 of the first node N1, and the detected VN1 = Vsensing; since VN1 = Vsen - Vth_M3 = Vsensing, and based on the known voltage value Vsen loaded at the second reset control signal terminal RSTC2 and the detected voltage value VN1 = Vsensing of the first node N1, the threshold voltage Vth_M3 of the second reset transistor M3 can be calculated as Vsen - VN1 = Vsen - Vsensing.

[0181] When the shift register unit is operating normally, both the first switch SW1 and the second switch SW2 in the detection unit are in the open state. The second reference voltage signal terminal V2, the third reference voltage signal terminal V3, the first reference signal terminal VREF1, and the second reference signal terminal VREF2 can be loaded with the same signal. Furthermore, the external IC can provide a suitable voltage value to the fixed voltage signal terminal electrically connected to the second reset transistor M3 based on the detected threshold voltage Vth_M3 of the second reset transistor M3, thereby adjusting the threshold voltage of the second reset transistor M3 and preventing leakage current from forming through the second reset transistor M3 at the first node N1.

[0182] It should be noted that the above detection process (i.e., the first stage, the second stage, and the third stage) can be implemented during power-on, power-off, and the blank time between frames. Furthermore, during the detection process, it is necessary to control the signals loaded onto the third reference signal terminal VREF3 and the second reset control signal terminal RSTC2. These signals can be set as global signals. Since it is necessary to read the voltage value of the first node N1, the first node N1 in the shift register unit to be detected (e.g., SR2 in Figure 4) needs to be connected to an external detection unit via signal traces. When it is necessary to detect transistors in multiple shift register units, the first node N1 in each shift register unit is individually led out via signal traces and connected to multiple external detection units, thus enabling simultaneous multi-point detection. That is, if it is necessary to detect transistors in N shift register units, then N detection units are needed, thereby enabling simultaneous multi-point detection.

[0183] Furthermore, since the reset signal terminal RST and the first reset control signal terminal RSTC1 in the last shift register unit are generally provided by the second reset control signal terminal RSTC2, the transistors in the last shift register unit generally cannot be detected.

[0184] The following explanation will use the structures shown in Figures 5 and 6 as examples to further illustrate the detection process of the threshold voltage of the first reset transistor M2 in the shift register.

[0185] In the first stage, the voltage value of the second reference signal terminal VREF2 is controlled to be vgh, and the voltage values ​​of the input control signal terminal INC, the first reference signal terminal VREF1, the first reset control signal terminal RSTC1, the third reference signal terminal VREF3, the second reset control signal terminal RSTC2, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the clock signal terminal CLK, the reset signal terminal RST, the first reference voltage signal terminal V1, the second reference voltage signal terminal V2, and the third reference voltage signal terminal V3 are controlled to be vgl. Then all transistors in the shift register SR remain in the off state. At the same time, the second switch SW2 is controlled to open; the first switch SW1 is controlled to close. The first switch SW1 connects the first node N1 with the initialization signal terminal Vinit. The first switch SW1 provides the signal of the initialization signal terminal Vinit to the first node N1 in the shift register unit SR. Then the voltage value of the first node N1 is VN1 = Vini, where Vini represents the voltage value of the signal of the initialization signal terminal Vinit.

[0186] In the second stage, the voltage value of the second reference signal terminal VREF2 is controlled to be vgh, the voltage value of the first reset control signal terminal RSTC1 is controlled to be Vsen, and the voltage values ​​of the input control signal terminal INC, the first reference signal terminal VREF1, the second reset control signal terminal RSTC2, the third reference signal terminal VREF3, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the clock signal terminal CLK, the reset signal terminal RST, the first reference voltage signal terminal V1, the second reference voltage signal terminal V2, and the third reference voltage signal terminal V3 are controlled to be vgl. Then, the first reset transistor M2 in the shift register SR turns on under the control of the high level of the first reset control signal terminal RSTC1, and provides the signal of the second reference signal terminal VREF2 to the first node N1, thus charging the first node N1. The voltage value of the first node N1 is VN1 = Vsen - Vth_M2. In addition, the first switch SW1 and the second switch SW2 are controlled to turn on. Here, Vsen represents the voltage value of the signal of the first reset control signal terminal RSTC1, and Vth_M2 represents the threshold voltage of the first reset transistor M2.

[0187] In the third stage, the voltage value of the second reference signal terminal VREF2 is controlled to be vgh, the voltage value of the first reset control signal terminal RSTC1 is controlled to be Vsen, and the voltage values ​​of the input control signal terminal INC, the first reference signal terminal VREF1, the second reset control signal terminal RSTC2, the third reference signal terminal VREF3, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the clock signal terminal CLK, the reset signal terminal RST, the first reference voltage signal terminal V1, the second reference voltage signal terminal V2, and the third reference voltage signal terminal V3 are controlled to be vgl. Furthermore, the first switch SW1 is controlled to open. When switch SW2 is closed, it connects the analog-to-digital converter (ADC) to the first node N1. The ADC can then detect the voltage value VN1 of the first node N1, which is Vsensing. Since VN1 = Vsen - Vth_M2 = Vsensing, and based on the known voltage value Vsen applied to the first reset control signal terminal RSTC1 and the detected voltage value VN1 = Vsensing of the first node N1, the threshold voltage Vth_M2 of the first reset transistor M2 can be calculated as Vsen - VN1 = Vsen - Vsensing.

[0188] It should be noted that the above only considers the threshold voltage shift of the first reset transistor M2 in the shift register. When the threshold voltages of other transistors in the shift register are normal, the threshold voltage of the first reset transistor M2 can be accurately detected. When the threshold voltages of all transistors in the shift register are positively shifted, the threshold voltage of the first reset transistor M2 can still be accurately detected. When the threshold voltages of all transistors in the shift register are negatively shifted, the detection of the threshold voltage of the first reset transistor M2 is distorted. According to the analysis, when the threshold voltages of all transistors in the shift register are negatively shifted, the first node N1 can form a leakage current path through the first control transistor M4, the second control transistor M5, the input transistor M1, and the second reset transistor M3, thereby affecting the voltage value of the first node N1 detected by the analog-to-digital converter (ADC). Therefore, this embodiment adjusts the voltage so that the first node N1 can be completely turned off through the first control transistor M4, the second control transistor M5, the input transistor M1, and the second reset transistor M3, thus avoiding the formation of a leakage current path.

[0189] The specific testing methods are as follows:

[0190] In the first stage, the voltage values ​​of the second reference signal terminal VREF2 and the first reference signal terminal VREF1 are controlled to be vgh. The voltage values ​​of the input control signal terminal INC, the clock signal terminal CLK, the second reset control signal terminal RSTC2, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl. The voltage values ​​of the third reference signal terminal VREF3, the first reset control signal terminal RSTC1, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl. Then, all transistors in the shift register SR remain in the off state. In addition, the second switch SW2 is controlled to open. The first switch SW1 is controlled to close. The first switch SW1 connects the first node N1 with the initialization signal terminal Vinit. The first switch SW1 provides the signal of the initialization signal terminal Vinit to the first node N1 in the shift register unit SR. Then, the voltage value of the first node N1 is VN1 = Vini, where Vini represents the voltage value of the signal of the initialization signal terminal Vinit.

[0191] In the second stage, the voltage values ​​of the second reference signal terminal VREF2 and the first reference signal terminal VREF1 are controlled to be vgh, the voltage value of the first reset control signal terminal RSTC1 is controlled to be Vsen, and the voltage values ​​of the input control signal terminal INC, the clock signal terminal CLK, the second reset control signal terminal RSTC2, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl. The voltage values ​​of the third reference signal terminal VREF3, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are also controlled to be lower than vgl. The voltage value of 2 is vgl; then the first reset transistor M1 in the shift register SR is turned on under the control of the high level of the first reset control signal terminal RSTC1, and the signal of the second reference signal terminal VREF2 is provided to the first node N1, so the first node N1 is charged, and the voltage value of the first node N1 is VN1 = Vsen - Vth_M2; and the first switch SW1 is turned on; the second switch SW2 is turned on; where Vsen represents the voltage value of the signal of the first reset control signal terminal RSTC1, and Vth_M2 represents the threshold voltage of the first reset transistor M2;

[0192] In the third stage, the voltage values ​​of the second reference signal terminal VREF2 and the first reference signal terminal VREF1 are controlled to be vgh, the voltage value of the first reset control signal terminal RSTC1 is controlled to be Vsen, and the voltage values ​​of the input control signal terminal INC, the clock signal terminal CLK, the second reset control signal terminal RSTC2, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl. The voltage values ​​of the third reference signal terminal VREF3, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl. Furthermore, the first switch SW1 is controlled to open. Open; control the second switch SW2 to close, the second switch SW2 connects the analog-to-digital converter (ADC) to the first node N1, then the ADC can detect the voltage value VN1 of the first node N1, and the detected VN1 = Vsensing; since VN1 = Vsen - Vth_M2 = Vsensing, and based on the known voltage value Vsen loaded on the first reset control signal terminal RSTC1 and the detected voltage value VN1 = Vsensing of the first node N1, the threshold voltage Vth_M2 of the first reset transistor M2 can be calculated as Vsen - VN1 = Vsen - Vsensing.

[0193] When the shift register unit is operating normally, both the first switch SW1 and the second switch SW2 in the detection unit are in the open state. The second reference voltage signal terminal V2, the third reference voltage signal terminal V3, the first reference signal terminal VREF1, and the second reference signal terminal VREF2 can be loaded with the same signal. Furthermore, the external IC can provide a suitable voltage value to the fixed voltage signal terminal electrically connected to the first reset transistor M2 based on the detected threshold voltage Vth_M2 of the first reset transistor M2, thereby adjusting the threshold voltage of the first reset transistor M2 and preventing leakage current from forming through the first node N1 via the first reset transistor M2.

[0194] It should be noted that the above detection process (i.e., the first stage, the second stage, and the third stage) can be implemented during power-on, power-off, and the blank time between frames. Furthermore, during the detection process, it is necessary to control the signals loaded onto the second reference signal terminal VREF2 and the first reset control signal terminal RSTC1. The signal at the second reference signal terminal VREF2 can be set as a global signal. The first reset control signal terminal RSTC1 (e.g., SR2 in Figure 9) needs to be led out through signal traces. Since it is necessary to read the voltage value of the first node N1, the first node N1 in the shift register unit to be detected (e.g., SR2 in Figure 9) needs to be connected to the external detection unit through signal traces. When it is necessary to detect transistors in multiple shift register units, the first node N1 in each shift register unit is led out separately through signal traces and connected to multiple external detection units, thus enabling simultaneous multi-point detection. That is, if it is necessary to detect transistors in N shift register units, then N detection units are needed, thereby enabling simultaneous multi-point detection.

[0195] As shown in Figure 9, since the RST and RSTC1 signals in the shift register unit are provided by the OUTC in the lower-level shift register unit, and since the RST and RSTC1 signals in the shift register unit can also be used as the IN and IC signals in the lower-level shift register unit, in order to ensure that INC and IN are low-level signals during the detection process, the detection position needs to be set at intervals to ensure that the detected shift register unit is not affected by the shift register unit before or after the previous stage.

[0196] Furthermore, since the reset signal terminal RST and the first reset control signal terminal RSTC1 in the last shift register unit are generally provided by the second reset control signal terminal RSTC2, the transistors in the last shift register unit generally cannot be detected.

[0197] The following explanation will use the structures shown in Figures 5 and 6 as examples to further illustrate the detection process of the threshold voltage of the input transistor M1 in the shift register.

[0198] In the first stage, the voltage value of the first reference signal terminal VREF1 is controlled to be vgh, and the voltage values ​​of the input control signal terminal INC, the second reference signal terminal VREF2, the first reset control signal terminal RSTC1, the third reference signal terminal VREF3, the second reset control signal terminal RSTC2, the input signal terminal IN, the first power supply terminal VDD1, the second power supply terminal VDD2, the clock signal terminal CLK, the reset signal terminal RST, the first reference voltage signal terminal V1, the second reference voltage signal terminal V2, and the third reference voltage signal terminal V3 are controlled to be vgl. Then all transistors in the shift register SR remain in the off state. At the same time, the second switch SW2 is controlled to open; the first switch SW1 is controlled to close. The first switch SW1 connects the first node N1 with the initialization signal terminal Vinit. The first switch SW1 provides the signal of the initialization signal terminal Vinit to the first node N1 in the shift register unit SR. Then the voltage value of the first node N1 is VN1 = Vini, where Vini represents the voltage value of the signal of the initialization signal terminal Vinit.

[0199] In the second stage, the voltage value of the first reference signal terminal VREF1 is controlled to be vgh, the voltage values ​​of the input control signal terminals INC and IN are controlled to be Vsen, and the voltage values ​​of the first reset control signal terminal RSTC1, the second reference signal terminal VREF2, the second reset control signal terminal RSTC2, the third reference signal terminal VREF3, the first power supply terminal VDD1, the second power supply terminal VDD2, the clock signal terminal CLK, the reset signal terminal RST, the first reference voltage signal terminal V1, the second reference voltage signal terminal V2, and the third reference voltage signal terminal V3 are controlled to be vgl. Then, the input transistor M1 in the shift register SR is turned on under the control of the high level of the input control signal terminal INC, and the signal of the first reference signal terminal VREF1 is provided to the first node N1, thus charging the first node N1. The voltage value of the first node N1 is VN1 = Vsen - Vth_M1. In addition, the first switch SW1 and the second switch SW2 are turned on. Here, Vsen represents the voltage value of the signal of the input control signal terminal INC, and Vth_M1 represents the threshold voltage of the input transistor M1.

[0200] In the third stage, the voltage value of the first reference signal terminal VREF1 is controlled to be vgh, the voltage value of the input control signal terminal INC and the input signal terminal IN is controlled to be Vsen, the voltage value of the first reset control signal terminal RSTC1, the second reference signal terminal VREF2, the second reset control signal terminal RSTC2, the third reference signal terminal VREF3, the first power supply terminal VDD1, the second power supply terminal VDD2, the clock signal terminal CLK, the reset signal terminal RST, the first reference voltage signal terminal V1, the second reference voltage signal terminal V2, and the third reference voltage signal terminal V3 is controlled to be vgl, and the first switch SW1 is controlled to open. When the second switch SW2 is closed, it connects the analog-to-digital converter (ADC) to the first node N1. The ADC can then detect the voltage value VN1 of the first node N1, which is Vsensing. Since VN1 = Vsen - Vth_M1 = Vsensing, and based on the known voltage value Vsen applied to the input control signal terminal INC and the detected voltage value VN1 = Vsensing of the first node N1, the threshold voltage Vth_M1 of the input transistor M1 can be calculated as Vsen - VN1 = Vsen - Vsensing.

[0201] It should be noted that the above only considers the threshold voltage shift of the input transistor M1 in the shift register. When the threshold voltages of other transistors in the shift register are normal, the threshold voltage of the input transistor M1 can be accurately detected. When the threshold voltages of all transistors in the shift register are positively shifted, the threshold voltage of the input transistor M1 can still be accurately detected. When the threshold voltages of all transistors in the shift register are negatively shifted, the detection of the threshold voltage of the input transistor M1 is distorted. According to the analysis, when the threshold voltages of all transistors in the shift register are negatively shifted, the first node N1 can form a leakage current path through the first control transistor M4, the second control transistor M5, the first reset transistor M2, and the second reset transistor M3, thereby affecting the voltage value of the first node N1 detected by the analog-to-digital converter (ADC). Therefore, this embodiment adjusts the voltage so that the first node N1 can be completely turned off through the first control transistor M4, the second control transistor M5, the first reset transistor M2, and the second reset transistor M3, thus avoiding the formation of a leakage current path.

[0202] The specific testing methods are as follows:

[0203] In the first stage, the voltage value of the first reference signal terminal VREF1 is controlled to be vgh, and the voltage values ​​of the clock signal terminal CLK, the first reset control signal terminal RSTC1, the second reset control signal terminal RSTC2, the first power supply terminal VDD1, the second power supply terminal VDD2, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl. The voltage values ​​of the input control signal terminal INC, the input signal terminal IN, the second reference signal terminal VREF2, the third reference signal terminal VREF3, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl. Then all transistors in the shift register SR remain in the off state. In addition, the second switch SW2 is controlled to open, and the first switch SW1 is controlled to close. The first switch SW1 connects the first node N1 with the initialization signal terminal Vinit. The first switch SW1 provides the signal of the initialization signal terminal Vinit to the first node N1 in the shift register unit SR. Then the voltage value of the first node N1 is VN1 = Vini, where Vini represents the voltage value of the signal of the initialization signal terminal Vinit.

[0204] In the second stage, the voltage value of the first reference signal terminal VREF1 is controlled to be vgh, the voltage value of the input control signal terminal INC and the input signal terminal IN is controlled to be Vsen, and the voltage values ​​of the clock signal terminal CLK, the first reset control signal terminal RSTC1, the second reset control signal terminal RSTC2, the first power supply terminal VDD1, the second power supply terminal VDD2, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl. The voltage values ​​of the second reference signal terminal VREF2, the third reference signal terminal VREF3, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl. Then, the input transistor M1 in the shift register SR is turned on under the control of the high level of the input control signal terminal INC, and the signal of the first reference signal terminal VREF1 is provided to the first node N1, thus charging the first node N1. The voltage value of the first node N1 is VN1 = Vsen - Vth_M1. In addition, the first switch SW1 is turned on and the second switch SW2 is turned on. Here, Vsen represents the voltage value of the signal of the input control signal terminal INC, and Vth_M1 represents the threshold voltage of the input transistor M1.

[0205] In the third stage, the voltage value of the first reference signal terminal VREF1 is controlled to be vgh; the voltage values ​​of the input control signal terminals INC and IN are controlled to be Vsen; the voltage values ​​of the clock signal terminal CLK, the first reset control signal terminal RSTC1, the second reset control signal terminal RSTC2, the first power supply terminal VDD1, the second power supply terminal VDD2, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl; the voltage values ​​of the second reference signal terminal VREF2, the third reference signal terminal VREF3, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl; and the first switch S is controlled... When W1 is turned on, the second switch SW2 is closed. The second switch SW2 connects the analog-to-digital converter (ADC) to the first node N1. The ADC can then detect the voltage value VN1 of the first node N1, and the detected VN1 = Vsensing. Since VN1 = Vsen - Vth_M1 = Vsensing, and based on the known voltage value Vsen applied to the input control signal terminal INC and the detected voltage value VN1 = Vsensing of the first node N1, the threshold voltage Vth_M1 of the input transistor M1 can be calculated as Vsen - VN1 = Vsen - Vsensing.

[0206] When the shift register unit is operating normally, both the first switch SW1 and the second switch SW2 in the detection unit are in the open state. The second reference voltage signal terminal V2, the third reference voltage signal terminal V3, the first reference signal terminal VREF1, and the second reference signal terminal VREF2 can be loaded with the same signal. Furthermore, the external IC can provide a suitable voltage value to the fixed voltage signal terminal electrically connected to the input transistor M1 based on the detected threshold voltage Vth_M1 of the input transistor M1, thereby adjusting the threshold voltage of the input transistor M1 and preventing the first node N1 from forming a leakage current path through the input transistor M1.

[0207] It should be noted that the above detection process (i.e., the first stage, the second stage, and the third stage) can be implemented during power-on, power-off, and the blank time between frames. Furthermore, during the detection process, it is necessary to control the signals loaded onto the first reference signal terminal VREF1, the input control signal terminal INC, and the input signal terminal IN. The signal at the first reference signal terminal VREF1 can be set as a global signal. The input signal terminal IN (e.g., SR2 in Figure 10) needs to be led out through signal traces. Since it is necessary to read the voltage value of the first node N1, the first node N1 in the shift register unit to be detected (e.g., SR2 in Figure 10) needs to be connected to the external detection unit through signal traces. When it is necessary to detect transistors in multiple shift register units, the first node N1 in each shift register unit is led out separately through signal traces and connected to multiple external detection units, thus enabling simultaneous multi-point detection. That is, if it is necessary to detect transistors in N shift register units, then N detection units are needed, thereby enabling simultaneous multi-point detection.

[0208] As shown in Figure 10, since the input signal terminal IN and the input control signal terminal INC in the shift register unit are provided by the cascaded signal terminal OUTC in the upper-level shift register unit, and since the input signal terminal IN and the input control signal terminal INC in the shift register unit can also serve as the reset signal terminal RST and the first reset control signal terminal RSTC1 in the upper-level shift register unit, in order to ensure that the reset signal terminal RST and the first reset control signal terminal RSTC1 are low-level signals during the detection process, it is necessary to set the detection position at intervals to ensure that the detected shift register unit is not affected by the shift register unit before or after the previous stage.

[0209] Furthermore, if the input transistor M1 in the first-stage shift register unit is detected, the signal from the frame start signal terminal STV can be input to the input signal terminal IN and the input control signal terminal INC, thus avoiding the need to increase the number of signals and simplifying the signal count.

[0210] For example, the above detection process can detect only the input crystal M1, or the first reset transistor M2, or the second reset transistor M3; it can also detect only the input crystal M1 and the first reset transistor M2, or the input crystal M1 and the second reset transistor M3, or the first reset transistor M2 and the second reset transistor M3; or it can detect all of the input crystal M1, the first reset transistor M2, and the second reset transistor M3. As for the detection order, no specific setting is made, and the detection process can refer to the above detection method, which will not be elaborated here.

[0211] It should be noted that if it is necessary to detect the input crystal M1, the first reset transistor M2, and the second reset transistor M3, then the signals of the first reference signal terminal VREF1, the second reference signal terminal VREF2, the third reference signal terminal VREF3, and the second reset control signal terminal RSTC2 can be set as global signals. The first reset control signal terminal RSTC1 needs to be brought out through signal traces (as shown in Figure 11), and the input signal terminal IN needs to be brought out through signal traces (as shown in Figure 11). Furthermore, the detection positions need to be set at intervals to ensure that the detected shift register unit is not affected by the shift register units of the preceding or following stages.

[0212] However, since the aforementioned detection unit is directly electrically connected to the first node N1 in the shift register unit, this typically introduces a resistive-capacitive load (as shown in Figures 12 and 13). When the shift register unit is outputting a signal normally, the bootstrap function of the first capacitor C1 in the shift register unit is required to ensure that the first output transistor M6 is fully turned on and outputs a high-level signal. When the first node N1 is electrically connected to the detection unit, it increases the external load. The boost voltage at the output signal terminal will be divided by the first capacitor C1 and the load capacitor C (as shown in Figures 12 and 13), resulting in insufficient secondary boost voltage at the first node. This leads to low output from the shift register unit, and ultimately, no output from the shift register unit. Therefore, the aforementioned electrical connection between the detection unit and the first node N1 is only suitable when the signal trace load is small, such as in locations near the last row register unit or on extremely small screens.

[0213] Based on the above problems, this disclosure provides another detection unit, as shown in Figures 14 and 15. The detection unit 300 includes: a first detection unit 301, which is electrically connected to the first terminal of the input transistor M1 and is configured to connect the first terminal of the input transistor M1 to the first reference signal terminal VREF1, or to connect the first terminal of the input transistor M1 to the initialization signal terminal Vinit.

[0214] In some embodiments of this disclosure, as shown in Figures 14 and 15, the first detection unit 301 includes: a third switch SW3, a fourth switch SW4, a fifth switch SW5, and a first analog-to-digital converter ADC1;

[0215] The first terminal of the third switch SW3 is electrically connected to the first electrode of the input transistor M1, and the second terminal of the third switch SW3 is electrically connected to the first reference signal terminal VREF1.

[0216] The first terminal of the fourth switch SW4 is electrically connected to the first electrode of the input transistor M1, and the second terminal of the fourth switch SW4 is electrically connected to the initialization signal terminal Vinit.

[0217] The first terminal of the fifth switch SW5 is electrically connected to the first electrode of the input transistor M1, and the second terminal of the fifth switch SW5 is electrically connected to the first analog-to-digital converter ADC1.

[0218] In some embodiments of this disclosure, as shown in Figures 14 and 15, the detection unit 300 further includes: a second detection unit 302, electrically connected to the first terminal of the first reset transistor M2, configured to connect the first terminal of the first reset transistor M2 to the second reference signal terminal VREF2, or connect the first terminal of the first reset transistor M2 to the initialization signal terminal Vinit, or connect the first terminal of the first reset transistor M2 to the first reference signal terminal VREF1.

[0219] In some embodiments of this disclosure, as shown in Figures 14 and 15, the second detection unit 302 includes: a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a ninth switch SW9, and a second analog-to-digital converter ADC2;

[0220] The first terminal of the sixth switch SW6 is electrically connected to the first electrode of the first reset transistor M2, and the second terminal of the sixth switch SW6 is electrically connected to the second reference signal terminal VREF2.

[0221] The first terminal of the seventh switch SW7 is electrically connected to the first electrode of the first reset transistor M2, and the second terminal of the seventh switch SW7 is electrically connected to the initialization signal terminal Vinit.

[0222] The first terminal of the eighth switch SW8 is electrically connected to the first electrode of the first reset transistor M2, and the second terminal of the eighth switch SW8 is electrically connected to the second analog-to-digital converter ADC2.

[0223] The first terminal of the ninth switch SW is electrically connected to the first electrode of the first reset transistor M2, and the second terminal of the ninth switch SW is electrically connected to the first reference signal terminal VREF1.

[0224] In some embodiments of this disclosure, as shown in Figures 14 and 15, the detection unit 300 further includes: a third detection unit 303, electrically connected to the first terminal of the second reset transistor M3, configured to connect the first terminal of the second reset transistor M3 to the third reference signal terminal VREF3, or connect the first terminal of the second reset transistor M3 to the initialization signal terminal Vinit, or connect the first terminal of the second reset transistor M3 to the first reference signal terminal VREF1.

[0225] In some embodiments of this disclosure, as shown in Figures 14 and 15, the third detection unit 303 includes: a tenth switch SW10, an eleventh switch SW11, a twelfth switch SW12, a thirteenth switch SW13, and a third analog-to-digital converter ADC3.

[0226] The first terminal of the tenth switch SW10 is electrically connected to the first electrode of the second reset transistor M3, and the second terminal of the tenth switch SW10 is electrically connected to the third reference signal terminal VREF3.

[0227] The first terminal of the eleventh switch SW11 is electrically connected to the first electrode of the second reset transistor M3, and the second terminal of the eleventh switch SW11 is electrically connected to the initialization signal terminal Vinit.

[0228] The first terminal of the twelfth switch SW12 is electrically connected to the first terminal of the second reset transistor M3, and the second terminal of the twelfth switch SW12 is electrically connected to the third analog-to-digital converter ADC3.

[0229] The first terminal of the thirteenth switch SW13 is electrically connected to the first terminal of the second reset transistor M3, and the second terminal of the thirteenth switch SW13 is electrically connected to the first reference signal terminal VREF1.

[0230] This embodiment of the invention utilizes the cooperation of a first detection unit, a second detection unit, and a third detection unit to detect the threshold voltage of the transistor in the shift register unit without increasing the load capacitor resistance of the first node, thereby avoiding affecting the normal operation of the shift register unit and improving display quality.

[0231] The following section will use the structures shown in Figures 14 and 15 as examples to further explain the detection process of the threshold voltage of the input transistor M1 in the shift register.

[0232] For example, the threshold voltage of the input transistor M1 in the shift register can be detected through the cooperation of the first detection unit 301 and the second detection unit 302. The specific process is as follows:

[0233] In the first stage, the voltage values ​​of the first reference signal terminal VREF1, the second reference signal terminal VREF2, and the second reset control signal terminal RSTC2 are controlled to be vgh; the voltage values ​​of the first reset control signal terminal RSTC1, the reset signal terminal RST, the clock signal terminal CLK, the first power supply terminal VDD1, the second power supply terminal VDD2, and the third reference voltage signal terminal V3 are controlled to be lower than vgl; the voltage values ​​of the input control signal terminal INC, the input signal terminal IN, the third reference signal terminal VREF3, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl; the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, the eighth switch SW8, the ninth switch SW9, the tenth switch SW10, the eleventh switch SW11, and the twelfth switch SW12 are controlled to open; the first... When switches SW3, SW7, and SW1 are closed, switch SW3 connects the first terminal of input transistor M1 to the first reference signal terminal VREF1; switch SW7 connects the first terminal of first reset transistor M2 to the initialization signal terminal Vinit; and switch SW1 connects the first terminal of second reset transistor M3 to the first reference signal terminal VREF1. The first reset transistor M2 is turned on under the control of a high level on the first reset control signal terminal RSTC1, and provides the initialization signal terminal Vinit to the first node N1 in the shift register unit SR. The voltage value of the first node N1 is VN1 = Vini, where Vini represents the voltage value of the initialization signal terminal Vinit.

[0234] In the second stage, the voltage values ​​of the first reference signal terminal VREF1, the third reference signal terminal VREF3, the first reset control signal terminal RSTC1, and the reset signal terminal RST are controlled to be vgh; the voltage values ​​of the input control signal terminal INC and the input signal terminal IN are controlled to be Vsen; the voltage values ​​of the clock signal terminal CLK, the second reset control signal terminal RSTC2, the first power supply terminal VDD1, the second power supply terminal VDD2, and the third reference voltage signal terminal V3 are controlled to be lower than vgl; the voltage values ​​of the second reference signal terminal VREF2, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl; and the voltage values ​​of the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, the eighth switch SW8, the ninth switch SW9, the tenth switch SW10, and the eleventh switch SW1 are controlled to be vgl. 1. When the twelfth switch SW12 is opened, the third switch SW3 and the thirteenth switch SW1 are closed. Then, the third switch SW3 connects the first terminal of the input transistor M1 to the first reference signal terminal VREF1. The thirteenth switch SW1 connects the first terminal of the second reset transistor M3 to the first reference signal terminal VREF1. Under the control of the high level of the input control signal terminal INC, the input transistor M1 is turned on and provides the signal of the first reference signal terminal VREF1 to the first node N1, thus charging the first node N1. The voltage value of the first node N1 is VN1 = Vsen - Vth_M1. Under the control of the high level of the first reset control signal terminal RSTC1, the first reset transistor M2 is turned on and transmits the voltage value of the first node N1 to the second detection unit 302.

[0235] In the third stage, the voltage values ​​of the first reference signal terminal VREF1, the third reference signal terminal VREF3, the first reset control signal terminal RSTC1, and the reset signal terminal RST are controlled to be vgh; the voltage values ​​of the input control signal terminal INC and the input signal terminal IN are controlled to be Vsen; the voltage values ​​of the clock signal terminal CLK, the second reset control signal terminal RSTC2, the first power supply terminal VDD1, the second power supply terminal VDD2, and the third reference voltage signal terminal V3 are controlled to be lower than vgl; the voltage values ​​of the second reference signal terminal VREF2, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl; the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, the eighth switch SW8, the ninth switch SW9, the tenth switch SW10, the eleventh switch SW11, and the twelfth switch SW12 are opened; the third switch SW3, the eighth switch SW8, and the thirteenth switch SW1 are closed; then the third switch SW3 connects the first terminal of the input transistor M1 to the first reference signal terminal V. REF1 is electrically connected; the thirteenth switch SW1 connects the first terminal of the second reset transistor M3 to the first reference signal terminal VREF1; then the eighth switch SW8 connects the first terminal of the first reset transistor M2 to the second analog-to-digital converter ADC2. The first reset transistor M2 is turned on under the control of the high level of the first reset control signal terminal RSTC1, and the first reset transistor M2 transmits the voltage value of the first node N1 to the second analog-to-digital converter ADC2 in the second detection unit 302; then the second analog-to-digital converter ADC2 can detect the voltage value VN1 of the first node N1, and the detected VN1 = Vsensing; since VN1 = Vsen - Vth_M1 = Vsensing, and according to the known voltage value Vsen loaded at the input control signal terminal INC and the detected voltage value VN1 = Vsensing of the first node N1, the threshold voltage Vth_M1 of the input transistor M1 can be calculated as Vsen - VN1 = Vsen - Vsensing.

[0236] For example, through the cooperation of the first detection unit 301 and the second detection unit 302, the current path for detecting the threshold voltage of the input transistor M1 in the shift register is from the third switch SW3 to the input transistor M1 to the first reset transistor M2 to the second analog-to-digital converter ADC2.

[0237] For example, as shown in Table 3:

[0238] Table 3

[0239] For example, the preset voltage value Vsen of the input control signal terminal INC is 7V, and the initial threshold voltage of the input transistor M1 is 1.5V;

[0240] In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1: VN1 = Vsensing = 10.56371, VN1 = Vsen - Vth_M1 ≈ 10.5. Therefore, the threshold voltage of input transistor M1, Vth_M1 = 7 - 10.5 = -3.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = -5. In the third stage, the ADC detects the voltage value of the first node N1: VN1 = Vsensing = 9.57044, VN1 = Vsen - Vth_M1 ≈ 9.5. Therefore, the threshold voltage of input transistor M1, Vth_M1 = 7 - 9.5 = -2.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = -5. △Vth_M1=-4; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1=Vsensing=8.57707, VN1=Vsen-Vth_M1≈8.5, then the threshold voltage of input transistor M1, Vth_M1=7-8.5=-1.5, and the change in the threshold voltage of input transistor M1, △Vth_M1=-3; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1=Vsensing=7.58359, VN1=Vsen-Vth_M1≈7.5, then the threshold voltage of input transistor M1, Vth_M1=7-7.5=-0.5, and the change in the threshold voltage of input transistor M1, △Vth_M1=-3; The threshold voltage change ΔVth_M1 = -1; in the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 6.59001, VN1 = Vsen - Vth_M1 ≈ 6.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 6.5 = 0.5, and the threshold voltage change ΔVth_M1 of input transistor M1 is -1; in the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 5.59634, VN1 = Vsen - Vth_M1 ≈ 5.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 5.5 = 1.5, and the input... The threshold voltage change of transistor M1, ΔVth_M1 = 0; in the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 4.60258, VN1 = Vsen - Vth_M1 ≈ 4.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 4.5 = 2.5, and the threshold voltage change of input transistor M1, ΔVth_M1 = 1; in the third stage, the ADC detects the voltage value of the first node N1, VN1 = Vsensing = 3.60872, VN1 = Vsen - Vth_M1 ≈ 3.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 3.5 = 3.5. The change in the threshold voltage of input transistor M1, ΔVth_M1 = 2; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 2.61530, VN1 = Vsen - Vth_M1 ≈ 2.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 2.5 = 4.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = 3; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 1.62083, Since VN1 = Vsen - Vth_M1 ≈ 1.5, the threshold voltage of input transistor M1, Vth_M1 = 7 - 1.5 = 5.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = 4. In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 0.62723, VN1 = Vsen - Vth_M1 ≈ 0.5. Therefore, the threshold voltage of input transistor M1, Vth_M1 = 7 - 0.5 = 6.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = 5.

[0241] For example, the threshold voltage of the input transistor M1 in the shift register can be detected through the cooperation of the first detection unit 301 and the third detection unit 303. The specific process is as follows:

[0242] In the first stage, the voltage values ​​of the first reference signal terminal VREF1, the third reference signal terminal VREF3, and the second reset control signal terminal RSTC2 are controlled to be vgh; the voltage values ​​of the clock signal terminal CLK, the first power supply terminal VDD1, the second power supply terminal VDD2, the first reset control signal terminal RSTC1, the reset signal terminal RST, and the third reference voltage signal terminal V3 are controlled to be lower than vgl; the voltage values ​​of the input control signal terminal INC, the input signal terminal IN, the second reference signal terminal VREF2, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl; the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, the eighth switch SW8, the tenth switch SW10, the twelfth switch SW12, and the thirteenth switch SW13 are controlled to open; the third... When switches SW3, SW9, and SW11 are closed, switch SW3 connects the first terminal of input transistor M1 to the first reference signal terminal VREF1; switch SW9 connects the first terminal of first reset transistor M2 to the first reference signal terminal VREF1; switch SW11 connects the first terminal of second reset transistor M3 to the initialization signal terminal Vinit; under the control of the high level of the second reset control signal terminal RSTC2, the second reset transistor M3 turns on and provides the signal of the initialization signal terminal Vinit to the first node N1 in the shift register unit SR. Then the voltage value of the first node N1 is VN1 = Vini, where Vini represents the voltage value of the signal of the initialization signal terminal Vinit.

[0243] In the second stage, the voltage values ​​of the first reference signal terminal VREF1, the third reference signal terminal VREF3, and the second reset control signal terminal RSTC2 are controlled to be vgh; the voltage values ​​of the input control signal terminal INC and the input signal terminal IN are controlled to be Vsen; the voltage values ​​of the clock signal terminal CLK, the first reset control signal terminal RSTC1, the reset signal terminal RST, the first power supply terminal VDD1, the second power supply terminal VDD2, and the third reference voltage signal terminal V3 are controlled to be lower than vgl; the voltage values ​​of the second reference signal terminal VREF2, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl; the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, the eighth switch SW8, the tenth switch SW10, the eleventh switch SW11, and the twelfth switch S are controlled to be vgl. When switches W12 and 13 (SW13) are open, switches SW3 and SW9 (SW9) are closed. Switch SW3 connects the first terminal of input transistor M1 to the first reference signal terminal VREF1. Switch SW9 connects the first terminal of reset transistor M2 to the first reference signal terminal VREF1. Input transistor M1 is turned on under the control of the high level of input control signal terminal INC, providing the signal of the first reference signal terminal VREF1 to the first node N1, thus charging the first node N1. The voltage value of the first node N1 is VN1 = Vsen - Vth_M1. The second reset transistor M3 is turned on under the control of the high level of the second reset control signal terminal RSTC2, and transmits the voltage value of the first node N1 to the third detection unit 303.

[0244] In the third stage, the voltage values ​​of the first reference signal terminal VREF1, the third reference signal terminal VREF3, and the second reset control signal terminal RSTC2 are controlled to be vgh; the voltage values ​​of the input control signal terminal INC and the input signal terminal IN are controlled to be Vsen; the voltage values ​​of the clock signal terminal CLK, the first reset control signal terminal RSTC1, the reset signal terminal RST, the first power supply terminal VDD1, the second power supply terminal VDD2, and the third reference voltage signal terminal V3 are controlled to be lower than vgl; the voltage values ​​of the second reference signal terminal VREF2, the first reference voltage signal terminal V1, and the second reference voltage signal terminal V2 are controlled to be vgl; the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, the eighth switch SW8, the tenth switch SW10, the eleventh switch SW11, and the thirteenth switch SW13 are controlled to be opened; the third switch SW3, the ninth switch SW9, and the twelfth switch SW12 are controlled to be closed; then the third switch SW3 connects the first terminal of the input transistor M1 to the first reference signal terminal VREF1. The ninth switch SW9 connects the first terminal of the first reset transistor M2 to the first reference signal terminal VREF1; the twelfth switch SW12 connects the first terminal of the second reset transistor M3 to the third analog-to-digital converter ADC3. The second reset transistor M3 then conducts under the control of the high level of the second reset control signal terminal RSTC2, transmitting the voltage value of the first node N1 to the third analog-to-digital converter ADC3 in the third detection unit 303. The third analog-to-digital converter ADC3 can then detect the voltage value VN1 of the first node N1, and the detected VN1 = Vsensing. Since VN1 = Vsen - Vth_M1 = Vsensing, and based on the known voltage value Vsen loaded at the input control signal terminal INC and the detected voltage value VN1 = Vsensing of the first node N1, the threshold voltage Vth_M1 of the input transistor M1 can be calculated as Vsen - VN1 = Vsen - Vsensing.

[0245] For example, through the cooperation of the first detection unit and the third detection unit, the current path for detecting the threshold voltage of the input transistor M1 in the shift register is from the third switch SW3 to the input transistor M1 to the second reset transistor M3 to the third analog-to-digital converter ADC3.

[0246] For example, as shown in Table 4:

[0247] Table 4

[0248] For example, the preset voltage value Vsen of the input control signal terminal INC is 7V, and the initial threshold voltage of the input transistor M1 is 1.5V;

[0249] In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1: VN1 = Vsensing = 10.56397, VN1 = Vsen - Vth_M1 ≈ 10.5. Therefore, the threshold voltage of input transistor M1, Vth_M1 = 7 - 10.5 = -3.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = -5. In the third stage, the ADC detects the voltage value of the first node N1: VN1 = Vsensing = 9.57071, VN1 = Vsen - Vth_M1 ≈ 9.5. Therefore, the threshold voltage of input transistor M1, Vth_M1 = 7 - 9.5 = -2.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = -5. △Vth_M1=-4; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1=Vsensing=8.57732, VN1=Vsen-Vth_M1≈8.5, then the threshold voltage of input transistor M1, Vth_M1=7-8.5=-1.5, and the change in the threshold voltage of input transistor M1, △Vth_M1=-3; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1=Vsensing=7.58386, VN1=Vsen-Vth_M1≈7.5, then the threshold voltage of input transistor M1, Vth_M1=7-7.5=-0.5, and the change in the threshold voltage of input transistor M1, △Vth_M1=-3; The threshold voltage change ΔVth_M1 = -1; in the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 6.59030, VN1 = Vsen - Vth_M1 ≈ 6.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 6.5 = 0.5, and the threshold voltage change ΔVth_M1 of input transistor M1 is -1; in the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 5.59664, VN1 = Vsen - Vth_M1 ≈ 5.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 5.5 = 1.5, and the input... The threshold voltage change of transistor M1, ΔVth_M1 = 0; in the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 4.60291, VN1 = Vsen - Vth_M1 ≈ 4.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 4.5 = 2.5, and the threshold voltage change of input transistor M1, ΔVth_M1 = 1; in the third stage, the ADC detects the voltage value of the first node N1, VN1 = Vsensing = 3.60909, VN1 = Vsen - Vth_M1 ≈ 3.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 3.5 = 3.5. The change in the threshold voltage of input transistor M1, ΔVth_M1 = 2; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 2.61521, VN1 = Vsen - Vth_M1 ≈ 2.5, then the threshold voltage of input transistor M1, Vth_M1 = 7 - 2.5 = 4.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = 3; In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 1.62125, Since VN1 = Vsen - Vth_M1 ≈ 1.5, the threshold voltage of input transistor M1, Vth_M1 = 7 - 1.5 = 5.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = 4. In the third stage, the analog-to-digital converter (ADC) detects the voltage value of the first node N1, VN1 = Vsensing = 0.62721, VN1 = Vsen - Vth_M1 ≈ 0.5. Therefore, the threshold voltage of input transistor M1, Vth_M1 = 7 - 0.5 = 6.5, and the change in the threshold voltage of input transistor M1, ΔVth_M1 = 5.

[0250] For example, the first reset transistor M2 can be detected by the cooperation of the second detection unit 302 and the first detection unit 301; or it can be detected by the cooperation of the second detection unit 302 and the third detection unit 303. The specific detection process can be referred to the above content, and will not be repeated here.

[0251] For example, the second reset transistor M3 can be detected by the cooperation of the third detection unit 303 and the first detection unit 301; or by the cooperation of the third detection unit 303 and the second detection unit 302. The specific detection process can be inferred by referring to the above content, and will not be elaborated here.

[0252] For example, when only the threshold voltage of the input transistor M1 needs to be detected, the circuit can be simplified appropriately, such as by deleting the third detection unit 303 or the second detection unit 302; when only the threshold voltage of the first reset transistor M2 needs to be detected, the circuit can be simplified appropriately, such as by deleting the third detection unit 303 or the first detection unit 301; when only the threshold voltage of the second reset transistor M3 needs to be detected, the circuit can be simplified appropriately, such as by deleting the second detection unit 302 or the first detection unit 301; thereby reducing the number of components used and lowering costs.

[0253] For example, to minimize the number of signals, the signals on the signal lines electrically connected to the first electrode of the input transistor of the first detection unit, the signal lines electrically connected to the first electrode of the first reset transistor of the second detection unit, and the signal lines electrically connected to the first electrode of the second reset transistor of the third detection unit are global signals, which can be shared by all shift register units. Therefore, when it is necessary to detect the threshold voltage of transistors in multiple shift register units, they need to be detected one by one. Furthermore, since it is necessary to read the voltage value of the first node N1, the first node N1 of the shift register unit to be detected (e.g., SR2 in Figure 16) needs to be connected to the external detection unit via signal traces, and the first reset control signal terminal RSTC1 and the input signal terminal IN need to be brought out via signal traces. This will inevitably increase the capacitor and resistor load; therefore, the size of the second output transistor M7 can be appropriately increased to mitigate the impact of the capacitor and resistor load.

[0254] It should be noted that the above detection method is also applicable to other shift register units, such as 18T1C, 19T1C, 10T1C, 8T1C, 17T1C, 14T1C, 11T1C, etc., without specific limitations. Furthermore, the voltage values ​​at each signal terminal are not unique during the detection process, as long as the switching states of the relevant transistors remain correct. Also, the voltage values ​​at the fixed voltage signal terminals are not specifically limited during the detection process and can be set according to requirements.

[0255] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0256] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, wherein the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0257] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, and the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0258] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to perform a series of operational steps on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0259] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0260] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0261] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A shift register unit, wherein, include: A first control circuit, electrically connected to a first node, is configured to provide a reference signal to the first node in response to a signal at a control signal terminal. The output circuit, electrically connected to the first node, is configured to provide a clock signal to the output signal and the cascaded signal in response to a signal on the first node. A reset circuit, electrically connected to the output circuit, is configured to provide a signal from the first reference voltage signal terminal to the output signal terminal in response to a signal from the reset signal terminal. The second control circuit, electrically connected to the second node, is configured to control the signal on the second node in response to the input signal terminal, the first power supply terminal, and the signal on the first node. The third control circuit, electrically connected to the third node, is configured to control the signal on the third node in response to the input signal terminal, the second power supply terminal, and the signal on the first node. A fourth control circuit, electrically connected to the first node, the second node, and the third node, is configured to provide a signal from the second reference voltage signal terminal to the first node in response to signals on the second node and the third node. The fifth control circuit, electrically connected to the second node and the third node, is configured to, in response to signals on the second node and the third node, provide a signal from the first reference voltage signal terminal to the output signal terminal and a signal from the second reference voltage signal terminal to the cascaded signal terminal.

2. The shift register unit as described in claim 1, wherein, The first control circuit includes: an input transistor; the control signal terminal includes an input control signal terminal; and the reference signal terminal includes a first reference signal terminal. The gate of the input transistor is electrically connected to the input control signal terminal, the first terminal of the input transistor is electrically connected to the first reference signal terminal, and the second terminal of the input transistor is electrically connected to the first node.

3. The shift register unit as described in claim 2, wherein, The first control circuit further includes: a first reset transistor; the control signal terminal further includes a first reset control signal terminal; the reference signal terminal further includes a second reference signal terminal; The gate of the first reset transistor is electrically connected to the first reset control signal terminal, the first terminal of the first reset transistor is electrically connected to the second reference signal terminal, and the second terminal of the first reset transistor is electrically connected to the first node.

4. The shift register unit as described in claim 3, wherein, The first control circuit further includes: a second reset transistor; the control signal terminal further includes a second reset control signal terminal; the reference signal terminal further includes a third reference signal terminal; The gate of the second reset transistor is electrically connected to the second reset control signal terminal, the first terminal of the second reset transistor is electrically connected to the third reference signal terminal, and the second terminal of the second reset transistor is electrically connected to the first node.

5. The shift register unit as described in any one of claims 1-4, wherein, The fourth control circuit includes: a first control transistor and a second control transistor; The gate of the first control transistor is electrically connected to the second node, the first terminal of the first control transistor is electrically connected to the first node, and the second terminal of the first control transistor is electrically connected to the second reference voltage signal terminal. The gate of the second control transistor is electrically connected to the third node, the first terminal of the second control transistor is electrically connected to the first node, and the second terminal of the second control transistor is electrically connected to the second reference voltage signal terminal.

6. The shift register unit as described in claim 5, wherein, The gates of the first control transistor, the second control transistor, the input transistor, the first reset transistor, and the second reset transistor each have a first gate and a second gate. The first control transistor, the second control transistor, the input transistor, the first reset transistor, and the second reset transistor are all electrically connected to the same fixed voltage signal terminal. Alternatively, the second gates of the first control transistor, the second control transistor, the input transistor, the first reset transistor, and the second reset transistor are electrically connected to different fixed voltage signal terminals.

7. The shift register unit as described in any one of claims 1-6, wherein, The output circuit includes: a first output transistor, a second output transistor, and a first capacitor; The gate of the first output transistor is electrically connected to the first node, the first terminal of the first output transistor is electrically connected to the clock signal terminal, and the second terminal of the first output transistor is electrically connected to the output signal terminal. The gate of the second output transistor is electrically connected to the first node, the first terminal of the second output transistor is electrically connected to the clock signal terminal, and the second terminal of the second output transistor is electrically connected to the cascaded signal terminal. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the output signal terminal.

8. The shift register unit as described in any one of claims 1-7, wherein, The reset circuit includes: a third reset transistor; The gate of the third reset transistor is electrically connected to the reset signal terminal, the first terminal of the third reset transistor is electrically connected to the first reference voltage signal terminal, and the second terminal of the third reset transistor is electrically connected to the output signal terminal.

9. The shift register unit as described in any one of claims 1-8, wherein, The second control circuit includes: a third control transistor, a fourth control transistor, and a fifth control transistor; The gate of the third control transistor is electrically connected to the first power supply terminal, the first electrode of the third control transistor is electrically connected to the first power supply terminal, and the second electrode of the third control transistor is electrically connected to the second node. The gate of the fourth control transistor is electrically connected to the first node, the first terminal of the fourth control transistor is electrically connected to the second node, and the second terminal of the fourth control transistor is electrically connected to the third reference voltage signal terminal. The gate of the fifth control transistor is electrically connected to the input signal terminal, the first terminal of the fifth control transistor is electrically connected to the second node, and the second terminal of the fifth control transistor is electrically connected to the third reference voltage signal terminal.

10. The shift register unit as described in any one of claims 1-9, wherein, The third control circuit includes: a sixth control transistor, a seventh control transistor, and an eighth control transistor; The gate of the sixth control transistor is electrically connected to the second power supply terminal, the first terminal of the sixth control transistor is electrically connected to the second power supply terminal, and the second terminal of the sixth control transistor is electrically connected to the third node. The gate of the seventh control transistor is electrically connected to the first node, the first terminal of the seventh control transistor is electrically connected to the third node, and the second terminal of the seventh control transistor is electrically connected to the third reference voltage signal terminal. The gate of the eighth control transistor is electrically connected to the input signal terminal, the first terminal of the eighth control transistor is electrically connected to the third node, and the second terminal of the eighth control transistor is electrically connected to the third reference voltage signal terminal.

11. The shift register unit as described in any one of claims 1-9, wherein, The fifth control circuit includes: a ninth control transistor, a tenth control transistor, an eleventh control transistor, and a twelfth control transistor; The gate of the ninth control transistor is electrically connected to the second node, the first terminal of the ninth control transistor is electrically connected to the cascaded signal terminal, and the second terminal of the ninth control transistor is electrically connected to the second reference voltage signal terminal. The gate of the tenth control transistor is electrically connected to the third node, the first terminal of the tenth control transistor is electrically connected to the cascaded signal terminal, and the second terminal of the tenth control transistor is electrically connected to the second reference voltage signal terminal. The gate of the eleventh control transistor is electrically connected to the second node, the first terminal of the eleventh control transistor is electrically connected to the output signal terminal, and the second terminal of the eleventh control transistor is electrically connected to the first reference voltage signal terminal. The gate of the twelfth control transistor is electrically connected to the third node, the first terminal of the twelfth control transistor is electrically connected to the output signal terminal, and the second terminal of the twelfth control transistor is electrically connected to the first reference voltage signal terminal.

12. The shift register unit as described in any one of claims 2-9, wherein, The transistors in the shift register unit include metal-oxide transistors.

13. A display device, wherein, include: Multiple shift register units as described in any one of claims 1-12 and at least one detection unit; The detection unit is electrically connected to the shift register unit and is configured to provide the initialization signal terminal to the first node in the shift register unit, and to detect the voltage value of the signal on the first node. Based on the voltage value of the control signal terminal in the shift register unit and the voltage value of the signal on the first node, the threshold voltage of the transistor in the shift register unit is obtained.

14. The display device as claimed in claim 13, wherein, The detection unit includes: a first switch, a second switch, and an analog-to-digital converter; The first end of the first switch is electrically connected to the first node, and the second end of the first switch is electrically connected to the initialization signal terminal; The first end of the second switch is electrically connected to the first node, and the second end of the second switch is electrically connected to the analog-to-digital converter.

15. The display device as claimed in claim 13, wherein, The detection unit includes: a first detection unit electrically connected to the first terminal of the input transistor, configured to connect the first terminal of the input transistor to the first reference signal terminal, or to connect the first terminal of the input transistor to the initialization signal terminal.

16. The display device as claimed in claim 15, wherein, The first detection unit includes: a third switch, a fourth switch, a fifth switch, and a first analog-to-digital converter; The first terminal of the third switch is electrically connected to the first electrode of the input transistor, and the second terminal of the third switch is electrically connected to the first reference signal terminal. The first terminal of the fourth switch is electrically connected to the first electrode of the input transistor, and the second terminal of the fourth switch is electrically connected to the initialization signal terminal. The first terminal of the fifth switch is electrically connected to the first electrode of the input transistor, and the second terminal of the fifth switch is electrically connected to the first analog-to-digital converter.

17. The display device as claimed in claim 15 or 16, wherein, The detection unit further includes: a second detection unit electrically connected to the first terminal of the first reset transistor, configured to connect the first terminal of the first reset transistor to the second reference signal terminal, or connect the first terminal of the first reset transistor to the initialization signal terminal, or connect the first terminal of the first reset transistor to the first reference signal terminal.

18. The display device as claimed in claim 17, wherein, The second detection unit includes: a sixth switch, a seventh switch, an eighth switch, a ninth switch, and a second analog-to-digital converter; The first terminal of the sixth switch is electrically connected to the first electrode of the first reset transistor, and the second terminal of the sixth switch is electrically connected to the second reference signal terminal. The first terminal of the seventh switch is electrically connected to the first electrode of the first reset transistor, and the second terminal of the seventh switch is electrically connected to the initialization signal terminal. The first terminal of the eighth switch is electrically connected to the first electrode of the first reset transistor, and the second terminal of the eighth switch is electrically connected to the second analog-to-digital converter. The first terminal of the ninth switch is electrically connected to the first electrode of the first reset transistor, and the second terminal of the ninth switch is electrically connected to the first reference signal terminal.

19. The display device according to any one of claims 15-18, wherein, The detection unit further includes: a third detection unit, electrically connected to the first terminal of the second reset transistor, configured to connect the first terminal of the second reset transistor to the third reference signal terminal, or connect the first terminal of the second reset transistor to the initialization signal terminal, or connect the first terminal of the second reset transistor to the first reference signal terminal.

20. The display device as claimed in claim 19, wherein, The third detection unit includes: a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a third analog-to-digital converter; The first terminal of the tenth switch is electrically connected to the first electrode of the second reset transistor, and the second terminal of the tenth switch is electrically connected to the third reference signal terminal. The first terminal of the eleventh switch is electrically connected to the first electrode of the second reset transistor, and the second terminal of the eleventh switch is electrically connected to the initialization signal terminal. The first terminal of the twelfth switch is electrically connected to the first electrode of the second reset transistor, and the second terminal of the twelfth switch is electrically connected to the third analog-to-digital converter; The first terminal of the thirteenth switch is electrically connected to the first electrode of the second reset transistor, and the second terminal of the thirteenth switch is electrically connected to the first reference signal terminal.

21. A method for detecting a display device as described in any one of claims 13-20, wherein, include: In the first stage, the detection unit provides the initialization signal to the first node in the shift register unit; In the second stage, the first control circuit in the shift register responds to the signal at the control signal terminal and provides the signal at the reference signal terminal to the first node. In the third stage, the detection unit detects the voltage value of the signal on the first node, and obtains the threshold voltage of the transistor in the shift register unit based on the voltage value of the signal at the control signal terminal in the shift register unit and the voltage value of the signal on the first node.

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