Display substrate and wearable device

Abstract

A display substrate and a wearable device, the display substrate comprising: a substrate and a plurality of sub-pixels disposed on the substrate, at least one sub-pixel comprising: a pixel driving circuit, the pixel driving circuit comprising: at least one transistor, the at least one transistor comprising: a driving transistor and a compensation transistor, a first pole of the compensation transistor being connected with a control pole of the driving transistor and a first area (21-1) of an active pattern of the compensation transistor respectively, a second pole of the compensation transistor being connected with a second pole of the driving transistor and a second area (21-2) of the active pattern of the compensation transistor respectively; an area of the first area (21-1) of the active pattern of the compensation transistor in the pixel driving circuit of the at least one sub-pixel is greater than an area of the second area (21-2) of the active pattern of the compensation transistor, and areas of the first area (21-1) of the active pattern of the compensation transistor in pixel driving circuits of at least two sub-pixels are different.

Description

Display substrates and wearable devices Technical Field

[0001] This article relates to the field of display technology, specifically to a display substrate and a wearable device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a wearable device.

[0005] In a first aspect, this disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, at least one sub-pixel comprising: a pixel driving circuit, the pixel driving circuit comprising: at least one transistor, the at least one transistor comprising: a driving transistor and a compensation transistor, the transistor comprising: an active pattern, a control electrode, a first electrode and a second electrode, the active pattern further comprising: a first region and a second region, the first electrode of the compensation transistor being connected to the control electrode of the driving transistor and the first region of the active pattern of the compensation transistor respectively, and the second electrode of the compensation transistor being connected to the second electrode of the driving transistor and the second region of the active pattern of the compensation transistor respectively;

[0006] The area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of at least one sub-pixel is greater than the area of ​​the second region of the active pattern of the compensation transistor, and the areas of the first regions of the active patterns of the compensation transistors in the pixel driving circuits of at least two sub-pixels are different.

[0007] In an exemplary embodiment, the sub-pixel includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the first sub-pixel emits red light, the second sub-pixel emits green light, and the third sub-pixel emits blue light;

[0008] The area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of at least one of the first and second sub-pixels is greater than the area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of the third sub-pixel.

[0009] In an exemplary embodiment, it further includes: a plurality of first scan signal lines disposed on the substrate, and the at least one transistor further includes: a write transistor, wherein the control electrode of the write transistor is electrically connected to at least one of the first scan signal lines;

[0010] The first scan signal line includes: a main signal line and a plurality of gate blocks, the plurality of gate blocks being located on the same side of the main signal line and connected to the main signal line, and at least a portion of the main signal line extending along a first direction;

[0011] The first region of the active pattern of the compensation transistor in the pixel driving circuit of the at least one sub-pixel at least partially overlaps with the orthographic projection of at least one gate block of at least one first scan signal line on the substrate.

[0012] In an exemplary embodiment, the overlap area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of at least one of the first and second sub-pixels with at least one gate block of at least one first scan signal line is greater than the overlap area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of the third sub-pixel with at least one gate block of at least one first scan signal line.

[0013] In an exemplary embodiment, it further includes: a plurality of second scan signal lines disposed on the substrate, wherein the control electrode of the compensation transistor is connected to at least one of the second scan signal lines;

[0014] The second scan signal line includes: a first scan section and a second scan section, wherein the second scan section is located on the side of the first scan section away from the substrate and is connected to the first scan section;

[0015] The orthographic projection of the first scanning unit on the substrate and the orthographic projection of the second scanning unit on the substrate at least partially overlap.

[0016] In an exemplary embodiment, the orthographic projection of the second scanning unit onto the substrate is within the range of the orthographic projection of the first scanning unit onto the substrate.

[0017] In an exemplary embodiment, it further includes: a plurality of first power lines disposed on the substrate, and the at least one transistor further includes: a light-emitting transistor, the first electrode of the light-emitting transistor being connected to at least one first power line, and the second electrode of the light-emitting transistor being connected to the first electrode of the driving transistor;

[0018] The first electrode of the light-emitting transistor includes: an electrode body portion, a first extension portion, a second extension portion, and a third extension portion, wherein the first extension portion, the second extension portion, and the third extension portion are respectively connected to the electrode body portion, and the first extension portion and at least one of the second extension portion and the third extension portion are located on different sides of the electrode body portion.

[0019] The electrode body portion extends at least partially along a second direction, at least one of the first extension portion and the second extension portion extends at least partially along a second direction, and the third extension portion extends at least partially along a first direction;

[0020] The minimum width of at least one of the electrode body and the third extension in the first direction is greater than the maximum width of at least one of the first extension and the second extension in the first direction, and the width of the first extension in the first direction is greater than the width of the second extension in the first direction.

[0021] In an exemplary embodiment, the system further includes: multiple light-emitting signal lines, multiple first scan signal lines, and multiple data signal lines disposed on a substrate; at least one transistor further includes: a write transistor; the control electrode of the light-emitting transistor is connected to at least one light-emitting signal line; the control electrode of the write transistor is connected to at least one first scan signal line; the first electrode of the write transistor is connected to at least one data signal line; the pixel driving circuit further includes: a capacitor; the capacitor includes: a first electrode plate and a second electrode plate; the second electrode plate is provided with a via exposing the first electrode plate; the first electrode of the light-emitting transistor in the pixel driving circuit of at least one sub-pixel is connected to the second electrode plate of the capacitor.

[0022] For a pixel driving circuit of at least one sub-pixel, the orthographic projection of the electrode body and the third extension on the substrate at least partially overlaps with the orthographic projection of the capacitor on the substrate, the orthographic projection of the first extension on the substrate at least partially overlaps with the orthographic projection of the light emission signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the second extension on the substrate at least partially overlaps with the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate.

[0023] A first straight line passes through the via, the first straight line being a straight line extending along a second direction and passing through the third extension.

[0024] In an exemplary embodiment, the orthographic projection of the second extension onto the substrate lies between the orthographic projection of the first electrode of the compensation transistor onto the substrate and the orthographic projection of the first electrode of the write transistor onto the substrate.

[0025] In an exemplary embodiment, it further includes: a plurality of capacitor connection portions disposed on the substrate, at least one capacitor connection portion extending at least partially along a first direction;

[0026] The second plates of capacitors in two adjacent pixel driving circuits arranged along the first direction are connected by at least one capacitor connection part.

[0027] The first poles of the light-emitting transistors in two adjacent pixel driving circuits arranged along the first direction are spaced apart.

[0028] The capacitor connection part is disposed on the same layer as the second plate of the capacitor.

[0029] In an exemplary embodiment, it further includes: a plurality of electrode connection portions disposed on the substrate, at least one electrode connection portion extending at least partially along a first direction;

[0030] The second plates of capacitors in two adjacent pixel driving circuits arranged along the first direction are spaced apart.

[0031] The first electrodes of the light-emitting transistors in two adjacent pixel driving circuits arranged along the first direction are connected by at least one electrode connection portion.

[0032] The electrode connection portion is disposed on the same layer as the first electrode of the light-emitting transistor.

[0033] In an exemplary embodiment, the orthographic projection of at least one electrode connection on the substrate at least partially overlaps with the orthographic projection of a capacitor in at least one pixel driving circuit on the substrate.

[0034] In an exemplary embodiment, at least one electrode connection portion is connected to the electrode body portion of the first electrode of the light-emitting transistor in one of the adjacent pixel driving circuits and the third extension portion of the first electrode of the light-emitting transistor in another adjacent pixel driving circuit.

[0035] In an exemplary embodiment, the system further includes: a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of third initial signal lines, and a plurality of light emission signal lines disposed on the substrate; and a pixel driving circuit for at least one sub-pixel is connected to the first scan signal lines, the second scan signal lines, the first reset signal lines, the second reset signal lines, the first initial signal lines, the second initial signal lines, the third initial signal lines, and the light emission signal lines, respectively.

[0036] At least a portion of at least one of the plurality of first scan signal lines, the plurality of second scan signal lines, the plurality of first reset signal lines, the plurality of second reset signal lines, the plurality of first initial signal lines, the plurality of second initial signal lines, the plurality of third initial signal lines, and the plurality of light emission signal lines extends along a first direction;

[0037] The orthographic projections of at least one pixel driving circuit connected to the second initial signal line, the second reset signal line, the light emission signal line, the first scan signal line, the second scan signal line, the first reset signal line, and the first initial signal line on the substrate are arranged sequentially along the second direction.

[0038] The orthographic projection of the third initial signal line connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line on the substrate.

[0039] In an exemplary embodiment, it further includes: multiple first power lines and multiple data signal lines, and a pixel driving circuit for at least one sub-pixel is connected to the first power lines and the data signal lines respectively. The pixel driving circuit further includes: a capacitor.

[0040] The plurality of first power lines and the plurality of data signal lines are arranged alternately, and at least a portion of at least one of the plurality of first power lines and the plurality of data signal lines extends along the second direction;

[0041] At least one first power line includes: a power block and a power connection portion, wherein the power block and the power connection portion extend at least partially along a second direction, and the length of the power block along the first direction is greater than the length of the power connection portion along the first direction;

[0042] The orthographic projection of at least one power block in at least one first power line onto the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor and compensation transistor in at least one pixel driving circuit onto the substrate.

[0043] In an exemplary embodiment, the orthographic projection of the first pole of the compensation transistor in at least one pixel driving circuit onto the substrate lies within the range of the orthographic projection of at least one power block in at least one first power line onto the substrate.

[0044] In an exemplary embodiment, the power block in the first power line to which the pixel driving circuit of the first sub-pixel is connected includes: a plurality of first power blocks and a plurality of second power blocks, and the power connection portion in the first power line to which the pixel driving circuit of the first sub-pixel is connected includes: a plurality of first power connection portions.

[0045] One end of at least one second power block is connected to at least one first power block via at least one first power connection part, and the other end of at least one second power block is connected to at least one first power block. The length of the second power block along the second direction is greater than the length of the first power block along the second direction.

[0046] The orthographic projection of the first power block on the substrate at least partially overlaps with the orthographic projections of the second reset signal line, the third initial signal line, and the first initial signal line on the substrate.

[0047] The orthographic projection of the second power block on the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor and the second transistor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first scan signal line, the second scan signal line, the first reset signal line and the second initial signal line on the substrate.

[0048] The orthographic projection of the first power connection portion on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of the light-emitting signal line on the substrate.

[0049] In an exemplary embodiment, the power block of the first power line to which the pixel driving circuit of the second sub-pixel is connected includes: a plurality of third power blocks, and the power connection part of the first power line to which the pixel driving circuit of the second sub-pixel is connected includes: a plurality of second power connection parts. The plurality of third power blocks and the plurality of second power connection parts are arranged alternately and connected to each other.

[0050] The orthographic projection of the third power block on the substrate also at least partially overlaps with the orthographic projection of at least one of the first scan signal line, the second scan signal line, the first reset signal line, and the second initial signal line on the substrate.

[0051] The orthographic projection of the second power connection portion on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first initial signal line, the second reset signal line, the third initial signal line, and the light emission signal line on the substrate.

[0052] In an exemplary embodiment, the power block in the first power line to which the pixel driving circuit of the third sub-pixel is connected includes a plurality of fourth power blocks, and the power connection part in the first power line to which the pixel driving circuit of the third sub-pixel is connected includes a plurality of third power connection parts. The plurality of fourth power blocks and the plurality of third power connection parts are arranged alternately and connected to each other.

[0053] The orthographic projection of the fourth power block on the substrate also at least partially overlaps with the orthographic projection of at least one of the first and second scan signal lines on the substrate.

[0054] The orthographic projection of the third power connection portion on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first initial signal line, the second initial signal line, the first reset signal line, the second reset signal line, the third initial signal line, and the light emission signal line on the substrate.

[0055] In an exemplary embodiment, the overlapping area of ​​the orthographic projection of the fourth power block on the substrate and the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate is greater than the overlapping area of ​​the orthographic projection of the second power block and at least one of the third power blocks on the substrate and the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate.

[0056] In an exemplary embodiment, at least one sub-pixel further includes: a light-emitting device and a pixel definition layer, wherein the light-emitting device includes: an anode, and the pixel definition layer includes: a first pixel opening, a second pixel opening, and a third pixel opening;

[0057] The area of ​​the anode of the light-emitting device of the first sub-pixel is smaller than the area of ​​the anode of the light-emitting device of the second sub-pixel, and the area of ​​the anode of the light-emitting device of the second sub-pixel is smaller than the area of ​​the anode of the light-emitting device of the third sub-pixel.

[0058] The length of at least one anode of the light-emitting device of the first sub-pixel and the light-emitting device of the second sub-pixel along the second direction is less than the length of the anode of the light-emitting device of the third sub-pixel along the second direction;

[0059] The first pixel opening exposes the anode of the light-emitting device of the first sub-pixel, the second pixel opening exposes the anode of the light-emitting device of the second sub-pixel, and the third pixel opening exposes the anode of the light-emitting device of the third sub-pixel.

[0060] In an exemplary embodiment, the orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the first power block in the first power line connected to the pixel driving circuit of at least one first sub-pixel on the substrate.

[0061] In an exemplary embodiment, the orthographic projection of the first power block in the first power line to which the pixel driving circuit of at least one first sub-pixel is connected on the substrate is located within the range of the orthographic projection of the at least one first pixel opening on the substrate.

[0062] In an exemplary embodiment, the orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projection of the second power block in the first power line connected to the pixel driving circuit of at least one first sub-pixel on the substrate, and at least partially overlaps with the orthographic projection of at least one data signal line on the substrate.

[0063] In an exemplary embodiment, the orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with the orthographic projection of at least one structure in the third power block and the second power connection portion of the first power line connected to at least one data signal line and the pixel driving circuit of at least one second sub-pixel, and the orthographic projection of the fourth power block connected to the pixel driving circuit of at least one third sub-pixel on the substrate.

[0064] In an exemplary embodiment, portions of the first power line connected to the pixel driving circuit of at least one second sub-pixel overlapping with at least one third pixel opening and portions of the first power line connected to the pixel driving circuit of at least one third sub-pixel overlapping with at least one third pixel opening are at least partially symmetrical with respect to a straight line extending along a second direction.

[0065] In an exemplary embodiment, at least one transistor includes at least one P-type transistor and at least one N-type transistor, the capacitor includes a first plate and a second plate, the at least one N-type transistor includes a first control electrode and a second control electrode, and the second scan signal line includes a first scan section and a second scan section.

[0066] The display substrate further includes: a circuit structure layer disposed on the substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0067] The first semiconductor layer includes at least: an active pattern of at least one P-type transistor of at least one pixel driving circuit;

[0068] The first conductive layer includes at least: multiple first scan signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple light emission signal lines, and the control electrode of at least one P-type transistor located in at least one pixel driving circuit and the first plate of a capacitor;

[0069] The second conductive layer includes at least: a first scanning section consisting of a plurality of first initial signal lines, a plurality of second scanning signal lines, a second plate of a capacitor located in at least one pixel driving circuit, and a first control electrode of at least one N-type transistor;

[0070] The second semiconductor layer includes at least: an active pattern of at least one N-type transistor located in at least one pixel driving circuit;

[0071] The third conductive layer includes at least: a second scanning section with multiple second scanning signal lines, multiple third initial signal lines, and a second control electrode of at least one N-type transistor located in at least one pixel driving circuit;

[0072] The fourth conductive layer includes at least: multiple second initial signal lines and a first and second electrode of at least one transistor located in at least one pixel driving circuit;

[0073] The fifth conductive layer includes at least: multiple data signal lines and multiple first power lines.

[0074] Secondly, this disclosure also provides a wearable device, including: the aforementioned display substrate.

[0075] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0076] Overview of the attached figures

[0077] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0078] Figure 1 is a schematic diagram of a display device;

[0079] Figure 2 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0080] Figure 3 is a timing diagram of the pixel driving circuit provided in Figure 2;

[0081] Figure 4 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0082] Figure 5 is a partial schematic diagram of the pixel driving circuit in the display substrate provided in Figure 4;

[0083] Figure 6 is a second schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0084] Figure 7 is a partial schematic diagram of the pixel driving circuit in the display substrate provided in Figure 6;

[0085] Figure 8 is a schematic diagram of some film layers of the display substrate provided in Figure 4;

[0086] Figure 9 is a schematic diagram of some film layers of the display substrate provided in Figure 6;

[0087] Figure 10 is a schematic diagram of some film layers of the display substrate provided in Figures 4 and 6;

[0088] Figure 11 is a schematic diagram of one structure of the second scan signal line;

[0089] Figure 12 is a schematic diagram of part of the film layer in the display substrate provided in Figure 4;

[0090] Figure 13 is a schematic diagram of a portion of the film layers in the display substrate shown in Figure 6;

[0091] Figure 14 is a schematic diagram of some film layers in the display substrate provided in Figures 4 and 6;

[0092] Figure 15 is a schematic diagram of some film layers in the display substrate provided in Figures 4 and 6;

[0093] Figure 16 is a schematic diagram of the first semiconductor layer pattern in Figures 4 and 6;

[0094] Figure 17 is a schematic diagram of the first conductive layer pattern in Figures 4 and 6;

[0095] Figure 18 is a schematic diagram after the first conductive layer pattern is formed in Figures 4 and 6;

[0096] Figure 19 is a schematic diagram of the second conductive layer pattern in Figure 4;

[0097] Figure 20 is a schematic diagram after the second conductive layer pattern is formed in Figure 4;

[0098] Figure 21 is a schematic diagram of the second conductive layer pattern in Figure 6;

[0099] Figure 22 is a schematic diagram after the second conductive layer pattern is formed in Figure 6;

[0100] Figure 23 is a schematic diagram of the second semiconductor layer pattern in Figures 4 and 6;

[0101] Figure 24 is a schematic diagram after the second semiconductor layer pattern is formed in Figure 4;

[0102] Figure 25 is a schematic diagram after the second semiconductor layer pattern is formed in Figure 6;

[0103] Figure 26 is a schematic diagram of the third conductive layer pattern in Figures 4 and 6;

[0104] Figure 27 is a schematic diagram after the formation of the third conductive layer pattern in Figure 4;

[0105] Figure 28 is a schematic diagram after the formation of the third conductive layer pattern in Figure 6;

[0106] Figure 29 is a schematic diagram after the fifth insulating layer pattern is formed in Figure 4;

[0107] Figure 30 is a schematic diagram after the fifth insulating layer pattern is formed in Figure 6;

[0108] Figure 31 is a schematic diagram of the fourth conductive layer pattern in Figure 4;

[0109] Figure 32 is a schematic diagram after the fourth conductive layer pattern is formed in Figure 4;

[0110] Figure 33 is a schematic diagram of the fourth conductive layer pattern in Figure 6;

[0111] Figure 34 is a schematic diagram after the fourth conductive layer pattern is formed in Figure 6;

[0112] Figure 35 is a schematic diagram after the first planarization layer pattern in Figure 4 is formed;

[0113] Figure 36 is a schematic diagram after the first planarization layer pattern in Figure 6 is formed;

[0114] Figure 37 is a schematic diagram of the fifth conductive layer pattern in Figures 4 and 6;

[0115] Figure 38 is a schematic diagram after the fifth conductive layer pattern is formed in Figure 4;

[0116] Figure 39 is a schematic diagram after the fifth conductive layer pattern is formed in Figure 6;

[0117] Figure 40 is a schematic diagram after the second flattening layer pattern in Figure 4 is formed;

[0118] Figure 41 is a schematic diagram of the second flattening layer pattern formed in Figure 6;

[0119] Figure 42 is a schematic diagram of the sixth conductive layer pattern in Figures 4 and 6;

[0120] Figure 43 is a schematic diagram after the formation of the sixth conductive layer pattern in Figure 4;

[0121] Figure 44 is a schematic diagram after the formation of the sixth conductive layer pattern in Figure 6;

[0122] Figure 45 is a schematic diagram after the pixel definition layer pattern is formed in Figure 4;

[0123] Figure 46 is a schematic diagram after the pixel definition layer pattern in Figure 6 is formed.

[0124] Detailed Explanation

[0125] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0126] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0127] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0128] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0129] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0130] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0131] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0132] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0133] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0134] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0135] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a display substrate, which may include a timing controller, a source driving circuit, a gate driving circuit, and a pixel array. The timing controller is connected to both the source driving circuit and the gate driving circuit. The source driving circuit is connected to multiple data lines (D1 to Dn), and the gate driving circuit is connected to multiple gate lines (G1 to Gm). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the gate lines and data lines respectively.

[0136] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the source drive circuit to the source drive circuit, and can provide clock signals, start signals, etc. of specifications suitable for the gate drive circuit to the gate drive circuit.

[0137] In an exemplary embodiment, the source driver circuit can use grayscale values ​​and control signals received from a timing controller to generate data voltages that will be provided to data lines D1, D2, D3, ..., Dn. For example, the source driver circuit can use a clock signal to sample grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number.

[0138] In an exemplary embodiment, the gate drive circuit can generate scan signals to be provided to gate lines G1, G2, G3, ..., Gm by receiving clock signals, start signals, etc., from a timing controller. For example, the gate drive circuit can sequentially provide drive signals with on-level pulses to gate lines G1 through Gm. For example, the gate drive circuit can be configured as a shift register and can generate drive signals by sequentially transmitting start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0139] In an exemplary embodiment, the display substrate may include a plurality of pixel units arranged in a matrix. At least one of the plurality of pixel units includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. Each of the first, second, and third sub-pixels includes a pixel driving circuit and a light-emitting device. The pixel driving circuits of the first, second, and third sub-pixels are respectively connected to a gate line and a data line. The pixel driving circuits are configured to receive the data voltage transmitted by the data line and output a corresponding current to the light-emitting device under the control of the gate line and the data line. The light-emitting devices of the first, second, and third sub-pixels are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0140] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel may be a green sub-pixel (G) that emits green light.

[0141] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0142] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged in a horizontal, vertical, or triangular manner, etc., and this disclosure does not limit the arrangement.

[0143] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0144] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, T refers to a transistor in the pixel driving circuit, C refers to a capacitor in the pixel driving circuit, the number before T refers to the number of transistors in the pixel driving circuit, and the number before C refers to the number of capacitors in the pixel driving circuit.

[0145] Figure 2 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 2, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8), 1 capacitor C, and the pixel driving circuit may be connected to 10 signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, first reset signal line Reset1, second reset signal line Reset2, light emission signal line EM, first initial signal line INITL1, second initial signal line INITL2, third initial signal line INITL3, and first power supply line VDD).

[0146] In an exemplary embodiment, capacitor C includes a first plate C1 and a second plate C2. The first plate C1 of capacitor C is electrically connected to a first node N1, and the second plate C2 of capacitor C is electrically connected to a first power line VDD.

[0147] In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is connected to the first initial signal line INITL1, and the second electrode of the first transistor T1 is connected to either the first node N1 or the third node N3. Figure 2 illustrates this using the example of the second electrode of the first transistor T1 being connected to the third node N3. The first transistor T1 can be referred to as the first initial transistor. When a conduction level scan signal is applied to the first reset signal line Reset1, the first transistor T1 transmits the initial signal of the first initial signal line INITL1 to either the first node N1 or the third node N3 to initialize the charge of either the first node N1 or the third node N3.

[0148] In an exemplary embodiment, the control electrode of the second transistor T2 is connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3. The second transistor T2 can be referred to as a compensation transistor. When a conduction-level scan signal is applied to the second scan signal line Gate2, the second transistor T2 causes the control electrode of the third transistor T3 to connect to its second electrode.

[0149] In an exemplary embodiment, the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0150] In an exemplary embodiment, the control electrode of the fourth transistor T4 is connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 can be referred to as a switching transistor, a write transistor, etc. When a conduction-level scan signal is applied to the first scan signal line Gate1, the fourth transistor T4 causes the data voltage of the data signal line Data to be input to the pixel driving circuit.

[0151] In an exemplary embodiment, the control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (which is also the first electrode of the light-emitting device L). The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line EM, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a drive current path between the first power supply line VDD and the second power supply line VSS.

[0152] In an exemplary embodiment, the control electrode of the seventh transistor T7 is connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INITL2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. The seventh transistor T7 can be referred to as the second initial transistor. When a conduction level scan signal is applied to the second reset signal line Reset2, the seventh transistor T7 transmits the initial signal of the second initial signal line INITL2 to the fourth node N4 (which is also the first electrode of the light-emitting device L), so as to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0153] In an exemplary embodiment, the control electrode of the eighth transistor T8 is connected to the second reset signal line Reset2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INITL3, and the second electrode of the eighth transistor T8 is connected to the second node N2. The eighth transistor T8 can be referred to as the third initial transistor. When a conduction level scan signal is applied to the second reset signal line Reset2, the eighth transistor T8 transmits the initial signal of the third initial signal line INITL3 to the second node N2, biasing the third transistor T3.

[0154] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0155] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0156] In an exemplary embodiment, the light-emitting device L may include a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). Exemplarily, the first electrode of the light-emitting device is electrically connected to a fourth node N4 in a pixel driving circuit, and the second electrode of the light-emitting device is electrically connected to a second power line VSS.

[0157] In an exemplary embodiment, the voltage value of at least one of the first initial signal line INITL1, the second initial signal line INITL2, and the third initial signal line INITL3 is constant, and it is a DC signal. In an exemplary embodiment, the DC signal can be one in which neither the magnitude nor the direction of the signal changes with time.

[0158] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal.

[0159] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0160] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor, the active layer of which is made of oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current.

[0161] In an exemplary embodiment, the P-type transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon, which has advantages such as high mobility and fast charging.

[0162] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0163] In an exemplary embodiment, in the pixel driving circuit provided in FIG2, the second transistor T2 can be an N-type transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be P-type transistors. The fact that the second transistor T2 is an N-type transistor can reduce the leakage current of the first node N1 and ensure the stability of the signal at the first node N1.

[0164] In an exemplary embodiment, the second transistor T2 in this disclosure is an N-type transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be P-type transistors. This realizes the integration of low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors on a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate. This allows the advantages of both to be utilized, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0165] Figure 3 is a timing diagram of the pixel driving circuit provided in Figure 2. The following describes an exemplary embodiment of this disclosure through the operation of the pixel driving circuit exemplified in Figure 2. The pixel driving circuit in Figure 2 includes eight transistors (first transistor T1 to eighth transistor T8) and one capacitor (capacitor C). The first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0166] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0167] In the first stage S1, also known as the initialization stage, the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, and the light emission signal line EM are high-level signals, while the signal of the second reset signal line Reset2 is low-level. The second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0168] When the second transistor T2 is turned on, the first node N1 and the third node N3 are also turned on. The seventh transistor T7 is also turned on. The initial signal of the second initial signal line INITL2 is written to the fourth node N4 (which is also the anode of the light-emitting device L) through the turned-on seventh transistor T7, initializing (resetting) the fourth node N4 (which is also the anode of the light-emitting device L) and clearing its internal pre-stored voltage, thus completing the initialization. When the eighth transistor T8 is turned on, the initial signal of the third initial signal line INITL3 is written to the second node N2, initializing (resetting) the second node N2 and clearing its internal pre-stored voltage, thus completing the initialization.

[0169] In the second stage S2, the signals of the first scan signal line Gate1, the second scan signal line Gate2, the second reset signal line Reset2, and the light emission signal line EM are high-level signals, while the signal of the first reset signal line Reset1 is low-level. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0170] When the first transistor T1 is turned on, the signal of the first initial signal line INITL1 is written to the third node N3, clearing the pre-stored voltage inside and initializing the third node N3. When the second transistor T2 is turned on, the signal of the third node N3 is written to the first node N1, clearing the pre-stored voltage inside and initializing the first node N1.

[0171] In the third stage (S3), the threshold compensation and data writing stage, the signals of the second scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the light emission signal line EM are high-level signals, while the signal of the first scan signal line Gate1 is low-level. The data signal line Data outputs the data signal. The second transistor T2 and the fourth transistor T4 are turned on, while the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0172] The second transistor T2 and the fourth transistor T4 are turned on. The data signal on the data signal line Data charges the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 is Vdata + Vth, where Vdata is the voltage value of the data signal and Vth is the threshold voltage of the third transistor T3.

[0173] In the fourth stage, S4, the bias stage, the signals of the first scan signal line Gate1, the first reset signal line Reset1, and the light emission signal line EM are high-level signals, while the signals of the second scan signal line Gate2 and the second reset signal line Reset2 are low-level signals. The seventh transistor T7 and the eighth transistor T8 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0174] When the seventh transistor T7 is turned on, the initial signal of the second initial signal line INITL2 is written to the fourth node N4 (which is also the anode of the light-emitting device L) through the turned-on seventh transistor T7, re-initializing (resetting) the fourth node N4 (which is also the anode of the light-emitting device L), clearing its internal pre-stored voltage, and completing the initialization. When the eighth transistor T8 is turned on, the initial signal of the third initial signal line INITL3 is written to the second node N2, causing the third transistor T3 to be in a bias state.

[0175] In the fifth stage (S5), the light-emitting stage, the signals of the first scan signal line Gate1, the first reset signal line Reset1, and the second reset signal line Reset2 are high-level signals, while the signals of the second scan signal line Gate2 and the light-emitting signal line EM are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0176] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power signal output from the first power line VDD provides a driving voltage to the fourth node N4 (which is also the first pole of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0177] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the first node N1 is Vdata + Vth, and the voltage value of the signal at the second node N2 is Vdd, where Vdd is the voltage value of the signal at the first power supply line, the driving current of the third transistor T3 is:

[0178] I = K * (Vgs - Vth) 2

[0179] =K*(Vdata+Vth-Vdd-Vth) 2

[0180] =K*(Vdata-Vdd) 2

[0181] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3.

[0182] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0183] In smaller display products (such as wearable watches), different sub-pixels use different light-emitting materials. Red and green sub-pixels use phosphorescent materials, while blue sub-pixels use fluorescent materials. This results in significant differences in the display effects of different sub-pixels, leading to uneven display and affecting the overall display quality.

[0184] Figure 4 is a schematic diagram of the structure of the display substrate provided in this embodiment of the present disclosure. Figure 5 is a partial schematic diagram of the pixel driving circuit in the display substrate provided in Figure 4. Figure 6 is a schematic diagram of the structure of the display substrate provided in this embodiment of the present disclosure. Figure 7 is a partial schematic diagram of the pixel driving circuit in the display substrate provided in Figure 6. Figure 8 is a partial schematic diagram of the film layer of the display substrate provided in Figure 4. Figure 9 is a partial schematic diagram of the film layer of the display substrate provided in Figure 6. As shown in Figures 4 to 9, the display substrate provided in this embodiment of the present disclosure includes: a substrate and a plurality of sub-pixels disposed on the substrate. At least one sub-pixel includes: a pixel driving circuit, the pixel driving circuit includes: at least one transistor (e.g., first transistor T1 to eighth transistor T8), the at least one transistor includes: a compensation transistor (second transistor T2) and a driving transistor (third transistor T3). The transistor includes: an active pattern, a control electrode, a first electrode and a second electrode, the active pattern includes: a first region and a second region. The first terminal of the compensation transistor (second transistor T2) is connected to the control terminal of the driving transistor (third transistor T3) and the first region 21-1 of the active pattern 21 of the compensation transistor (second transistor T2), respectively. The second terminal of the compensation transistor (second transistor T2) is connected to the second terminal of the driving transistor (third transistor T3) and the second region 21-2 of the active pattern 21 of the compensation transistor (second transistor T2).

[0185] As shown in Figures 8 and 9, the area of ​​the first region 21-1 of the active pattern of the compensation transistor (second transistor T2) in the pixel driving circuit of at least one sub-pixel is greater than the area of ​​the second region 21-2 of the active pattern of the compensation transistor (second transistor T2), and the areas of the first region 21-1 of the active pattern of the compensation transistor (second transistor T2) in the pixel driving circuits of at least two sub-pixels are different.

[0186] Because different sub-pixels use different luminescent materials, some sub-pixels have lower luminous efficiency and are prone to dimming, meaning that some sub-pixels have lower black-state voltages (the voltage that makes the sub-pixel dim). This disclosure addresses this by setting different areas of the first region 21-1 of the active pattern of the compensation transistor (second transistor T2) in the pixel driving circuit of at least two sub-pixels. This allows for adjustment of the black-state voltages of different sub-pixels, reducing the difference in black-state voltages between them, ensuring the brightness uniformity of the display substrate, and improving the display effect of the display substrate.

[0187] In an exemplary embodiment, as shown in Figures 4 to 9, a sub-pixel may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3, wherein the first sub-pixel P1 emits red light, the second sub-pixel P2 emits green light, and the third sub-pixel P3 emits blue light.

[0188] In an exemplary embodiment, as shown in Figures 8 and 9, the area of ​​the first region 21-1 of the active pattern of the compensation transistor in the pixel driving circuit of at least one of the first sub-pixels P1 and P2 is greater than the area of ​​the first region 21-1 of the active pattern of the compensation transistor in the pixel driving circuit of the third sub-pixel P3.

[0189] In an exemplary embodiment, as shown in Figures 8 and 9, the display substrate further includes a plurality of first scan signal lines Gate1 disposed on the substrate. The first scan signal lines Gate1 include a main signal line 10 and a plurality of gate blocks 20, the plurality of gate blocks 20 being located on the same side of the main signal line 10 and connected to the main signal line 10, and at least a portion of the main signal line 10 extending along a first direction D1.

[0190] In an exemplary embodiment, as shown in Figures 8 and 9, the first region 21-1 of the active pattern of the compensation transistor (second transistor T2) in the pixel driving circuit of at least one sub-pixel at least partially overlaps with the orthographic projection of at least one gate block 20 of at least one first scan signal line Gate1 on the substrate.

[0191] In an exemplary embodiment, as shown in Figures 8 and 9, the overlap area of ​​the first region 21-1 of the active pattern of the compensation transistor (second transistor T2) in the pixel driving circuit of at least one sub-pixel of the first sub-pixel P1 and the second sub-pixel P2 with at least one gate block 20 of at least one first scan signal line Gate1 is greater than the overlap area of ​​the first region 21-1 of the active pattern of the compensation transistor (second transistor T2) in the pixel driving circuit of the third sub-pixel P3 with at least one gate block 20 of at least one first scan signal line Gate1.

[0192] In this disclosure, because the light-emitting materials of the first and second sub-pixels are different from those of the third sub-pixel, the luminous efficiency of the third sub-pixel is lower, making it easier for it to darken; that is, the black-state voltage (the voltage that makes the sub-pixel darken) of the third sub-pixel is smaller. The larger the overlap area between the first region 21-1 of the active pattern of the compensation transistor (second transistor T2) in the pixel driving circuit of the sub-pixel and at least one gate block 20 of at least one first scan signal line Gate1, the smaller the black-state voltage of the sub-pixel, and the easier it is for the sub-pixel to darken. This disclosure reduces the black state voltage of the first and second sub-pixels by ensuring the brightness uniformity of the display substrate and improving the display effect of the display substrate through the fact that the first region 21-1 of the active pattern of the compensation transistor (second transistor T2) in the pixel driving circuit of at least one of the first sub-pixels P1 and P2 overlaps with the first gate block 20 of at least one first scan signal line Gate1, which is greater than the overlap area of ​​the first region 21-1 of the active pattern of the compensation transistor (second transistor T2) in the pixel driving circuit of the third sub-pixel P3.

[0193] Figure 10 is a schematic diagram of a portion of the film layer of the display substrate provided in Figures 4 and 6. As shown in Figure 10, the areas of the channel regions 31-3 of the active patterns of the driving transistors (third transistor T3) in the pixel driving circuits of at least two sub-pixels are different.

[0194] This disclosure ensures that the cross voltage of different sub-pixels is close by making the area of ​​the channel region of the active pattern of the driving transistor (third transistor) in the pixel driving circuit of at least two sub-pixels different, thereby reducing the difference in display effect between different sub-pixels, ensuring the display uniformity of the display product, and improving the display effect of the display product.

[0195] In an exemplary embodiment, as shown in FIG10, the area of ​​the channel region 31-3 of the active pattern 31 of the third transistor in the pixel driving circuit of at least one of the first sub-pixels P1 and the second sub-pixel P2 is greater than the area of ​​the channel region 31-3 of the active pattern 31 of the third transistor in the pixel driving circuit of the third sub-pixel P3.

[0196] In an exemplary embodiment, the shape of the channel region 31-3 of the active pattern 31 of the third transistor in the pixel driving circuit of at least one of the first sub-pixels P1 and P2 can be a double-digit or horizontally flipped "S" shape.

[0197] In an exemplary embodiment, as shown in FIG10, the channel region 31-3 of the active pattern 31 of the third transistor in the pixel driving circuit of the third sub-pixel P3 includes: a first channel portion 31A, a second channel portion 31B, and a third channel portion 31C. The first channel portion 31A is connected to one end of the second channel portion 31B, and the third channel portion 31C is connected to the other end of the second channel portion 31B. The first channel portion 31A and the third channel portion 31C are located on different sides of the second channel portion 31B.

[0198] In an exemplary embodiment, as shown in FIG10, at least one of the first channel portion 31A and the third channel portion 31C extends along the first direction D1, and the second channel portion 31B extends along the second direction D2, wherein the first direction D1 intersects the second direction D2.

[0199] In this disclosure, since the light-emitting materials of the first and second sub-pixels are different from those of the third sub-pixel, when the channel region of the active pattern 31 of the third transistor in the pixel driving circuit of the third sub-pixel has the same shape and area as the channel region of the active pattern 31 of the third transistor in the pixel driving circuit of at least one of the first and second sub-pixels, the voltage across the third sub-pixel is greater than that of the first and second sub-pixels. In this disclosure, a portion of the channel region of the active pattern 31 of the third transistor in the pixel driving circuit of the third sub-pixel adopts a straightening design. By shortening the length of the channel region of the active pattern 31 of the third transistor in the pixel driving circuit of the third sub-pixel, the voltage across the third sub-pixel is reduced, making the voltage across the third sub-pixel close to that of the first and second sub-pixels. This not only achieves uniform display but also reduces the power consumption of the display substrate.

[0200] In an exemplary embodiment, as shown in Figures 4 to 7, the display substrate may further include: a plurality of second scan signal lines Gate2, a plurality of first reset signal lines Reset1, a plurality of second reset signal lines Reset2, a plurality of first initial signal lines INITL1, a plurality of second initial signal lines INITL2, a plurality of third initial signal lines INITL3, a plurality of light emission signal lines EM, a plurality of first power supply lines VDD, and a plurality of data signal lines Data disposed on the substrate.

[0201] In an exemplary embodiment, as shown in Figures 4 to 7, at least a portion of at least one of the following signal lines extends along a first direction D1: a plurality of first scan signal lines Gate1, a plurality of second scan signal lines Gate2, a plurality of first reset signal lines Reset1, a plurality of second reset signal lines Reset2, a plurality of first initial signal lines INITL1, a plurality of second initial signal lines INITL2, a plurality of third initial signal lines INITL3, and a plurality of light-emitting signal lines EM. At least a portion of at least one of the following signal lines extends along a second direction D2: a plurality of first power lines VDD and a plurality of data signal lines Data.

[0202] In an exemplary embodiment, as shown in Figures 4 to 7, the second initial signal line INITL2, the second reset signal line Reset2, the light emission signal line EM, the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, and the first initial signal line INITL1 connected by at least one pixel driving circuit are arranged sequentially along the second direction D2 on the substrate.

[0203] In an exemplary embodiment, as shown in Figures 4 to 7, the orthographic projection of the third initial signal line INITL3 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line Reset2 on the substrate.

[0204] In an exemplary embodiment, as shown in Figures 4 to 7, the orthographic projection of the second initial signal line INITL2 connected to at least one row of pixel driving circuits on the substrate can at least partially overlap with the orthographic projection of the first reset signal line Reset1 connected to the previous row of pixel driving circuits on the substrate.

[0205] In an exemplary embodiment, multiple first power lines VDD and multiple data signal lines Data are arranged alternately.

[0206] In an exemplary embodiment, as shown in Figures 8 and 9, the second scan signal line Gate2 includes a first scan section Gate2A and a second scan section Gate2B. The second scan section Gate2B is located on the side of the first scan section Gate2A away from the substrate and is connected to the first scan section Gate2A. The orthographic projection of the first scan section Gate2A on the substrate at least partially overlaps with the orthographic projection of the second scan section Gate2B on the substrate.

[0207] Figure 11 is a schematic diagram of one structure of the second scanning signal line. As shown in Figure 11, the orthogonal projection of the second scanning unit Gate 2B on the substrate and the orthogonal projection of the first scanning unit Gate 2A on the substrate have a non-overlapping area, that is, the second scanning unit Gate 2B and the first scanning unit Gate 2A adopt a staggered design.

[0208] In an exemplary embodiment, as shown in Figures 8 and 9, the orthographic projection of the second scanning unit Gate 2B onto the substrate is within the range of the orthographic projection of the first scanning unit Gate 2A onto the substrate. The arrangement of the second scanning signal lines in this disclosure ensures the morphological consistency of the compensation transistors in the pixel driving circuits of different sub-pixels under process fluctuations.

[0209] In an exemplary embodiment, FIG12 is a schematic diagram of a portion of the film layer in the display substrate provided in FIG4, and FIG13 is a schematic diagram of a portion of the film layer in the display substrate provided in FIG6. As shown in FIG12 and FIG13, in at least one pixel driving circuit, the first electrode of the light-emitting transistor (fifth transistor T5) includes: an electrode body portion 531, a first extension portion 532, a second extension portion 533, and a third extension portion 534. The first extension portion 532, the second extension portion 533, and the third extension portion 534 are respectively connected to the electrode body portion 531.

[0210] In an exemplary embodiment, in the first electrode of the light-emitting transistor (fifth transistor T5) of at least one pixel driving circuit, the first extension 532 and at least one of the second extension 533 and the third extension 534 are located on different sides of the electrode body portion 531. The first extension 532 is located on the side of the electrode body portion 531 closer to the previous row of pixel driving circuits. At least one of the second extension 533 and the third extension 534 is located on the side of the electrode body portion 531 closer to the previous row of pixel driving circuits.

[0211] In an exemplary embodiment, as shown in Figures 12 and 13, the electrode body portion 531 extends at least partially along the second direction D2, at least one of the first extension portion 532 and the second extension portion 533 extends at least partially along the second direction D2, and the third extension portion 534 extends at least partially along the first direction D1. The minimum width of at least one structure of the electrode body portion 531 and the third extension portion 534 along the first direction D1 is greater than the maximum width of at least one of the first extension portion 532 and the second extension portion 533 along the first direction D1, and the width of the first extension portion 532 along the first direction D1 is greater than the width of the second extension portion 533 along the first direction D1.

[0212] In an exemplary embodiment, as shown in Figures 12 and 13, the second electrode plate is provided with a through hole V that exposes the first electrode plate C1.

[0213] In an exemplary embodiment, as shown in Figures 12 and 13, for a pixel driving circuit of at least one sub-pixel, the orthogonal projections of the electrode body 531 and the third extension 534 of the first pole of the light-emitting transistor (fifth transistor T5) onto the substrate at least partially overlap with the orthogonal projection of the capacitor C onto the substrate.

[0214] In an exemplary embodiment, as shown in Figures 12 and 13, the orthographic projection of the first extension 532 of the first electrode of the light-emitting transistor (fifth transistor T5) onto the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line EM connected to the pixel driving circuit onto the substrate. The orthographic projection of the first extension 532 of the first electrode of the light-emitting transistor (fifth transistor T5) onto the substrate and the orthographic projection of the capacitor C onto the substrate may not overlap.

[0215] In an exemplary embodiment, as shown in Figures 12 and 13, the orthographic projection of the second extension 533 of the first electrode of the light-emitting transistor (fifth transistor T5) onto the substrate at least partially overlaps with the orthographic projection of the first scan signal line Gate1 connected to the pixel driving circuit onto the substrate. The orthographic projection of the second extension 533 of the first electrode of the light-emitting transistor (fifth transistor T5) onto the substrate and the orthographic projection of the capacitor C onto the substrate may not overlap.

[0216] In an exemplary embodiment, as shown in Figures 12 and 13, a first straight line L1 passes through a via V, wherein the first straight line L1 is a straight line extending along the second direction D2 and passing through the third extension 534 of the first pole of the light-emitting transistor (fifth transistor T5) in the pixel driving circuit.

[0217] In this disclosure, the width of the portion of the first electrode of the fifth transistor that overlaps with the capacitor is greater than the width of the portion that does not overlap with the first electrode after absorption. This reduces the voltage drop of the first electrode of the fifth transistor while ensuring the transmittance of the display substrate.

[0218] In an exemplary embodiment, for a pixel driving circuit of at least one sub-pixel, the orthographic projection of the second extension 533 of the first electrode of the light-emitting transistor (fifth transistor T5) onto the substrate is located between the orthographic projection of the first electrode of the compensation transistor (second transistor T2) onto the substrate and the orthographic projection of the first electrode of the write transistor (fourth transistor T4) onto the substrate. The second extension 533 of the first electrode of the light-emitting transistor (fifth transistor T5) acts as a shield between the orthographic projection of the first electrode of the compensation transistor (second transistor T2) onto the substrate and the first electrode of the write transistor (fourth transistor T4), thus preventing crosstalk from the data signal transmitted by the first electrode of the write transistor (fourth transistor T4) to the first electrode (i.e., the first node) of the compensation transistor (second transistor T2), thereby improving the reliability of the display substrate.

[0219] In an exemplary embodiment, as shown in FIG12, the display substrate may further include: a plurality of capacitor connection portions 30, at least one capacitor connection portion 30 extending at least partially along a first direction D1. The second plates C2 of capacitors C in two adjacent pixel driving circuits arranged along the first direction D1 are connected via at least one capacitor connection portion 30. The first electrodes 53 of light-emitting transistors (fifth transistor T5) in two adjacent pixel driving circuits arranged along the first direction D1 are spaced apart.

[0220] In an exemplary embodiment, the capacitor connection portion 30 is disposed on the same layer as the second plate C2 of the capacitor C.

[0221] In this disclosure, the integrated structure of the second plate of the capacitor and multiple capacitor connection portions in the pixel driving circuit arranged along the first direction serves as a power connection line extending along the first direction D1. The multiple power connection lines and multiple first power lines are interwoven horizontally and vertically, which can ensure the consistency of the power signals transmitted in different sub-pixels and guarantee the display uniformity of the display substrate.

[0222] In an exemplary embodiment, as shown in FIG13, the display substrate may further include: a plurality of electrode connection portions 40, the electrode connection portions 40 extending at least partially along a first direction D1. The second plates C2 of capacitors C in two adjacent pixel driving circuits arranged along the first direction D1 are spaced apart; the first electrodes 53 of light-emitting transistors (fifth transistors T5) in two adjacent pixel driving circuits arranged along the first direction D1 are connected through at least one electrode connection portion 40.

[0223] In an exemplary embodiment, as shown in FIG13, the electrode connection portion 40 is disposed on the same layer as the first electrode 53 of the light-emitting transistor (fifth transistor T5).

[0224] In an exemplary embodiment, as shown in FIG13, the orthographic projection of at least one electrode connection portion 40 on the substrate at least partially overlaps with the orthographic projection of capacitor C in at least one pixel driving circuit on the substrate.

[0225] In this disclosure, the integrated structure of the first electrode 53 of the light-emitting transistor (fifth transistor T5) and multiple electrode connection portions in the pixel driving circuit arranged along the first direction serves as a power connection line extending along the first direction D1. The multiple power connection lines and multiple first power lines are interwoven horizontally and vertically, which can ensure the consistency of the power signals transmitted in different sub-pixels and guarantee the display uniformity of the display substrate.

[0226] In an exemplary embodiment, as shown in FIG13, at least one electrode connection portion 40 is connected to the electrode body portion 531 in the first pole of the light-emitting transistor (fifth transistor T5) in one of the adjacent pixel driving circuits and the third extension portion 534 in the first pole of the light-emitting transistor (fifth transistor T5) in another adjacent pixel driving circuit.

[0227] In an exemplary embodiment, at least one first power line VDD includes a power block and a power connection portion, the power block and the power connection portion extending at least partially along a second direction D2, and the length of the power block along a first direction D1 being greater than the length of the power connection portion along the first direction D1. The orthographic projection of at least one power block in the at least one first power line VDD onto the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor C and the compensation transistor (second transistor T2) in at least one pixel driving circuit onto the substrate.

[0228] In an exemplary embodiment, the orthographic projection of the first electrode of the compensation transistor (second transistor T2) in at least one pixel driving circuit onto the substrate lies within the range of the orthographic projection of at least one power block in at least one first power line VDD onto the substrate. This arrangement, where the orthographic projection of the first electrode of the compensation transistor (second transistor T2) in at least one pixel driving circuit lies within the range of the orthographic projection of at least one power block in at least one first power line VDD onto the substrate, allows the first power line to act as a shield for the compensation transistor, thereby improving the characteristics of the compensation transistor and enhancing the reliability of the display substrate.

[0229] In an exemplary embodiment, FIG14 is a schematic diagram of a portion of the film layer in the display substrate provided in FIGS. 4 and 6. As shown in FIG14, the power block in the first power line VDD to which the pixel driving circuit of the first sub-pixel P1 is connected includes: a plurality of first power blocks DL11 and a plurality of second power blocks DL12. The power connection portion in the first power line VDD to which the pixel driving circuit of the first sub-pixel P1 is connected includes: a plurality of first power connection portions DL13. One end of at least one second power block DL12 is connected to at least one first power block DL11 through at least one first power connection portion DL13, and the other end of at least one second power block DL12 is connected to at least one first power block DL11. The length of the second power block DL12 along the second direction D2 is greater than the length of the first power block DL11 along the second direction D2.

[0230] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the first power block DL11 on the substrate at least partially overlaps with the orthographic projections of the second reset signal line Reset2, the third initial signal line INITL3, and the first initial signal line INITL1 on the substrate.

[0231] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the second power block DL12 on the substrate at least partially overlaps with the orthographic projection of the capacitor C and the first electrode of the second transistor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, and the second initial signal line INITL2 on the substrate.

[0232] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the first power connection portion DL13 on the substrate at least partially overlaps with the orthographic projection of the capacitor C in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of the light emission signal line EM on the substrate.

[0233] In an exemplary embodiment, as shown in FIG14, the power block of the first power line VDD to which the pixel driving circuit of the second sub-pixel P2 is connected includes: a plurality of third power blocks DL21, and the power connection part of the first power line VDD to which the pixel driving circuit of the second sub-pixel P2 is connected includes: a plurality of second power connection parts DL22. The plurality of third power blocks DL21 and the plurality of second power connection parts DL22 are arranged alternately and connected to each other.

[0234] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the third power block DL21 on the substrate also at least partially overlaps with the orthographic projection of at least one of the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, and the second initial signal line INITL2 on the substrate.

[0235] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the second power connection portion DL22 on the substrate at least partially overlaps with the orthographic projection of the capacitor C in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first initial signal line INITL1, the second reset signal line Reset2, the third initial signal line INITL3 and the light emission signal line EM on the substrate.

[0236] In an exemplary embodiment, as shown in FIG14, the power block in the first power line VDD to which the pixel driving circuit of the third sub-pixel P3 is connected includes: a plurality of fourth power blocks DL31, and the power connection part in the first power line VDD to which the pixel driving circuit of the third sub-pixel P3 is connected includes: a plurality of third power connection parts DL32. The plurality of fourth power blocks DL31 and the plurality of third power connection parts DL32 are arranged alternately and connected to each other.

[0237] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the fourth power block DL31 on the substrate also at least partially overlaps with the orthographic projection of at least one of the first scan signal lines Gate1 and Gate2 on the substrate.

[0238] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the third power connection portion DL32 on the substrate at least partially overlaps with the orthographic projection of the capacitor C in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the first initial signal line INITL1, the second initial signal line INITL2, the first reset signal line Reset1, the second reset signal line Reset2, the third initial signal line INITL3, and the light emission signal line EM.

[0239] In an exemplary embodiment, as shown in FIG14, the overlapping area of ​​the orthographic projection of the fourth power block DL31 on the substrate and the orthographic projection of the capacitor C in at least one pixel driving circuit on the substrate is greater than the overlapping area of ​​the orthographic projection of at least one power block of the second power block DL12 and the third power block DL21 on the substrate and the orthographic projection of the capacitor C in at least one pixel driving circuit on the substrate.

[0240] In an exemplary embodiment, FIG15 is a schematic diagram of a portion of the film layers in the display substrate provided in FIG4 and FIG6. As shown in FIG15, at least one sub-pixel further includes: a light-emitting device and a pixel definition layer. The light-emitting device includes: an anode 50, and the pixel definition layer may be provided with multiple pixel openings H.

[0241] In an exemplary embodiment, as shown in FIG15, the area of ​​the anode 510 of the light-emitting device of the first sub-pixel P1 is smaller than the area of ​​the anode 520 of the light-emitting device of the second sub-pixel P2, and the area of ​​the anode 520 of the light-emitting device of the second sub-pixel P2 is smaller than the area of ​​the anode 530 of the light-emitting device of the third sub-pixel P3.

[0242] In an exemplary embodiment, as shown in FIG15, at least one of the anodes 510 of the light-emitting device of the first sub-pixel P1 and the anode 520 of the light-emitting device of the second sub-pixel P2 has a length along the second direction D2 that is less than the length along the second direction D2 of the anode 530 of the light-emitting device of the third sub-pixel P3.

[0243] In an exemplary embodiment, the anode of at least one light-emitting device may include an anode body portion and an anode connecting portion. The anode body portion and the anode connecting portion are connected, and the anode connecting portion is connected to an anode connecting electrode through a via in a second planarization layer. The shape of the anode body portion may be circular, square, or other structures, and this disclosure does not limit it in any way.

[0244] In an exemplary embodiment, the pixel definition layer includes: a first pixel opening H1, a second pixel opening H2, and a third pixel opening H3.

[0245] In an exemplary embodiment, the first pixel opening H1 exposes the anode 510 of the light-emitting device of the first sub-pixel P1, and its orthographic projection on the substrate is within the range of the orthographic projection of the main body portion of the anode 510 of the light-emitting device of the first sub-pixel P1 on the substrate. The centerline extending from the first pixel opening H1 along the second direction D2 coincides with the centerline extending from the anode body portion of the anode 510 of the light-emitting device of the first sub-pixel P1.

[0246] In an exemplary embodiment, the second pixel opening H2 exposes the anode 520 of the light-emitting device of the second sub-pixel P2, and its orthographic projection on the substrate is within the range of the orthographic projection of the main body portion of the anode 520 of the light-emitting device of the second sub-pixel P2 on the substrate. The centerline extending from the second pixel opening H2 along the second direction D2 coincides with the centerline extending from the anode body portion of the anode 520 of the light-emitting device of the second sub-pixel P2.

[0247] In an exemplary embodiment, the third pixel opening H3 exposes the anode 530 of the light-emitting device of the third sub-pixel P3, and its orthographic projection on the substrate is within the range of the orthographic projection of the main body portion of the anode 530 of the light-emitting device of the third sub-pixel P3 on the substrate. The centerline extending from the third pixel opening H3 along the second direction D2 coincides with the centerline extending from the anode body portion of the anode 530 of the light-emitting device of the third sub-pixel P3.

[0248] In an exemplary embodiment, as shown in FIG15, the orthographic projection of at least one first pixel opening H1 on the substrate at least partially overlaps with the orthographic projection of the first power block DL11 in the first power line VDD connected to the pixel driving circuit of at least one first sub-pixel P1 on the substrate. The centerline extending along the second direction of at least one first pixel opening H1 coincides with the centerline extending along the second direction of the first power block DL11.

[0249] In an exemplary embodiment, as shown in FIG15, the orthographic projection of the first power block DL11 in the first power line VDD to which the pixel driving circuit of at least one first sub-pixel P1 is connected is located within the range of the orthographic projection of at least one first pixel opening H1 on the substrate.

[0250] In this disclosure, at least one first pixel opening H1 is located below a first power block DL11 with a large area, which at least partially flattens the area below the first pixel opening H1, ensuring that the metal structure below the first pixel opening is symmetrical. This can improve the color shift problem caused by the asymmetry of the metal structure below the first pixel opening and ensure that the light output of the first sub-pixel P1 is uniform.

[0251] In an exemplary embodiment, as shown in FIG15, the orthographic projection of at least one second pixel opening H2 on the substrate at least partially overlaps with the orthographic projection of the second power block DL12 in the first power line VDD connected to the pixel driving circuit of at least one first sub-pixel P1 on the substrate, and at least partially overlaps with the orthographic projection of at least one data signal line Data on the substrate. The centerline extending along the second direction of at least one second pixel opening H2 coincides with the centerline extending along the second direction of the second power block DL12.

[0252] In this disclosure, at least one second pixel opening H2 is located below a second power block DL12 with a large area, which at least partially flattens the area below the at least one second pixel opening H2, ensuring that the metal structure (first power line) below the second pixel opening is symmetrical. This can improve the color shift problem caused by the asymmetry of the metal structure below the second pixel opening and ensure that the light output of the second sub-pixel P2 is uniform.

[0253] In an exemplary embodiment, as shown in FIG15, the orthographic projection of at least one third pixel opening H3 on the substrate at least partially overlaps with at least one structure in the third power block DL21 and the second power connection portion DL22 in the first power line VDD connected to at least one data signal line Data and at least one second sub-pixel P2 pixel driving circuit, and the orthographic projection of the fourth power block DL31 connected to the pixel driving circuit of at least one third sub-pixel P3 on the substrate.

[0254] In an exemplary embodiment, the first power line VDD connected to the pixel driving circuit of at least one second sub-pixel P2 that overlaps with at least one third pixel opening H3 and the first power line VDD connected to the pixel driving circuit of at least one third sub-pixel P3 that overlaps with at least one third pixel opening H3 are at least partially symmetrical with respect to a straight line extending along the second direction D2.

[0255] In this disclosure, at least one third pixel opening has two first power lines spanning below it, and the symmetrical metal structure below at least one third pixel opening can improve the color shift problem caused by the asymmetry of the metal structure below the third pixel opening, thus ensuring uniform light output from the third sub-pixel P3.

[0256] In an exemplary embodiment, as shown in Figures 4 and 6, at least one transistor includes at least one P-type transistor (first transistor T1, third transistor T3 to eighth transistor T8) and at least one N-type transistor (second transistor T2). The at least one pixel driving circuit further includes a capacitor C, which includes a first plate and a second plate. The at least one N-type transistor includes a first control electrode and a second control electrode.

[0257] In an exemplary embodiment, the display substrate further includes a circuit structure layer disposed on the substrate. The circuit structure layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer.

[0258] In an exemplary embodiment, as shown in Figures 4 and 6, the first semiconductor layer includes at least: an active pattern of at least one P-type transistor of at least one pixel driving circuit.

[0259] In an exemplary embodiment, as shown in Figures 4 and 6, the first conductive layer includes at least: multiple first scan signal lines Gate1, multiple first reset signal lines Reset1, multiple second reset signal lines Reset2, multiple light emission signal lines EM, and the control electrode of at least one P-type transistor located in at least one pixel driving circuit and the first electrode plate C1 of capacitor C.

[0260] In an exemplary embodiment, as shown in Figures 4 and 6, the second conductive layer includes at least: a plurality of first initial signal lines INITL1, a first scanning section Gate2A of a plurality of second scanning signal lines Gate2, a second plate C2 of a capacitor C located in at least one pixel driving circuit, and a first control electrode of at least one N-type transistor.

[0261] In an exemplary embodiment, as shown in Figures 4 and 6, the second semiconductor layer includes at least an active pattern of at least one N-type transistor located in at least one pixel driving circuit.

[0262] In an exemplary embodiment, as shown in Figures 4 and 6, the third conductive layer includes at least: a second scan section Gate2B of a plurality of second scan signal lines Gate2, a plurality of third initial signal lines INITL3, and a second control electrode of at least one N-type transistor located in at least one pixel driving circuit.

[0263] In an exemplary embodiment, as shown in Figures 4 and 6, the fourth conductive layer includes at least: a plurality of second initial signal lines INITL2 and a first and second pole of at least one transistor located in at least one pixel driving circuit.

[0264] In an exemplary embodiment, as shown in Figures 4 and 6, the fifth conductive layer includes at least: multiple data signal lines (Data) and multiple first power lines (VDD).

[0265] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on the side of the circuit structure layer away from the substrate. The light-emitting structure layer includes a sixth conductive layer, a pixel definition layer, an organic structure layer, and a seventh conductive layer.

[0266] In an exemplary embodiment, the sixth conductive layer includes at least an anode of at least one light-emitting device. The organic structural layer includes at least an organic light-emitting layer of at least one light-emitting device. The seventh conductive layer includes at least a cathode of at least one light-emitting device.

[0267] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0268] Figures 16 to 46 are schematic diagrams illustrating the fabrication process of a display substrate provided in an exemplary embodiment. Figures 16 to 46 are illustrated using the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 located in the i-th row as examples.

[0269] The fabrication process of the display substrate provided in this disclosure may include, as shown in Figures 16 to 46:

[0270] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the first semiconductor thin film using a patterning process to form a first semiconductor layer pattern, as shown in FIG16. FIG16 is a schematic diagram of the first semiconductor layer pattern in FIG4 and FIG6.

[0271] In an exemplary embodiment, as shown in FIG16, the first semiconductor layer pattern may include at least an active pattern of at least one P-type transistor located in at least one pixel driving circuit. Exemplarily, the active patterns of at least one P-type transistor include, for example, the active patterns 11 of the first transistor, 31 of the third transistor, 41 of the fourth transistor, 51 of the fifth transistor, 61 of the sixth transistor, 71 of the seventh transistor, and 81 of the eighth transistor.

[0272] In an exemplary embodiment, for at least one pixel driving circuit, the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, and the active pattern 71 of the seventh transistor are integrally formed. The active pattern 11 of the first transistor and the active pattern 81 of the eighth transistor are separately configured.

[0273] In an exemplary embodiment, in the first direction D1, the active patterns 41 of the fourth transistor and 51 of the fifth transistor of at least one column of pixel driving circuits are located on the side of the active pattern 31 of the third transistor of the same column of pixel driving circuits near the next column of pixel driving circuits, and the active patterns 11 of the first transistor and 61 of the sixth transistor of at least one column of pixel driving circuits are located on the side of the active pattern 31 of the third transistor of the same column of pixel driving circuits near the previous column of pixel driving circuits. In the second direction D2, the active pattern 11 of the first transistor of at least one row of pixel driving circuits is located on the side of the active pattern 31 of the third transistor of the same row of pixel driving circuits near the next row of pixel driving circuits, and the active patterns 51 of the fifth transistor, 71 of the seventh transistor, and 81 of the eighth transistor of at least one row of pixel driving circuits are near the side of the previous row of pixel driving circuits.

[0274] In an exemplary embodiment, for at least one pixel driving circuit, the shape of at least one of the active patterns of the first transistor's active pattern 11, the sixth transistor's active pattern 61, the seventh transistor's active pattern 71, and the eighth transistor's active pattern 81 can be "I" shaped. The shape of the fourth transistor's active pattern 41 can be "7" shaped, and the shape of the fifth transistor's active pattern 51 can be a horizontally flipped "L" shaped.

[0275] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, for at least one pixel driving circuit, the first region 31-1 of the active pattern 31 of the third transistor may simultaneously serve as the second region 41-2 of the active pattern 41 of the fourth transistor and the second region 51-2 of the active pattern 51 of the fifth transistor. The second region 31-2 of the active pattern 31 of the third transistor may simultaneously serve as the first region 61-1 of the active pattern 61 of the sixth transistor. The second region 61-2 of the active pattern 61 of the sixth transistor may simultaneously serve as the first region 71-2 of the active pattern 71 of the seventh transistor. The first regions 11-1 and 11-2 of the active pattern 11 of the first transistor, the first region 41-1 of the active pattern 41 of the fourth transistor, the first region 51-1 of the active pattern 51 of the fifth transistor, the first region 71-1 of the active pattern 71 of the seventh transistor, and the first regions 81-1 and 81-2 of the active pattern 81 of the eighth transistor may be configured individually.

[0276] In an exemplary embodiment, the area of ​​the channel region 31-3 of the active pattern of the third transistor in the pixel driving circuit of at least one of the first and second sub-pixels is greater than the area of ​​the channel region 31-3 of the active pattern of the third transistor in the pixel driving circuit of the third sub-pixel.

[0277] In an exemplary embodiment, the shape of the channel region 31-3 of the active pattern of the third transistor in the pixel driving circuit of at least one of the first and second sub-pixels can be a horizontally flipped "S" shape.

[0278] In an exemplary embodiment, the channel region 31-3 of the active pattern of the third transistor in the pixel driving circuit of the third sub-pixel may include: a first channel portion 31A, a second channel portion 31B, and a third channel portion 31C.

[0279] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive layer pattern located on the first insulating layer, as shown in Figures 17 and 18. Figure 17 is a schematic diagram of the first conductive layer pattern in Figures 4 and 6, and Figure 18 is a schematic diagram of Figures 4 and 6 after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0280] In an exemplary embodiment, as shown in Figures 17 and 18, the first conductive layer pattern may include: a first scan signal line Gate1, a first reset signal line Reset1, a second reset signal line Reset2, a light emission signal line EM, and the control electrode of at least one P-type transistor located in at least one pixel driving circuit, and the first electrode C1 of a capacitor. Exemplarily, the control electrode of at least one P-type transistor includes, for example, the control electrode 12 of a first transistor, the control electrode 32 of a third transistor, the control electrode 42 of a fourth transistor, the control electrode 52 of a fifth transistor, the control electrode 62 of a sixth transistor, the control electrode 72 of a seventh transistor, and the control electrode 82 of an eighth transistor.

[0281] In an exemplary embodiment, the first reset signal line Reset1 and the first scan signal line Gate1 connected to at least one row of pixel driving circuits are located on the side of the first plate C1 of the capacitor of the pixel driving circuit closer to the next row of pixel driving circuits, and the first reset signal line Reset1 connected to at least one row of pixel driving circuits is located on the side of the first scan signal line Gate1 connected to at least one row of pixel driving circuits away from the first plate C1 of the capacitor of the pixel driving circuit.

[0282] In an exemplary embodiment, the light-emitting signal line EM and the second reset signal line Reset2 connected to at least one row of pixel driving circuits are located on the side of the first plate C1 of the capacitor of the pixel driving circuit closer to the previous row of pixel driving circuits, and the second reset signal line Reset2 connected to at least one row of pixel driving circuits is located on the side of the light-emitting signal line EM connected to at least one row of pixel driving circuits away from the first plate C1 of the capacitor of the pixel driving circuit.

[0283] In an exemplary embodiment, the shape of the first reset signal line Reset1 can be a line shape in which the main body extends along the first direction D1. The area where the first reset signal line Reset1, to which at least one pixel driving circuit is connected, overlaps with the active pattern of the first transistor can be the control electrode 12 of the first transistor.

[0284] In an exemplary embodiment, the shape of the first scan signal line Gate1 can be a line shape in which the main body extends along the first direction D1. The first scan signal line Gate1 includes a main signal line 10 and a plurality of gate blocks 20. The plurality of gate blocks 20 in the first scan signal line are located on the side of the main signal line 10 close to the first reset signal line Reset1.

[0285] In an exemplary embodiment, the main signal line 10 is a line shape extending along the first direction D1, and the gate block 20 can be a block structure.

[0286] In an exemplary embodiment, at least one of the gate blocks 20 has a length along the second direction D2 that is greater than the length of the main signal line 10 along the second direction D2.

[0287] In an exemplary embodiment, the main signal line 10 at least partially overlaps with the active pattern of the fourth transistor. The area where the main signal line 10 of the first scan signal line Gate 1, to which at least one pixel driving circuit is connected, overlaps with the active pattern of the fourth transistor can be the control electrode 42 of the fourth transistor.

[0288] In an exemplary embodiment, the shape of the light-emitting signal line EM can be a line shape extending along the first direction D1 of the main body portion. The area where the light-emitting signal line EM connected to at least one pixel driving circuit overlaps with the active pattern of the fifth transistor can be the control electrode 52 of the fifth transistor, and the area where the light-emitting signal line EM connected to at least one pixel driving circuit overlaps with the active pattern of the sixth transistor can be the control electrode 62 of the sixth transistor.

[0289] In an exemplary embodiment, the shape of the second reset signal line Reset2 can be a line shape in which the main body extends along the first direction D1. The area where the second reset signal line Reset2, connected to at least one pixel driving circuit, overlaps with the active pattern of the seventh transistor can be the control electrode 72 of the seventh transistor, and the area where the second reset signal line Reset2, connected to at least one pixel driving circuit, overlaps with the active pattern of the eighth transistor can be the control electrode 82 of the eighth transistor.

[0290] In an exemplary embodiment, the first plate C1 of the capacitor in at least one pixel driving circuit can be rectangular in shape, and the corners of the rectangle can be chamfered. Exemplarily, the first plate C1 of the capacitor can serve as the control electrode 32 of the third transistor.

[0291] In an exemplary embodiment, the first scan signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2, and the light emission signal line EM can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0292] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel regions of the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor. The first semiconductor layer in the area not shielded by the first conductive layer is conducted.

[0293] In an exemplary embodiment, the control electrode of the first transistor is disposed across the active pattern of the first transistor, the control electrode of the third transistor is disposed across the active pattern of the third transistor, the control electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, the control electrode of the fifth transistor is disposed across the active pattern of the fifth transistor, the control electrode of the sixth transistor is disposed across the active pattern of the sixth transistor, the control electrode of the seventh transistor is disposed across the active pattern of the seventh transistor, and the control electrode of the eighth transistor is disposed across the active pattern of the eighth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0294] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second insulating film and the second conductive film using a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer, as shown in Figures 19 to 22. Figure 19 is a schematic diagram of the second conductive layer pattern in Figure 4; Figure 20 is a schematic diagram of Figure 4 after the second conductive layer pattern is formed; Figure 21 is a schematic diagram of the second conductive layer pattern in Figure 6; and Figure 22 is a schematic diagram of Figure 6 after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0295] In an exemplary embodiment, as shown in Figures 19 to 22, the second conductive layer pattern may include: a first initial signal line INITL1, a first scan portion Gate 2A of a second scan signal line, and a first control electrode of at least one N-type transistor and a second electrode C2 of a capacitor located in at least one pixel driving circuit. Exemplarily, the first control electrode of at least one N-type transistor may include: a first control electrode 22A of a second transistor.

[0296] In an exemplary embodiment, the orthographic projection of the first initial signal line INITL1 connected to the pixel driving circuit on the substrate is located on the side where the orthographic projection of the first reset signal line connected to the pixel driving circuit on the substrate is far from the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate.

[0297] In an exemplary embodiment, the orthographic projection of the first scan portion Gate2A of the second scan signal line Gate2 connected to the pixel driving circuit on the substrate is located between the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate and the orthographic projection of the first reset signal line connected to the pixel driving circuit on the substrate.

[0298] In an exemplary embodiment, the shape of the first initial signal line INITL1 can be a line shape in which the main body extends along the first direction D1.

[0299] In an exemplary embodiment, the shape of the first scanning portion Gate2A of the second scan signal line Gate2 can be a line shape in which the main body extends along the first direction D1. The area where the first scanning portion Gate2A of the second scan signal line Gate2, to which at least one pixel driving circuit is connected, overlaps with the active pattern of the second transistor can be the first control electrode 22A of the second transistor.

[0300] In an exemplary embodiment, the main outline of the second electrode C2 of the capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the main body of the second electrode C2 on the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor on the substrate. The second electrode C2 of the capacitor is provided with an opening V, which can be rectangular in shape and located in the middle of the second electrode C2, so that the second electrode C2 of the capacitor forms a ring structure. The opening V exposes the insulating layer covering the first electrode of the capacitor, and the orthographic projection of the first electrode of the capacitor on the substrate covers the orthographic projection of the opening V on the substrate. In the exemplary embodiment, the opening V exposes the first electrode of the capacitor, so that the first electrode of the subsequently formed second transistor is connected to the first electrode of the capacitor.

[0301] In an exemplary embodiment, in the display substrate provided in FIG4, the first conductive layer pattern may further include: a capacitor connection portion 30 located between adjacent pixel driving circuits.

[0302] In an exemplary embodiment, the capacitor connection portion 30 extends at least partially along the first direction D1. The second plates C2 of capacitors in adjacent pixel driving circuits located in the same row are electrically connected through the capacitor connection portion 30.

[0303] In an exemplary embodiment, in the display substrate provided in FIG6, the second plates C2 of the capacitors of adjacent pixel driving circuits located in the same row are spaced apart.

[0304] In an exemplary embodiment, the first scanning section Gate2A of the first initial signal line INITL1 and the second scanning signal line Gate2 can be designed with equal width or with non-equal width, and can be a straight line or a broken line. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0305] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: on the substrate on which the aforementioned pattern is formed, including: sequentially depositing a third insulating film and a second semiconductor film on the substrate, and patterning the third insulating film and the second semiconductor film by a patterning process to form a third insulating layer pattern and a second semiconductor layer pattern located on the third insulating layer, as shown in Figures 23 to 25. Figure 23 is a schematic diagram of the second semiconductor layer pattern in Figures 4 and 6, Figure 24 is a schematic diagram of the second semiconductor layer pattern after it is formed in Figure 4, and Figure 25 is a schematic diagram of the second semiconductor layer pattern after it is formed in Figure 6.

[0306] In an exemplary embodiment, as shown in Figures 23 to 25, the second semiconductor layer pattern may include an active pattern of at least one N-type transistor located in at least one pixel driving circuit. Exemplarily, the active pattern of the at least one N-type transistor includes an active pattern 21 of the second transistor.

[0307] In an exemplary embodiment, as shown in Figures 11 and 12, the active pattern 21 of the second transistor is configured separately.

[0308] In an exemplary embodiment, the active pattern 21 of the second transistor is in the shape of an "I".

[0309] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, for at least one pixel driving circuit, the first region 21-1 and the second region 21-2 of the active pattern 21 of the second transistor are separately configured.

[0310] In an exemplary embodiment, the active pattern 21 of the second transistor is disposed across the first control electrode of the second transistor.

[0311] In an exemplary embodiment, the area of ​​the first region 21-1 of the active pattern of the second transistor in the pixel driving circuit of at least one sub-pixel is greater than the area of ​​the second region 21-2 of the active pattern of the second transistor.

[0312] In an exemplary embodiment, the area of ​​the first region 21-1 of the active pattern of the second transistor in the pixel driving circuit of at least one of the first and second sub-pixels is greater than the area of ​​the first region 21-1 of the active pattern of the second transistor in the pixel driving circuit of the third sub-pixel.

[0313] In an exemplary embodiment, the first region of the active pattern of the second transistor in the pixel driving circuit of at least one sub-pixel at least partially overlaps with the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate. Exemplarily, the first region of the active pattern of the second transistor in the pixel driving circuit of at least one sub-pixel at least partially overlaps with the orthographic projection of at least one gate block of the first scan signal line connected to the pixel driving circuit on the substrate.

[0314] In an exemplary embodiment, the overlap area of ​​the first region of the active pattern of the second transistor in the pixel driving circuit of at least one of the first and second sub-pixels with at least one gate block of the first scan signal line connected to the pixel driving circuit is greater than the overlap area of ​​the first region of the active pattern of the second transistor in the pixel driving circuit of the third sub-pixel with at least one gate block of the first scan signal line connected to the pixel driving circuit.

[0315] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the fourth insulating film and the third conductive film using a patterning process to form a fourth insulating layer pattern and a third conductive layer pattern located on the fourth insulating layer, as shown in Figures 26 to 28. Figure 26 is a schematic diagram of the third conductive layer pattern in Figures 4 and 6; Figure 27 is a schematic diagram of Figure 4 after the formation of the third conductive layer pattern; and Figure 28 is a schematic diagram of Figure 6 after the formation of the third conductive layer pattern. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0316] In an exemplary embodiment, as shown in Figures 26 to 28, the third conductive layer pattern may include: a second scan portion Gate2B of the second scan signal line Gate2, a third initial signal line INITL3, and a second control electrode of at least one N-type transistor located in at least one pixel driving circuit. Exemplarily, the second control electrode of the at least one N-type transistor may include: a second control electrode 22B of the second transistor.

[0317] In an exemplary embodiment, the shape of the second scanning portion Gate2B of the second scan signal line Gate2 connected to at least one pixel driving circuit can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second scanning portion Gate2B of the second scan signal line Gate2 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the first scan line of the second scan signal line Gate2 connected to at least one pixel driving circuit on the substrate. The area where the second scanning portion Gate2B of the second scan signal line Gate2 connected to at least one pixel driving circuit overlaps with the active pattern of the second transistor can serve as the second control electrode 22B of the second transistor.

[0318] In an exemplary embodiment, the orthographic projection of the second scan portion Gate2B of the second scan signal line Gate2 connected to at least one pixel driving circuit on the substrate is located within the range of the orthographic projection of the first scan line of the second scan signal line Gate2 connected to at least one pixel driving circuit on the substrate.

[0319] In an exemplary embodiment, the shape of the third initial signal line INITL3 can be a line shape in which the main portion extends along the first direction D1. The orthographic projection of the third initial signal line INITL3 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line on the substrate.

[0320] In an exemplary embodiment, the second scanning section Gate2B of the second scanning signal line Gate2 and the third initial signal line INITL3 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0321] (6) Forming a fifth insulating layer pattern includes: depositing a fifth insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the fifth insulating film by a patterning process to form a fifth insulating layer pattern covering the aforementioned pattern. The fifth insulating layer has multiple via patterns, as shown in Figures 29 and 30. Figure 29 is a schematic diagram of the fifth insulating layer pattern formed in Figure 4, and Figure 30 is a schematic diagram of the fifth insulating layer pattern formed in Figure 6.

[0322] In an exemplary embodiment, as shown in Figures 29 and 30, the plurality of vias in the fifth insulating layer pattern include at least: a first via V1 to a sixteenth via V16 located in at least one pixel driving circuit.

[0323] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 are etched away, exposing the surface of the first region of the active layer of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active layer of the first transistor through the via.

[0324] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the orthographic projection of the second region of the active pattern of the first transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor. The second via V2 is configured to allow the second terminal of the subsequently formed first transistor (which is also the second terminal of the second transistor, the second terminal of the third transistor, and the first terminal of the sixth transistor) to be connected to the second region of the active pattern of the first transistor through the via.

[0325] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection range of the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor). The third via V3 is configured to allow the first electrode of the subsequently formed third transistor (which is also the second electrode of the fourth transistor, the second electrode of the fifth transistor, and the second electrode of the eighth transistor) to be connected to the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) through the via.

[0326] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the second region of the active pattern of the third transistor (which is also the first region of the active pattern of the sixth transistor) onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the sixth transistor). The fourth via V4 is configured to allow the second electrode of the subsequently formed first transistor (which is also the second electrode of the second transistor, the second electrode of the third transistor, and the first electrode of the sixth transistor) to be connected to the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the sixth transistor) through the via.

[0327] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The fifth via V5 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0328] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The fourth, third, second, and first insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The sixth via V6 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0329] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) onto the substrate. The fourth, third, second, and first insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor). The seventh via V7 is configured to allow the second electrode of the subsequently formed sixth transistor (which is also the second electrode of the seventh transistor) to be connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) through the via.

[0330] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The fourth, third, second, and first insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the active pattern of the seventh transistor. The eighth via V8 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first region of the active pattern of the seventh transistor through the via.

[0331] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the orthographic projection of the first region of the active pattern of the eighth transistor onto the substrate. The fourth, third, second, and first insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the active pattern of the eighth transistor. The ninth via V9 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the first region of the active pattern of the eighth transistor through the via.

[0332] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the orthographic projection of the second region of the active pattern of the eighth transistor onto the substrate. The fourth, third, second, and first insulating layers within the tenth via V10 are etched away, exposing the surface of the first region of the active pattern of the eighth transistor. The tenth via V10 is configured to allow the first terminal of the subsequently formed third transistor (which is also the second terminal of the fourth, fifth, and eighth transistors) to be connected to the second region of the active pattern of the eighth transistor through the via.

[0333] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the substrate is located within the orthogonal projection of the first electrode of the capacitor (which is also the second electrode of the third transistor) onto the substrate. The fourth, third, and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the first electrode of the capacitor (which is also the second electrode of the third transistor). The eleventh via V11 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first electrode of the capacitor (which is also the second electrode of the third transistor) through the via.

[0334] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second plate of the capacitor on the substrate. The fourth and third insulating layers within the twelfth via V12 are etched away, exposing the surface of the second plate of the capacitor. The twelfth via V12 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the second plate of the capacitor through the via.

[0335] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the range of the orthographic projection of the first initial signal line onto the substrate. The fourth and third insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first initial signal line. The thirteenth via V13 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first initial signal line through the via.

[0336] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the orthographic projection range of the first region of the active pattern of the second transistor onto the substrate. The fourth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the first region of the active pattern of the second transistor. The fourteenth via V14 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first region of the active pattern of the second transistor through the via.

[0337] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the second region of the active pattern of the second transistor onto the substrate. The fourth insulating layer within the fifteenth via V15 is etched away, exposing the surface of the second region of the active pattern of the second transistor. The fifteenth via V15 is configured to allow the second terminal of the subsequently formed first transistor (which is also the second terminal of the second transistor, the second terminal of the third transistor, and the third terminal of the sixth transistor) to be connected to the second region of the active pattern of the second transistor through the via.

[0338] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the third initial signal line on the substrate. The sixteenth via V16 exposes the surface of the third initial signal line. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the third initial signal line through the via.

[0339] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern, as shown in Figures 31 to 34. Figure 31 is a schematic diagram of the fourth conductive layer pattern in Figure 4, Figure 32 is a schematic diagram of Figure 4 after the fourth conductive layer pattern is formed, Figure 33 is a schematic diagram of the fourth conductive layer pattern in Figure 6, and Figure 34 is a schematic diagram of Figure 6 after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0340] In an exemplary embodiment, as shown in Figures 31 to 34, in the display substrate provided in Figures 4 and 6, the fourth conductive layer pattern may include: a second initial signal line INITL2 and a first pole 13 and a second pole 14 of a first transistor to a first pole 83 and a second pole 84 of an eighth transistor located in at least one pixel driving circuit.

[0341] In an exemplary embodiment, in the display substrate provided in FIG6, the fourth conductive layer pattern may further include an electrode connection portion 40 disposed between two adjacent pixel driving circuits.

[0342] In an exemplary embodiment, in at least one pixel driving circuit, the first electrode 13 of the first transistor is separately disposed and is shaped as a strip extending at least partially along the second direction D2. The first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor through a first via and is electrically connected to the first initial signal line through a thirteenth via.

[0343] In an exemplary embodiment, the second electrode 14 of the first transistor, the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 63 of the sixth transistor are integrally structured and are L-shaped. The second electrode 14 of the first transistor (which is also the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 63 of the sixth transistor) is connected to the second region of the active pattern of the first transistor through a second via, connected to the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the sixth transistor) through a fourth via V4, and connected to the second region of the active pattern of the second transistor through a fifteenth via.

[0344] In an exemplary embodiment, the first electrode 23 of the second transistor is provided separately. The first electrode 23 of the second transistor is strip-shaped, extending at least partially along the second direction D2. The first electrode 23 of the second transistor is connected to the first plate of the capacitor (which is also the second electrode of the third transistor) through an eleventh via, and to the first region of the active pattern of the second transistor through a fourteenth via.

[0345] In an exemplary embodiment, the orthographic projection of the first electrode 23 of the second transistor onto the substrate at least partially overlaps with the orthographic projection of the first scan signal line onto the substrate.

[0346] In an exemplary embodiment, the first electrode 33 of the third transistor, the second electrode 44 of the fourth transistor, the second electrode 54 of the fifth transistor, and the second electrode 84 of the eighth transistor are a single structure, and their shape is a horizontally flipped "7". The first electrode 33 of the third transistor (which is also the second electrode 44 of the fourth transistor, the second electrode 54 of the fifth transistor, and the second electrode 84 of the eighth transistor) is connected to the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) through a third via, and is connected to the second region of the active pattern of the eighth transistor through a tenth via.

[0347] In an exemplary embodiment, the first electrode 43 of the fourth transistor is separately disposed and is block-shaped. The first electrode 43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through a fifth via.

[0348] In an exemplary embodiment, the first electrode 53 of the fifth transistor is provided separately. The first electrode 53 of the fifth transistor is connected to the first region of the active pattern of the fifth transistor through a sixth via, and is connected to the second electrode of the capacitor through a twelfth via.

[0349] In an exemplary embodiment, in the display substrate provided in Figures 4 and 6, the first electrode 53 of the fifth transistor includes: an electrode body portion 531, a first extension portion 532, a second extension portion 533, and a third extension portion 534. The first extension portion 532, the second extension portion 533, and the third extension portion 534 are respectively connected to the electrode body portion 531. In at least one pixel driving circuit, the first extension portion 532 of the first electrode 53 of the fifth transistor is located on the side of the electrode body portion 531 near the previous row of pixel driving circuits, and the second extension portion 533 and the third extension portion 534 of the first electrode 53 of the fifth transistor in at least one pixel driving circuit are located on the side of the electrode body portion 531 near the next row of pixel driving circuits.

[0350] In an exemplary embodiment, in the display substrate provided in Figures 4 and 6, the main body portion of the electrode body 531 extends along a second direction D2. At least one of the first extension portion 532 and the second extension portion 533 extends at least partially along the second direction D2. The third extension portion 534 extends at least partially along a first direction D1.

[0351] In an exemplary embodiment, in the display substrate provided in FIG4 and FIG6, for the first electrode 53 of the fifth transistor of at least one pixel driving circuit, the minimum width of at least one portion of the electrode body portion 531 and the third extension portion 534 along the first direction D1 is greater than the maximum width of at least one extension portion of the first extension portion 532 and the second extension portion 533 along the first direction D1, and the width of the first extension portion 532 along the first direction D1 is greater than the width of the second extension portion 533 along the first direction D1.

[0352] In an exemplary embodiment, in the display substrate provided in FIG4 and FIG6, the orthographic projection of the electrode body portion 531 and the third extension portion 534 of the first pole 53 of the fifth transistor in at least one pixel driving circuit onto the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit onto the substrate.

[0353] In an exemplary embodiment, in the display substrate provided in Figures 4 and 6, the first straight line L1 extends along the second direction D2 and passes through the third extension 534 of the first electrode 53 of the fifth transistor in at least one pixel driving circuit. The first straight line L1 passes through a via of the second electrode plate of the capacitor.

[0354] In an exemplary embodiment, in the display substrate provided in FIG4 and FIG6, the orthographic projection of the first extension 532 of the first pole 53 of the fifth transistor in at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line connected to the pixel driving circuit on the substrate.

[0355] In an exemplary embodiment, in the display substrate provided in FIG4 and FIG6, the orthographic projection of the second extension 533 of the first pole of the fifth transistor in at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate.

[0356] In an exemplary embodiment, in the display substrate provided in FIG4 and FIG6, in at least one pixel driving circuit, the orthographic projection of the second extension 533 of the first pole of the fifth transistor on the substrate is located between the orthographic projection of the first pole 23 of the second transistor on the substrate and the orthographic projection of the first pole 43 of the fourth transistor on the substrate.

[0357] In an exemplary embodiment, in the display substrate provided in FIG6, the electrode connection portion 40 extends at least partially along the first direction D1. At least one electrode connection portion 40 is connected to the electrode body portion 531 in the first electrode of the fifth transistor in one adjacent pixel driving circuit and the third extension portion 534 in the first electrode of the fifth transistor in another adjacent pixel driving circuit.

[0358] In an exemplary embodiment, the orthographic projection of the electrode connection portion 40 on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate.

[0359] In an exemplary embodiment, the second electrode 64 of the sixth transistor and the second electrode 74 of the seventh transistor are integrally formed. The second electrode 64 of the sixth transistor (which is also the second electrode 74 of the seventh transistor) is block-shaped, and the second electrode 64 of the sixth transistor (which is also the second electrode 74 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) through a seventh via.

[0360] In an exemplary embodiment, the first electrode 73 of the seventh transistor is shaped as a strip extending at least partially along the second direction D2. The first electrode 73 of the seventh transistor is connected to the first region of the active pattern of the seventh transistor via an eighth via.

[0361] In an exemplary embodiment, the first electrode 83 of the eighth transistor is separately provided and is in the shape of a strip extending at least partially along the first direction D1. The first electrode 83 of the eighth transistor is connected to the first region of the active pattern of the eighth transistor through a ninth via and to the third initial signal line through a sixteenth via.

[0362] In an exemplary embodiment, the shape of the second initial signal line INITL2 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second initial signal line INITL2 connected to at least one pixel driving circuit on the substrate is located on the side of the orthographic projection of the second reset signal line connected to at least one pixel driving circuit on the substrate that is far from the side of the orthographic projection of the light emission signal line connected to at least one pixel driving circuit on the substrate that is far from the substrate.

[0363] In an exemplary embodiment, the orthographic projection of the first pole 73 of the seventh transistor in at least one pixel driving circuit in the i-th row pixel driving circuit onto the substrate is located on the side of the orthographic projection of the second initial signal line INITL(i) connected to the i-th row pixel driving circuit onto the substrate that is close to the orthographic projection of the second reset signal line connected to the i-th row pixel driving circuit onto the substrate, and the second initial signal line INITL(i) connected to the i-th row pixel driving circuit is connected to the first pole 73 of the seventh transistor in at least one pixel driving circuit in the i-th row pixel driving circuit.

[0364] In an exemplary embodiment, the orthographic projection of the second initial signal line INITL(i+1) connected to the pixel driving circuit of the i+1th row on the substrate is located between the orthographic projection of the second scan signal line connected to the pixel driving circuit of the i-th row on the substrate and the orthographic projection of the first initial signal line connected to the pixel driving circuit of the i-th row on the substrate.

[0365] In an exemplary embodiment, the orthographic projection of the second initial signal line connected to at least one row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the first reset signal line connected to the previous row of pixel driving circuits on the substrate. For example, the orthographic projection of the second initial signal line INITL(i+1) connected to the (i+1)th row of pixel driving circuits on the substrate at least partially overlaps with the orthographic projection of the first reset signal line connected to the (i)th row of pixel driving circuits on the substrate.

[0366] (8) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: depositing a sixth insulating film on a substrate having the aforementioned pattern, patterning the sixth insulating film using a patterning process to form a sixth insulating layer, coating the first planarization film on the sixth insulating layer, and patterning the first planarization film using a patterning process to form a first planarization layer pattern covering the aforementioned pattern. The first planarization layer has a plurality of via patterns. As shown in Figures 35 and 36. Figure 35 is a schematic diagram of the first planarization layer pattern formed in Figure 4, and Figure 36 is a schematic diagram of the first planarization layer pattern formed in Figure 6.

[0367] In an exemplary embodiment, as shown in Figures 35 and 36, in the display substrate provided in Figures 4 and 6, the plurality of via patterns on the first planarization layer pattern include: seventeenth via V17 to nineteenth via V19.

[0368] In an exemplary embodiment, the orthogonal projection of the seventeenth via V17 onto the substrate is within the range of the orthogonal projection of the first electrode of the fourth transistor onto the substrate. The sixth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the first electrode of the fourth transistor. The seventeenth via V17 is configured to allow subsequently formed data signal lines to be connected to the first electrode of the fourth transistor through the via.

[0369] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate. The sixth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the first electrode of the fifth transistor. The eighteenth via V18 is configured to allow a subsequently formed first power line to be connected to the first electrode of the fifth transistor through the via.

[0370] In an exemplary embodiment, the orthogonal projection of the nineteenth via V19 onto the substrate is within the range of the orthogonal projection of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) onto the substrate. The sixth insulating layer within the nineteenth via V19 is etched away, exposing the surface of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor). The nineteenth via V19 is configured to allow the subsequently formed anode connection electrode to be connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the via.

[0371] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer pattern. As shown in Figures 37 to 39, Figure 37 is a schematic diagram of the fifth conductive layer pattern in Figures 4 and 6, Figure 38 is a schematic diagram of Figure 4 after the fifth conductive layer pattern is formed, and Figure 39 is a schematic diagram of Figure 6 after the fifth conductive layer pattern is formed. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0372] In an exemplary embodiment, as shown in Figures 37 to 39, the fifth conductive layer pattern in the display substrates provided in Figures 4 and 6 may include at least: a data signal line Data, a first power supply line VDD, and an anode connection electrode AL located in at least one pixel driving circuit.

[0373] In an exemplary embodiment, multiple first power lines VDD and multiple data signal lines Data are arranged alternately.

[0374] In an exemplary embodiment, the data signal line Data can be a line shape in which the main body extends along the second direction D2, and is electrically connected to the first electrode of the fourth transistor through the seventeenth via.

[0375] In an exemplary embodiment, the anode connection electrode AL is electrically connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the nineteenth via.

[0376] In an exemplary embodiment, the first power line VDD can be a line shape in which the main body extends along the second direction D2. The first power line VDD is electrically connected to the first electrode of the fifth transistor through the eighteenth via.

[0377] In an exemplary embodiment, the first power line VDD to which the pixel driving circuit of the first sub-pixel is connected includes: a plurality of first power blocks DL11, a plurality of second power blocks DL12, and a plurality of first power connection portions DL13. At least one of the first power blocks DL11, the second power blocks DL12, and the first power connection portions DL13 extends at least partially along the second direction D2.

[0378] In an exemplary embodiment, one end of at least one second power block DL12 is connected to at least one first power block DL11 via at least one first power connection portion DL13, and the other end of at least one second power block DL12 is connected to at least one first power block DL11.

[0379] In an exemplary embodiment, at least one of the first power block DL11 and the second power block DL12 has a length along the first direction D1 greater than the length of the first power connection portion DL13 along the first direction D1. The length of the second power block DL12 along the second direction D2 is greater than the length of the first power block DL11 along the second direction D2.

[0380] In an exemplary embodiment, the orthographic projection of the first power block DL11 on the substrate at least partially overlaps with the orthographic projections of the second reset signal line, the third initial signal line, and the first initial signal line on the substrate, and there is no overlap with the orthographic projection of at least one of the second initial signal line and the light emission signal line on the substrate.

[0381] In an exemplary embodiment, the orthographic projection of the second power block DL12 on the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor and the second transistor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first scan signal line, the second scan signal line, the first reset signal line, and the second initial signal line on the substrate.

[0382] In an exemplary embodiment, the orthographic projection of the first pole of the second transistor in the pixel driving circuit of the first sub-pixel onto the substrate is located within the range of the orthographic projection of the second power block DL12 onto the substrate.

[0383] In an exemplary embodiment, the orthographic projection of the first power connection portion DL13 on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of the light emission signal line on the substrate.

[0384] In an exemplary embodiment, the first power line VDD to which the pixel driving circuit of the second sub-pixel is connected includes: a plurality of third power blocks DL21 and a plurality of second power connection portions DL22. At least one of the third power blocks DL21 and the second power connection portions DL22 extends at least partially along the second direction D2.

[0385] In an exemplary embodiment, a plurality of third power blocks DL21 and a plurality of second power connection parts DL22 are arranged alternately and connected to each other.

[0386] In an exemplary embodiment, the length of the third power block DL21 along the first direction D1 is greater than the length of the second power connection portion DL22 along the first direction D1.

[0387] In an exemplary embodiment, the orthographic projection of the third power block DL21 on the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor and the second transistor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first scan signal line, the second scan signal line, the first reset signal line, and the second initial signal line on the substrate.

[0388] In an exemplary embodiment, the orthographic projection of the first pole of the second transistor of the pixel driving circuit of the second sub-pixel onto the substrate is within the range of the orthographic projection of the third power block DL21 onto the substrate.

[0389] In an exemplary embodiment, the orthographic projection of the second power connection portion DL22 on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first initial signal line, the second reset signal line, the third initial signal line, and the light emission signal line on the substrate.

[0390] In an exemplary embodiment, the first power line VDD to which the pixel driving circuit of the third sub-pixel is connected includes: a plurality of fourth power blocks DL31 and a plurality of third power connection portions DL32. At least one of the fourth power blocks DL31 and the third power connection portions DL32 extends at least partially along the second direction D2.

[0391] In an exemplary embodiment, a plurality of fourth power blocks DL31 and a plurality of third power connection parts DL32 are arranged alternately and connected to each other.

[0392] In an exemplary embodiment, the length of the fourth power block DL31 along the first direction D1 is greater than the length of the third power connection portion DL32 along the first direction D1.

[0393] In an exemplary embodiment, the orthographic projection of the fourth power block DL31 on the substrate at least partially overlaps with the orthographic projection of the first pole of the capacitor and the second transistor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first scan signal lines and the second scan signal lines on the substrate.

[0394] In an exemplary embodiment, the orthographic projection of the first pole of the second transistor of the pixel driving circuit of the third sub-pixel onto the substrate is within the range of the orthographic projection of the fourth power block DL31 onto the substrate.

[0395] In an exemplary embodiment, the orthographic projection of the third power connection portion DL32 on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first initial signal line, the second initial signal line, the first reset signal line, the second reset signal line, the third initial signal line, and the light emission signal line on the substrate.

[0396] In an exemplary embodiment, the overlapping area of ​​the orthographic projection of the fourth power block DL31 on the substrate with the capacitor in at least one pixel driving circuit is greater than the overlapping area of ​​the orthographic projection of at least one of the second power block DL12 and the third power block DL21 on the substrate with the capacitor in at least one pixel driving circuit.

[0397] (10) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: depositing a seventh insulating film on a substrate having the aforementioned pattern, patterning the seventh insulating film using a patterning process to form a seventh insulating layer, coating a second planarization film on the seventh insulating layer, and patterning the second planarization film using a patterning process to form a second planarization layer pattern covering the aforementioned pattern, wherein the second planarization layer has a plurality of via patterns. As shown in Figures 40 and 41, Figure 40 is a schematic diagram of Figure 4 after the second planarization layer pattern has been formed, and Figure 41 is a schematic diagram of Figure 6 after the second planarization layer pattern has been formed.

[0398] In an exemplary embodiment, the plurality of via patterns on the second planarization layer pattern include: a twentieth via V20.

[0399] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is within the range of the orthographic projection of the anode connection electrode onto the substrate. The seventh insulating layer within the twentieth via V20 is etched away, exposing the surface of the anode connection electrode. The twentieth via V20 is configured to allow the anode of a subsequently formed light-emitting device to be connected to the anode connection electrode through the via.

[0400] At this point, the circuit structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include multiple pixel driving circuits and multiple signal lines connected to the pixel driving circuits. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate. The pixel driving circuit for at least one sub-pixel includes at least one P-type transistor, at least one N-type transistor, and at least one capacitor, the capacitor including a first electrode and a second electrode.

[0401] The circuit structure layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a first planarization layer, a fifth conductive layer, a seventh insulating layer, and a second planarization layer, which are sequentially disposed on the substrate.

[0402] In an exemplary embodiment, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0403] In an exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0404] In an exemplary embodiment, at least one of the first to fifth conductive layers may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0405] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0406] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials.

[0407] In an exemplary embodiment, after the circuit structure layer is fabricated, a light-emitting structure layer is fabricated on the circuit structure layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0408] (11) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer pattern may include: depositing a sixth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the sixth conductive thin film using a patterning process to form a sixth conductive layer pattern. As shown in Figures 42 to 44, Figure 42 is a schematic diagram of the sixth conductive layer pattern in Figures 4 and 6, Figure 43 is a schematic diagram of Figure 4 after the formation of the sixth conductive layer pattern, and Figure 44 is a schematic diagram of Figure 6 after the formation of the sixth conductive layer pattern.

[0409] In an exemplary embodiment, as shown in Figures 42 to 44, the sixth conductive layer pattern may include at least: anodes 50 of a plurality of light-emitting devices.

[0410] In an exemplary embodiment, the area of ​​the anode 510 of the light-emitting device of the first sub-pixel is smaller than the area of ​​the anode 520 of the light-emitting device of the second sub-pixel, and the area of ​​the anode 520 of the light-emitting device of the second sub-pixel is smaller than the area of ​​the anode 530 of the light-emitting device of the third sub-pixel.

[0411] In an exemplary embodiment, at least one of the anodes 510 of the light-emitting device of the first sub-pixel and the anode 520 of the light-emitting device of the second sub-pixel has a length along the second direction D2 that is less than the length along the second direction D2 of the anode 530 of the light-emitting device of the third sub-pixel.

[0412] In an exemplary embodiment, the orthographic projection of the anode 510 of the light-emitting device of at least one first sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first power block in the first power line connected to the pixel driving circuit of at least one first sub-pixel on the substrate. Exemplarily, the orthographic projection of the first power block in the first power line connected to the pixel driving circuit of at least one first sub-pixel on the substrate is located within the range of the orthographic projection of the anode of the light-emitting device of at least one first sub-pixel on the substrate.

[0413] In an exemplary embodiment, the orthographic projection of the anode 520 of the light-emitting device of at least one second sub-pixel on the substrate at least partially overlaps with the orthographic projection of the second power block in the first power line connected to the pixel driving circuit of at least one first sub-pixel on the substrate, and at least partially overlaps with the orthographic projection of at least one data signal line on the substrate.

[0414] In an exemplary embodiment, the orthographic projection of the anode 530 of the light-emitting device of at least one third sub-pixel on the substrate at least partially overlaps with at least one structure in the third power block and the second power connection portion of the first power line connected to at least one data signal line and the pixel driving circuit of at least one second sub-pixel, as well as the orthographic projection of the fourth power block connected to the pixel driving circuit of at least one third sub-pixel on the substrate.

[0415] In an exemplary embodiment, a first power line connected to the pixel driving circuit of at least one second sub-pixel that overlaps with the anode of the light-emitting device of at least one third sub-pixel and a first power line connected to the pixel driving circuit of at least one third sub-pixel that overlaps with the anode of the light-emitting device of at least one third sub-pixel are at least partially symmetrical with respect to a straight line extending along the second direction D2.

[0416] (12) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer pattern covering the aforementioned pattern, wherein the pixel definition layer has a plurality of via patterns. As shown in Figures 45 and 46, Figure 45 is a schematic diagram of the pixel definition layer pattern formed in Figure 4, and Figure 46 is a schematic diagram of the pixel definition layer pattern formed in Figure 6.

[0417] In an exemplary embodiment, the plurality of via patterns on the pixel definition layer pattern include: pixel openings H. Pixel openings H include: a first pixel opening H1, a second pixel opening H2, and a third pixel opening H3.

[0418] In an exemplary embodiment, the orthographic projection of the pixel opening H onto the substrate is within the range of the orthographic projection of the anode of at least one light-emitting device onto the substrate. The pixel opening H exposes the surface of the anode of at least one light-emitting device. The pixel opening H is configured to allow the organic light-emitting layer of the subsequently formed light-emitting device to be connected to the anode of at least one light-emitting device through the via.

[0419] In an exemplary embodiment, the area of ​​the pixel opening of the anode of the light-emitting device exposing the first sub-pixel is smaller than the area of ​​the pixel opening of the anode of the light-emitting device exposing the second sub-pixel, and the area of ​​the pixel opening of the anode of the light-emitting device exposing the second sub-pixel is smaller than the area of ​​the pixel opening of the anode of the light-emitting device exposing the third sub-pixel.

[0420] In an exemplary embodiment, the first pixel opening H1 exposes the anode 510 of the light-emitting device of the first sub-pixel P1, and its orthographic projection on the substrate is within the range of the orthographic projection of the main body portion of the anode 510 of the light-emitting device of the first sub-pixel P1 on the substrate. The centerline extending from the first pixel opening H1 along the second direction D2 coincides with the centerline extending from the anode body portion of the anode 510 of the light-emitting device of the first sub-pixel P1.

[0421] In an exemplary embodiment, the second pixel opening H2 exposes the anode 520 of the light-emitting device of the second sub-pixel P2, and its orthographic projection on the substrate is within the range of the orthographic projection of the main body portion of the anode 520 of the light-emitting device of the second sub-pixel P2 on the substrate. The centerline extending from the second pixel opening H2 along the second direction D2 coincides with the centerline extending from the anode body portion of the anode 520 of the light-emitting device of the second sub-pixel P2.

[0422] In an exemplary embodiment, the third pixel opening H3 exposes the anode of the light-emitting device of the third sub-pixel P3, and its orthographic projection on the substrate is within the range of the orthographic projection of the main body portion of the anode of the light-emitting device of the third sub-pixel P3 on the substrate. The centerline extending from the third pixel opening H3 along the second direction D2 coincides with the centerline extending from the anode body portion of the anode 530 of the light-emitting device of the third sub-pixel P3.

[0423] In an exemplary embodiment, the orthographic projection of at least one first pixel opening H1 onto the substrate at least partially overlaps with the orthographic projection of a first power block on the substrate in a first power line connected to the pixel driving circuit of at least one first sub-pixel P1. The centerline extending along the second direction of at least one first pixel opening H1 may coincide with the centerline extending along the second direction of the first power block.

[0424] In an exemplary embodiment, the orthographic projection of the first power block in the first power line to which the pixel driving circuit of at least one first sub-pixel P1 is connected on the substrate is located within the range of the orthographic projection of at least one first pixel opening H1 on the substrate.

[0425] In this disclosure, at least one first pixel opening H1 is located below a first power block DL11 with a large area, which at least partially flattens the area below the first pixel opening H1, ensuring that the metal structure below the first pixel opening is symmetrical. This can improve the color shift problem caused by the asymmetry of the metal structure below the first pixel opening and ensure that the light output of the first sub-pixel P1 is uniform.

[0426] In an exemplary embodiment, the orthographic projection of at least one second pixel opening H2 on the substrate at least partially overlaps with the orthographic projection of a second power block in a first power line connected to the pixel driving circuit of at least one first sub-pixel P1 on the substrate, and at least partially overlaps with the orthographic projection of at least one data signal line on the substrate. The centerline extending along the second direction of at least one second pixel opening H2 coincides with the centerline extending along the second direction of the second power block.

[0427] In this disclosure, at least one second pixel opening H2 is located below a second power block with a large area. The area below at least one second pixel opening H2 is at least partially flattened to ensure that the metal structure (first power line) below the second pixel opening is symmetrical. This can improve the color shift problem caused by the asymmetry of the metal structure below the second pixel opening and ensure that the light output of the second sub-pixel P2 is uniform.

[0428] In an exemplary embodiment, the orthographic projection of at least one third pixel opening H3 on the substrate at least partially overlaps with at least one structure in the third power block and the second power connection portion of the first power line connected to at least one data signal line and the pixel driving circuit of at least one second sub-pixel P2, and the orthographic projection of the fourth power block connected to the pixel driving circuit of at least one third sub-pixel P3 on the substrate.

[0429] In an exemplary embodiment, a first power line connected to the pixel driving circuit of at least one second sub-pixel P2 that overlaps with at least one third pixel opening H3 and a first power line connected to the pixel driving circuit of at least one third sub-pixel P3 that overlaps with at least one third pixel opening are at least partially symmetrical with respect to a straight line extending along the second direction D2.

[0430] (13) On a substrate with a pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern. On a substrate with an organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned by a patterning process to form a seventh conductive layer.

[0431] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0432] In an exemplary embodiment, the seventh conductive layer may include at least the cathodes of a plurality of light-emitting devices.

[0433] At this point, the luminescent structure layer has been successfully fabricated on the substrate.

[0434] In an exemplary embodiment, the sixth conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0435] In an exemplary embodiment, the seventh conductive layer can be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0436] In an exemplary embodiment, the subsequent preparation process may include: forming an encapsulation structure layer on the light-emitting structure layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0437] The display substrate described in this embodiment can be used in display products of any resolution.

[0438] This disclosure also provides a wearable device, including: a display substrate provided in any of the foregoing embodiments.

[0439] In an exemplary embodiment, the wearable device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0440] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0441] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0442] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

A display substrate, comprising: The substrate and a plurality of sub-pixels disposed on the substrate, at least one sub-pixel including: a pixel driving circuit, the pixel driving circuit including: at least one transistor, the at least one transistor including: a driving transistor and a compensation transistor, the transistor including: an active pattern, a control electrode, a first electrode and a second electrode, the active pattern including: a first region and a second region, the first electrode of the compensation transistor being connected to the control electrode of the driving transistor and the first region of the active pattern of the compensation transistor respectively, and the second electrode of the compensation transistor being connected to the second electrode of the driving transistor and the second region of the active pattern of the compensation transistor respectively; The area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of at least one sub-pixel is greater than the area of ​​the second region of the active pattern of the compensation transistor, and the areas of the first regions of the active patterns of the compensation transistors in the pixel driving circuits of at least two sub-pixels are different. The display substrate according to claim 1, wherein, The sub-pixel includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the first sub-pixel emits red light, the second sub-pixel emits green light, and the third sub-pixel emits blue light; The area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of at least one of the first and second sub-pixels is greater than the area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of the third sub-pixel. The display substrate according to claim 2 further includes: Multiple first scan signal lines disposed on a substrate, wherein the at least one transistor further includes a write transistor, the control electrode of which is electrically connected to at least one first scan signal line; The first scan signal line includes: a main signal line and a plurality of gate blocks, the plurality of gate blocks being located on the same side of the main signal line and connected to the main signal line, and at least a portion of the main signal line extending along a first direction; The first region of the active pattern of the compensation transistor in the pixel driving circuit of the at least one sub-pixel at least partially overlaps with the orthographic projection of at least one gate block of at least one first scan signal line on the substrate. The display substrate according to claim 3, wherein, The overlap area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of at least one of the first and second sub-pixels with at least one gate block of at least one first scan signal line is greater than the overlap area of ​​the first region of the active pattern of the compensation transistor in the pixel driving circuit of the third sub-pixel with at least one gate block of at least one first scan signal line. The display substrate according to claim 2 further includes: Multiple second scan signal lines are disposed on the substrate, and the control electrode of the compensation transistor is connected to at least one of the second scan signal lines; The second scan signal line includes: a first scan section and a second scan section, wherein the second scan section is located on the side of the first scan section away from the substrate and is connected to the first scan section; The orthographic projection of the first scanning unit on the substrate and the orthographic projection of the second scanning unit on the substrate at least partially overlap. According to claim 5, the display substrate, wherein, The orthographic projection of the second scanning unit onto the substrate is within the range of the orthographic projection of the first scanning unit onto the substrate. The display substrate according to claim 2 further includes: Multiple first power lines are disposed on the substrate, and the at least one transistor further includes: a light-emitting transistor, the first electrode of the light-emitting transistor is connected to at least one first power line, and the second electrode of the light-emitting transistor is connected to the first electrode of the driving transistor; The first electrode of the light-emitting transistor includes: an electrode body portion, a first extension portion, a second extension portion, and a third extension portion, wherein the first extension portion, the second extension portion, and the third extension portion are respectively connected to the electrode body portion, and the first extension portion and at least one of the second extension portion and the third extension portion are located on different sides of the electrode body portion. The electrode body portion extends at least partially along a second direction, at least one of the first extension portion and the second extension portion extends at least partially along a second direction, and the third extension portion extends at least partially along a first direction; The minimum width of at least one of the electrode body and the third extension in the first direction is greater than the maximum width of at least one of the first extension and the second extension in the first direction, and the width of the first extension in the first direction is greater than the width of the second extension in the first direction. The display substrate according to claim 7 further comprises: The pixel driving circuit includes multiple light-emitting signal lines, multiple first scan signal lines, and multiple data signal lines disposed on a substrate. At least one transistor further includes a write transistor. The control electrode of the light-emitting transistor is connected to at least one light-emitting signal line, the control electrode of the write transistor is connected to at least one first scan signal line, and the first electrode of the write transistor is connected to at least one data signal line. The pixel driving circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate. The second electrode plate has a via exposing the first electrode plate. The first electrode of the light-emitting transistor in the pixel driving circuit of at least one sub-pixel is connected to the second electrode plate of the capacitor. For a pixel driving circuit of at least one sub-pixel, the orthographic projection of the electrode body and the third extension on the substrate at least partially overlaps with the orthographic projection of the capacitor on the substrate, the orthographic projection of the first extension on the substrate at least partially overlaps with the orthographic projection of the light emission signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the second extension on the substrate at least partially overlaps with the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate. A first straight line passes through the via, the first straight line being a straight line extending along a second direction and passing through the third extension. The display substrate according to claim 8, wherein, The orthographic projection of the second extension on the substrate lies between the orthographic projection of the first electrode of the compensation transistor on the substrate and the orthographic projection of the first electrode of the write transistor on the substrate. The display substrate according to claim 9 further includes: A plurality of capacitor connection portions disposed on a substrate, wherein at least one capacitor connection portion extends at least partially along a first direction; The second plates of capacitors in two adjacent pixel driving circuits arranged along the first direction are connected by at least one capacitor connection part. The first poles of the light-emitting transistors in two adjacent pixel driving circuits arranged along the first direction are spaced apart. The capacitor connection part is disposed on the same layer as the second plate of the capacitor. The display substrate according to claim 9 further includes: A plurality of electrode connection portions disposed on a substrate, wherein at least one electrode connection portion extends at least partially along a first direction; The second plates of capacitors in two adjacent pixel driving circuits arranged along the first direction are spaced apart. The first electrodes of the light-emitting transistors in two adjacent pixel driving circuits arranged along the first direction are connected by at least one electrode connection portion. The electrode connection portion is disposed on the same layer as the first electrode of the light-emitting transistor. The display substrate according to claim 11, wherein, The orthographic projection of at least one electrode connection on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate. The display substrate according to claim 11, wherein, At least one electrode connection portion is connected to the electrode body portion of the first electrode of the light-emitting transistor in one of the adjacent pixel driving circuits and the third extension portion of the first electrode of the light-emitting transistor in another adjacent pixel driving circuit. The display substrate according to claim 2 further includes: Multiple first scan signal lines, multiple second scan signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple first initial signal lines, multiple second initial signal lines, multiple third initial signal lines, and multiple light emission signal lines are disposed on the substrate. The pixel driving circuit of at least one sub-pixel is connected to the first scan signal lines, second scan signal lines, first reset signal lines, second reset signal lines, first initial signal lines, second initial signal lines, third initial signal lines, and light emission signal lines, respectively. At least a portion of at least one of the plurality of first scan signal lines, the plurality of second scan signal lines, the plurality of first reset signal lines, the plurality of second reset signal lines, the plurality of first initial signal lines, the plurality of second initial signal lines, the plurality of third initial signal lines, and the plurality of light emission signal lines extends along a first direction; The orthographic projections of at least one pixel driving circuit connected to the second initial signal line, the second reset signal line, the light emission signal line, the first scan signal line, the second scan signal line, the first reset signal line, and the first initial signal line on the substrate are arranged sequentially along the second direction. The orthographic projection of the third initial signal line connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line on the substrate. The display substrate according to claim 14 further comprises: Multiple first power lines and multiple data signal lines, and a pixel driving circuit for at least one sub-pixel is connected to the first power lines and the data signal lines respectively. The pixel driving circuit also includes a capacitor. The plurality of first power lines and the plurality of data signal lines are arranged alternately, and at least a portion of at least one of the plurality of first power lines and the plurality of data signal lines extends along the second direction; At least one first power line includes: a power block and a power connection portion, wherein the power block and the power connection portion extend at least partially along a second direction, and the length of the power block along the first direction is greater than the length of the power connection portion along the first direction; The orthographic projection of at least one power block in at least one first power line onto the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor and compensation transistor in at least one pixel driving circuit onto the substrate. The display substrate according to claim 15, wherein, The orthographic projection of the first electrode of the compensation transistor in at least one pixel driving circuit onto the substrate lies within the range of the orthographic projection of at least one power block in at least one first power line onto the substrate. The display substrate according to claim 16, wherein, The power supply block in the first power supply line to which the pixel driving circuit of the first sub-pixel is connected includes: a plurality of first power supply blocks and a plurality of second power supply blocks; the power supply connection part in the first power supply line to which the pixel driving circuit of the first sub-pixel is connected includes: a plurality of first power supply connection parts. One end of at least one second power block is connected to at least one first power block via at least one first power connection part, and the other end of at least one second power block is connected to at least one first power block. The length of the second power block along the second direction is greater than the length of the first power block along the second direction. The orthographic projection of the first power block on the substrate at least partially overlaps with the orthographic projections of the second reset signal line, the third initial signal line, and the first initial signal line on the substrate. The orthographic projection of the second power block on the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor and the second transistor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first scan signal line, the second scan signal line, the first reset signal line and the second initial signal line on the substrate. The orthographic projection of the first power connection portion on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of the light-emitting signal line on the substrate. The display substrate according to claim 17, wherein, The power block of the first power line connected to the pixel driving circuit of the second sub-pixel includes: a plurality of third power blocks, and the power connection part of the first power line connected to the pixel driving circuit of the second sub-pixel includes: a plurality of second power connection parts. The plurality of third power blocks and the plurality of second power connection parts are arranged alternately and connected to each other. The orthographic projection of the third power block on the substrate also at least partially overlaps with the orthographic projection of at least one of the first scan signal line, the second scan signal line, the first reset signal line, and the second initial signal line on the substrate. The orthographic projection of the second power connection portion on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first initial signal line, the second reset signal line, the third initial signal line, and the light emission signal line on the substrate. The display substrate according to claim 18, wherein, The power block in the first power line to which the pixel driving circuit of the third sub-pixel is connected includes: a plurality of fourth power blocks; the power connection part in the first power line to which the pixel driving circuit of the third sub-pixel is connected includes: a plurality of third power connection parts; the plurality of fourth power blocks and the plurality of third power connection parts are arranged alternately and connected to each other. The orthographic projection of the fourth power block on the substrate also at least partially overlaps with the orthographic projection of at least one of the first and second scan signal lines on the substrate. The orthographic projection of the third power connection portion on the substrate at least partially overlaps with the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate, and at least partially overlaps with the orthographic projection of at least one of the first initial signal line, the second initial signal line, the first reset signal line, the second reset signal line, the third initial signal line, and the light emission signal line on the substrate. The display substrate according to claim 19, wherein, The overlapping area of ​​the orthographic projection of the fourth power block on the substrate and the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate is greater than the overlapping area of ​​the orthographic projection of the second power block and at least one of the third power blocks on the substrate and the orthographic projection of the capacitor in at least one pixel driving circuit on the substrate. The display substrate according to claim 19, wherein, At least one sub-pixel further includes: a light-emitting device and a pixel definition layer, wherein the light-emitting device includes: an anode, and the pixel definition layer includes: a first pixel opening, a second pixel opening, and a third pixel opening; The area of ​​the anode of the light-emitting device of the first sub-pixel is smaller than the area of ​​the anode of the light-emitting device of the second sub-pixel, and the area of ​​the anode of the light-emitting device of the second sub-pixel is smaller than the area of ​​the anode of the light-emitting device of the third sub-pixel. The length of at least one anode of the light-emitting device of the first sub-pixel and the light-emitting device of the second sub-pixel along the second direction is less than the length of the anode of the light-emitting device of the third sub-pixel along the second direction; The first pixel opening exposes the anode of the light-emitting device of the first sub-pixel, the second pixel opening exposes the anode of the light-emitting device of the second sub-pixel, and the third pixel opening exposes the anode of the light-emitting device of the third sub-pixel. The display substrate according to claim 21, wherein, The orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the first power block on the substrate in the first power line connected to the pixel driving circuit of at least one first sub-pixel. The display substrate according to claim 22, wherein, The orthographic projection of the first power block in the first power line connected to the pixel driving circuit of at least one first sub-pixel on the substrate is located within the range of the orthographic projection of the opening of at least one first pixel on the substrate. The display substrate according to claim 21, wherein, The orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projection of the second power block in the first power line connected to the pixel driving circuit of at least one first sub-pixel on the substrate, and at least partially overlaps with the orthographic projection of at least one data signal line on the substrate. The display substrate according to claim 21, wherein, The orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with at least one structure in the third power block and the second power connection portion of the first power line connected to at least one data signal line and the pixel driving circuit of at least one second sub-pixel, and the orthographic projection of the fourth power block connected to the pixel driving circuit of at least one third sub-pixel on the substrate. The display substrate according to claim 25, wherein, A portion of the first power line connected to the pixel driving circuit of at least one second sub-pixel that overlaps with at least one third pixel opening, and a portion of the first power line connected to the pixel driving circuit of at least one third sub-pixel that overlaps with at least one third pixel opening, are at least partially symmetrical with respect to a straight line extending along the second direction. The display substrate according to claim 15, wherein, At least one transistor includes at least one P-type transistor and at least one N-type transistor, the capacitor includes a first plate and a second plate, the at least one N-type transistor includes a first control electrode and a second control electrode, and the second scan signal line includes a first scan section and a second scan section. The display substrate further includes: a circuit structure layer disposed on the substrate, the circuit structure layer including: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; The first semiconductor layer includes at least: an active pattern of at least one P-type transistor of at least one pixel driving circuit; The first conductive layer includes at least: multiple first scan signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple light emission signal lines, and the control electrode of at least one P-type transistor located in at least one pixel driving circuit and the first plate of a capacitor; The second conductive layer includes at least: a first scanning section consisting of a plurality of first initial signal lines, a plurality of second scanning signal lines, a second plate of a capacitor located in at least one pixel driving circuit, and a first control electrode of at least one N-type transistor; The second semiconductor layer includes at least: an active pattern of at least one N-type transistor located in at least one pixel driving circuit; The third conductive layer includes at least: a second scanning section with multiple second scanning signal lines, multiple third initial signal lines, and a second control electrode of at least one N-type transistor located in at least one pixel driving circuit; The fourth conductive layer includes at least: multiple second initial signal lines and a first and second electrode of at least one transistor located in at least one pixel driving circuit; The fifth conductive layer includes at least: multiple data signal lines and multiple first power lines. A wearable device, comprising: The display substrate as described in any one of claims 1 to 27.

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