Pixel element array and integrated circuit

Abstract

The utility model provides a pixel element array and an integrated circuit, the integrated circuit comprises a plurality of floating diffusion regions, and the floating diffusion regions are connected to a common contact through patterned conductive layer ohms, thereby avoiding the need for an independent contact of each floating diffusion region. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and conductive layers stacked on each other in an alternating manner. A contact electrode is disposed over and in direct (e.g., direct and ohmic) contact with the conductive layer. Conductive layers are connected directly (e.g., directly and ohmically) to respective surfaces of each of the plurality of floating diffusion regions. The respective surfaces connected by the conductive layers are coplanar with each other. Each floating diffusion region may be associated with a respective pixel of a pixel array of an image sensor.

Description

Technical Field

[0001] The utility model relates to a pixel element array and an integrated circuit. Background Art

[0002] Integrated circuits (ICs) with image sensors are widely used in modern electronic devices, such as cameras and mobile phones. In recent years, complementary metal-oxide semiconductor (CMOS) image sensors have begun to be widely used, largely replacing charge-coupled device (CCD) image sensors. Compared with CCD image sensors, CMOS image sensors have the advantages of low power consumption, small size, fast data processing speed, direct data output, and low manufacturing cost, and are becoming more and more popular. Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors. Utility Model Content

[0003] An embodiment of the utility model provides an integrated circuit, wherein the integrated circuit includes: a semiconductor substrate, including a first semiconductor substrate region and a second semiconductor substrate region; a first floating diffusion region, located in the first semiconductor substrate region; a second floating diffusion region, located in the second semiconductor substrate region; an isolation region, arranged between the first semiconductor substrate region and the second semiconductor substrate region; a gate structure, arranged above the semiconductor substrate and adjacent to the first semiconductor substrate region; and a conductive layer, directly connected to the first floating diffusion region and the second floating diffusion region, wherein the gate structure has a maximum height greater than that of the conductive layer.

[0004] An embodiment of the utility model provides a pixel element array, comprising: an isolation region; a plurality of pixel components, adjacent to the isolation region along different surfaces of the isolation region, each of the plurality of pixel components comprising a respective floating diffusion region; a dielectric layer, extending above the isolation region and having side walls forming openings above corresponding floating diffusion regions within the plurality of pixel components; a conductive layer, extending from above the dielectric layer to directly and ohmically connect to a corresponding first floating diffusion region surface of each corresponding floating diffusion region adjacent to each of the plurality of pixel components; and a contact etch stop layer, disposed on and along the side walls of the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1 A cross-sectional elevation view of some embodiments of a portion of a pixel circuit array of an image sensor is shown.

[0007] Figure 2 Cross-sectional plan views of some embodiments of a portion of a pixel circuit array of an image sensor are shown.

[0008] Figure 3 A cross-sectional elevation view of some embodiments of a larger portion of a pixel circuit array of an image sensor is shown.

[0009] Figure 4 A cross-sectional plan view of some embodiments of a portion of a pixel circuit array of an image sensor is shown, showing a conductive layer connecting multiple floating diffusions to a common contact.

[0010] Figure 5 A top view of some embodiments of a portion of a pixel circuit array of an image sensor is shown, showing a conductive layer connecting multiple floating diffusions to a common contact.

[0011] Figure 6 A top view of some embodiments of a portion of a pixel circuit array of an image sensor is shown, showing a conductive layer connecting multiple floating diffusions to a common contact.

[0012] Figure 7 A top view of some embodiments of a portion of a pixel circuit array of an image sensor is shown, showing a conductive layer connecting multiple floating diffusions to a common contact.

[0013] Figure 8 Cross-sectional plan views of some embodiments of a portion of a pixel circuit array of an image sensor are shown.

[0014] Figures 9 to 25 are cross-sectional elevation views illustrating some embodiments of a series of incremental fabrication steps as a series of cross-sectional views.

[0015] Fig.26 A flow chart is shown illustrating some embodiments of a method in flow chart form according to some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "underlying," "below," "lower," "overlying," "upper," or the like may be used herein to describe the relationship of one component or feature illustrated in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0018] Electronic image sensors are used in a variety of devices to provide cameras and other imaging capabilities for visible light and other parts of the electromagnetic spectrum (e.g., near infrared light). As image sensors are required to provide higher resolution imaging, faster imaging, and lower power consumption, new technologies are needed to provide improved image sensor performance.

[0019] When producing semiconductor components (e.g., integrated chips) by fabricating different structures of semiconductor devices thereon, accurate positioning of the structures can be difficult to achieve. The challenges increase as the photodiode pitch shrinks because the features positioned relative to each other are smaller. For example, smaller pixel circuits increase the difficulty of precise overlay control to provide contact landing on each floating diffusion area. In addition, the closely spaced contacts for each floating diffusion result in an array of metal contact structures arranged in close proximity to each other in the dielectric material, which increases unwanted parasitic capacitance between adjacent floating diffusions. A new solution is needed to reduce such challenges and problems and provide better manufacturability and improved image sensor performance.

[0020] In accordance with at least one embodiment, a common connection is provided to multiple floating diffusion regions of an integrated circuit. Such a common connection can be provided by a direct electrical connection (e.g., ohmic coupling) between a conductive layer (e.g., conductive interconnect layer M0) and multiple floating diffusion regions (e.g., n-type semiconductor regions) without inserting an elongated electrical conductor (e.g., a via or contact) through a dielectric material, close to other elongated electrical conductors. Thus, parasitic capacitance present between elongated electrical conductors that are generally oriented in parallel and separated by dielectric material can be mitigated. The reduction in parasitic capacitance can enable higher performance of image sensors even at higher pixel densities.

[0021] In some embodiments, a conductive layer can provide common electrical interconnection of multiple floating diffusion regions of multiple photodiodes of an image sensor. Contacts can be formed to connect directly to the conductive layer (e.g., via ohmic coupling), avoiding the need for multiple separate contacts for multiple floating diffusion regions. For example, if each pixel circuit has its own contact extending through the interlayer dielectric, parasitic capacitance will exist at the contacts of adjacent floating diffusion regions, and more such parasitic capacitance will be more severe as the pixel pitch decreases to increase pixel density and image sensor resolution. Using a conductive layer to contact multiple floating diffusion regions can reduce parasitic capacitance as pixel design rules are scaled down.

[0022] Figure 1 A cross-sectional elevation view of some embodiments of a portion 100 of a pixel circuit array of an image sensor is shown. Figure 2 The diagonally extending dashed line 1-1 shows Figure 1 . The isolation region 102 is formed in the semiconductor substrate to isolate the semiconductor substrate region 107 of the first pixel from the semiconductor substrate region 127 of the second pixel. As an example, the isolation region 102 can be an oxide dielectric region, a shallow trench isolation region, a deep trench isolation region, etc. The floating diffusion region 101 is formed in the semiconductor substrate region 107. The floating diffusion region 101 extends from the first surface of the semiconductor substrate region 107 into the semiconductor substrate region 107. The floating diffusion region 121 is formed in the semiconductor substrate region 127. The floating diffusion region 121 extends from the first surface of the semiconductor substrate region 127 into the semiconductor substrate region 127. In some embodiments, the first semiconductor substrate region 107 and the semiconductor substrate region 127 are p-type regions (e.g., regions doped with p-type dopants). In some embodiments, the floating diffusion region 101 is an n-type region (e.g., a region doped with n-type dopants).

[0023] The dielectric layer 108 is adjacent to the first surface of the semiconductor substrate region 107 and the first surface of the semiconductor substrate region 127. A hole is provided in the dielectric layer 108 at the location of the floating diffusion regions 101 and 121. The conductive layer 113 is disposed on a portion of the first dielectric layer 108, over the floating diffusion region 101, and over the floating diffusion region 121, electrically connecting the first surface of the floating diffusion region 101 to the first surface of the floating diffusion region 121. The contact etch stop layer 116 is disposed directly over and in contact with the conductive layer 113, and is disposed directly over and in contact with the portion of the dielectric layer 108 not covered by the conductive layer 113. The interlayer dielectric region 117 is disposed over and in contact with the contact etch stop layer 116.

[0024] An opening is formed through the interlayer dielectric region 117 and the contact etch stop layer 116, and the opening extends to a portion of the first surface of the conductive layer 113. A contact 118 of a conductive material (e.g., metal) is formed in the opening to provide a partial electrical connection extending from the first surface of the conductive layer 113 to the first surface of the interlayer dielectric region 117, the first surface of the interlayer dielectric region 117 being opposite to a second surface in contact with the contact etch stop layer 116.

[0025] Figure 2 A cross-sectional plan view of some embodiments of a portion 200 of a pixel circuit array of an image sensor is shown. Figure 1 The dashed line 2-2 shows Figure 2 The cross section shown in . Figure 1 shown in and Figure 2 Outside the components that the dashed line 1-1 crosses, Figure 2 The other components in the Figure 1 Icons outside the plane.

[0026] Floating diffusion region 141 is shown as being formed within semiconductor substrate region 147. Floating diffusion region 161 is shown as being formed within semiconductor substrate region 167. Semiconductor substrate region 107, semiconductor substrate region 127, semiconductor substrate region 147, and semiconductor substrate region 167 are isolated from one another by isolation region 102. Floating diffusion region 101 within semiconductor substrate region 107, floating diffusion region 121 within semiconductor substrate region 127, floating diffusion region 141 within semiconductor substrate region 147, and floating diffusion region 161 within semiconductor substrate region 167 illustrate a portion 200 of a pixel cell array of an image sensor. The pixel cell array may be extended to include more than 100 pixels. Figure 2 Many pixels are shown.

[0027] Various examples of patterns of conductive layer 113 that electrically connect floating diffusion area 101, floating diffusion area 121, floating diffusion area 141, and floating diffusion area 161 together to allow the use of a common electrical contact are shown in dashed lines. As an example, a portion of conductive layer 113 may be located between and connect floating diffusion area 101 and floating diffusion area 161. As another example, a portion of conductive layer 113 may be located between and connect floating diffusion area 161 and floating diffusion area 121. As another example, a portion of conductive layer 113 may be located between and connect floating diffusion area 121 and floating diffusion area 141. As yet another example, a portion of conductive layer 113 may be located between and connect floating diffusion area 141 and floating diffusion area 101. As another example, a portion of conductive layer 113 may be located between and connect floating diffusion area 101 and floating diffusion area 121. As another example, a portion of conductive layer 113 may be located between and connect floating diffusion area 141 and floating diffusion area 161. A combination of multiple such examples may connect more than two (e.g., three, four, or more) floating diffusion regions together to share a common connection. The connection provided by the pattern of conductive layer 113 is not limited to a thin rectangular area between pairs of floating diffusion regions, but may include any suitable geometry or shape, such as a polygon covering all of the multiple floating diffusion regions to be connected, one or more portions of the polygon being removed to form one or more holes, curved features (e.g., arc features), straight line features, combinations thereof, and the like.

[0028] In various embodiments, the conductive layer 113 may be formed of a conductive material, such as a metal, a metal compound (e.g., a metal nitride), etc. As an example, the conductive layer may include titanium nitride (TiN), titanium and titanium nitride (Ti / TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), one or more other suitable conductive materials, or a combination thereof. The formation and patterning of the conductive layer 113, its interconnection with a plurality of floating diffusion regions, and the formation and interconnection of common contacts may be achieved without complicating the complementary metal oxide semiconductor (CMOS) manufacturing process.

[0029] Figure 3 1 shows a cross-sectional elevation view of some embodiments of a larger portion 300 of a pixel circuit array of an image sensor. The pixel circuit array includes Figure 1 Description and description of components and Figure 1 Additional components other than .

[0030] A transistor gate dielectric layer 305 is formed on a portion of the first surface of the semiconductor substrate region 107. A transistor gate 304 is formed on the first surface of the transistor gate dielectric layer 305, opposite to a second surface of the transistor gate dielectric layer 305, which contacts the first surface of the semiconductor substrate region 107. A sidewall spacer 306 is formed along one or more sides of the transistor gate 304. A dielectric layer 108 is formed on the first surface of the transistor gate 304, opposite to a second surface of the transistor gate 304 that contacts the transistor gate dielectric layer 305, and above a first end of the sidewall spacer 306, opposite to a second end of the sidewall spacer 306, which contacts the first surface of the semiconductor substrate region 107. A contact etch stop layer 116 is formed on the dielectric layer 108. An interlayer dielectric region 117 is formed on the contact etch stop layer 116. An opening is formed through the interlayer dielectric region 117 and the contact etch stop layer 116, and the opening extends to the first surface of the transistor gate 304. A contact 338 of a conductive material (e.g., metal) is formed in the opening to provide electrical connection from the first surface of the transistor gate 304 to a portion of the first surface of the interlayer dielectric region 117.

[0031] A transistor gate dielectric layer 325 is formed on a portion of the first surface of the semiconductor substrate region 127. A transistor gate 324 is formed on the first surface of the transistor gate dielectric layer 325, opposite to the second surface of the transistor gate dielectric layer 325, the transistor gate dielectric layer 325 being in contact with the first surface of the semiconductor substrate region 127. A sidewall spacer 326 is formed along one or more sides of the transistor gate 324. A dielectric layer 108 is formed on the first surface of the transistor gate 324, opposite to the second surface of the transistor gate 324 being in contact with the transistor gate dielectric layer 325, and over a first end of the sidewall spacer 326, opposite to the second end of the sidewall spacer 326 being in contact with the first surface of the semiconductor substrate region 127. As described above, a contact etch stop layer 116 is formed on the dielectric layer 108, and an interlayer dielectric region 117 is formed on the contact etch stop layer 116. An opening is formed through the ILD region 117 and the contact etch stop layer 116, and the opening extends to the first surface of the transistor gate 324. A contact 358 of a conductive material (e.g., metal) is formed in the opening to provide an electrical connection from the first surface of a portion of the transistor gate 324 to the first surface of the ILD region 117.

[0032] Semiconductor region 320 is formed in semiconductor substrate region 107. Semiconductor region 320 has a first doping type (e.g., p-type) that is different from a second doping type (e.g., n-type) of semiconductor substrate region 107 to form a photodiode for a first pixel of the pixel array, the photodiode being sensitive to incident electromagnetic radiation (e.g., light) 399. Semiconductor region 340 is formed in semiconductor substrate region 127. Semiconductor region 340 has a first doping type and semiconductor substrate region 107 has a second doping type to form a photodiode for a second pixel of the pixel array, the photodiode being sensitive to incident electromagnetic radiation (e.g., light) 399. The above components together constitute integrated circuit 303.

[0033] Second integrated circuit 312 includes semiconductor substrate 398, dielectric layer 397, contact etch stop layer 376, interlayer dielectric 377, contact 328, contact 348, and contact 368. Features such as transistors and other components (not shown) can be formed in or on semiconductor substrate 398. Dielectric layer 397 is formed on a first surface of semiconductor substrate 398 and can extend over the components. Contact etch stop layer 376 is formed on a first surface of dielectric layer 397. Interlayer dielectric 377 is formed on a first surface of contact etch stop layer 376. A hole is formed through interlayer dielectric 377, contact etch stop layer 376, and dielectric layer 397. Conductive material such as metal is disposed in the hole to form contact 328, contact 348, and contact 368.

[0034] The second integrated circuit 312 is paired with the integrated circuit 303 to form a stacked integrated circuit structure. In some embodiments, the stacked integrated circuit structure is a backside-illuminated image sensor, also known as a backside-illumination (BSI) image sensor, which can detect electromagnetic radiation (e.g., light) 399 incident on the integrated circuit 303 while providing an electrical connection to the second integrated circuit 312. In some embodiments, the BSI image sensor can include a photodiode formed in the integrated circuit 303, and the second side of the integrated circuit 303 can be thinned to allow the incident electromagnetic radiation to reach the photodiode without excessive attenuation and without being blocked by structures fabricated on the first side of the integrated circuit 303. However, the process window of the joint will be critical in a complex layout environment, so the tolerance of manufacturing the joint on the integrated circuit 303 and the second integrated circuit 312 and the tolerance of the mating alignment of the integrated circuit 303 and the second integrated circuit 312 will be strict.

[0035] Figure 4 A cross-sectional plan view of some embodiments of a portion 400 of a pixel circuit array for an image sensor is shown, showing a conductive layer connecting multiple floating diffusions to a common contact.

[0036] Figure 4 Show about Figure 2 The features shown and described and a contact 118 connected to the conductive layer 113 are shown. The conductive layer 113 is shown to include one or more conductive layer features (e.g., strips) 113a, 113b, 113c, 113d, 113e, and 113f. The conductive layer feature 113a is located between and connects the floating diffusion area 101 and the floating diffusion area 161. The conductive layer feature 113b is located between and connects the floating diffusion area 161 and the floating diffusion area 121. The conductive layer feature 113c is located between and connects the floating diffusion area 121 and the floating diffusion area 141. The conductive layer feature 113d is located between and connects the floating diffusion area 141 and the floating diffusion area 101. The conductive layer feature 113e is located between and connects the floating diffusion area 101 and the floating diffusion area 121. The conductive layer feature 113f is located between and connects the floating diffusion area 141 and the floating diffusion area 161.

[0037] Contact 118 is shown connected to conductive layer 113 at the intersection of conductive layer feature 113e and conductive layer feature 113f. However, contact 118 may be connected anywhere along conductive layer 113, such as at the intersection of conductive layer feature 113a and conductive layer feature 113d, at the intersection of conductive layer feature 113a and conductive layer feature 113b, at the intersection of conductive layer feature 113b and conductive layer feature 113c, at the intersection of conductive layer feature 113c and conductive layer feature 113d, at a location along conductive layer feature 113a, at a location along conductive layer feature 113b, at a location along conductive layer feature 113c, at a location along conductive layer feature 113d, at a location along conductive layer feature 113e, at a location along conductive layer feature 113f, or at a location along another conductive layer feature, such as a conductive layer feature of a different size, shape, or location (e.g., anywhere on a polygonal conductive layer feature).

[0038] Figure 5 A top view of some embodiments of a portion 500 of a pixel circuit array for an image sensor is shown, showing a conductive layer connecting multiple floating diffusions to a common contact. Figure 5 In the example of , the conductive layer 113 is implemented in the form of a polygon (eg, a rectangle, eg, a square) that electrically connects a plurality of (eg, four) floating diffusion regions (eg, the floating diffusion region 101) separated by the isolation region 102. Figure 5 In the example of FIG. 1 , contact 118 is formed on and connected to conductive layer 113 (eg, at the center of the polygon). Alternatively, contact 118 may be formed on and connected to any portion of the polygon of conductive layer 113.

[0039] Figure 6A top view of some embodiments of a portion 600 of a pixel circuit array of an image sensor is shown, showing a conductive layer connecting multiple floating diffusions to a common contact. Figure 6 In the example of , the conductive layer 113 is implemented in the form of a ring (eg, a rectangular block, such as a square block) that electrically connects a plurality of (eg, four) floating diffusion regions (eg, the floating diffusion region 101) separated by the isolation region 102. Figure 6 In the example of FIG. 1 , the contact 118 is formed on and connected to the strip on one side of the ring. Alternatively, the contact 118 can be formed on and connected to any portion of the conductive layer 113 ring.

[0040] Figure 7 A top view of some embodiments of a portion 700 of a pixel circuit array of an image sensor is shown, showing a conductive layer connecting a plurality of floating diffusions to contacts. Figure 7 In the example of , the conductive layer 113 is implemented in the form of radial strips (eg, crosses) that electrically connect multiple (eg, four) floating diffusion regions (eg, floating diffusion region 101) separated by the isolation region 102. Figure 7 In the example of FIG. 1 , the joint 118 is formed at the intersection of the radial stripes and connected to the radial stripes (eg, at the center of the radial stripe pattern). Alternatively, the joint 118 may be formed on and connected to any portion of the radial stripe pattern.

[0041] Figure 6 , Figure 7 and Figure 8 Examples of the form of the conductive layer 113 are shown (e.g., a square, a block, or a cross), but the metal connection pattern can be implemented in a variety of shapes, including those different from the examples shown. Figure 7 The diagonal conductors shown in Figure 6 The side components of the ring shown in (eg, square boxes) can achieve a Z or N type pattern. Any shape, form, or pattern that provides electrical connection to a common contact for multiple floating diffusion regions can be used.

[0042] Figure 8 A cross-sectional plan view of some embodiments of a portion 800 of a pixel circuit array of an image sensor is shown. Figure 3 The dotted line 8-8 in the figure indicates Figure 8. The transistor gate 304 is surrounded by sidewall spacers 306, which are surrounded by a portion of the dielectric layer 108. The transistor gate 324 is surrounded by sidewall spacers 326, which are surrounded by a portion of the dielectric layer 108 identified as dielectric layer portion 128. The transistor gate 344 is surrounded by sidewall spacers 346, which are surrounded by a portion of the dielectric layer 108 identified as dielectric layer portion 148. The transistor gate 364 is surrounded by sidewall spacers 366, which are surrounded by a portion of the dielectric layer 108 identified as dielectric layer portion 168. The dielectric layer portion is surrounded by the contact etch stop layer 116. The conductive layer 113 is located in the center between the four transistors and is surrounded by the contact etch stop layer 116. The recessed area of ​​the conductive layer 113 that contacts the underlying floating diffusion regions 101, 121, 141 and 161 is Figure 8 Below the plane in the conductive layer 113, holes 136, 156, 176 and 196 are left filled with portions of the contact etch stop layer 116.

[0043] Figures 9 to 25 is a cross-sectional elevation view illustrating some embodiments of a series of incremental manufacturing steps as a series of cross-sectional views. Figures 9 to 25 Described as a series of steps, it should be understood that these steps are not limiting, because the order of the steps can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the illustrated and / or described steps can be omitted in whole or in part.

[0044] Fig. 9 A cross-sectional plan view of some embodiments of a portion 900 of a pixel circuit array of an image sensor is shown. Semiconductor substrate 919 includes semiconductor substrate region 107, semiconductor substrate region 127, and isolation region 102. Isolation region 102 is formed in the semiconductor substrate to separate semiconductor substrate region 107 (e.g., a p-type semiconductor substrate region) from semiconductor substrate region 127 (e.g., a p-type semiconductor substrate region). Gate structure 922 includes transistor gate dielectric layer 305 and transistor gate 324. Transistor gate dielectric layer 305 is formed on semiconductor substrate region 107. Transistor gate dielectric layer 325 is formed on semiconductor substrate region 127. Transistor gate 304 (e.g., polysilicon) is formed on transistor gate dielectric layer 305. Transistor gate 324 (e.g., polysilicon) is formed on transistor gate dielectric layer 325. In some embodiments, transistor gate dielectric layer 305 and transistor gate 304 may be formed by a deposition process followed by a patterning process.

[0045] Sidewall spacers 306 are formed around transistor gate 304. Sidewall spacers 326 are formed around transistor gate 324. In some embodiments, sidewall spacers 306 and 326 may be formed by depositing a sidewall spacer material to extend continuously over transistor gate 304 and transistor gate 324, which is then etched to remove the sidewall spacer material from horizontal surfaces, leaving sidewall spacers 306 and 326 along opposing sides of transistor gate 304 and transistor gate 324. In various embodiments, the sidewall spacer material may include silicon nitride, silicon dioxide (SiO2), silicon oxynitride (e.g., SiON), silicon carbide, Si3N4, etc. In various embodiments, the sidewall spacer material may be formed to a thickness of about 500 angstroms.

[0046] Fig.10 1 shows a cross-sectional plan view of some embodiments of a portion 1000 of a pixel circuit array of an image sensor. A dielectric layer 108 (eg, a dielectric film) is formed on the Fig. 9 As an example, the dielectric layer 108 may be an oxide layer (e.g., silicon dioxide (SiO2)), a nitride layer (e.g., silicon nitride (SiN)), etc. In some embodiments, a deposition process (e.g., a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PE-CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, ion beam deposition, sputtering, etc.) may be used.

[0047] Fig.11 A cross-sectional plan view of some embodiments of a portion 1100 of a pixel circuit array of an image sensor is shown. A first patterned layer 1109 (eg, a photoresist layer, a hard mask layer, etc.) is applied to Fig.10 The structure shown leads to Fig.11 In some embodiments, lithography techniques can be used to expose the first patterned layer 1109 to a pattern of electromagnetic radiation (eg, light) that differentiates areas of the first patterned layer 1109 that are to be removed and areas of the first patterned layer 1109 that are to be retained.

[0048] Fig.12 A cross-sectional plan view of some embodiments of a portion 1200 of a pixel circuit array of an image sensor is shown. After patterned lithography exposure, a first patterned layer (e.g., Fig. 9A removal technique (eg, including a chemical photoresist developer) is performed on the dielectric layer 1109 in the embodiment of the present invention to produce openings 1201 and 1221, wherein the first patterned layer has been removed to expose portions of the dielectric layer 108. First patterned layer regions 1229, 1239, and 1249 of the first patterned layer are retained.

[0049] Fig.13 A cross-sectional plan view of some embodiments of a portion 1300 of a pixel circuit array of an image sensor is shown. An etchant 1310 is applied to create an opening in the dielectric layer 108 that is similar to an opening through the first patterned layer (e.g., Fig.12 The etchant 1310 may be a plasma etchant having tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), etc.

[0050] Fig.14 A cross-sectional plan view of some embodiments of a portion 1400 of a pixel circuit array of an image sensor is shown. Implantation techniques may be performed to Fig.12 and Fig.13 The corresponding openings formed form the floating diffusion area 101 and the floating diffusion area 121 . Fig.14 Ions 1411 are shown for use in an implantation technique. In some embodiments, ions 1411 may include dopant species such as phosphorus, arsenic, antimony, and the like.

[0051] Fig.15 A cross-sectional plan view of some embodiments of a portion 1500 of a pixel circuit array of an image sensor is shown. The remaining portion of the first patterned layer (eg, Fig. 9 1109), including a first patterned layer region (e.g., Fig.12 1229 , 1239 and 1249 ), leaving the dielectric layer 108 with the floating diffusion regions 101 and 121 , which are below the corresponding openings in the dielectric layer 108 .

[0052] Fig.16A cross-sectional plan view of some embodiments of a portion 1600 of a pixel circuit array of an image sensor is shown. Conductive layer 113 (e.g., a metal film such as titanium nitride (TiN)) is deposited over dielectric layer 108 and over floating diffusion regions 101 and 121 and contacts floating diffusion regions 101 and 121 through their respective openings in dielectric layer 108. In some embodiments, conductive layer 113 may include a metal formed by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing.

[0053] In some embodiments, conductive layer 113 may be a conductive material, such as a metal or a metal compound, such as titanium nitride, tantalum nitride, titanium, tantalum, copper, aluminum, or a combination of one or more of the foregoing. In addition, in some embodiments, conductive layer 113 may be, for example, about 10-100 nanometers thick. Conductive layer 113 may be formed to have a height above semiconductor substrate region 107 and above semiconductor substrate region 127 that is less than the gate height of transistor gate 304 and transistor gate 324 above semiconductor substrate region 107 and above semiconductor substrate region 127.

[0054] Fig.17 A cross-sectional plan view of some embodiments of a portion 1700 of a pixel circuit array of an image sensor is shown. A second patterned layer 1714 (eg, a photoresist layer, a hard mask layer, etc.) is applied to Fig.16 The conductive layer 113 of the structure shown in FIG. Fig.17 In some embodiments, lithography techniques may be used to expose the second patterned layer 1714 to a pattern of electromagnetic radiation (eg, light) that differentiates areas of the second patterned layer 1714 that are to be removed from areas of the second patterned layer 1714 that are to be retained.

[0055] Fig.18 A cross-sectional plan view of some embodiments of a portion 1800 of a pixel circuit array of an image sensor is shown. A removal technique (e.g., a photoresist developer) is applied to the second patterned layer 1714 to remove portions of the second patterned layer 1714 above the transistor gate 304 and the transistor gate 324, but to leave portions of the second patterned layer 1714 above the conductive layer 113, including above the floating diffusion region 101 and the floating diffusion region 121 and the region electrically connecting the floating diffusion region 101 to the floating diffusion region 121. An etchant 1815 is applied to remove portions of the conductive layer 113 beyond the portions of the conductive layer 113 that are to be retained to electrically connect the plurality of floating diffusion regions together. The etching technique may be, for example, a dry etching technique suitable for etching through the exposed regions of the conductive layer 113.

[0056] Fig.19A cross-sectional plan view of some embodiments of a portion 1900 of a pixel circuit array of an image sensor is shown. Any remaining portions of the second patterned layer (e.g., Fig.18 1714), leaving a portion of the conductive layer 113 that electrically connects the floating diffusion area 101 to the floating diffusion area 121.

[0057] Fig. 20 A cross-sectional plan view of some embodiments of a portion 2000 of a pixel circuit array of an image sensor is shown. A contact etch stop layer 116, such as silicon nitride (SiN), is formed over the remaining portion of the conductive layer 113 and the remaining portion of the dielectric layer 108. In some embodiments, the contact etch stop layer 116 can be deposited using a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, a LPCVD process, ion beam deposition, sputtering, etc.).

[0058] Fig.21 A cross-sectional plan view of some embodiments of a portion 2100 of a pixel circuit array of an image sensor is shown. An interlayer dielectric 2117 is formed over the contact etch stop layer 116. In some embodiments, the interlayer dielectric 2117 may include silicon dioxide, carbon doped silicon oxide (SiCOH), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), borosilicate glass (BSG), fluorosilicate glass (FSG), undoped silicate glass (USG), etc.

[0059] Fig. 22 A cross-sectional plan view of some embodiments of a portion 2200 of a pixel circuit array of an image sensor is shown. Openings 2219, 2229, and 2239 are formed in the interlayer dielectric 2117, exposing corresponding portions of the contact etch stop layer 116. In some embodiments, the openings 2219, 2229, and 2239 may be formed by a first etching process.

[0060] Fig.23A cross-sectional plan view of some embodiments of a portion 2300 of a pixel circuit array of an image sensor is shown. Openings 2219, 2229, and 2239 extend through contact etch stop layer 116, and for openings 2219 and 2239, through dielectric layer 108, exposing a portion of the first surface of transistor gate 304 through opening 2219, exposing a portion of the first surface of transistor gate 324 through opening 2239, and exposing a portion of conductive layer 113 through opening 2229. In some embodiments, openings 2219, 2229, and 2239 may extend through contact etch stop layer 116 by a first etching process. In other embodiments, openings 2219, 2229, and 2239 may extend through contact etch stop layer 116 by a second etching process separate from the first etching process.

[0061] Fig.24 A cross-sectional plan view of some embodiments of a portion 2400 of a pixel circuit array of an image sensor is shown. Contacts 338, 118, and 358 are each formed through an opening (e.g., Fig.23 2219, 2229 and 2239) are formed of a conductive material (e.g., metal). In some embodiments, contacts 338, 118 and 358 can be formed by openings (e.g., Fig.23 The metal is deposited in 2219, 2229 and 2239) and then a planarization process (e.g., a chemical mechanical planarization process) is performed. In some embodiments, the metal can be formed by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, chemical plating, some other deposition process, or a combination of the foregoing.

[0062] Fig.25 A cross-sectional plan view of some embodiments of a portion 2500 of a pixel circuit array of an image sensor is shown. Fig.25 and Fig.24 320 and 340 are different in that it includes semiconductor regions 320 and semiconductor regions 340 formed in corresponding regions of the semiconductor substrate, resulting in a p-type / n-type (PN) junction to form a photodiode sensitive to electromagnetic radiation (e.g., light). By detecting light incident on the photodiode, the image sensor can assign intensity levels to pixels in the pixel array of the image sensor. Although semiconductor regions 320 and 340 are shown in accordance with other manufacturing techniques, the formation of the semiconductor regions can be performed earlier, and the size, shape, and location of the semiconductor regions can be different. Fig.25 After the processing is completed, for example, in the formation of Fig.25 Following those features shown, such a wafer may optionally be stacked with other wafers or dies and then singulated into individual dies corresponding to individual integrated circuit structures.

[0063] Although not explicitly described, it should be understood that the source region and the drain region may be disposed within a semiconductor substrate (e.g., semiconductor substrate region 107 or semiconductor substrate region 127) to form a transistor together with transistor gate 304 or transistor gate 324, which may be used as a transfer transistor or a reset transistor for a pixel circuit of an image sensor, for example. The source region and the drain region may be, for example, doped to have a first conductivity type opposite to a second conductivity type of a channel region below transistor gate dielectric layers 305 and 325. Transistor gates 304 and 324 may be, for example, doped polysilicon or a metal, such as aluminum, copper, or a combination thereof. Transistor gate dielectric layers 305 and 325 may be, for example, an oxide, such as silicon dioxide, or a dielectric material with a high dielectric constant. Sidewall spacers 306 and 326 may be, for example, made of silicon nitride (e.g., Si3N4). Contacts 118, 338, and 358 may be, for example, made of a metal such as copper or tungsten.

[0064] In some embodiments, the integrated circuit features of the icons can have a square, rectangular, or circular shape when viewed from above. However, in other embodiments, for example due to the practicality of many etching processes, the corners of the squares shown can be rounded, resulting in features having a square or rectangular shape with rounded corners, or having a circular or oval shape.

[0065] Fig.26 A flow chart of a method 2600 in the form of a flow chart according to some embodiments is shown. Although the method and other methods shown and / or described herein are shown as a series of steps or events, it should be understood that the present disclosure is not limited to the order or steps shown. Therefore, in some embodiments, the steps can be performed in an order different from the order shown, and / or can be performed simultaneously. In addition, in some embodiments, the steps or events shown can be subdivided into multiple steps or events, which can be performed at different times or simultaneously with other steps or sub-steps. In some embodiments, some illustrated steps or events can be omitted, and other unillustrated steps or events can be included.

[0066] At block 2601, an isolation region is formed between a first semiconductor substrate region and a second semiconductor substrate region. Fig. 9 A cross-sectional view corresponding to block 2601 is shown. Block 2601 may also include one or more of blocks 2602, 2603, and 2604. At block 2602, an isolation region is formed between the second semiconductor substrate and the third semiconductor substrate region. At block 2603, an isolation region is formed between the third semiconductor substrate region and the fourth semiconductor substrate region. At block 2604, an isolation region is formed between the first semiconductor substrate region and the fourth semiconductor substrate region.

[0067] At block 2605, first and second photosensitive regions and first and second transistor regions are formed in the first semiconductor substrate region. Figures 9 to 14 A cross-sectional view corresponding to block 2605 is shown.

[0068] At block 2606, a dielectric layer is formed. The dielectric layer extends from over the isolation region to over the first semiconductor substrate region and over the second semiconductor substrate region.

[0069] At block 2607, the dielectric layer is patterned to form openings exposing the first semiconductor substrate region and the second semiconductor substrate region. The formed openings are coextensive with surfaces of a first floating diffusion region to be formed in the first semiconductor substrate region and a second floating diffusion region to be formed in the second semiconductor substrate region.

[0070] At block 2608, a first floating diffusion region is formed in the first semiconductor substrate region, and a second floating diffusion region is formed in the second semiconductor substrate region. Block 2608 may also include one or both of blocks 2609 and 2610. At block 2609, a third floating diffusion region is formed in the third semiconductor substrate region. At block 2610, a fourth floating diffusion region is formed in the fourth semiconductor substrate region. The floating diffusion region may be formed, for example, by implantation or the like.

[0071] At block 2611, a conductive layer electrically connected to the first floating diffusion region and the second floating diffusion region is formed over the first floating diffusion region and the second floating diffusion region. Figures 16 to 19 A cross-sectional view corresponding to block 2611 is shown. Block 2611 may also include one or more of blocks 2612, 2613, and 2614. At block 2612, a conductive layer is formed to be in direct contact with the first floating diffusion region and the second floating diffusion region. At block 2613, a conductive layer is formed to extend to and electrically connect to the third floating diffusion region, and the conductive layer may be in direct contact therewith. At block 2614, a conductive layer is formed to extend to and electrically connect to the fourth floating diffusion region, and the conductive layer may be in direct contact therewith. At block 2615, a hole may be formed in the conductive layer in some embodiments.

[0072] At block 2616, in some embodiments, the conductive layer may be formed to include an elongated portion. For example, the conductive layer may be formed to include a radially oriented elongated portion extending outward from a central region to connect to a plurality of first, second, third, and fourth floating diffusion regions. Any or all of blocks 2611, 2612, 2613, 2614, 2615, and 2616 may be performed individually or in combination, for example, simultaneously. For example, deposition or etching techniques may be used to provide selectivity in forming the conductive layer, thereby allowing additive or subtractive manufacturing techniques to accomplish patterned conductive layer formation.

[0073] At block 2617, an electrical contact is formed adjacent to and electrically connected to a first surface of the conductive layer, wherein the first surface is opposite to a second surface adjacent to and electrically connected to the first, second, third, and fourth floating diffusion regions. Figure 22 to Figure 24 A cross-sectional view corresponding to block 2617 is shown.

[0074] Some embodiments relate to an integrated circuit comprising a plurality of floating diffusion regions that are ohmically connected to a common contact through a patterned conductive layer, thereby avoiding the need for a separate contact for each floating diffusion region. The integrated circuit comprises a semiconductor substrate and an interconnect structure disposed above the semiconductor substrate. The interconnect structure comprises a plurality of dielectric layers and a conductive layer stacked on each other in an alternating manner. A contact electrode is disposed above the conductive layer and is directly ohmically connected to the conductive layer. The conductive layer is directly connected to a corresponding surface of each of the plurality of floating diffusion regions. In some embodiments, the conductive layer is ohmically (e.g., directly and ohmically) connected to a corresponding surface of each of the plurality of floating diffusion regions. The surfaces connected by the conductive layer are coplanar with each other. Each floating diffusion region can be associated with a corresponding pixel of a pixel array of an image sensor. As used herein, the terms "ohmic" and "ohmic ground" refer to a direct physical contact electrical connection at a surface interface between two conductive or semiconductor components.

[0075] Some embodiments relate to an integrated circuit, wherein the integrated circuit includes: a semiconductor substrate, including a first semiconductor substrate region and a second semiconductor substrate region; a first floating diffusion region, located in the first semiconductor substrate region; a second floating diffusion region, located in the second semiconductor substrate region; an isolation region, arranged between the first semiconductor substrate region and the second semiconductor substrate region; a gate structure, arranged above the semiconductor substrate and adjacent to the first semiconductor substrate region; and a conductive layer, directly connected to the first floating diffusion region and the second floating diffusion region, wherein the gate structure has a maximum height greater than that of the conductive layer.

[0076] In some embodiments, the integrated circuit also includes a third floating diffusion region located in a third semiconductor substrate region, wherein the isolation region is arranged between the third floating diffusion region and the first floating diffusion region and between the third floating diffusion region and the second floating diffusion region, and wherein the conductive layer is electrically connected to the third floating diffusion region; and a fourth floating diffusion region located in a fourth semiconductor substrate region, wherein the isolation region is arranged between the fourth floating diffusion region and the first floating diffusion region, between the fourth floating diffusion region and the second floating diffusion region, and between the fourth floating diffusion region and the third floating diffusion region, and wherein the conductive layer is electrically connected to the fourth floating diffusion region.

[0077] In some embodiments, the integrated circuit further includes a first inter-layer dielectric (ILD) layer surrounding a first conductive contact physically contacting the gate structure and further surrounding a second conductive contact physically contacting a top portion of the conductive layer.

[0078] In some embodiments, the integrated circuit further includes a conductive contact adjacent to a first surface of the conductive layer, the first surface being opposite to a second surface of the conductive layer adjacent to the first floating diffusion region and the second floating diffusion region.

[0079] In some embodiments, the conductive layer has sidewalls forming a hole covering a portion of the isolation region, the hole being located between each pair of two diagonally opposite ones selected from among the first semiconductor substrate region, the second semiconductor substrate region, the third semiconductor substrate region, and the fourth semiconductor substrate region.

[0080] In some embodiments, the conductive layer includes a first extended portion extending from a central region to a first connection region adjacent to the first floating diffusion region, a second extended portion extending from the central region to a second connection region adjacent to the second floating diffusion region, a third extended portion extending from the central region to a third connection region adjacent to the third floating diffusion region, and a fourth extended portion extending from the central region to a fourth connection region adjacent to the fourth floating diffusion region.

[0081] In some embodiments, the first sensor structure includes a first transistor region, a first photosensitive region and the first floating diffusion region, wherein the first photosensitive region is located in the first semiconductor substrate region, the first transistor region is located in the first semiconductor substrate region and is located between the first photosensitive region and the first floating diffusion region, and the second sensor structure includes a second transistor region, a second photosensitive region and the second floating diffusion region, wherein the second photosensitive region is located in the second semiconductor substrate region, the second transistor region is located in the second semiconductor substrate and is located between the second photosensitive region and the second floating diffusion region.

[0082] Some embodiments relate to a pixel element array comprising: an isolation region; a plurality of pixel components adjacent to the isolation region along different surfaces of the isolation region, each of the plurality of pixel components comprising a respective floating diffusion region; a dielectric layer extending above the isolation region and having sidewalls forming openings above corresponding floating diffusion regions within the plurality of pixel components; a conductive layer extending from above the dielectric layer to directly and ohmically connect a corresponding first floating diffusion region surface of each corresponding floating diffusion region adjacent to each of the plurality of pixel components; and a contact etch stop layer disposed above and along the sidewalls of the conductive layer.

[0083] In some embodiments, the pixel element array also includes a conductive contact extending through the contact etching stop layer and adjacent to a first conductive layer surface opposite to a second conductive layer surface of the conductive layer, the second conductive layer surface adjacent to each corresponding first floating diffusion area surface, the conductive contact being in direct electrical and ohmic contact with the first conductive layer surface, the conductive contact providing a common electrical connection for the multiple pixel components, and each corresponding floating diffusion area being electrically connected to the conductive contact via the conductive layer.

[0084] In some embodiments, the pixel element array further includes a transmission gate disposed above the pixel element, wherein the dielectric layer and the contact etch stop layer continuously extend from below the top of the transmission gate to above the top of the transmission gate.

[0085] In some embodiments, the conductive layer includes a plurality of elongated portions extending radially outward from a center of the conductive layer to provide a direct and ohmic connection to a surface of each respective first floating diffusion region.

[0086] In some embodiments, an inner boundary of the conductive layer is formed by a sidewall of the conductive layer extending in a closed loop around the contact etch stop layer.

[0087] In some embodiments, respective portions of the conductive layer adjacent to respective floating diffusion regions are surrounded by the dielectric layer, and a common portion of the conductive layer is adjacent to the dielectric layer away from respective floating diffusion regions.

[0088] Some embodiments relate to a method for manufacturing an integrated circuit. The method includes: forming an isolation region in a substrate between a first semiconductor substrate region and a second semiconductor substrate region; forming a dielectric layer extending from above the isolation region to above the first semiconductor substrate region and the second semiconductor substrate region; patterning the dielectric layer to form an opening exposing the first semiconductor substrate region and the second semiconductor substrate region; implanting a substrate according to the opening to form a first floating diffusion region in the first semiconductor substrate region and a second floating diffusion region in the second semiconductor substrate region; and forming a conductive layer above the dielectric layer and within the opening, the conductive layer being electrically connected to the first floating diffusion region and the second floating diffusion region.

[0089] In some embodiments, wherein the first floating diffusion region is formed in the first semiconductor substrate region and the second floating diffusion region is formed in the second semiconductor substrate region, further comprising forming a third floating diffusion region in the third semiconductor substrate region and forming a fourth floating diffusion region in the fourth semiconductor substrate region, wherein the isolation region is formed between the first semiconductor substrate region and the second semiconductor substrate region, further comprising forming the isolation region between the second semiconductor substrate region and the third semiconductor substrate region, between the third semiconductor substrate region and the fourth semiconductor substrate region, and between the fourth semiconductor substrate region and the first semiconductor substrate region, and wherein the conductive layer electrically connected to the first floating diffusion region and electrically connected to the second floating diffusion region is formed, further comprising forming the conductive layer electrically connected to the third floating diffusion region and electrically connected to the fourth floating diffusion region.

[0090] In some embodiments, the method further includes: forming a conductive contact adjacent to a first surface of the conductive layer, the first surface being opposite to a second surface of the conductive layer, the second surface adjacent to the first floating diffusion region, the second floating diffusion region, the third floating diffusion region and the fourth floating diffusion region.

[0091] In some embodiments, the method further includes: patterning the conductive layer to form a hole covering a portion of the isolation region, the hole being located between each pair of two diagonally opposite ones selected from the first semiconductor substrate region, the second semiconductor substrate region, the third semiconductor substrate region, and the fourth semiconductor region.

[0092] In some embodiments, the method further includes: patterning the conductive layer to include a first extended portion extending from a central area to a first connection area adjacent to the first floating diffusion area, a second extended portion extending from the central area to a second connection area adjacent to the second floating diffusion area, a third extended portion extending from the central area to a third connection area adjacent to the third floating diffusion area, and a fourth extended portion extending from the central area to a fourth connection area adjacent to the fourth floating diffusion area.

[0093] In some embodiments, the method further includes: forming a first photosensitive region and a first transistor region in the first semiconductor substrate region, and forming a second photosensitive region and a second transistor region in the second semiconductor substrate region, wherein the first photosensitive region is located in the first semiconductor substrate region, and the first transistor region is located in the first semiconductor substrate region between the first photosensitive region and the first floating diffusion region, and wherein the second sensor structure includes a second transistor region, a second photosensitive region and the second floating diffusion region, wherein the second photosensitive region is located in the second semiconductor substrate region, and the second transistor region is located in the second semiconductor substrate region between the second photosensitive region and the second floating diffusion region.

[0094] In some embodiments, forming the conductive layer further comprises: forming a conductive layer in direct and ohmic contact with the first floating diffusion region and in direct and ohmic contact with the second floating diffusion region.

[0095] It should be understood that in this written description and the appended claims, the terms "first," "second," "second," "third," etc., are used merely for convenience of description to distinguish between different general identifiers of a figure or series of figures. By themselves, these terms do not imply any temporal ordering or structural proximity of these components, and are not intended to describe corresponding components in different illustrated embodiments and / or non-illustrated embodiments. For example, a "first dielectric layer" described in conjunction with a first figure does not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" that is not described in the illustrated embodiments.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to it without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, characterized in that: include: A semiconductor substrate, comprising a first semiconductor substrate region and a second semiconductor substrate region; A first floating diffusion region, located in the first semiconductor substrate region; a second floating diffusion region, located in the second semiconductor substrate region; an isolation region, disposed between the first semiconductor substrate region and the second semiconductor substrate region; a gate structure disposed above the semiconductor substrate and adjacent to the first semiconductor substrate region; as well as A conductive layer is directly connected to the first floating diffusion region and the second floating diffusion region, wherein the gate structure has a maximum height greater than that of the conductive layer.

2. The integrated circuit according to claim 1, characterized in that Also includes: a third floating diffusion region located in the third semiconductor substrate region, wherein the isolation region is disposed between the third floating diffusion region and the first floating diffusion region and between the third floating diffusion region and the second floating diffusion region, and wherein the conductive layer is electrically connected to the third floating diffusion region; as well as A fourth floating diffusion region is located in a fourth semiconductor substrate region, wherein the isolation region is arranged between the fourth floating diffusion region and the first floating diffusion region, between the fourth floating diffusion region and the second floating diffusion region, and between the fourth floating diffusion region and the third floating diffusion region, wherein the conductive layer is electrically connected to the fourth floating diffusion region.

3. The integrated circuit according to claim 1, characterized in that Also includes: A conductive contact is adjacent to a first surface of the conductive layer, the first surface being opposite to a second surface of the conductive layer adjacent to the first floating diffusion region and the second floating diffusion region.

4. The integrated circuit according to claim 1, characterized in that wherein the first sensor structure comprises a first transistor region, a first photosensitive region and the first floating diffusion region, wherein the first photosensitive region is located in the first semiconductor substrate region, the first transistor region is located in the first semiconductor substrate region and between the first photosensitive region and the first floating diffusion region, and The second sensor structure includes a second transistor region, a second photosensitive region and the second floating diffusion region, wherein the second photosensitive region is located in the second semiconductor substrate region, and the second transistor region is located in the second semiconductor substrate and between the second photosensitive region and the second floating diffusion region.

5. A pixel element array, characterized in that: include: quarantine area; a plurality of pixel components adjacent to the isolation region along different surfaces of the isolation region, each of the plurality of pixel components including a respective floating diffusion region; a dielectric layer extending over the isolation region and having sidewalls forming openings over corresponding floating diffusion regions within the plurality of pixel components; a conductive layer extending from above the dielectric layer to directly and ohmically connect adjacent to a corresponding first floating diffusion region surface of each corresponding floating diffusion region of each of the plurality of pixel components; as well as The contact etching stop layer is arranged on the side wall of the conductive layer and along the side wall.

6. The pixel element array according to claim 5, characterized in that: Also includes: A conductive contact extends through the contact etch stop layer and is adjacent to a first conductive layer surface opposite to a second conductive layer surface of the conductive layer, wherein the second conductive layer surface is adjacent to each corresponding first floating diffusion area surface, the conductive contact is in direct electrical and ohmic contact with the first conductive layer surface, the conductive contact provides a common electrical connection for the multiple pixel components, and each corresponding floating diffusion area is electrically connected to the conductive contact via the conductive layer.

7. The pixel element array according to claim 5, characterized in that: Also includes: A transmission gate is disposed above the pixel component, wherein the dielectric layer and the contact etching stop layer continuously extend from below the top of the transmission gate to above the top of the transmission gate.

8. The pixel element array according to claim 5, characterized in that: The conductive layer includes a plurality of elongated portions extending radially outward from a center of the conductive layer to provide a direct and ohmic connection to a surface of each respective first floating diffusion region.

9. The pixel element array according to claim 5, characterized in that: An inner boundary of the conductive layer is formed by a sidewall of the conductive layer extending in a closed loop around the contact etch stop layer.

10. The pixel element array according to claim 5, characterized in that: Respective portions of the conductive layers adjacent to the corresponding floating diffusion regions are surrounded by the dielectric layer, and common portions of the conductive layers are adjacent to the dielectric layer while being away from the corresponding floating diffusion regions.

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