Integrated power device and HEMT transistor

Abstract

The utility model discloses an integrated power device and an HEMT transistor. An integrated power device includes a heterostructure having a channel layer and a barrier layer, a source contact, a drain contact, and a gate region disposed on the barrier layer between the source contact and the drain contact. An insulating field structure is disposed on the barrier layer between the gate region and the drain contact. A field plate extends over the insulating field structure. The insulating field structure includes a first dielectric region made of a first dielectric material on the barrier layer and a second dielectric region made of a second dielectric material on the first dielectric region, the second dielectric material being selectively etchable relative to the first dielectric material. The field plate is in contact with the first dielectric region on a side of the insulating field structure facing the gate region. According to the technology of the utility model, some limitations on the performance aspect of the device in the known scheme are overcome.

Description

Technical Field

[0001] The present disclosure relates to normally-off heterojunction integrated devices. Background Art

[0002] As is known, a heterostructure comprises successive layers or regions of material, generally semiconductor materials, having different band gaps and defining heterojunctions at respective interfaces, wherein, based on the physical and structural properties of the materials constituting the heterojunction, a two-dimensional electron gas (2DEG) may be formed. Some heterostructures have attracted great interest in the manufacture of field effect transistors because of both their resistance to breakdown and the density and mobility of charge carriers near the heterojunction. For example, AlGaN / GaN (aluminum gallium nitride / gallium nitride) heterostructures are increasingly used to produce high electron mobility transistors (HEMTs) for high power and high frequency applications. The two-dimensional electron gas is in fact formed in the intrinsic region of the material having a narrower band gap.

[0003] AlGaN / GaN HEMTs are generally normally on, however, in order to ensure correct operation and simplify the drive circuitry, it is convenient to use normally off AlGaN / GaN HEMTs in many practical applications. Different technologies are known for making normally off AlGaN / GaN HEMTs. Among these, the so-called "p-GaN gate" technology is used on a commercial scale and requires the formation of a p-doped GaN region on an AlGaN / GaN heterostructure, which includes a GaN channel layer and an AlGaN barrier layer defining a heterojunction. The p-doped GaN region, or p-GaN gate region, is formed between the heterostructure and the gate electrode.

[0004] Devices in known solutions have performance limitations. Utility Model Content

[0005] In view of the above problems faced in the design of integrated devices, embodiments of the present disclosure are intended to provide integrated power devices and HEMT transistors with improved performance.

[0006] The solution is functionally correct in that it defines the effect of all normally-off HEMTs; however, the performance may not be satisfactory, especially in terms of maximum operating frequency. The limitation is mainly due to the gate-to-drain capacitance and the charge that therefore needs to be removed or injected to complete the switching of the device. It is therefore considered necessary to have a normally-off device that will have a higher switching speed and will therefore be used in applications at higher frequencies.

[0007] It is an object of the present disclosure to provide an integrated power device which will enable the above mentioned limitations to be overcome or at least mitigated.

[0008] According to the present disclosure, an integrated device is provided.

[0009] An embodiment of the present disclosure provides an integrated power device, comprising: a heterostructure, including a channel layer and a barrier layer; a source contact, a drain contact and a gate region, wherein the gate region is on the barrier layer, between the source contact and the drain contact, and the gate region has a top side, a first lateral side, and a second lateral side; an insulating field structure, on the barrier layer, between the gate region and the drain contact; and a field plate, on the insulating field structure, wherein the insulating field structure comprises: a first dielectric region of a first dielectric material on the barrier layer; and a second dielectric region of a second dielectric material on the first dielectric region, the second dielectric material being selectively etchable relative to the first dielectric material; wherein, on the side of the insulating field structure facing the gate region, the field plate contacts the first dielectric region; and wherein the field plate overlaps with the first lateral side of the gate region, partially overlaps with the top side of the gate region, and does not overlap with the second lateral side of the gate region.

[0010] In some embodiments, the device includes an insulated gate structure between the field plate and the gate region, wherein the window is between the insulated gate structure and the second dielectric region and the field plate contacts the first dielectric region in the window.

[0011] In some embodiments, the window is located less than 200 nm from the gate region.

[0012] In some embodiments, the first dielectric region has a first thickness less than 10 nm.

[0013] In some embodiments, the insulating field structure has: a minimum thickness on the side of the insulating field structure facing the gate region, corresponding to the first thickness of the first dielectric region; a maximum thickness on the side of the insulating field structure facing the drain terminal; and an intermediate thickness between the side of the insulating field structure facing the gate region and the side facing the drain terminal.

[0014] In some embodiments, the insulating field structure has a stepped profile and includes a third dielectric region on the second dielectric region.

[0015] In some embodiments, the second dielectric region has a second thickness between 30 nm and 50 nm, and wherein the third dielectric region has a third thickness between 100 nm and 150 nm.

[0016] In some embodiments, the third dielectric region is made of a third dielectric material that is selectively etchable relative to the second dielectric material.

[0017] In some embodiments, the first dielectric region, the second dielectric region, and the third dielectric region are made of aluminum oxide, silicon oxide, and silicon nitride, respectively.

[0018] In some embodiments, the second dielectric region of the insulating field structure has a sloped profile.

[0019] In some embodiments, the barrier layer has a first conductivity type and the gate region has a second conductivity type opposite to the first conductivity type.

[0020] An embodiment of the present disclosure also provides a HEMT transistor, which includes: a heterostructure having a first surface; a source terminal on the first surface; a drain terminal on the first surface; a gate region on the first surface, between the source terminal and the drain terminal, the gate region having a top side, a first lateral side facing the drain terminal, and a second lateral side facing the source terminal; a first dielectric layer between the source terminal and the drain terminal, on the gate region and the first surface; a first insulating structure on the first dielectric layer and in contact with the drain terminal; a second insulating structure on the first dielectric layer and in contact with the source terminal, the first insulating structure not in contact with the second insulating structure; and a field plate of a conductive material, between the gate region and the drain terminal, on the first insulating structure, partially on the second insulating structure, and partially overlapping with the gate region.

[0021] In some embodiments, the second insulating structure includes: a first portion overlapping the top side, the first lateral side, and the second lateral side of the gate region; and a second portion overlapping the first lateral side of the gate region, partially overlapping the top side of the gate region, but not overlapping the second lateral side of the gate region.

[0022] In some embodiments, the first portion and the second portion of the second insulating structure are made of different materials.

[0023] In some embodiments, the field plate is electrically coupled to the source terminal.

[0024] The technology of the present invention provides an integrated power device and a HEMT transistor with improved performance, overcoming or at least alleviating certain limitations of the known solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] For a better understanding of the present disclosure, some embodiments thereof will be described purely by way of non-limiting examples and with reference to the accompanying drawings, in which:

[0026] Figure 1 is a cross-sectional view through an integrated device according to one embodiment of the present disclosure;

[0027] Figure 2 Shows Figure 1 Magnified detail of the device;

[0028] Figure 3 is a cross-sectional view through an integrated device according to various embodiments of the present disclosure;

[0029] Figure 4 is a cross-sectional view through an integrated device according to another embodiment of the present disclosure;

[0030] Figure 5-Figure 8 is a cross-sectional view through a semiconductor wafer in successive steps of a method for manufacturing an integrated device according to an embodiment of the present disclosure;

[0031] Fig. 9 shows a cross-sectional view through a semiconductor wafer at a step in a method for manufacturing an integrated device according to various embodiments of the present disclosure;

[0032] Fig.10 and Fig.11 shows cross-sectional views through a semiconductor wafer in successive steps of a method for manufacturing an integrated device according to another embodiment of the present disclosure;

[0033] Fig.12 A cross-sectional view through a semiconductor wafer at a step in a method for manufacturing an integrated device according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] refer to Figure 1 and Figure 2 , the integrated power device 1 is an embodiment of the present disclosure. The device 1 is a normally-off heterojunction integrated device, in particular a HEMT (high electron mobility transistor), and includes a channel layer 2, a barrier layer 3, a gate region 5, a source contact 7, a drain contact 8, and a gate contact 9. The source contact 7 and the drain contact 8 may be embedded or may not be embedded relative to the barrier layer 3.

[0035] The channel layer 2 and the barrier layer 3 are made of corresponding semiconductor materials with different band gaps and form a heterostructure 10, which has a heterojunction 10a at a common interface. For example, the channel layer 2 is of intrinsic gallium nitride (GaN), while the barrier layer 3 is of aluminum gallium nitride (AlGaN) and has N-type conductivity. A two-dimensional electron gas (2DEG) is formed in the channel region of the channel layer 2 at the heterojunction 10, between the source contact 7 and the drain contact 8.

[0036] In addition to the channel layer 2 and the barrier layer 3, the integrated device 1 may include other layers belonging to or connected to the heterostructure 10, including, not necessarily and in a non-limiting manner: a substrate having mechanical support and / or electrical functionality, such as silicon or silicon carbide (SiC); a buffer layer between the substrate and the channel layer 2; an interlayer between the channel layer 2 and the barrier layer 3, such as aluminum nitride (AlN); and a cap layer on the channel layer 3, such as GaN.

[0037] The gate region 5 is formed in contact with the barrier layer 3 between the source contact 7 and the drain contact 8 and, in some embodiments, is of the same material forming the doped channel layer 2 (GaN) so as to have an opposite conductivity to the barrier layer 3, particularly in Figure 1 A gate contact 9 extends over the gate region 5 .

[0038] Field plate 12 (with Figure 1 The field plate 12 is connected to the source contact 7 in a manner not shown in the figure and extends over the barrier layer 3 between the gate region 5 and the drain contact 8 and partially also extends over the gate region 5 and the gate contact 9. An insulating field structure 13 separates the field plate 12 from the barrier layer 3 between the drain contact 8 and the gate region 5. An insulating gate structure 15 separates the field plate 12 from the gate region 5 and from the gate contact 9, as well as from the barrier layer 3 between the source contact 7 and the gate region 5. A protective layer 16 of a dielectric material, such as silicon oxide, covers the field plate 12, the insulating field structure 13, and the insulating gate structure 15 and receives the source terminal 7a, the drain terminal 8a, and the gate terminal (not shown in the figure). Figure 1 ), which extend to the source contact 7, the drain contact 8, and the gate contact 9 respectively.

[0039] Insulation field structure 13 Figure 1 In the embodiment of the present invention, the insulating field structure 13 has a variable thickness, which increases in a stepwise manner from the gate region 5 to the drain contact 9. In more detail, the insulating field structure 13 includes a first dielectric region 13a, a second dielectric region 13b, and a third dielectric region 13c, which are stacked on top of each other and extend from the drain contact 8 toward the gate region 5 to different extents.

[0040] In some embodiments, the first dielectric region 13a, the second dielectric region 13b, and the third dielectric region 13c are portions of a layer of a first dielectric material, a second dielectric material, and a third dielectric material, respectively, which are distinguished from each other and are selectively etchable relative to the material of adjacent portions of the insulating field structure 13. In particular, the first dielectric region 13a, the second dielectric region 13b, and the third dielectric region 13c may be aluminum oxide (Al2O3), respectively. 2 O 3 ), silicon oxide, and silicon nitride.

[0041] The first dielectric region 13 a extends over the barrier layer 3 from the gate contact 8 to the gate region 5 , wherein it is connected upwards to the insulating gate structure 15 , and has a thickness T1 not greater than 10 nm and for example comprised between 3 nm and 5 nm.

[0042] The second dielectric region 13b extends a distance D upward from the drain contact 8 above the first dielectric region 13a to the gate region 5, in such a way that a window 17 having a width W is defined between the second dielectric region 13b and the insulating gate structure 15. The window 17 is occupied by the portion of the field plate 12 that is in contact with the first dielectric region 13a. In one embodiment, the distance D is, for example, 300nm and the width W is, for example, 100nm. The distance D and the width W can be selected in such a way that the edge of the window 17 opposite the second dielectric region 13b will maintain a desired distance of typically less than 200nm from the gate region 5. For example, with the values ​​indicated above (D=300nm, W=200nm), the window 17 is arranged at a distance of 100nm from the gate region 5.

[0043] The second dielectric region 13b has a second thickness T2 not greater than 100 nm and for example comprised between 30 nm and 50 nm. In one embodiment, the second thickness T2 is ten times greater than the first thickness T1.

[0044] The third dielectric region 13c extends from the drain contact 8 above the second dielectric region 13b, is shorter than the second dielectric region 13b to form a step, and is partially covered by the field plate 2. The third dielectric region 13c has a third thickness T3 that is not greater than 500nm and is included, for example, between 100nm and 150nm. In some embodiments, the third thickness T3 is three times the second thickness T2.

[0045] The field plate 12 thus has three levels, corresponding to the first dielectric region 13 a , the second dielectric region 13 b , and the third dielectric region 13 c at respective distances T1 , T1 + T2 , and T1 + T2 + T3 from the surface of the barrier layer 3 .

[0046] In some embodiments, the insulating gate structure 15 includes a first portion 15a, a second portion 15b, and a third portion 15c, which may be parts of the same layer of the first dielectric region 13a, the second dielectric region 13b, and the third dielectric region 13c, respectively, which are made of the same material and therefore have the same thickness. In practice, the first layer of the first dielectric region 13a forming the insulating field structure 13 and the first portion 15a of the insulating gate structure 15 extend continuously between the source contact 7 and the drain contact 8, covering the barrier layer 3, the gate region 5, and the gate contact 9. The second layer of the second dielectric region 13b forming the insulating field structure 13 and the second portion 15b of the insulating gate structure 15 cover the gate region 5 and the gate contact 9 and extend to the window 17 where the second layer is interrupted. The second portion 15b of the insulating gate structure 15 defines the window 17 on the side facing the gate region 5.

[0047] The third layer forms a third dielectric region 13c of the insulating field structure 13 and a third portion 15c of the insulating gate structure 15, which extends from the source contact until it partially covers the gate region 5 and the gate contact 9. For example, the third portion 15c of the insulating gate structure 15 extends to a middle plane P perpendicular to the surface of the barrier layer 3, the gate region 5 and the gate contact 9.

[0048] According to different embodiments ( Figure 3 ), where the same parts as those already illustrated are designated by the same reference numerals, in the integrated device 100, the insulating field structure 113 and the insulating gate structure 115 have the same Figure 1 The insulating field structure 113 and the insulating gate structure 15 have the same shape and size. In this case, however, the first dielectric region 113a of the insulating field structure 113 is made of a first material, such as aluminum oxide, while the second region 113b and the third region 113c of the insulating field structure 113 are both made of a second material, such as silicon oxide or silicon nitride, which is selectively etchable relative to the first material. Similarly, the first portion 115a of the insulating gate structure 115 is made of a first material, while the second portion 115b and the third portion 115c are both made of the same material.

[0049] Figure 4 An integrated device 200 according to various embodiments of the present disclosure is shown. The integrated device 200 includes a channel layer 2 and a barrier layer 3, which form: a heterostructure 10 and a heterojunction 10a; a gate region 5 having a doping type opposite to that of the barrier layer 3; a source contact 7; a drain contact 8; and a gate contact 9. The integrated device 200 further includes a field plate 212, an insulating field structure 213, and an insulating gate structure 215. The insulating field structure 213 separates the field plate 212 from the barrier layer 3 between the drain contact 8 and the gate region 5. The insulating gate structure 215 separates the field plate 212 from the gate region 5 and from the gate contact 9, as well as from the barrier layer 3 between the source contact 7 and the gate region 5.

[0050] The insulating field structure 213 has a thickness which is constant in a section near the gate region 5 and variable in another section in a ramped manner up to the drain contact 8. In more detail, the insulating field structure 213 comprises a first dielectric region 213a and a second dielectric region 213b.

[0051] The first dielectric region 213a extends over the barrier layer 3 from the gate contact 8 to the gate region 5, where it is connected upwards to the insulating gate structure 215. The first dielectric region 213a is made of a first material, such as aluminum oxide, and has a first constant thickness T1 not greater than 10 nm, such as comprised between 3 nm and 5 nm.

[0052] The second dielectric region 213b is made of a second material that is selectively etchable relative to the material of the first dielectric region 213a and extends above the first dielectric region 213a to form an upward slope that starts at a distance D from the gate region 5 and extends to the drain contact 8. A window 217 of width W is thus defined between the insulating gate structure 215 and the beginning of the slope of the second dielectric region 213b. The field plate 212 is thus in contact with the first dielectric region 213a through the window 217. The distance D and the width W are, for example, 300nm and 100nm, respectively. At the end of the slope, the second dielectric region 213b reaches a second maximum thickness T2′, which is not greater than 100nm and is included, for example, between 30nm and 50nm. At this point, the thickness of the dielectric field structure 213 is therefore T1+T2′.

[0053] The field plate 212 has a horizontal surface corresponding to and in contact with the first dielectric region 213 a and an inclined surface matching a slope formed by the second dielectric region 213 b .

[0054] In one embodiment, the insulating gate structure 215 includes a first portion 215a and a second portion 215b, which may be parts of the same layer forming the first dielectric region 213a and the second dielectric region 213b, respectively. The first layer forming the first dielectric region 213a of the insulating field structure 213 and the first portion 215a of the insulating gate structure 215 extends continuously between the source contact 7 and the drain contact 8, covering the barrier layer 3, the gate region 5, and the gate contact 9. The second layer forming the second dielectric region 213b of the insulating field structure 213 and the second portion 215b of the insulating gate structure 215 covers the gate region 5 and the gate contact 9 and extends to the window 17 where the second layer is interrupted. The second portion 215b of the insulating gate structure 215 defines the window 17 on the side facing the gate region 5.

[0055] refer to Figures 5 to 9 In the method for manufacturing the integrated device 1 according to the embodiment of the present disclosure, the heterostructure 10 is initially fabricated in the semiconductor wafer 50, and the gate region 5 and the gate contact 9 are formed on the heterostructure 10. Then, the first dielectric layer 30, the second dielectric layer 32, and the third dielectric layer 33 are successively laid on the heterostructure 10 and on the gate region 5, covering both.

[0056] The first dielectric layer 30 is made of a first material, such as aluminum oxide, and has a first thickness T1. The second dielectric layer 32 is made of a second material, such as silicon oxide, and has a second thickness T2. The third dielectric layer 33 is made of a third material, such as silicon nitride, and in one embodiment has a thickness less than the third thickness T3.

[0057] The first dielectric layer 30 defines a first dielectric region 13 a of the insulating field structure 13 and a first portion 15 a of the insulating gate structure 15 .

[0058] Next ( Figure 6 ), source contact 7 and drain contact 8 are formed. For this purpose, the first dielectric layer 30, the second dielectric layer 32, and the third dielectric layer 33 are etched using the same mask, and after the annealing step, a metal sputtering operation is performed.

[0059] The third dielectric layer 33 is then increased until a third desired thickness T3 is obtained by using further deposition of the third material. The increase in the third dielectric layer 33 due to the further deposition is determined by Figure 7 In this step, the source contact 7 and the drain contact 8 are covered so as to remain separated from each other during the subsequent formation of the field plate 12 .

[0060] The third dielectric layer 33 and the second dielectric layer 32 are then Figure 8 3. The first dielectric layer 32 is selectively etched in the order shown in the figure. For the etching operation, a corresponding mask is used, which is not shown for the sake of simplicity. If the selected material is selectively etchable, the etching stops automatically on the bottom layer. In particular, the third dielectric region 13c of the insulating field structure 13 and the third part 15c of the insulating source structure 15 are obtained from the third dielectric layer 33. The window 17 is opened in the second dielectric layer 32, thereby separating the second dielectric region 13b of the insulating gate structure 13 from the second part 15b of the insulating source structure 15 and exposing the first dielectric region 13a.

[0061] The metal layer 35 is then formed by metal evaporation and then patterned using another mask (not shown) to form the field plate 12 ( Fig. 9 ). During this step, the source contact 7 and the drain contact 8 are covered and protected by the portion of the third dielectric layer 33 obtained during the deposition, so as to be able to increase to the third thickness T3.

[0062] The final processing steps are then carried out, among which are the step of laying down the protection layer 16 and the step of providing the source terminal 7a and the drain terminal 8a. Figure 1 The integrated device 1 is thus obtained.

[0063] According to a variant not shown in the method, before the formation of the source contact 7 and the drain contact 8, the third dielectric layer 33 and the second dielectric layer 32 are selectively etched successively in that order to define the insulating field structure 13 (the third dielectric region 13c and the second dielectric region 13b) and the insulating source structure 15. In particular, according to one embodiment, after the etching of the third dielectric layer 33 and the second dielectric layer 32, the contact window is opened for the source contact 7 and the drain contact 8, and the metal layer is laid by sputtering and then defined to simultaneously form the source contact 7, the drain contact 8, and the field plate 13. Alternatively, the first metal layer is formed by sputtering, then the contact window is opened for the source contact 7 and the drain contact 8, and the metal layer is sputtered to form the insulating field structure 13, and finally the source contact 7 and the drain contact 8 are formed by metal evaporation.

[0064] According to different embodiments of the method of the present disclosure ( Fig.10 ), the heterostructure 10 and the gate region 5 are initially formed. Then, a first dielectric layer 30 and a second dielectric layer 332 of, for example, silicon oxide are continuously laid in sequence on the heterostructure 10 and on the gate region 5, thus covering both. The first dielectric layer 30 and the second dielectric layer 332 are then patterned to open contact windows, in which the source contact 7 and the drain contact 8 are formed. The second dielectric layer 332 can be replaced to the final desired thickness by further deposition of the second dielectric material, which also covers the source contact 7 and the drain contact 8.

[0065] refer to Fig.11, the second layer 332 is then defined to form an insulating field structure using "grayscale" lithographic technology, which makes it possible to obtain different densities of photoresist from a single layer (see, for example, Yu Pang, Yi Shu, Mohammad Shavetipur, Xuefeng Wang, Mohammad Ali Mohammad, Yi Yang, Haiming Zhao, Ningqin Deng, Roya Maboudian, and Tian-Ling Ren, "3D Stretchable Arch ribbon Array Fabricated via Grayscale Lithography", Scientific Reports, volume 6, Article number: 28552 (2016)). In practice, the photoresist layer is exposed and impressed in different ways using diffraction through a mask with variable density and / or aperture width. In areas with higher density and / or aperture width, the photoresist is exposed more and a lower final density is obtained; conversely, in areas with lower density and / or aperture width, the photoresist is exposed to a lesser extent and a higher final density is obtained. Fig.11 Neutralization in the subsequent Fig.12 , the variable density of the photoresist layer is represented by different shades of gray; darker shades of gray correspond to areas with higher density, and lighter shades of gray correspond to areas with lower density.

[0066] Therefore, in order to obtain Figure 3 The integrated device 100 may use a protective photoresist layer 350 ( Fig.11 ), the protective photoresist layer 350 has a portion 350a containing a minimum density, a portion 350b containing a medium density, and a portion 350c containing a maximum density on the first dielectric region 113a, the second region 113b, and the third region 113c of the insulating field structure 113, respectively.

[0067] On the contrary, in order to obtain Figure 3 The integrated device 200 may use a protective photoresist layer 360 ( Fig.12 ), the protective photoresist layer 330 has a portion 360a having a minimum density, a portion 360b having a linearly variable density, and a portion 360c having a maximum density on the first dielectric region 213a and the second region 213b of the insulating field structure 213. The density of the portion 360b varies between the minimum density of the portion 360a and the maximum density of the portion 360c.

[0068] The present disclosure enables advantageously improved performance of integrated power devices, in particular HEMTs of the normally-off type. More precisely, the use of materials that can be selectively etched relative to each other for producing an insulating field structure enables the thickness of the first part of the insulating field structure to be controlled with an accuracy in the nanometer range. The limits of accuracy are in fact determined by the deposition process, by which a layer with a thickness of even a few atoms may be formed. Thanks to the selectivity of the material, without any need for fine time control, the etching of the overlapping structure stops automatically, and the thickness of the underlying layer, in particular the thickness of the first part of the insulating field structure, is not involved therein. In this way, near the gate region, the field plate can be reduced to a distance of only a few nanometers from the barrier layer, that is, equal to the thickness of only the first part of the insulating field structure. This makes it possible to significantly reduce the gate-drain capacitance and, therefore, reduce the accumulated charge, thereby facilitating the performance of the integrated device. As the distance from the gate region increases, the thickness of the insulating field structure can be increased according to design preferences, thereby maintaining the breakdown resistance. The profile of the insulating field structure can also be selected according to design preferences, such as stepped or ramped. Advantageously, the thickness of the insulating field structure has at least an intermediate value between a minimum value near the gate region and a maximum value at the drain terminal.

[0069] Finally, it is evident that modifications and variations may be made to the integrated device and to the method described herein, without thereby departing from the scope of the present disclosure as defined in the appended claims.

[0070] For example, the insulating field structure may have more steps (four or more) depending on design preference.

[0071] The integrated power device can be summarized as comprising: a heterostructure (10) comprising a channel layer (2) and a barrier layer (3); a source contact (7), a drain contact (8) and a gate region (5), wherein the gate region (5) is on the barrier layer (3) and between the source contact (7) and the drain contact (8); an insulating field structure (13) arranged on the barrier layer (3) and between the gate region (5) and the drain contact (8); and a field plate (12) on the insulating field structure (13), wherein the insulating field structure (13; 113; 213) comprises a channel layer (2) and a barrier layer (3); a source contact (7), a drain contact (8) and a gate region (5), wherein the gate region (5) is on the barrier layer (3) and between the source contact (7) and the drain contact (8); 3) and a second dielectric region (13b; 113b; 213b) of a second dielectric material on the first dielectric region (13a; 113a; 213a), the second dielectric material being selectively etchable relative to the first dielectric material; and wherein, on a side of the insulating field structure (13; 113; 213) facing the gate region (5), the field plate (12) is in contact with the first dielectric region (13a; 113a; 213a).

[0072] A window (17; 217) may be defined between the insulating gate structure (15) and the second dielectric region (13b; 113b; 213b) and the field plate (12) may be in contact with the first dielectric region (13a; 113a; 213a) in the window (17; 217).

[0073] The window (17; 217) may be arranged at a distance (D') less than 200 nm from the gate region (5).

[0074] The first dielectric region (13a; 113a; 213a) may have a first thickness (T1) smaller than 10 nm, for example between 3 nm and 5 nm.

[0075] The insulating field structure (13; 113; 213) may have a minimum thickness on the side of the insulating field structure (13; 113; 213) facing the gate region (5), corresponding to the first thickness (T1) of the first dielectric region (13a; 113a; 213a), a maximum thickness (T1+T2+T3; T1+T2') on the side of the insulating field structure (13; 113; 213) facing the drain terminal (3), and an intermediate thickness (T1+T2) between the side of the insulating field structure (13; 113; 213) facing the gate region (5) and the side facing the drain terminal (3).

[0076] The insulating field structure (13; 113) may have a stepped profile and may include a third dielectric region (13c; 113c) on the second dielectric region (13b; 113b).

[0077] The second dielectric region (13b; 113b) may have a second thickness (T2) not greater than 100 nm, for example between 30 nm and 50 nm, and the third dielectric region (13c; 113c) may have a third thickness (T3) not greater than 500 nm, for example between 100 nm and 150 nm.

[0078] The third dielectric region (13c) may be made of a third dielectric material that is selectively etchable relative to the second dielectric material.

[0079] The first dielectric region (13a), the second dielectric region (13b), and the third dielectric region (13c) may be made of aluminum oxide, silicon oxide, and silicon nitride, respectively.

[0080] The second dielectric region (213b) of the insulating field structure (213) may have a sloped profile.

[0081] The barrier layer (3) may have a first conductivity type and the gate region (5) may have a second conductivity type opposite to the first conductivity type.

[0082] The method for manufacturing an integrated power device can be summarized as comprising: forming a heterostructure (10) comprising a channel layer (2) and a barrier layer (3); forming a source contact (7), a drain contact (8) and a gate region (5) between the source contact (7) and the drain contact (8) on the barrier layer (3); forming an insulating field structure (13) on the barrier layer (3) between the gate region (5) and the drain contact; and forming a field plate (12) on the insulating field structure (13); wherein forming the insulating field structure (13; 113; 213) comprises: forming a first dielectric layer (30) of a first dielectric material on the barrier layer (3); forming a first dielectric layer (30) of a first dielectric material on the first dielectric ... A second dielectric layer (32; 332) of a second dielectric material is formed on the dielectric layer (13a; 113a; 213a), the second dielectric material being selectively etchable relative to the first dielectric material; the second dielectric layer (32; 332) on the side of the insulating field structure (13; 113; 213) facing the gate region (5) is selectively etched to expose a portion of the first dielectric layer (30) at the gate region (5); and the field plate (12) is in contact with the first dielectric region (13a; 113a; 213a) in which the first dielectric region (13a; 113a; 213a) has been exposed.

[0083] Selectively etching may include defining a window (17; 217) between the insulating gate structure (15) and the second dielectric region (13b; 113b; 213b) and the field plate (12) may contact the first dielectric region (13a; 113a; 213a) in the window (17; 217).

[0084] Forming the insulating field structure (13) may include: forming a third dielectric layer (33) of a third dielectric material on the second dielectric layer (13b), the third dielectric material being selectively etchable relative to the second dielectric material; and selectively etching the third dielectric material (33) to expose the second dielectric layer (32) between the window (17; 217) and the drain contact (8) and define a stepped profile of the insulating field structure (13).

[0085] Forming the insulating field structure (113; 213) may include patterning the second layer (332) using greyscale photolithography techniques to define a stepped or sloped profile of the insulating field structure (113; 213).

[0086] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0087] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. An integrated power device, characterized in that: include: Heterostructures, including channel layers and barrier layers; a source contact, a drain contact, and a gate region, wherein the gate region is on the barrier layer and between the source contact and the drain contact, the gate region having a top side, a first lateral side, and a second lateral side; an insulating field structure on the barrier layer and between the gate region and the drain contact; as well as A field plate, on the insulating field structure, wherein the insulating field structure comprises: a first dielectric region of a first dielectric material on the barrier layer; and a second dielectric region of a second dielectric material on the first dielectric region, the second dielectric material being selectively etchable relative to the first dielectric material; wherein, on a side of the insulating field structure facing the gate region, the field plate is in contact with the first dielectric region; and The field plate overlaps the first lateral side of the gate region, partially overlaps the top side of the gate region, and does not overlap the second lateral side of the gate region.

2. The device according to claim 1, characterized in that An insulated gate structure is included between the field plate and the gate region, wherein a window is between the insulated gate structure and the second dielectric region and the field plate contacts the first dielectric region in the window.

3. The device according to claim 2, characterized in that The window is located at a distance of less than 200 nm from the gate region.

4. The device according to claim 1, characterized in that The first dielectric region has a first thickness less than 10 nm.

5. The device according to claim 1, characterized in that the insulating field structure having: a minimum thickness on the side of the insulating field structure facing the gate region corresponding to the first thickness of the first dielectric region; a maximum thickness on the side of the insulating field structure facing the drain terminal; and an intermediate thickness between the side of the insulating field structure facing the gate region and the side facing the drain terminal.

6. The device according to claim 5, characterized in that The insulating field structure has a stepped profile and includes a third dielectric region on the second dielectric region.

7. The device according to claim 6, characterized in that The second dielectric region has a second thickness between 30 nm and 50 nm, and wherein the third dielectric region has a third thickness between 100 nm and 150 nm.

8. The device according to claim 6, characterized in that The third dielectric region is made of a third dielectric material that is selectively etchable relative to the second dielectric material.

9. The device according to claim 6, characterized in that The first dielectric region, the second dielectric region, and the third dielectric region are made of aluminum oxide, silicon oxide, and silicon nitride, respectively.

10. The device according to claim 1, characterized in that The second dielectric region of the insulating field structure has a sloped profile.

11. The device according to claim 1, characterized in that The barrier layer has a first conductivity type and the gate region has a second conductivity type opposite to the first conductivity type.

12. A HEMT transistor, characterized in that: include: A heterostructure having a first surface; a source terminal on the first surface; a drain terminal on the first surface; a gate region on the first surface between the source terminal and the drain terminal, the gate region having a top side, a first lateral side facing the drain terminal, and a second lateral side facing the source terminal; a first dielectric layer between the source terminal and the drain terminal, on the gate region and on the first surface; a first insulating structure on the first dielectric layer and in contact with the drain terminal; a second insulating structure on the first dielectric layer and in contact with the source terminal, the first insulating structure not in contact with the second insulating structure; as well as A field plate of a conductive material is between the gate region and the drain terminal, on the first insulating structure, partially on the second insulating structure, and partially overlaps the gate region.

13. The HEMT transistor according to claim 12, characterized in that The second insulating structure comprises: a first portion overlapping the top side, the first lateral side, and the second lateral side of the gate region; and The second portion overlaps the first lateral side of the gate region and partially overlaps the top side of the gate region, but does not overlap the second lateral side of the gate region.

14. The HEMT transistor according to claim 13, characterized in that The first portion and the second portion of the second insulating structure are made of different materials.

15. The HEMT transistor according to claim 12, wherein: The field plate is electrically coupled to the source terminal.

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