Display panel

Abstract

A display panel includes: a base layer; a circuit layer disposed on the base layer and including a plurality of pixel pattern units arranged in a first direction and a second direction crossing the first direction; a valley defined between the plurality of pixel pattern units; and a filler disposed in the valley, in which each of the plurality of pixel pattern units includes at least one semiconductor layer and at least one conductive layer, and in which a portion of a side surface of the valley is defined by at least one layer among the at least one semiconductor layer and the at least one conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0044373, filed on April 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display panel, and more particularly, to a display panel having improved durability. Background Art

[0004] A display device provides information to a user by displaying various images in a display screen. Typically, a display device displays information within an assigned screen. In recent years, a display device including a foldable flexible display panel has been developed. Compared with a rigid display panel, a flexible display panel may have high flexibility and low durability. Utility Model Content

[0005] Embodiments of the present disclosure provide a display panel having improved durability.

[0006] According to an embodiment, a display panel includes: a base layer; a circuit layer, which is disposed on the base layer and includes a plurality of pixel pattern units arranged in a first direction and in a second direction intersecting the first direction; a valley, defined between the plurality of pixel pattern units; and a filling member, which is disposed in the valley, wherein each of the plurality of pixel pattern units includes at least one semiconductor layer and at least one conductive layer, and wherein a portion of a side surface of the valley is defined by at least one layer among the at least one semiconductor layer and the at least one conductive layer.

[0007] In an embodiment, the at least one layer may be in direct contact with the filler.

[0008] In an embodiment, the filler may be an organic material.

[0009] In an embodiment, a portion of a bottom surface of the valley may be defined by any one of the at least one semiconductor layer and the at least one conductive layer.

[0010] In an embodiment, any one of the layers may be in direct contact with the filler.

[0011] In an embodiment, the valley may include a first valley extending in the first direction and a second valley extending in the second direction crossing the first direction.

[0012] In an embodiment, each of the plurality of pixel pattern units may include a first sub-pixel pattern unit and a second sub-pixel pattern unit that is linearly symmetrical to the first sub-pixel pattern unit.

[0013] In an embodiment, the circuit layer may include: a first semiconductor layer, arranged on the base layer; a first insulating layer, covering the first semiconductor layer; a first conductive layer, arranged on the first insulating layer; a second insulating layer, covering the first conductive layer; a second conductive layer, arranged on the second insulating layer; a third insulating layer, covering the second conductive layer; a second semiconductor layer, arranged on the third insulating layer; a fourth insulating layer, covering the second semiconductor layer; a third conductive layer, arranged on the fourth insulating layer; and a fifth insulating layer, covering the third conductive layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be inorganic insulating layers.

[0014] In an embodiment, the valley may be provided by removing at least a portion of each of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer.

[0015] In an embodiment, the portion of the side surface of the valley may be defined by at least one of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer.

[0016] In an embodiment, a portion of a bottom surface of the valley may be defined by at least one of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer.

[0017] According to an embodiment, a display panel includes: a base layer; a circuit layer including at least one semiconductor layer, at least one conductive layer and at least one inorganic insulating layer; a light-emitting element layer disposed on the circuit layer; and an encapsulation layer disposed on the light-emitting element layer, wherein a valley formed by removing a portion of the at least one inorganic insulating layer is defined in the circuit layer, and a portion of a side surface of the valley is defined by at least one layer among the at least one semiconductor layer and the at least one conductive layer.

[0018] In an embodiment, the display panel may further include an organic filler filled in the valley.

[0019] In an embodiment, the at least one layer among the at least one semiconductor layer and the at least one conductive layer may be in direct contact with the organic filler.

[0020] In an embodiment, a portion of a bottom surface of the valley may be defined by any one of the at least one semiconductor layer and the at least one conductive layer.

[0021] In an embodiment, any one of the at least one semiconductor layer and the at least one conductive layer may be in direct contact with the organic filler.

[0022] In an embodiment, the valley may include a plurality of first valleys and a plurality of second valleys intersecting the plurality of first valleys, wherein each of the plurality of first valleys may extend in a first direction and the plurality of first valleys may be spaced apart from each other in a second direction intersecting the first direction, and wherein each of the plurality of second valleys may extend in the second direction and the plurality of second valleys may be spaced apart from each other in the first direction.

[0023] According to an embodiment, a display panel includes: a base layer; a circuit layer, which is disposed on the base layer and includes a plurality of pixel pattern units and a plurality of inorganic insulating layers, the plurality of pixel pattern units being arranged in a first direction and in a second direction intersecting the first direction; a valley, which is defined by removing portions of the plurality of inorganic insulating layers between the plurality of pixel pattern units; and a filler, which is filled in the valley and is an organic filler, wherein each of the pixel pattern units may include at least one semiconductor layer and at least one conductive layer, wherein the at least one semiconductor layer and the at least one conductive layer exposed by the valley are in direct contact with the filler.

[0024] In an embodiment, the valley may include a first valley extending in the first direction and a second valley extending in the second direction crossing the first direction.

[0025] In an embodiment, each of the plurality of pixel pattern units may include a first sub-pixel pattern unit and a second sub-pixel pattern unit that is linearly symmetrical to the first sub-pixel pattern unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0027] Figure 1A is a perspective view of an electronic device according to an embodiment.

[0028] Figure 1B is a perspective view of an electronic device according to an embodiment.

[0029] Figure 2 is a plan view of a display panel according to an embodiment.

[0030] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0031] Figure 4 is a partial cross-sectional view showing a portion of a display panel according to an embodiment.

[0032] Figure 5 is an enlarged plan view showing a portion of a display panel according to an embodiment.

[0033] Figure 6 is a plan view of a stacking order of pixel pattern units according to an embodiment.

[0034] Figure 7 is a plan view of a stacking order of pixel pattern units according to an embodiment.

[0035] Figure 8 is a plan view of a stacking order of pixel pattern units according to an embodiment.

[0036] Fig. 9 is a plan view of a stacking order of pixel pattern units according to an embodiment.

[0037] Fig.10 is a plan view of a stacking order of pixel pattern units according to an embodiment.

[0038] Fig.11 is an enlarged plan view showing a portion of a display panel according to an embodiment.

[0039] Fig.12 is a schematic cross-sectional view illustrating a part of a method of manufacturing a display panel according to an embodiment.

[0040] Fig.13A is according to the embodiment corresponding to Fig.11 A cross-sectional view along line II' shown in FIG.

[0041] Fig. 13B is according to the embodiment corresponding to Fig.11 A cross-sectional view along line II-II' shown in FIG.

[0042] Fig.14 is according to the embodiment corresponding to Fig.11 A cross-sectional view along line II' shown in FIG. DETAILED DESCRIPTION

[0043] In the present disclosure, the expression that a first component (or region, layer, part, portion, etc.) is "on" a second component, that a first component is "connected to" a second component, or that a first component is "coupled to" a second component means that the first component can be directly on the second component, that the first component is directly connected to the second component, or that the first component is directly coupled to the second component, or that a third component is between the first component and the second component.

[0044] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. The expression "and / or" includes one or more combinations that the related components can define.

[0045] Although the terms "first", "second", etc. may be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present disclosure. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0046] In addition, the terms “below”, “beneath”, “on”, and “over” etc. are used to describe the relationship of components shown in the drawings. These terms, which are relative concepts, can be described based on the directions shown in the drawings.

[0047] It will be understood that the terms "include", "comprising", "having", etc. specify the presence of the features, quantities, steps, operations, elements or components, or a combination thereof, described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements or components, or a combination thereof.

[0048] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formalized sense.

[0049] Terms such as "component" and "unit" refer to software components or hardware components that perform specific functions. Hardware components may include, for example, field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Software components may refer to executable code in an addressable storage medium and / or data used by the executable code. Thus, software components may be, for example, object-oriented software components, class components, and task components, and may include processes, functions, properties, programs, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, or variables.

[0050] Hereinafter, the present disclosure will now be more fully described with reference to the accompanying drawings in which embodiments are shown. However, the present disclosure may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0051] Figure 1A and Figure 1B is a perspective view of an electronic device EDE according to an embodiment.

[0052] Reference Figure 1A and Figure 1B , the electronic device EDE according to the embodiment may include a display surface DS defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. The electronic device EDE may provide an image IM to a user via the display surface DS.

[0053] In an embodiment, the display surface DS may include a display area DA and a non-display area NDA disposed around the display area DA. The display area DA may display an image IM, and the non-display area NDA may not display the image IM. The non-display area NDA may surround the display area DA. However, the present disclosure is not limited thereto, and the shape of the display area DA and the shape of the non-display area NDA may be changed.

[0054] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In addition, in the present disclosure, the meaning of "on a plane" may be defined as a state of "when viewed in the third direction DR3".

[0055] In an embodiment, a sensor area ED-SA may be defined within a display area DA of the electronic device EDE. Figure 1A One sensor area ED-SA is schematically shown, but the number of the sensor areas ED-SA is not limited thereto. The sensor area ED-SA may be omitted, or two or more sensor areas ED-SA may be provided.

[0056] In an embodiment, the sensor area ED-SA may be a part of the display area DA. Therefore, the electronic device EDE may display an image via the sensor area ED-SA. In an embodiment, the sensor area ED-SA may be a non-display area in which the image IM is not displayed.

[0057] In an embodiment, the electronic module may be disposed in a portion overlapping the sensor area ED-SA. The electronic module may receive an external input transmitted via the sensor area ED-SA and / or provide an output via the sensor area ED-SA. For example, the electronic module may be a camera module, a sensor such as a proximity sensor that measures a distance, a sensor that recognizes a part of a user's body (e.g., a fingerprint, an iris, or a face), and / or a small lamp that outputs a light beam, but the present disclosure is not particularly limited thereto.

[0058] In an embodiment, the electronic device EDE may include a folding area FA and a plurality of non-folding areas NFA1 and NFA2. The non-folding areas NFA1 and NFA2 may include a first non-folding area NFA1 and a second non-folding area NFA2. The folding area FA may be disposed between the first non-folding area NFA1 and the second non-folding area NFA2. The folding area FA may refer to a foldable area, and the first non-folding area NFA1 and the second non-folding area NFA2 may refer to a first non-foldable area and a second non-foldable area.

[0059] In the embodiments and Figure 1B As shown in , the folding area FA can be folded relative to a folding axis FX parallel to the first direction DR1. In a state where the electronic device EDE is folded, the folding area FA has a predetermined curvature and a predetermined curvature radius. The first non-folding area NFA1 and the second non-folding area NFA2 can face each other, and the electronic device EDE can be folded inwardly so that the display surface DS is not exposed to the outside.

[0060] In an embodiment, the electronic device EDE can be folded outward so that the display surface DS is exposed to the outside. In an embodiment, the electronic device EDE can be folded inward or outward from the unfolding operation, but the present disclosure is not limited thereto. In an embodiment, the electronic device EDE can select any one of the unfolding operation, the inward folding operation, and the outward folding operation. In an embodiment, a plurality of folding axes are defined in the electronic device EDE, and the electronic device EDE can be folded inward or outward from the unfolding operation for each of the plurality of folding axes.

[0061] exist Figure 1A and Figure 1BIn the embodiment of the foldable electronic device EDE, an example has been described, but the present disclosure is not limited to the foldable electronic device EDE. For example, the present disclosure can be applied to a bar-shaped rigid electronic device, such as an electronic device that does not include a folding area FA. In addition, the present disclosure can also be applied to various electronic devices such as a rollable electronic device and a slidable electronic device.

[0062] Figure 2 is a plan view of a display panel DP according to an embodiment.

[0063] In the examples and with reference to Figure 2 , a display area DP-DA and a non-display area DP-NDA arranged around the display area DP-DA may be defined in the display panel DP. The display area DP-DA and the non-display area DP-NDA may be distinguished from each other depending on whether a pixel PX is provided. The pixel PX is provided in the display area DP-DA. The scan drive unit SDV, the data drive unit, and the light emitting drive unit EDV may be arranged in the non-display area DP-NDA. The data drive unit may be a part of a circuit included in a driver chip DIC. In an embodiment, at least a part of the scan drive unit SDV and the light emitting drive unit EDV may be provided in the display area DP-DA.

[0064] In an embodiment, the display panel DP may include a first panel area AA1, a bending area BA, and a second panel area AA2 defined in the second direction DR2. The second panel area AA2 and the bending area BA may be partial areas of the non-display area DP-NDA. The bending area BA is disposed between the first panel area AA1 and the second panel area AA2.

[0065] In the embodiment, the first panel area AA1 corresponds to Figure 1A The first panel area AA1 may include a first non-folding area NFA10, a second non-folding area NFA20, and a folding area FA0. The first non-folding area NFA10, the second non-folding area NFA20, and the folding area FA0 correspond to Figure 1A and Figure 1B The first non-folding area NFA1, the second non-folding area NFA2 and the folding area FA.

[0066] In an embodiment, the width of the bending area BA parallel to the first direction DR1 and the width (or length) of the second panel area AA2 parallel to the first direction DR1 may be smaller than the width (or length) of the first panel area AA1 parallel to the first direction DR1. The area with a shorter length in the bending axis direction may be bent more easily.

[0067] In an embodiment, the display panel DP may include pixels PX, initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, light emission control lines ECL1 to ECLm, data lines DL1 to DLn, first and second control lines CSL1 and CSL2, driving voltage lines PL, and a plurality of pads PD. In this case, "m" and "n" are natural numbers greater than or equal to 1.

[0068] In embodiments, pixels PX may be electrically connected to initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, and data lines DL1 to DLn.

[0069] In an embodiment, the initialization scan lines GIL1 to GILm, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, and the black scan lines GBL1 to GBLm may extend in the first direction DR1 and may be electrically connected to the scan driving unit SDV. The data lines DL1 to DLn may extend in the second direction DR2 and may be electrically connected to the driving chip DIC via the bending area BA. The light emission control lines ECL1 to ECLm may extend in a direction opposite to the first direction DR1 and may be electrically connected to the light emission driving unit EDV.

[0070] In an embodiment, the driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be arranged in different layers. The portion of the driving voltage line PL extending in the second direction DR2 may extend to the second panel area AA2 via the bending area BA. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0071] In an embodiment, the first control line CSL1 may be electrically connected to the scan driving unit SDV and may extend toward the lower end of the second panel area AA2 via the bending area BA. The second control line CSL2 may be electrically connected to the light emitting driving unit EDV and may extend toward the lower end of the second panel area AA2 via the bending area BA.

[0072] In an embodiment, when viewed on a plane, the pad PD may be arranged adjacent to the lower end of the second panel area AA2. The driving chip DIC, the driving voltage line PL, the first control line CSL1, and the second control line CSL2 may be electrically connected to the pad PD. The flexible circuit film FCB may be electrically connected to the pad PD via an anisotropic conductive adhesive layer.

[0073] Figure 3 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the present disclosure.

[0074] In an embodiment, Figure 3 A plurality of pixels PX are shown as an example (see Figure 2 ) is an equivalent circuit diagram of one pixel PXij among the pixels PX. Since the plurality of pixels PX have the same circuit structure, detailed descriptions of the other pixels PX will be omitted because of the description of the circuit structure of the pixel PXij.

[0075] In the examples and with reference to Figure 2 and Figure 3 , the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th light emission control line ECLj among the light emission control lines ECL1 to ECLm, the first drive voltage line VL1 and the second drive voltage line VL2, and the first initialization voltage line VL3 and the second initialization voltage line VL4. It should be understood that i is an integer greater than or equal to 1 and less than or equal to n, and j is an integer greater than or equal to 1 and less than or equal to m.

[0076] In an embodiment, the pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. As an example, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but the present disclosure is not particularly limited thereto. The pixel circuit PDC may control the amount of current flowing in the light emitting element ED in response to the i-th data signal Di. The light emitting element ED may emit a light beam having a predetermined brightness to correspond to the amount of current provided from the pixel circuit PDC.

[0077] In an embodiment, the pixel circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a capacitor Cst. According to an embodiment, the configuration of the pixel circuit PDC is not limited to Figure 3 The embodiment shown in . Figure 3 The pixel circuit PDC shown in FIG. 1 is merely an example, and the configuration of the pixel circuit PDC may be modified and implemented.

[0078] In an embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be low temperature polycrystalline silicon (LTPS) transistors.

[0079] In detail, in an embodiment, the first transistor T1 that directly affects the brightness of the light-emitting element ED includes a polycrystalline silicon semiconductor layer with high reliability, and therefore, a high-resolution display device can be realized. At the same time, since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not large even if the driving time is long. That is, since the color change of the image caused by the voltage drop is not large even during low-frequency driving, low-frequency driving can be performed. In this way, since the oxide semiconductor has a low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can adopt an oxide transistor, and therefore the leakage current that may flow to the gate electrode of the first transistor T1 can be prevented, and at the same time, power consumption can be reduced.

[0080] In an embodiment, some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the other transistors of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0081] The configuration of the pixel circuit PDC according to the present disclosure is not limited to Figure 3 The embodiment shown in . Figure 3The pixel circuit PDC shown in is only an example and the configuration of the pixel circuit PDC can be modified and implemented. For example, in an embodiment, all of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be P-type transistors or N-type transistors. Alternatively, the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 may be P-type transistors, and the third transistor T3, the fourth transistor T4 and the seventh transistor T7 may be N-type transistors.

[0082] In an embodiment, the jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj may transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a voltage level corresponding to the image signal.

[0083] In an embodiment, the first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT and VAINT to the pixels PXij, respectively.

[0084] In an embodiment, the first transistor T1 is connected between the light emitting element ED and the first driving voltage line VL1 receiving the first driving voltage ELVDD. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or referred to as an anode) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the capacitor Cst. The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2, and supply a driving current to the light emitting element ED.

[0085] In an embodiment, the second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 may be turned on according to the j-th write scan signal GWj transmitted via the j-th write scan line GWLj, and may transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0086] In an embodiment, the third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 may be turned on according to the j-th compensation scan signal GCj transmitted via the j-th compensation scan line GCLj, may connect the third electrode of the first transistor T1 and the second electrode of the first transistor T1 to each other, and thus may diode-connect the first transistor T1.

[0087] In an embodiment, the fourth transistor T4 is connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line GILj. The fourth transistor T4 is turned on according to the jth initialization scan signal GIj transmitted via the jth initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1, and initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0088] In an embodiment, the fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode (e.g., the second node N2) of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th light emission control line ECLj.

[0089] In an embodiment, according to the jth light emitting control signal EMj transmitted via the jth light emitting control line ECLj, the fifth transistor T5 and the sixth transistor T6 are turned on at the same time. The first driving voltage ELVDD applied via the turned-on fifth transistor T5 can be compensated via the diode-connected first transistor T1, and then can be transmitted to the light emitting element ED via the sixth transistor T6.

[0090] In an embodiment, the seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 to which the second initialization voltage VAINT is transmitted, a second electrode connected to the second node N2, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than or equal to the voltage level of the first initialization voltage VINT.

[0091] In an embodiment, one end of the capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be electrically connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than that of the first driving voltage ELVDD.

[0092] Figure 4 is a partial cross-sectional view showing a portion of the display panel DP according to the embodiment.

[0093] In the examples and with reference to Figure 4 , the display panel DP may include a display layer 100 , a sensor layer 200 , and an anti-reflection layer 300 . The display layer 100 may include a base layer 110 , a barrier layer BRL, a buffer layer BFL, a circuit layer 120 , an element layer 130 , and an encapsulation layer 140 .

[0094] In an embodiment, the base layer 110 may be a glass substrate, a metal substrate, a polymer substrate, etc. However, the present disclosure is not limited thereto, and the base layer 110 may be an inorganic layer, an organic layer, or a composite material layer. In an embodiment, the base layer 110 may include a plurality of sub-base layers. For example, each of the plurality of sub-base layers may include at least one of a polyimide-based resin, an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy-based resin, a polyurethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In the specification, an "X"-based resin (or a word before "base resin") refers to a resin containing an "X" functional group. For example, a "polyimide-based resin" refers to a "resin in which a functional group of polyimide may be included in a base material".

[0095] In an embodiment, a barrier layer BRL may be disposed on the base layer 110. A buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer 110 to the first semiconductor pattern SCP1. In addition, the buffer layer BFL may adjust a heat supply rate during a crystallization process for forming the first semiconductor pattern SCP1 so that the first semiconductor pattern SCP1 is uniformly formed.

[0096] In an embodiment, each of the barrier layer BRL and the buffer layer BFL may include a plurality of inorganic layers. Each of the plurality of inorganic layers may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon, but the present disclosure is not particularly limited thereto.

[0097] In an embodiment, the first lower metal layer BML1 may be disposed between the barrier layer BRL and the buffer layer BFL. The first lower metal layer BML1 may be referred to as a first lower layer, a first lower light blocking layer, a first lower electrode layer, a first lower shielding layer, a first light blocking layer, a first metal layer, a first electrode layer, a first shielding layer, or a first overlapping layer. Figure 4 Unlike the illustration of FIG. 1 , the first lower metal layer BML1 may be disposed between the plurality of inorganic layers of the barrier layer BRL. In an embodiment, the first lower metal layer BML1 may be omitted.

[0098] In an embodiment, one pixel PX may include a light emitting element ED and a pixel circuit PDC. The circuit layer 120 may be disposed on the buffer layer BFL, and the element layer 130 may be disposed on the circuit layer 120. Figure 4 , the pixel circuit PDC may be included in the circuit layer 120 , and the light emitting element ED may be included in the element layer 130 .

[0099] In an embodiment, Figure 4 FIG. 4 shows a silicon thin film transistor S-TFT and an oxide thin film transistor O-TFT of a pixel circuit PDC. The silicon thin film transistor S-TFT may be Figure 3 The oxide thin film transistor O-TFT may be one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 described in Figure 3 One of the third transistor T3 and the fourth transistor T4 described in .

[0100] In an embodiment, the first semiconductor pattern SCP1 may be disposed on the buffer layer BFL. The first semiconductor pattern SCP1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon and polycrystalline silicon, etc. For example, the first semiconductor pattern SCP1 may include low temperature polycrystalline silicon.

[0101] In an embodiment, Figure 4Only a portion of the first semiconductor pattern SCP1 disposed on the buffer layer BFL is shown, and the first semiconductor pattern SCP1 may also be disposed in another region. The first semiconductor pattern SCP1 may be arranged in a specific rule across a plurality of pixels. Depending on whether the first semiconductor pattern SCP1 is doped, the first semiconductor pattern SCP1 may have different electrical characteristics. The first semiconductor pattern SCP1 may include a first region having a higher electrical conductivity and a second region having a lower electrical conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be a region doped at a concentration lower than that of the first region.

[0102] In an embodiment, the conductivity of the first region is greater than that of the second region, and the first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to an active region (or channel) of a transistor. In other words, a portion of the first semiconductor pattern SCP1 may be an active region of a transistor, another portion of the first semiconductor pattern SCP1 may be a source region or a drain region of the transistor, and another portion of the first semiconductor pattern SCP1 may be a connection electrode or a connection signal line.

[0103] In an embodiment, a source region SE1, an active region AC1, and a drain region DE1 of a silicon thin film transistor S-TFT may be formed of a first semiconductor pattern SCP1. The source region SE1 and the drain region DE1 may extend from the active region AC1 in opposite directions in a cross section.

[0104] In an embodiment, Figure 4 FIG. 4 shows a portion of a connection signal line CSL formed by the first semiconductor pattern SCP1. The connection signal line CSL may be electrically connected to the sixth transistor T6 (see FIG. 4 ). Figure 3 ) and the second electrode of the seventh transistor T7 (see Figure 3 )'s second electrode.

[0105] In an embodiment, the circuit layer 120 may include a plurality of inorganic layers and a plurality of organic layers. In an embodiment, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 sequentially stacked on the buffer layer BFL may be inorganic layers, and the sixth insulating layer 60 and the seventh insulating layer 70 may be organic layers. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be referred to as inorganic insulating layers. In an embodiment, except Figure 4 In addition to the insulating layers shown in FIG. 1 , other insulating layers may be added and may be omitted. Figure 4At least some of the insulating layers shown in .

[0106] In an embodiment, the first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the first semiconductor pattern SCP1. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. The insulating layer of the circuit layer 120 to be described below and the first insulating layer 10 may have a single-layer structure or a multi-layer structure.

[0107] In an embodiment, a gate electrode GT1 of a silicon thin film transistor S-TFT is disposed on the first insulating layer 10. The gate electrode GT1 may be a part of a metal pattern. The gate electrode GT1 overlaps with the active region AC1. In a process of doping the first semiconductor pattern SCP1, the gate electrode GT1 may be used as a mask. The gate electrode GT1 may include titanium, silver, an alloy containing silver, molybdenum, an alloy containing molybdenum, aluminum, an alloy containing aluminum, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, or indium zinc oxide, but the present disclosure is not particularly limited thereto.

[0108] In an embodiment, the second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate electrode GT1. The second insulating layer 20 may be an inorganic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the second insulating layer 20 may have a single-layer structure including a silicon nitride layer.

[0109] In an embodiment, the third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may be an inorganic layer and may have a single layer structure or a multilayer structure. For example, the third insulating layer 30 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer. Figure 3 One electrode Csta of the capacitor Cst may be disposed between the second insulating layer 20 and the third insulating layer 30. In addition, the other electrode of the capacitor Cst may be disposed between the first insulating layer 10 and the second insulating layer 20.

[0110] In an embodiment, the second semiconductor pattern SCP2 may be disposed on the third insulating layer 30. The second semiconductor pattern SCP2 may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions classified according to whether the metal oxide is reduced. The region in which the metal oxide is reduced (hereinafter referred to as the reduction region) has a higher conductivity than the region in which the metal oxide is not reduced (hereinafter referred to as the non-reduction region). The reduction region is substantially used as a source region / drain region or a signal line of a transistor. The non-reduction region substantially corresponds to an active region (or semiconductor region or channel) of a transistor. In other words, a portion of the second semiconductor pattern SCP2 may be an active region of a transistor, another portion of the second semiconductor pattern SCP2 may be a source region / drain region of a transistor, and another portion of the second semiconductor pattern SCP2 may be a signal transmission region.

[0111] In an embodiment, the source region SE2, the active region AC2, and the drain region DE2 of the oxide thin film transistor O-TFT may be formed by the second semiconductor pattern SCP2. The source region SE2 and the drain region DE2 may extend from the active region AC2 in opposite directions in a cross section.

[0112] In an embodiment, the oxide thin film transistor O-TFT may overlap with the second lower metal layer BML2. The second lower metal layer BML2 may be referred to as a second lower layer, a second lower light blocking layer, a second lower electrode layer, a second lower shielding layer, a second light blocking layer, a second metal layer, a second electrode layer, a second shielding layer, or a second overlapping layer.

[0113] In an embodiment, a light beam input from the lower side of the display panel DP is blocked by the second lower metal layer BML2 and thus may not be provided to the active area AC2 of the oxide thin film transistor O-TFT. The second lower metal layer BML2 may be disposed between the second insulating layer 20 and the third insulating layer 30. The second lower metal layer BML2 may be connected to the capacitor Cst (see Figure 3 ) includes the same material and may be formed through the same process. In an embodiment, the second lower metal layer BML2 may be omitted.

[0114] In an embodiment, the fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may cover the second semiconductor pattern SCP2. The fourth insulating layer 40 may be an inorganic layer and may have a single-layer structure or a multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the fourth insulating layer 40 may have a single-layer structure including silicon oxide.

[0115] In an embodiment, a gate electrode GT2 of an oxide thin film transistor O-TFT is disposed on a fourth insulating layer 40. The gate electrode GT2 may be a part of a metal pattern. The gate electrode GT2 overlaps with the active region AC2. In the process of reducing the second semiconductor pattern SCP2, the gate electrode GT2 may be used as a mask. In an embodiment, the second lower metal layer BML2 may be used as a bottom gate electrode. For example, the second lower metal layer BML2 may be electrically connected to the gate electrode GT2 or receive a signal that is the same as a signal received by the gate electrode GT2. However, this is merely an example, and the present disclosure is not particularly limited thereto.

[0116] In an embodiment, the fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the gate electrode GT2. The fifth insulating layer 50 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. For example, the fifth insulating layer 50 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0117] In an embodiment, the first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be electrically connected to the connection signal line CSL via a first contact hole CH1 passing through the first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50.

[0118] In an embodiment, a valley VLY formed by removing at least a portion of each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 (or at least some of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50) may be defined in the circuit layer 120. The valley VLY may be referred to as a valley or a groove.

[0119] In an embodiment, the valley VLY may not overlap with the light emitting region PXA to be described below in a plane. For example, the valley VLY may overlap with the first spacer HSPC in a plane. However, this is merely an example, and the present disclosure is not particularly limited thereto.

[0120] In an embodiment, a filler OM may be disposed in the valley VLY. The filler OM may include an insulating material. The filler OM may include an organic material. An impact applied to the display panel DP may be absorbed by the valley VLY and the filler OM filled in the valley VLY. Thus, the impact transmitted to the display area DP-DA (see Figure 2 ) can be dispersed by the valley VLY and the filler OM, or the transfer of the impact can be blocked. For example, even when a crack occurs in the inorganic layer, the transfer of the crack can be blocked by the valley VLY and the filler OM. Therefore, the durability of the display panel DP can be improved.

[0121] In an embodiment, at least one of at least one semiconductor layer and at least one conductive layer included in the circuit layer 120 may be used as a mask to form the valley VLY more deeply. Figure 4 It is shown that the first semiconductor pattern SCP1 is used as a mask. As the valley VLY becomes deeper, the impact transmitted into the display panel DP is better dispersed, or the transmission of the impact or the transmission of the crack can be more easily blocked. Therefore, the durability of the display panel DP can be further improved.

[0122] In an embodiment, Figure 4 It is shown that the valley VLY is provided by removing a portion of the buffer layer BFL in the thickness direction, but the present disclosure is not particularly limited thereto. For example, the valley VLY may be defined by removing only a portion of the first insulating layer 10, may be provided by removing the entire buffer layer BFL in the thickness direction, or may be provided by removing at least a portion of the barrier layer BRL in the thickness direction.

[0123] In an embodiment, a sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The second connection electrode CNE20 may be disposed on the sixth insulating layer 60. The second connection electrode CNE20 may be electrically connected to the first connection electrode CNE10 via a second contact hole CH2 passing through the sixth insulating layer 60. A seventh insulating layer 70 may be disposed on the sixth insulating layer 60 to cover the second connection electrode CNE20.

[0124] In an embodiment, each of the filler OM, the sixth insulating layer 60, and the seventh insulating layer 70 may include an organic material or an organic matter. For example, each of the filler OM, the sixth insulating layer 60, and the seventh insulating layer 70 may include a general polymer such as polystyrene (PS), benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer such as polyimide, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof, but the present disclosure is not particularly limited to the above examples.

[0125] In an embodiment, the filler OM may be filled in the valley VLY by the same process as that of the sixth insulating layer 60, or may be filled in the valley VLY by a process different from that of the sixth insulating layer 60. Therefore, in an embodiment, the first connection electrode CNE10 or an electrode (or a conductive pattern) disposed on the same layer as the layer on which the first connection electrode CNE10 is disposed may be disposed on the valley VLY and the filler OM.

[0126] In an embodiment, an element layer 130 including a light emitting element ED may be disposed on the circuit layer 120. The element layer 130 may be referred to as a light emitting element layer. The light emitting element ED may include a pixel electrode AE ​​(or anode), a first functional layer HFL, a light emitting layer EL, a second functional layer EFL, and a common electrode CE (or cathode). The first functional layer HFL, the second functional layer EFL, and the common electrode CE may be provided in common to the pixel PX.

[0127] In an embodiment, the pixel electrode AE ​​may be disposed on the seventh insulating layer 70. The pixel electrode AE ​​may be electrically connected to the second connection electrode CNE20 via the third contact hole CH3 passing through the seventh insulating layer 70. The pixel electrode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. In an embodiment, the pixel electrode AE ​​includes a reflective layer formed of silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, or a compound thereof, and a transparent electrode layer or a semi-transparent electrode layer formed on the reflective layer. The transparent electrode layer or the semi-transparent electrode layer may include at least one selected from indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, indium oxide, and aluminum-doped zinc oxide. For example, the pixel electrode AE ​​may include a multilayer structure in which indium tin oxide, silver, and indium tin oxide are sequentially stacked.

[0128] In an embodiment, a pixel defining film PDL may be disposed on the seventh insulating layer 70. A pixel defining opening PDLop through which a portion of the pixel electrode AE ​​is exposed may be defined in the pixel defining film PDL. That is, the pixel defining film PDL may cover the edge of the pixel electrode AE. The light emitting area PXA may be defined by the pixel defining opening PDLop defined in the pixel defining film PDL. For example, one light emitting area PXA may be defined in the light emitting element ED.

[0129] In an embodiment, the pixel defining film PDL may have a characteristic of absorbing a light beam, and for example, the pixel defining film PDL may have a black color. The pixel defining film PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, and / or an oxide of a metal.

[0130] In an embodiment, the first spacer HSPC may be disposed on the pixel defining film PDL. The first protrusion spacer SPC may be disposed on the first spacer HSPC. The first spacer HSPC and the first protrusion spacer SPC may have an integral shape and may be formed of the same material. For example, the first spacer HSPC and the first protrusion spacer SPC may be formed by a halftone mask via the same process. However, this is merely an example, and the present disclosure is not limited thereto. For example, the first spacer HSPC and the first protrusion spacer SPC may include different materials and may be formed via separate processes.

[0131] In an embodiment, the first functional layer HFL may be disposed on the pixel electrode AE, the pixel defining layer PDL, the first spacer HSPC, and the first protrusion spacer SPC. The first functional layer HFL may include a hole transport layer, a hole injection layer, or both.

[0132] In an embodiment, the light emitting layer EL may be disposed on the first functional layer HFL and may be disposed in a region corresponding to the pixel defining opening PDLop of the pixel defining film PDL. The light emitting layer EL may include an organic material, an inorganic material, or an organic / inorganic material that emits a light beam having a predetermined color. The second functional layer EFL may be disposed on the first functional layer HFL and cover the light emitting layer EL. The second functional layer EFL may include an electron transport layer, an electron injection layer, or an electron transport layer and an electron injection layer. The common electrode CE may be disposed on the second functional layer EFL.

[0133] In an embodiment, the element layer 130 may further include a cap layer CPL disposed on the common electrode CE. The cap layer CPL may improve the luminous efficiency by the principle of constructive interference. For example, the cap layer CPL may include a material having a refractive index of 1.6 or higher for a light beam having a wavelength of 589 nm. The cap layer CPL may be an organic cap layer including an organic material, an inorganic cap layer including an inorganic material, or a composite cap layer including an organic material and an inorganic material. For example, the cap layer CPL may include a carbocyclic compound, a heterocyclic compound, an amine-containing compound, a porphine derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex and / or any combination thereof. The carbocyclic compound, the heterocyclic compound and the amine-containing compound may be optionally substituted with a substituent including O, N, S, Se, Si, F, Cl, Br, I and / or any combination thereof.

[0134] In an embodiment, the encapsulation layer 140 may be disposed on the element layer 130. The encapsulation layer 140 may include an inorganic layer 141, an organic layer 142, and an inorganic layer 143 which are sequentially stacked, and the layers constituting the encapsulation layer 140 are not limited thereto.

[0135] In an embodiment, the inorganic layers 141 and 143 may protect the element layer 130 from moisture and oxygen, and the organic layer 142 may protect the element layer 130 from foreign matter such as dust particles. The inorganic layers 141 and 143 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer, etc. The organic layer 142 may include an acrylic-based organic layer, but the present disclosure is not particularly limited thereto.

[0136] In an embodiment, the sensor layer 200 may be disposed on the display layer 100. The sensor layer 200 may be referred to as a sensor, an input detection layer, or an input detection panel. The sensor layer 200 may include a sensor base layer 210, a first sensor conductive layer 220, a sensor insulating layer 230, a second sensor conductive layer 240, and / or a sensor cover layer 250.

[0137] In an embodiment, the sensor base layer 210 may be directly disposed on the display layer 100. The sensor base layer 210 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the sensor base layer 210 may be an organic layer including an epoxy-based resin, an acrylic-based resin, and / or an imide-based resin. The sensor base layer 210 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3.

[0138] In an embodiment, each of the first sensor conductive layer 220 and the second sensor conductive layer 240 may have a single layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3 .

[0139] In an embodiment, the conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al) and / or their alloys. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide, indium zinc oxide, zinc oxide and / or indium zinc tin oxide. In addition, the transparent conductive layer may include conductive polymers such as poly (3,4-ethylenedioxythiophene) (PEDOT), metal nanowires and / or graphene, etc.

[0140] In an embodiment, the conductive layer of the multi-layer structure may include a metal layer. For example, the metal layer may have a three-layer structure of titanium / aluminum / titanium. The conductive layer of the multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0141] In an embodiment, the sensor insulating layer 230 may be disposed between the first sensor conductive layer 220 and the second sensor conductive layer 240. The sensor insulating layer 230 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0142] Alternatively, in an embodiment, the sensor insulating layer 230 may include an organic layer. The organic layer may include at least one of acrylate-based resin, methacrylate-based resin, polyisoprene-based resin, vinyl-based resin, epoxy-based resin, polyurethane-based resin, cellulose-based resin, siloxane-based resin, polyimide-based resin, polyamide-based resin, and perylene-based resin.

[0143] In an embodiment, the sensor cover layer 250 may be disposed on the sensor insulating layer 230 and cover the second sensor conductive layer 240. The second sensor conductive layer 240 may include a conductive pattern. The sensor cover layer 250 may cover the conductive pattern to reduce or eliminate the possibility of damage to the conductive pattern in subsequent processes. The sensor cover layer 250 may include an inorganic material. For example, the sensor cover layer 250 may include silicon nitride, but the present disclosure is not particularly limited thereto. In an embodiment, the sensor cover layer 250 may be omitted.

[0144] In an embodiment, the anti-reflection layer 300 may be disposed on the sensor layer 200. The anti-reflection layer 300 may include a spacer layer 310, a plurality of color filters 320, and a planarization layer 330.

[0145] In an embodiment, the spacer layer 310 may be disposed to overlap with the conductive pattern of the second sensor conductive layer 240. The sensor cover layer 250 may be disposed between the spacer layer 310 and the second sensor conductive layer 240. The spacer layer 310 may prevent an external light beam from being reflected by the second sensor conductive layer 240. The material of the spacer layer 310 is not particularly limited as long as the material absorbs the light beam. The spacer layer 310 is a layer having a black color, and in an embodiment, the spacer layer 310 may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, and / or an oxide of the metal.

[0146] In an embodiment, a plurality of partition openings 310op may be defined in the partition layer 310. The partition openings 310op may overlap the plurality of light emitting layers EL, respectively. The color filters 320 may be arranged to correspond to the partition openings 310op, respectively. The color filters 320 may transmit light beams provided from the light emitting layers EL overlapped with the color filters 320.

[0147] In an embodiment, the planarization layer 330 may cover the partition layer 310 and the color filter 320. The planarization layer 330 may include an organic material, and a flat surface may be provided to an upper surface of the planarization layer 330. In an embodiment, the planarization layer 330 may be omitted.

[0148] In an embodiment, the anti-reflection layer 300 may include a reflection adjustment layer instead of the color filter 320. For example, in Figure 4 In the illustration of FIG. 3 , the color filter 320 may be omitted, and a reflection adjustment layer may be added to the position where the color filter 320 is omitted. The reflection adjustment layer may selectively absorb a light beam of a partial wavelength band among a light beam reflected from the inside of the display panel and / or the electronic device or a light beam input from the outside of the display panel and / or the electronic device.

[0149] As an example, in an embodiment, the reflection adjustment layer absorbs a light beam having a first wavelength region in the range of about 490nm to about 505nm and a light beam having a second wavelength region in the range of about 585nm to about 600nm, so that the light transmittance in the first wavelength region and the second wavelength region is about 40% or less. The reflection adjustment layer can absorb a light beam having a wavelength deviating from the wavelength range of the red light beam, the green light beam, and the blue light beam emitted from the light emitting layer EL. In this way, the reflection adjustment layer can absorb a light beam having a wavelength that does not belong to the wavelength range of the red light beam, the green light beam, or the blue light beam emitted from the light emitting layer EL, thereby preventing or minimizing a reduction in the brightness of the display panel and / or the electronic device. In addition, at the same time, a reduction in the luminous efficiency of the display panel and / or the electronic device can be prevented or minimized, and visibility can be improved.

[0150] In an embodiment, the reflection adjustment layer may be provided as an organic material layer including a dye, a pigment, or a combination thereof. The reflection adjustment layer may include a tetraazaporphyrin (TAP)-based compound, a porphyrin-based compound, a metal porphyrin-based compound, an oxazine-based compound, a squarylium-based compound, a triarylmethane-based compound, a polymethine-based compound, a tetraquinone-based compound, a phthalocyanine-based compound, an azo-based compound, a perylene-based compound, a xanthene-based compound, a diimmonium-based compound, a dipyrromethene-based compound, a cyanine-based compound, and / or a combination thereof.

[0151] In an embodiment, the reflection adjusting layer may have a transmittance of about 64% to about 72%.The transmittance of the reflection adjusting layer may be adjusted according to the content of the pigment and / or dye contained in the reflection adjusting layer.

[0152] In an embodiment, the anti-reflection layer 300 may include a retarder and / or a polarizer. The anti-reflection layer 300 may include at least a polarizing film. In this case, the anti-reflection layer 300 may be attached to the sensor layer 200 via an adhesive layer.

[0153] Figure 5 FIG. 1 is a diagram showing a display panel DP according to an embodiment (see FIG. Figure 2 ) is an enlarged plan view of a portion of the ).

[0154] In the embodiments, reference Figure 4 and Figure 5 , the display panel DP may include a plurality of pixel pattern units PXpu arranged on the base layer 110. Some of the components included in the circuit layer 120 may constitute the pixel pattern units PXpu. For example, each of the pixel pattern units PXpu may include at least one semiconductor layer and at least one conductive layer. This will be described in detail below.

[0155] In an embodiment, the pixel pattern units PXpu may be arranged in the first direction DR1 and the second direction DR2. The pixel pattern units PXpu may have substantially the same or similar shapes.

[0156] In an embodiment, each of the pixel pattern units PXpu may include a first sub-pixel pattern unit PXpu1 and a second sub-pixel pattern unit PXpu2. The first sub-pixel pattern unit PXpu1 and the second sub-pixel pattern unit PXpu2 may be linearly symmetrical to each other. For example, the first sub-pixel pattern unit PXpu1 and the second sub-pixel pattern unit PXpu2 may be linearly symmetrical to each other with respect to a line extending in the second direction DR2.

[0157] In an embodiment, each of the first sub-pixel pattern unit PXpu1 and the second sub-pixel pattern unit PXpu2 may include Figure 3 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, and the capacitor Cst are shown in FIG. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, and the capacitor Cst included in each of the first sub-pixel pattern unit PXpu1 and the second sub-pixel pattern unit PXpu2 may not be included in one pixel PXij (see FIG. Figure 3 For example, some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 included in each of the first sub-pixel pattern unit PXpu1 and the second sub-pixel pattern unit PXpu2 and one capacitor Cst may be included in one pixel, and the others may be included in another pixel adjacent to the one pixel.

[0158] In an embodiment, a valley VLY may be formed between pixel pattern units PXpu. The valley VLY may include a first valley VLY1 extending in a first direction DR1 and a second valley VLY2 extending in a second direction DR2. Each of the first valley VLY1 and the second valley VLY2 may be provided in plurality. The first valleys VLY1 may be spaced apart from each other in the second direction DR2, and the second valleys VLY2 may be spaced apart from each other in the first direction DR1. For example, on a plane, when viewed in a third direction DR3, the valley VLY may have a grid shape.

[0159] In an embodiment, the valley VLY may be defined by removing a portion of the circuit layer 120. In particular, the valley VLY may be defined by removing at least some of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. That is, the valley VLY may be defined by removing a portion of at least one inorganic insulating layer included in the circuit layer 120. A filler OM may be disposed in the valley VLY, and the filler OM may be an organic material. When an external impact is applied to the display panel DP, the impact may be absorbed by the valley VLY and the filler OM filled in the valley VLY. Therefore, the impact transmitted to the display area DP-DA (see Figure 2 ) can be dispersed, or the transfer of the impact can be blocked. Therefore, the durability of the display panel DP can be improved.

[0160] Figures 6 to 10 is a plan view according to a stacking order of the pixel pattern unit PXpu according to an embodiment. Figures 6 to 10 The circuit layer 120 (see Figure 4 ) is a plan view of the arrangement order of the conductive layers and the semiconductor layers in the embodiment of the present invention, and Figures 6 to 10 yes Figure 5 An enlarged view of the AA' region is shown in FIG.

[0161] In the examples and with reference to Figure 4 and Figure 6 , the first semiconductor layer SCL1 may be disposed between the buffer layer BFL and the first insulating layer 10. The first semiconductor layer SCL1 may include a first semiconductor pattern SCP1.

[0162] In an embodiment, the first semiconductor layer SCL1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon and / or polycrystalline silicon, etc. For example, the first semiconductor layer SCL1 may include low temperature polycrystalline silicon.

[0163] In the examples and with reference to Figure 4 and Figure 7 , the first conductive layer MPL1 may be disposed between the first insulating layer 10 and the second insulating layer 20 .

[0164] In an embodiment, the first conductive layer MPL1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, and / or a transparent conductive material, etc. For example, the first conductive layer MPL1 may include silver, an alloy containing silver, molybdenum, an alloy containing molybdenum, aluminum, an alloy containing aluminum, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, and / or indium zinc oxide, etc., but the present disclosure is not particularly limited thereto.

[0165] In an embodiment, the first conductive layer MPL1 may include first, second, and third conductive patterns MP11, MP12, and MP13.

[0166] In an embodiment, the first conductive pattern MP11 may be a gate electrode GT1. The first conductive pattern MP11 may be provided in an island shape. The first conductive pattern MP11 together with the first semiconductor pattern SCP1 may constitute a first transistor T1.

[0167] In an embodiment, the second conductive pattern MP12 may correspond to Figure 3 The jth write scan line GWLj or Figure 2 The second conductive pattern MP12 and the first semiconductor pattern SCP1 together may constitute the second transistor T2 and the seventh transistor T7. The j-th write scan line GWLj may correspond to the (j-1)th black scan line or the (j+1)th black scan line. In an embodiment, Figure 7 The second transistor T2 and the seventh transistor T7 shown in FIG. 1 may be included in different pixels.

[0168] In the embodiment, the third conductive pattern MP13 corresponds to Figure 3 The third conductive pattern MP13 may correspond to one of the light emitting control lines ECL1 to ECLm. For example, the third conductive pattern MP13 may correspond to the (j-1)th light emitting control line or the (j+1)th light emitting control line. The third conductive pattern MP13 together with the first semiconductor pattern SCP1 may constitute the fifth transistor T5 and the sixth transistor T6. In an embodiment, Figure 7 The second transistor T2 and the fifth and sixth transistors T5 and T6 shown in FIG. 5 may be included in different pixels.

[0169] In the examples and with reference to Figure 4 and Figure 8 , the second conductive layer MPL2 may be disposed between the second insulating layer 20 and the third insulating layer 30 .

[0170] In embodiments, the second conductive layer MPL2 may include metal, alloy, conductive metal oxide, and / or transparent conductive material, etc. For example, the second conductive layer MPL2 may have a single layer structure including molybdenum.

[0171] In an embodiment, the second conductive layer MPL2 may include first, second, third, and fourth conductive patterns MP21, MP22, MP23, and MP24.

[0172] In an embodiment, the first conductive pattern MP21 may overlap the first conductive pattern MP11. An opening MP21op may be defined in the first conductive pattern MP21. The first conductive pattern MP21 together with the first conductive pattern MP11 may constitute a first capacitor Cst (see Figure 3). The first driving voltage ELVDD (see Figure 3 ) may be provided to the first conductive pattern MP21.

[0173] In an embodiment, the second conductive pattern MP22 may be a j-th compensation scan line GCLj (see Figure 3 The third conductive pattern MP23 may be the j-th initialization scan line GILj (see Figure 3 The fourth conductive pattern MP24 may be a first initialization voltage VINT (see Figure 3 ) provided to the first initialization voltage line VL3 (see Figure 3 ) part.

[0174] In the embodiments, reference Figure 4 and Fig. 9 , the second semiconductor layer SCL2 may be disposed between the third insulating layer 30 and the fourth insulating layer 40 .

[0175] In an embodiment, the second semiconductor layer SCL2 may include an oxide semiconductor. The second semiconductor layer SCL2 may be disposed on the first semiconductor layer SCL1 (see Figure 6 ) and may not overlap with the first semiconductor layer SCL1. The second semiconductor layer SCL2 may include a second semiconductor pattern SCP2.

[0176] In the embodiments, reference Figure 4 and Fig.10 , the third conductive layer MPL3 may be disposed between the fourth insulating layer 40 and the fifth insulating layer 50 .

[0177] In embodiments, the third conductive layer MPL3 may include metal, alloy, conductive metal oxide, and / or transparent conductive material, etc. The third conductive layer MPL3 may have a multi-layer structure in which titanium and molybdenum are sequentially stacked, but the present disclosure is not particularly limited thereto.

[0178] In an embodiment, the third conductive layer MPL3 may include first conductive patterns MP31 and second conductive patterns MP32 .

[0179] In an embodiment, the first conductive pattern MP31 may correspond to the j-th compensation scan line GCLj (see Figure 3 The first conductive pattern MP31 and the second semiconductor pattern SCP2 may constitute the third transistor T3. The second conductive pattern MP32 may correspond to the jth initialization scan line GILj (see Figure 3 ). The second conductive pattern MP32 and the second semiconductor pattern SCP2 together may constitute a fourth transistor T4.

[0180] Fig.11FIG. 1 is a diagram showing a display panel DP according to an embodiment (see FIG. Figure 2 ) is an enlarged plan view of a portion of the ). Fig.12 is a schematic cross-sectional view illustrating a part of a method of manufacturing a display panel according to an embodiment.

[0181] In the examples and with reference to Fig.11 and Fig.12 , forming a covering third conductive layer MPL3 (see Fig.10 ) of the fifth insulating layer 50. A photoresist layer PR is formed on the fifth insulating layer 50. The photoresist layer PR may be a layer patterned by a photomask. Thereafter, at least a portion of each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50, the buffer layer BFL, and the barrier layer BRL is removed (e.g., etched), so that the valley VLY and the plurality of contact holes P-CNT may be formed.

[0182] In an embodiment, each of the plurality of contact holes P-CNT may be etched and provided until the first semiconductor layer SCL1 (see Figure 6 ), the second semiconductor layer SCL2 (see Fig. 9 )、the first conductive layer MPL1 (see Figure 7 ), the second conductive layer MPL2 (see Figure 8 ) and the third conductive layer MPL3 (see Fig.10 ) is exposed. At least one of the plurality of contact holes P-CNT may correspond to the first contact hole CH1 (see Figure 4 ).

[0183] In the embodiments and Fig.12 As shown in , the valley VLY may be defined by removing the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 from a non-pattern region in which the first semiconductor layer SCL1, the second semiconductor layer SCL2, the first conductive layer MPL1, the second conductive layer MPL2, and the third conductive layer MPL3 are not arranged. Alternatively, the valley VLY may be defined by removing at least a portion of each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 and the buffer layer BFL from the non-pattern region, or may be defined by removing at least a portion of each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50, the buffer layer BFL, and the barrier layer BRL.

[0184] In an embodiment, as the valley VLY becomes deeper, the voltage transmitted to the display panel DP (see Figure 2) can be more easily dispersed, or the transmission of the impact or the transmission of the crack can be more easily blocked. Therefore, according to an embodiment, in order to form a deeper valley VLY, at least one of the first semiconductor layer SCL1, the second semiconductor layer SCL2, the first conductive layer MPL1, the second conductive layer MPL2, and the third conductive layer MPL3 can be used as a mask. For example, when the valley VLY and the plurality of contact holes P-CNT are formed by etching, the etching rate of each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 can be greater than the etching rate of each of the first semiconductor layer SCL1, the second semiconductor layer SCL2, the first conductive layer MPL1, the second conductive layer MPL2, and the third conductive layer MPL3. Therefore, when the valley VLY is formed, the first semiconductor layer SCL1, the second semiconductor layer SCL2, the first conductive layer MPL1, the second conductive layer MPL2, and / or the third conductive layer MPL3 can be used as a mask (or hard mask) and can be continuously opened during etching.

[0185] Fig.13A is according to the embodiment corresponding to Fig.11 A cross-sectional view along line II' shown in FIG. Fig. 13B is according to the embodiment corresponding to Fig.11 A cross-sectional view along line II-II' shown in FIG.

[0186] In the examples and with reference to Fig.11 , Fig.12 , Fig.13A and Fig. 13B , a portion of the side surface VS of the valley VLY may be defined by at least one of the first semiconductor layer SCL1, the second semiconductor layer SCL2, the first conductive layer MPL1, the second conductive layer MPL2, and the third conductive layer MPL3. Fig.13A It is shown that a portion of the side surface VS of the valley VLY is defined by the first semiconductor layer SCL1 .

[0187] In an embodiment, the valley VLY may be etched and provided until the first semiconductor layer SCL1, the second semiconductor layer SCL2 (see Fig. 9 )、the first conductive layer MPL1 (see Figure 7 ), the second conductive layer MPL2 (see Figure 8 ) and the third conductive layer MPL3 (see Fig.10 ) is exposed. Therefore, portions of the bottom surfaces VB, V-Bp1, V-Bp2, and V-Bp3 of the valley VLY may be defined by at least one of the first semiconductor layer SCL1, the second semiconductor layer SCL2, the first conductive layer MPL1, the second conductive layer MPL2, and the third conductive layer MPL3.

[0188] In the examples and with reference to Fig. 13B , the bottom surfaces VB, V-Bp1, V-Bp2, and V-Bp3 of the valley VLY may be defined by various components. For example, the first bottom surface VB, which is the lowest bottom surface, may be defined by the buffer layer BFL. However, this is merely an example, and the first bottom surface VB may be defined by the barrier layer BRL or may be defined by the base layer 110.

[0189] In an embodiment, the second bottom surface V-Bp1 may be defined by the second conductive pattern MP12 of the first conductive layer MPL1. The third bottom surface V-Bp2 may be defined by the first conductive pattern MP31 of the third conductive layer MPL3. The fourth bottom surface V-Bp3 may be defined by the first conductive pattern MP21 of the second conductive layer MPL2.

[0190] According to an embodiment, a pixel pattern unit PXpu (see Fig.11 ) can be used as a mask to form the valley VLY. Therefore, even when a predetermined area between the pixel pattern units PXpu is not ensured, the valley VLY can be easily formed. Therefore, since the valley VLY is formed without additionally defining a separate area for forming the valley VLY, the resolution of the display panel DP may not be deteriorated.

[0191] According to an embodiment, a filler OM including an organic material is filled in the valley VLY. Therefore, when the valley VLY is formed, at least one of the exposed first semiconductor layer SCL1, the second semiconductor layer SCL2, the first conductive layer MPL1, the second conductive layer MPL2, and the third conductive layer MPL3 may be in direct contact with the filler OM. In addition, the filler OM has an insulating property. Therefore, components constituting the pixel pattern unit PXpu exposed by the valley VLY may not be short-circuited to each other.

[0192] In an embodiment, after the filler OM is filled in the valley VLY, a connection electrode CNE may be formed. The connection electrode CNE may be electrically connected to the first semiconductor layer SCL1 exposed by the contact hole P-CNT. The connection electrode CNE may be connected to the first connection electrode CNE10 (see Figure 4 ) are simultaneously formed through the same process. Therefore, the connection electrode CNE may be disposed to overlap the valley VLY and may be disposed on the filler OM.

[0193] In an embodiment, the minimum distance DTm between any one of the plurality of contact holes P-CNT and the valley VLY may be designed to be greater than or equal to a predetermined distance. For example, the minimum distance DTm may be greater than or equal to about 1 micron (e.g., about 1.8 microns). Therefore, when a filler OM is formed in the valley VLY, the possibility of organic material filling in the plurality of contact holes P-CNT may be eliminated. However, the minimum distance DTm is merely an example and is not particularly limited to the above values.

[0194] Fig.14 is according to the embodiment corresponding to Fig.11 A cross-sectional view along line II' shown in FIG.

[0195] In the examples and with reference to Fig.11 and Fig.14 , the connection electrode CNE may be electrically connected to the first semiconductor layer SCL1 exposed via the contact hole P-CNT. Thereafter, a sixth insulating layer 60 may be formed on the fifth insulating layer 50. The sixth insulating layer 60 may include an organic material, and when the sixth insulating layer 60 is formed, the organic material may be filled in the valley VLY. In this case, the connection electrode CNE may be disposed so as not to overlap the valley VLY.

[0196] As described above, in an embodiment, the impact applied to the display panel can be absorbed by the valley defined in the circuit layer and the filler filled in the valley. Therefore, the impact transmitted to the display area can be dispersed, and / or the transmission of the impact can be blocked. For example, even when cracks appear in the inorganic layer, the transmission of the cracks can be blocked by the valley and the filler. In addition, at least one of the at least one semiconductor layer and the at least one conductive layer included in the circuit layer can be used as a mask to form a deeper valley. Since the depth of the valley becomes larger, the impact transmitted to the display panel can be dispersed more easily, or the transmission of the impact or the transmission of the crack can be blocked more easily. Therefore, the durability of the display panel can be further improved.

[0197] Although the above has been described with reference to the embodiments of the present disclosure, it is to be understood that, without departing from the spirit and technical scope of the present disclosure described in the appended claims, a person skilled in the art or a person with ordinary knowledge in the art may make various modifications and changes to the present disclosure. Therefore, the technical scope of the present disclosure is not limited to the detailed description of the specification, but should be defined by the appended claims. In addition, without departing from the scope of the present disclosure, the embodiments or parts of the embodiments may be combined in whole or in part.

Claims

1. A display panel, It is characterized in that The display panel comprises: Base layer; a circuit layer disposed on the base layer and comprising a plurality of pixel pattern units arranged in a first direction and in a second direction intersecting the first direction; a valley defined between the plurality of pixel pattern units; and a filling member, disposed in the valley, Each of the plurality of pixel pattern units includes at least one semiconductor layer and at least one conductive layer, and Part of the side surface of the valley is defined by at least one layer among the at least one semiconductor layer and the at least one conductive layer.

2. The display panel according to claim 1, It is characterized in that The at least one layer is in direct contact with the filler.

3. The display panel according to claim 1, It is characterized in that A portion of a bottom surface of the valley is defined by any one of the at least one semiconductor layer and the at least one conductive layer.

4. The display panel according to claim 3, It is characterized in that Any one of the layers is in direct contact with the filler.

5. The display panel according to claim 1, It is characterized in that The valleys include first valleys extending in the first direction and second valleys extending in the second direction intersecting the first direction.

6. The display panel according to claim 1, It is characterized in that Each of the plurality of pixel pattern units includes a first sub-pixel pattern unit and a second sub-pixel pattern unit that is linearly symmetrical to the first sub-pixel pattern unit.

7. The display panel according to claim 1, It is characterized in that The circuit layer comprises: A first semiconductor layer, disposed on the base layer; a first insulating layer, configured to cover the first semiconductor layer; A first conductive layer, disposed on the first insulating layer; a second insulating layer, configured to cover the first conductive layer; a second conductive layer, disposed on the second insulating layer; a third insulating layer, configured to cover the second conductive layer; A second semiconductor layer is disposed on the third insulating layer; a fourth insulating layer, configured to cover the second semiconductor layer; A third conductive layer is disposed on the fourth insulating layer; and a fifth insulating layer configured to cover the third conductive layer, and Wherein, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer are inorganic insulating layers.

8. The display panel according to claim 7, It is characterized in that The valley is provided by removing at least a portion of each of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer.

9. The display panel according to claim 7, It is characterized in that The portion of the side surface of the valley is defined by at least one of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer.

10. The display panel according to claim 7, It is characterized in that A portion of a bottom surface of the valley is defined by at least one of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer.

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