Asynchronous edge detection circuit suitable for transfer switching equipment

By designing an asynchronous edge detection circuit including inverter, multiplexer and AND gate, the asynchronous edge detection problem in converter switch appliances is solved, and the asynchronous enable and reset functions are realized, ensuring the stability of the detection results and Efficient utilization of resources.

CN222167113UActive Publication Date: 2024-12-13SCHNEIDER WINGOAL TIANJIN ELECTRIC EQUIP
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Patent Information

Application Number
CN202420001259.7
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-01-02
Publication Date
2024-12-13
Estimated Expiration
2034-01-02

AI Technical Summary

Technical Problem

In converter switch appliances, it is difficult for the prior art to realize asynchronous edge detection, and external detection circuits are required when the microcontroller resources are insufficient, resulting in increased resource occupation and complexity.

Method used

An asynchronous edge detection circuit including inverter, multiplexer, in-phase device and AND gate is designed. Asynchronous enable and reset functions are realized through En-signal, In-signal and Out-signal interfaces, and can self-held detection. As a result, the microcontroller interrupt resources are not occupied.

Benefits of technology

It realizes rising edge detection of the converter switch appliance, has asynchronous enable and reset functions, and all components are simple logic circuits, stable and reliable, and does not occupy microcontroller interrupt resources. It is suitable for environments with limited resources.

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Abstract

The utility model relates to an asynchronous edge detection circuit suitable for transfer switching equipment, which belongs to the technical field of detection circuits, and comprises elements, an external interface and an internal network, the elements comprise U1A, U1B, U1C, U1D, U1E, U2, U3, U4A and U5A; the U1A, the U1B, the U1C, the U1D and the U1E are phase inverters, the U2 and the U3 are alternative multiplexers, the U4A is an in-phase device, the U5A is an AND gate, the external interface comprises En-signal, In-signal and Out-signal, the En-signal is an enable input signal, a high level is effective, the In-signal is an input signal, the Out-signal is an output signal, the internal network comprises Edge and Sw, the Edge is an edge signal, and the Sw is a selection signal. According to the circuit, rising edge detection of the change-over switch electric appliance is realized, a detection result can be self-maintained, asynchronous enabling or resetting can be realized, and all elements are simple logic circuits, are stable and reliable, and do not occupy interruption resources of a single chip microcomputer.
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Description

Technical Field

[0001] The utility model relates to the technical field of detection circuits, in particular to an asynchronous edge detection circuit suitable for switching electrical appliances. Background Art

[0002] Transfer switch electrical equipment, namely ATSE. It is mainly used in emergency power supply systems with rated voltage not exceeding 1000V AC or 1500V DC, and interrupts power supply to loads during power supply conversion.

[0003] In the application of switching electrical appliances, it is sometimes necessary to detect the level edge. Usually, the detection is done by using the microcontroller interrupt method. However, if the microcontroller resources are insufficient, an external detection circuit is required. Therefore, an asynchronous edge detection circuit suitable for switching electrical appliances is designed. Utility Model Content

[0004] The utility model provides an asynchronous edge detection circuit suitable for a switching electrical appliance, solves the problems raised in the above background, realizes rising edge detection, can self-hold the detection result, and can be asynchronously enabled or reset.

[0005] The utility model solves the above technical problems as follows: an asynchronous edge detection circuit suitable for switching electrical appliances, including components, external interfaces and internal networks, characterized in that: the components include U1A, U1B, U1C, U1D, U1E, U2, U3, U4A, U5A; the U1A, U1B, U1C, U1D, U1E are inverters, the U2 and U3 are two-to-one multiplexers, the U4A is a non-inverter, and the U5A is an AND gate;

[0006] The external interface includes En-signal, In-signal and Out-signal, wherein En-signal is an enable input signal, which is valid at a high level, In-signal is an input signal, and Out-signal is an output signal;

[0007] The internal network includes Edge and Sw, wherein Edge is an edge signal and Sw is a selection signal.

[0008] On the basis of the above technical solution, the present invention can also be improved as follows.

[0009] Furthermore, in the two-to-one multiplexer of U2 and U3, when ~A / B is at a low level, 1Y=1A, otherwise, 1Y=1B.

[0010] Furthermore, when the En-signal is at a low level, the out-signal outputs a low level.

[0011] Furthermore, when En-signal is high, if In-signal has no rising edge, out-signal outputs a low level; if a rising edge occurs, out-signal outputs a high level, and then no matter how In-signal changes, out-signal remains high until En-signal becomes low.

[0012] The utility model provides an asynchronous edge detection circuit suitable for switching electrical appliances, which has the following advantages:

[0013] This circuit realizes the rising edge detection of the transfer switch electrical appliance, and can self-hold the detection result, and can be asynchronously enabled or reset. All components are simple logic circuits, which are stable and reliable and do not occupy the interrupt resources of the microcontroller.

[0014] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiment of the utility model with the accompanying drawings. The specific implementation method of the utility model is given in detail by the following embodiments and their drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0016] Figure 1 An edge detection principle diagram of an asynchronous edge detection circuit suitable for a switching electrical appliance provided in one embodiment of the utility model. DETAILED DESCRIPTION

[0017] The following is combined with Figure 1 The principles and features of the present invention are described, and the examples given are only used to explain the present invention, and are not used to limit the scope of the present invention. The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0018] It should be noted that when a component is referred to as being "fixed to" another component, it may be directly on the other component or there may also be a component centered. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may also be a component centered. When a component is considered to be "set on" another component, it may be directly set on the other component or there may also be a component centered. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0020] like Figure 1 As shown, an asynchronous edge detection circuit suitable for a switching device includes components, an external interface and an internal network, characterized in that: the components include U1A, U1B, U1C, U1D, U1E, U2, U3, U4A, and U5A; U1A, U1B, U1C, U1D, and U1E are inverters, U2 and U3 are two-to-one multiplexers, U4A is a non-inverter, and U5A is an AND gate;

[0021] The external interface includes En-signal, In-signal and Out-signal, wherein En-signal is an enable input signal, which is valid at a high level, In-signal is an input signal, and Out-signal is an output signal;

[0022] The internal network includes Edge and Sw, wherein Edge is an edge signal and Sw is a selection signal.

[0023] Preferably, in the two-to-one multiplexer of U2 and U3, when ~A / B is at a low level, 1Y=1A, otherwise, 1Y=1B.

[0024] Preferably, when the En-signal is at a low level, the out-signal outputs a low level.

[0025] Preferably, when En-signal is at a high level, if In-signal has no rising edge, out-signal outputs a low level; if a rising edge occurs, out-signal outputs a high level, and then no matter how In-signal changes, out-signal remains at a high level until En-signal becomes a low level.

[0026] The specific working principle and use method of the utility model are as follows:

[0027] 1. When En-signal is low level:

[0028] SW=VCC, output high level. At this time, out-signal=En-signal, output low level.

[0029] 2. When En-signal is high:

[0030] Due to the fixed delay of the inverter, when In-signal jumps from low level to high level, there is a rising edge, and In-inv jumps from high level to low level after 5 delays. Therefore, during the delay process, In-inv is still high level, and at the input end of U5A, In-inv and In-signal are both high level, and the output edge is high. At other times, In-inv and In-signal are opposite or both low level, and the AND gate output is low.

[0031] Because En-signal is high, SW = edge. At the rising edge of In-signal, due to the delay of the inverter, SW will be high for a period of time. At this time, out-signal = En-signal, also high, and out-buf = out-signal, also high. After the delay of the inverter, SW is low. At this time, out-signal = out-buf, locked at a high level. After that, no matter how In-signal changes, out-signal is always high.

[0032] The above description is only a preferred embodiment of the utility model and does not impose any form of limitation on the utility model. Any ordinary technician in the industry can smoothly implement the utility model as shown in the drawings of the specification and described above. However, any equivalent changes, modifications and evolutions made by technicians familiar with the profession without departing from the scope of the technical solution of the utility model using the technical content disclosed above are all equivalent embodiments of the utility model. At the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the utility model are still within the protection scope of the technical solution of the utility model.

Claims

1. An asynchronous edge detection circuit suitable for a switching device, comprising components, an external interface and an internal network, characterized in that: The components include U1A, U1B, U1C, U1D, U1E, U2, U3, U4A, and U5A; U1A, U1B, U1C, U1D, and U1E are inverters, U2 and U3 are two-to-one multiplexers, U4A is a non-inverting device, and U5A is an AND gate; The external interface includes En-signal, In-signal and Out-signal, wherein En-signal is an enable input signal, which is valid at a high level, In-signal is an input signal, and Out-signal is an output signal; The internal network includes Edge and Sw, wherein Edge is an edge signal and Sw is a selection signal.

2. According to claim 1, an asynchronous edge detection circuit suitable for a switching device, characterized in that: In the two-to-one multiplexer of U2 and U3, when ~A / B is at a low level, 1Y=1A, otherwise, 1Y=1B.

3. According to claim 1, an asynchronous edge detection circuit suitable for a switching device, characterized in that: When the En-signal is at a low level, the out-signal outputs a low level.

4. The asynchronous edge detection circuit suitable for switching electrical appliances according to claim 1, characterized in that: When En-signal is high, if In-signal has no rising edge, out-signal outputs low level; if there is a rising edge, out-signal outputs high level, and then no matter how In-signal changes, out-signal remains high until En-signal becomes low level.