Capacity expansion device of solid state disk
Through the expansion device of the solid-state drive, the rapid expansion of the solid-state drive is achieved by using high-speed connectors and multiplexers, which solves the problem of insufficient storage capacity, reduces costs and provides a flexible capacity expansion solution, suitable for those who need to increase storage Scene.
Patent Information
- Application Number
- CN202420934341.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-30
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2034-04-30
AI Technical Summary
When the storage amount of existing solid-state drives increases, the expansion requirements are difficult to meet, and the replacement cost is high and the original SSD disk is wasted, making it lack flexible expansion solutions.
A solid-state hard disk expansion device is designed, and the capacity expansion device of the first backplane and the second backplane is connected through high-speed connectors, and data communication is carried out with a non-volatile memory group through multiple channels, so as to achieve rapid capacity expansion of the secondary board by hooking the secondary board. , and enhance signal quality through MUX chips, supporting secondary board buckles at different capacity points.
It realizes rapid expansion of SSD disks, reduces costs, and provides flexible capacity expansion solutions. It has a simple structure and a wide range of applications.
Smart Images
Figure CN222167584U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of servers, and in particular relates to a capacity expansion device for a solid state hard disk. Background Art
[0002] With the rapid development of technologies such as cloud computing, big data, and artificial intelligence, the demand for storage capacity is also increasing. As a high-performance, high-reliability device, SSD is gradually becoming an important choice in these fields. Solid State Disk (SSD), also known as solid-state drive, is a hard disk made of solid-state electronic storage chip arrays. SSD consists of a control unit and a storage unit (FLASH chip, DRAM chip). Flash-based solid-state drives are the main category of solid-state drives. Their internal structure is very simple. The main body of the solid-state drive is actually a PCB board, and the most basic accessories on this PCB board are the control chip, cache chip (some low-end hard drives do not have cache chips) and flash memory chips for storing data.
[0003] As the amount of stored data increases, the demand for capacity during the use of SSD disks is getting greater and greater, and there is a need for capacity expansion. Currently, larger-capacity SSD disks are used to directly replace the original ones. The cost of replacement is relatively high, and the replaced SSD disks are directly wasted. Utility Model Content
[0004] In view of the above-mentioned deficiencies in the prior art, the utility model provides a capacity expansion device for a solid state hard disk to solve the above-mentioned technical problems.
[0005] The utility model provides a capacity expansion device for a solid state hard disk, comprising:
[0006] A first backplane and a second backplane, the first backplane being a mainboard of a solid state drive, the first backplane being connected to the second backplane via a high-speed connector;
[0007] The first backplane includes a controller, the controller includes a plurality of channels;
[0008] The first backplane includes a first memory group, wherein the first memory group includes a plurality of non-volatile memories;
[0009] The second backplane includes a second memory group, wherein the second memory group includes a plurality of non-volatile memories;
[0010] The controller is connected to the non-volatile memories in the first memory group and the non-volatile memories in the second memory group through a plurality of channels.
[0011] In an optional implementation, the first memory group includes 8 non-volatile memories, and the second memory group includes 8 non-volatile memories.
[0012] In an optional embodiment, the controller includes 16 channels.
[0013] In an optional embodiment, the 16 channels of the controller are divided into a first channel group and a second channel group. The controller is connected one-to-one to the eight non-volatile memories of the first backplane through the eight channels of the first channel group, and the controller is connected one-to-one to the eight non-volatile memories of the second backplane through the eight channels of the second channel group.
[0014] In an optional embodiment, the controller includes a first channel, a second channel, a third channel, a fourth channel, a fifth channel, a sixth channel, a seventh channel and an eighth channel.
[0015] In an optional embodiment, the four chip select signal pins of the first channel are connected to the first non-volatile memory of the first memory group, and the other four chip select signal pins of the first channel are connected to the first non-volatile memory of the second memory group; the four chip select signal pins of the second channel are connected to the second non-volatile memory of the first memory group, and the other four chip select signal pins of the second channel are connected to the second non-volatile memory of the second memory group; the four chip select signal pins of the third channel are connected to the third non-volatile memory of the first memory group, and the other four chip select signal pins of the third channel are connected to the third non-volatile memory of the second memory group; the four chip select signal pins of the fourth channel are connected to the fourth non-volatile memory of the first memory group, and the other four chip select signal pins of the fourth channel are connected to the fourth non-volatile memory of the second memory group. volatile memory; the four chip select signal pins of the fifth channel are connected to the fifth non-volatile memory of the first memory group, and the other four chip select signal pins of the fifth channel are connected to the fifth non-volatile memory of the second memory group; the four chip select signal pins of the sixth channel are connected to the sixth non-volatile memory of the first memory group, and the other four chip select signal pins of the sixth channel are connected to the sixth non-volatile memory of the second memory group; the four chip select signal pins of the seventh channel are connected to the seventh non-volatile memory of the first memory group, and the other four chip select signal pins of the seventh channel are connected to the seventh non-volatile memory of the second memory group; the four chip select signal pins of the eighth channel are connected to the eighth non-volatile memory of the first memory group, and the other four chip select signal pins of the eighth channel are connected to the eighth non-volatile memory of the second memory group.
[0016] In an optional embodiment, the first backplane includes a U.2 connector.
[0017] In an optional embodiment, the TOP surface of the first backplane includes a controller, 3 memory devices, 4 non-volatile memories and a high-speed connector; the Bottom surface of the first backplane includes 2 memory devices, 4 non-volatile memories and a power chip.
[0018] In an optional embodiment, the TOP surface of the second backplane includes 4 non-volatile memories and multiplexers corresponding to the 4 non-volatile memories, and a high-speed connector; the Bottom surface of the second backplane includes 4 non-volatile memories and multiplexers corresponding to the 4 non-volatile memories.
[0019] In an optional embodiment, both the first back plate and the second back plate are provided with temperature sensors.
[0020] The beneficial effect of the utility model is that the capacity expansion device of the solid state disk provided by the utility model can realize the rapid capacity expansion of the SSD disk by buckling the sub-board when the capacity of the SSD disk is insufficient and the capacity of the SSD disk needs to be increased, thereby saving costs. At the same time, sub-boards of different capacity points can be buckled to flexibly and freely expand the capacity of the SSD disk.
[0021] In addition, the utility model has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 This is a schematic diagram of a first mainboard topology of a solid state drive expansion device according to an embodiment of the utility model.
[0024] Figure 2 This is a schematic diagram of a first sub-board topology of a solid-state hard disk expansion device according to an embodiment of the utility model.
[0025] Figure 3 This is a schematic diagram of a second mainboard topology of a solid state drive expansion device according to an embodiment of the utility model.
[0026] Figure 4 This is a schematic diagram of the second sub-board topology of the solid-state hard disk expansion device of an embodiment of the utility model.
[0027] Figure 5 This is a TOP surface device distribution diagram of a mainboard of a solid state hard disk expansion device according to an embodiment of the utility model.
[0028] Figure 6 This is a diagram of the distribution of components on the bottom surface of a mainboard of a capacity expansion device for a solid state hard disk according to an embodiment of the utility model.
[0029] Figure 7 This is a TOP surface device distribution diagram of a sub-board of a capacity expansion device for a solid state hard disk according to an embodiment of the utility model.
[0030] Figure 8 This is a diagram of the distribution of components on the bottom surface of a sub-board of a capacity expansion device for a solid state hard disk according to an embodiment of the utility model. DETAILED DESCRIPTION
[0031] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0033] The abbreviations and key terms of this utility model are as follows:
[0034] SSD: Solid State Drive, abbreviated as SSD, is a hard disk made of a solid-state electronic storage chip array.
[0035] NAND Flash: A non-volatile memory based on NAND technology. It is a type of Flash memory that uses a nonlinear macrocell mode internally, providing a cheap and effective solution for the implementation of solid-state large-capacity memory. NandFlash memory has the advantages of large capacity and fast rewrite speed, and is suitable for storing large amounts of data.
[0036] Channel: A channel is a set of physical pins in NAND Flash that is responsible for receiving and transmitting data and commands.
[0037] Target: NAND Flash usually contains one or more Targets. Target has independent chip select units and can be addressed individually. It usually contains one or more LUNs.
[0038] CE: A Target contains one or more LUNs. One or more LUNs on a Target share a set of data signals. Each Target is controlled by a CE pin (chip select), which means that several LUNs on a Target share one CE signal.
[0039] MUX chip: A multiplexer for high-speed memory signals, used to enhance the signal quality of NAND Flash high-speed signal lines.
[0040] SDRAM: Synchronous Dynamic Random-access Memory, referred to as SDRAM, is a dynamic random access memory (DRAM) with a synchronous interface. It waits for a clock signal before responding to control inputs, so that it can be synchronized with the computer's system bus. The clock is used to drive a finite state machine to pipeline incoming instructions. This allows SDRAM to have a more complex operating mode.
[0041] I2C: Inter-Integrated Circuit, I2C bus is a two-wire serial communication bus developed by PHILIPS, using a multi-master-slave architecture to connect microcontrollers and their peripheral low-speed devices. It is a bus standard widely used in the field of microelectronic communication control. It is a special form of synchronous communication with the advantages of fewer interface lines, simple control method, small device package, and higher communication rate.
[0042] Specifically, the capacity expansion device of the solid state drive includes:
[0043] A first backplane and a second backplane, the first backplane being the mainboard of the solid state drive, the first backplane being connected to the second backplane via a high-speed connector; the second backplane being a secondary board;
[0044] The first backplane includes a controller, the controller includes a plurality of channels;
[0045] The first backplane includes a first memory group, and the first memory group includes a plurality of non-volatile memories;
[0046] The second backplane includes a second memory group, and the second memory group includes a plurality of non-volatile memories;
[0047] The controller is connected to the non-volatile memories in the first memory group and the non-volatile memories in the second memory group through a plurality of channels.
[0048] The controller on the main board controls the non-volatile memory of the sub-board through a high-speed connector.
[0049] Specifically, on the basis of the conventional SSD structure, a high-speed connector is added as the SSD main board, and a separate sub-board is made with NAND Flash particles and a high-speed connector integrated thereon. The sub-board can be connected to the main board through the high-speed connector to realize data communication between the controller and the NAND Flash of the sub-board, thereby increasing the number of NAND Flash and expanding the capacity of the SSD disk.
[0050] When the number of channels (NAND Channel) of the controller is 16, the connection topology is as follows Figure 1 As shown, including:
[0051] The controller itself has 16 NAND channels, namely Channel 0~15. Each channel is independent and will not affect each other. The 16 channels are divided into two parts, Channel 0~7 is the first part, and Channel 8~15 is the second part. The controller communicates with the NAND Flash on the mainboard through Channel 0~7, and Channel 8~15 is connected to the high-speed connector of the mainboard. When the sub-board is buckled onto the mainboard, the controller's Channel 8~15 can communicate with the NAND Flash of the sub-board through the connector.
[0052] Each channel of the controller has 8 CEs. This design only uses 4 of them, CE0~CE3, to select different targets of NAND Flash particles.
[0053] There are 8 NAND Flash particles on the motherboard, each of which has 4 Targets and two groups of IO signals. The first 7 channels of the controller are CH0~CH7. Each channel is connected to an independent NAND Flash particle. The CE0~CE3 of each channel controls the 4 Targets0~3 of the NAND Flash particle. In each channel, different Targets of the NAND Flash particles share the IO, WE, CLE, ALE, WP, DQS_P, DQS_N, RE_P, and RE_N signals. The different Targets of the NAND Flash particles are selected through the CE0~3 signals in the Channel.
[0054] Please refer to Figure 2There are 8 NAND Flash particles on the sub-board. Channel 8~15 of the controller is connected to the NAND Flash of the sub-board through a high-speed connector. The connection method is similar to Channel 0~7 of the controller. In each Channel, different Targets of NAND Flash particles share IO, WE, CLE, ALE, WP, DQS_P, DQS_N, RE_P, and RE_N signals. Different Targets of NAND Flash particles are selected through CE0~3 signals in the Channel.
[0055] When the controller has 8 NAND channels, the design structure is as follows:
[0056] The controller has 8 channels, namely Channel 0 to Channel 7. The NAND Flash particles on the main board and the NAND Flash particles on the sub-board share these 8 channels. Each channel selects and distinguishes the Target of different NAND Flash particles through different CE signals.
[0057] Please refer to Figure 3 and Figure 4 In addition to being connected to an independent NAND Flash, each channel signal of the controller must also be connected to a high-speed connector. There are 8 NAND Flash particles distributed on the main board and 8 NAND Flash particles distributed on the sub-board. Each channel of the controller is connected to 1 NAND Flash on the main board and 1 NAND Flash on the sub-board respectively.
[0058] Each channel of the controller has a total of 8 CEs, namely CE0~CE7. CE0~CE3 are used to control the selection of 4 different targets of a NAND Flash particle on the main board, and CE4~CE7 are used to control the selection of 4 different targets of a NAND Flash particle on the sub-board. In each channel, in addition to the CE signal, different targets of the NAND Flash particles share the IO, WE, CLE, ALE, WP, DQS_P, DQS_N, RE_P, and RE_N signals.
[0059] Please refer to Figure 5 There are 3 SDRAM and 4 NAND Flash memories, a controller, a high-speed connector and a U.2 connector on the TOP surface of the motherboard. A temperature sensor U2 is provided near the NAND Flash, a temperature sensor U3 is provided near the 3 SDRAM memories, and a temperature sensor U4 is provided near the controller. Temperature sensors U2, U3 and U4 are all electrically connected to the controller.
[0060] Please refer to Figure 6 There are 2 SDRAMs, 4 NAND Flashes and a power chip on the bottom side of the motherboard. In addition to supplying power to the devices on the motherboard, the power chip also supplies power to the devices on the NAND Flash sub-board through a high-speed connector.
[0061] Under normal circumstances, the SSD mainboard can be used as an independent SSD disk. When the disk capacity is insufficient and needs to be increased, the NAND Flash sub-board is snapped onto the mainboard to achieve disk capacity expansion. By snapping NAND Flash sub-boards of different capacity points, the SSD disk capacity can be flexibly expanded.
[0062] The sub-board mainly has high-speed connectors, NAND Flash particles and MUX chips. The signals of NAND Flash particles are connected to the high-speed connector through the MUX chip to communicate with the mainboard controller. Since the wiring between the sub-board NAND Flash particles and the mainboard controller is too long and passes through the connector, the signal attenuation is relatively large, so a MUX chip is added in the middle to enhance the signal quality between the controller and the NAND Flash particles.
[0063] Please refer to Figure 7 The TOP surface of the sub-board includes 4 non-volatile memories and multiplexers corresponding to the 4 non-volatile memories, as well as a high-speed connector.
[0064] Please refer to Figure 8 The bottom surface of the sub-board includes four non-volatile memories and multiplexers corresponding to the four non-volatile memories.
[0065] A maximum of 8 NAND Flash particles can be placed on the sub-board, each NAND Flash particle uses a NANDChannel and a MUX chip. The sub-board can be filled with 8 NAND Flash particles, or only a few of them, or NAND Flash particles of different capacities, to configure the total capacity of the NAND sub-board, and combine the capacity points of the NAND sub-board to 2T / 4T / 8T.
[0066] A temperature sensor U1 is also placed on the NAND Flash sub-board, which is connected to the controller of the mainboard through the I2C interface via a high-speed connector. The controller can monitor the working temperature of the NAND Flash particles on the sub-board in real time. When the NAND Flash working temperature exceeds the threshold of the SSD disk, the temperature control strategy is implemented to slow down the business. If the temperature continues to rise, the business will be stopped.
[0067] Considering the size limitation of the slots on the server and the fact that the maximum thickness of a 2.5-inch SSD disk is usually 15mm, the mainboard part of the SSD disk is designed to be 7mm thick, and the sub-board part is designed to be 7mm thick. In this way, when the sub-board is buckled onto the mainboard, the overall thickness of the expanded SSD disk will not exceed 15mm.
[0068] The high-speed connector supports at least 8 NAND Channel signal channels, as well as NAND Flash working power supply and other functional pins.
[0069] In the high-speed connector part, select two pins and connect them to the two GPIO pins of the controller. On the slave board, pull up and down the two pins of the connector to achieve four combinations of 00, 01, 10, and 11, which correspond to different capacity points of the slave board. 00 means only the main board without the slave board, and 01, 10, and 11 correspond to the 2T / 4T / 8T capacity of the slave board respectively.
[0070] When powered on, the controller identifies different values of the two GPIO pins 00~11 and switches the corresponding firmware to correspond to the NAND Flash sub-boards with different capacity points.
[0071] The main pin classifications of high-speed connectors are as follows:
[0072] ①8 groups of Channel pins, each group of Channel includes IO0~7, ALE, CLE, WP, RE_P, RE_N, DQS_P, DQS_N, CE0~3 (or CE4~7);
[0073] ②4 power pins, NAND Flash power supply P1V2, P2V5, P12V_VPP, and temperature sensor power supply P3V3;
[0074] ③NAND Flash sub-board capacity identification pin, by pulling up and down 2 pins corresponding to different NAND Flash sub-board capacity points, it is easy for the main board to identify.
[0075] Although the present invention is described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person skilled in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person skilled in the art who is familiar with the present technical field may easily think of changes or substitutions within the technical scope disclosed in the present invention, and these shall be within the scope of protection of the present invention.
Claims
1. A capacity expansion device for a solid state hard disk, characterized in that: include: A first backplane and a second backplane, the first backplane being a mainboard of a solid state drive, the first backplane being connected to the second backplane via a high-speed connector; The first backplane includes a controller, the controller includes a plurality of channels; The first backplane includes a first memory group, wherein the first memory group includes a plurality of non-volatile memories; The second backplane includes a second memory group, wherein the second memory group includes a plurality of non-volatile memories; The controller is connected to the non-volatile memories in the first memory group and the non-volatile memories in the second memory group through a plurality of channels.
2. The capacity expansion device of a solid state drive according to claim 1, characterized in that: The first memory group includes 8 non-volatile memories, and the second memory group includes 8 non-volatile memories.
3. The capacity expansion device of a solid state drive according to claim 2, characterized in that: The controller includes 16 channels.
4. The capacity expansion device of a solid state hard disk according to claim 2, characterized in that: The 16 channels of the controller are divided into a first channel group and a second channel group. The controller is connected one by one to the eight non-volatile memories of the first backplane through the eight channels of the first channel group, and the controller is connected one by one to the eight non-volatile memories of the second backplane through the eight channels of the second channel group.
5. The capacity expansion device of a solid state drive according to claim 2, characterized in that: The controller includes a first channel, a second channel, a third channel, a fourth channel, a fifth channel, a sixth channel, a seventh channel and an eighth channel.
6. The capacity expansion device of a solid state drive according to claim 5, characterized in that: The four chip selection signal pins of the first channel are connected to the first non-volatile memory of the first memory group, and the other four chip selection signal pins of the first channel are connected to the first non-volatile memory of the second memory group; The four chip select signal pins of the second channel are connected to the second non-volatile memory of the first memory group, and the other four chip select signal pins of the second channel are connected to the second non-volatile memory of the second memory group; the four chip select signal pins of the third channel are connected to the third non-volatile memory of the first memory group, and the other four chip select signal pins of the third channel are connected to the third non-volatile memory of the second memory group; the four chip select signal pins of the fourth channel are connected to the fourth non-volatile memory of the first memory group, and the other four chip select signal pins of the fourth channel are connected to the fourth non-volatile memory of the second memory group; the four chip select signal pins of the fifth channel are connected to the fifth non-volatile memory of the first memory group, and the other four chip select signal pins of the fifth channel are connected to the fifth non-volatile memory of the second memory group; the four chip select signal pins of the sixth channel are connected to the sixth non-volatile memory of the first memory group, and the other four chip select signal pins of the sixth channel are connected to the sixth non-volatile memory of the second memory group; the four chip select signal pins of the seventh channel are connected to the seventh non-volatile memory of the first memory group, and the other four chip select signal pins of the seventh channel are connected to the seventh non-volatile memory of the second memory group; The four chip selection signal pins of the eighth channel are connected to the eighth non-volatile memory of the first memory group, and the other four chip selection signal pins of the eighth channel are connected to the eighth non-volatile memory of the second memory group.
7. The capacity expansion device of a solid state drive according to claim 1, characterized in that: The first backplane includes a U.2 connector.
8. The capacity expansion device of a solid state drive according to claim 1, characterized in that: The TOP surface of the first backplane includes a controller, 3 memory devices, 4 non-volatile memories and a high-speed connector; the Bottom surface of the first backplane includes 2 memory devices, 4 non-volatile memories and a power chip.
9. The capacity expansion device of a solid state drive according to claim 1, characterized in that: The TOP surface of the second backplane includes 4 non-volatile memories and multiplexers corresponding to the 4 non-volatile memories, and a high-speed connector; the Bottom surface of the second backplane includes 4 non-volatile memories and multiplexers corresponding to the 4 non-volatile memories.
10. The capacity expansion device of a solid state drive according to claim 1, characterized in that: The first back plate and the second back plate are both provided with temperature sensors.