Integrated chip

Abstract

An integrated chip includes a first semiconductor substrate. The first semiconductor substrate includes a doped region. A first light sensor and a second light sensor are in a first semiconductor substrate. The trench isolation layer at least partially surrounds the first light sensor and the second light sensor and extends between the first light sensor and the second light sensor. The trench isolation layer has a first pair of sidewalls. The first semiconductor substrate extends from the first light sensor between the first pair of sidewalls to the second light sensor. The doped region is between the first pair of sidewalls. The first light sensor and the first gate partially form a first transistor. The second light sensor and the second gate partially form a second transistor. A second semiconductor substrate is over the first gate and the second gate. A third transistor is along the second semiconductor substrate. The third transistor is coupled to the first transistor.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated chip. Background Art

[0002] Complementary metal-oxide semiconductor (CMOS) image sensors are widely used in modern electronic devices, such as cameras, tablet computers, and smart phones. CMOS image sensors can be front-side illuminated (FSI) or back-side illuminated (BSI). Compared with FSI image sensors, BSI image sensors have better sensitivity, better angle response, and greater metal wiring flexibility. Utility Model Content

[0003] Some embodiments of the present invention provide an integrated chip, characterized in that it includes: a first semiconductor substrate including a doped region; a first light sensor and a second light sensor, wherein the second light sensor is laterally spaced apart from the first light sensor in the first semiconductor substrate; a trench isolation layer at least partially surrounding the first light sensor and the second light sensor and extending between the first light sensor and the second light sensor, the trench isolation layer having a first pair of side walls between the first light sensor and the second light sensor, wherein the first semiconductor substrate extends from the first light sensor between the first pair of side walls of the trench isolation layer to the second light sensor, and wherein the doped region is disposed in the trench isolation layer. The invention relates to a semiconductor device comprising: a semiconductor layer comprising: a semiconductor device comprising: a semiconductor layer formed between the first pair of side walls of the separation layer; a first gate and a second gate, respectively above the first photosensor and the second photosensor, the first photosensor and the first gate partially forming a first transistor, and the second photosensor and the second gate partially forming a second transistor; a first metal interconnect and a second metal interconnect, respectively above the first gate and the second gate, the first metal interconnect coupled to the first gate, and the second metal interconnect coupled to the second gate; a second semiconductor substrate, above the first gate and the second gate and spaced apart from the first gate and the second gate; and a third transistor, along the second semiconductor substrate, wherein the third transistor is coupled to the first transistor.

[0004] In addition, other embodiments of the present invention provide an integrated chip, characterized in that it includes: a first semiconductor substrate, including a shared floating diffusion area; a first light sensor and a second light sensor, in the first semiconductor substrate, the first light sensor and the second light sensor are on opposite sides of the shared floating diffusion area; a first transfer gate and a second transfer gate, respectively on the first light sensor and the second light sensor, the first light sensor, the shared floating diffusion area and the first transfer gate partially form a first transfer transistor, and the second light sensor, the shared floating diffusion area and the second transfer gate partially form a second transfer transistor; a first metal interconnect and a second metal interconnect, respectively on the first transfer gate and the second transfer gate, the first metal interconnect is coupled to the first transfer gate, and the second metal interconnect is coupled to the second transfer gate; a second semiconductor substrate, on the first a first transfer transistor and the second transfer transistor above and spaced apart from the first transfer transistor and the second transfer transistor; a first pixel transistor, along the second semiconductor substrate; a third metal interconnect, between the first pixel transistor and the shared floating diffusion region, the third metal interconnect coupled to the first pixel transistor and the shared floating diffusion region; and a trench isolation layer, laterally surrounding the first light sensor and the second light sensor, the trench isolation layer extending between the first light sensor and the second light sensor, wherein a first pair of side walls of the trench isolation layer define an opening in the trench isolation layer and between the first light sensor and the second light sensor, wherein the first semiconductor substrate extends from the first light sensor between the first pair of side walls of the trench isolation layer to the second light sensor, and wherein the shared floating diffusion region is between the first pair of side walls of the trench isolation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1 A top view of some embodiments of an integrated chip including pixels along a first semiconductor substrate is shown.

[0007] Figure 2 and Figure 3 Shows Figure 1 Cross-sectional views of some embodiments of an integrated chip.

[0008] Figure 4 Shows Figure 1-Figure 3 Circuit diagrams of some embodiments of an integrated chip.

[0009] Figure 5 Shows Figure 1 A top view of some embodiments of an integrated chip, wherein a plurality of pixels are arranged along a first semiconductor substrate.

[0010] Figure 6 Shows Figure 5 Cross-sectional views of some embodiments of an integrated chip.

[0011] Figure 7 Shows Figure 1 A top view of some embodiments of an integrated chip in which four transfer transistors share a floating diffusion region.

[0012] Figure 8 and Fig. 9 Shows Figure 7 Cross-sectional views of some embodiments of an integrated chip.

[0013] Fig.10 Shows Figure 7-Figure 9 Circuit diagrams of some embodiments of an integrated chip.

[0014] Fig.11 A top view of some embodiments of an integrated chip including pixels along a first semiconductor substrate is shown.

[0015] Fig.12 Shows Fig.11 Cross-sectional views of some embodiments of an integrated chip.

[0016] Figure 13 to Figure 36 Various views of some embodiments of a method for forming an integrated chip including pixels along a first semiconductor substrate are shown.

[0017] Fig.37 A flow chart illustrating some embodiments of a method for forming an integrated chip including pixels along a first semiconductor substrate. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0020] The integrated chip includes an image sensor. The image sensor includes a pixel along a semiconductor substrate. The pixel includes a first light sensor and a first floating diffusion region in the substrate. The pixel also includes a second light sensor and a second floating diffusion region in the substrate. The first transfer gate is above the first light sensor and the second transfer gate is above the second light sensor. The first light sensor, the first floating diffusion region, and the first transfer gate partially form a first transfer transistor. The second light sensor, the second floating diffusion region, and the second transfer gate partially form a second transfer transistor. The pixel also includes a pixel transistor (e.g., a reset transistor, a source follower transistor, and a select transistor) along the substrate and next to the transfer transistor. For example, the source / drain region of the pixel transistor is in the substrate and next to the light sensor. The pixel transistor is coupled to one or more transfer transistors.

[0021] Because the pixel transistors are in the substrate and next to the transfer transistors, the performance of the integrated chip may be reduced. For example, the source / drain regions of the pixel transistors take up space in the substrate, thereby reducing the available space for the first and second light sensors. Therefore, the light-sensitive area of ​​the pixel may be reduced. In addition, because the pixel transistors are arranged along the substrate, it may be challenging to reduce the pitch of the pixels.

[0022] In various embodiments of the present invention, the pixel transistors are spaced apart above the substrate to increase the space available for the light sensor in the substrate. For example, the light sensor is disposed in a first substrate, the transfer transistor is arranged along the first substrate, and the pixel transistor is arranged along a second substrate. The second substrate is bonded to the first substrate.

[0023] By placing the pixel transistors along a substrate separate from the transfer transistors and the light sensor, the performance of the integrated chip can be improved. For example, since the pixel transistors are arranged along a second substrate separate from the first substrate, the area of ​​the light sensor can be increased. Therefore, the light-sensitive area of ​​the pixel can be increased. In addition, since fewer transistors are arranged along the first substrate, the pitch of the pixels can be more easily reduced.

[0024] Figure 1 A top view 100 of some embodiments of an integrated chip including pixels 102 along a first semiconductor substrate 104 is shown. Figure 2 Shows Figure 1 A first cross-sectional view 200 of some embodiments of an integrated chip. Figure 3 Shows Figure 1 and Figure 2 A second cross-sectional view 300 of some embodiments of an integrated chip. In some embodiments, Figure 2 The cross-sectional view 200 may be, for example, along Figure 1 In some embodiments, Figure 3 The cross-sectional view 300 may be, for example, along Figure 1 The line B-B' is intercepted.

[0025] Reference Figure 1-Figure 3 , the integrated chip includes a first chip 138. The first chip 138 includes a pixel 102. The pixel 102 includes a first light sensor 106 and a second light sensor 108 in a first substrate 104. For example, the first substrate 104 includes a first photodiode region 110, a second photodiode region 112, and a bulk region 114. The first photodiode region 110 and the second photodiode region 112 are arranged along the front side 104a of the first substrate 104. The bulk region 114 of the first substrate 104 surrounds the first and second photodiode regions (110, 112). The bulk region 114 of the first substrate 104 has a first doping type (e.g., p-type). The first and second photodiode regions (110, 112) have a second doping type (e.g., n-type) different from the first doping type. The first light sensor 106 is formed by a first PN junction between the first photodiode region 110 and the bulk region 114 of the first substrate 104. The second photosensor 108 is formed by a second PN junction between the second photodiode region 112 and the bulk region 114 of the first substrate 104 .

[0026] Because pixel 102 includes first and second photosensors (106, 108) in the same pixel, pixel 102 may be referred to as a dual photodetector pixel. In some cases, a dual photodetector pixel may have improved performance (eg, focusing speed) compared to a single photodetector pixel.

[0027] A first transmission gate 118 and a second transmission gate 120 are respectively above the first light sensor 106 and the second light sensor 108. A gate dielectric layer 119 is between the first and second transmission gates (118, 120) and the first substrate 104. The first transmission gate 118, the gate dielectric layer 119, and the first light sensor 106 partially form a first transmission transistor 122. The second transmission gate 120, the gate dielectric layer 119, and the second light sensor 108 partially form a second transmission transistor 124.

[0028] The first chip 138 also includes a first dielectric structure 130 over the first substrate 104. A first metal interconnect structure 132 is disposed within the first dielectric structure 130 and is coupled to various features of the pixel 102 (e.g., the floating diffusion region 116, the transfer gates 118, 120, and / or some other features). The first metal interconnect structure 132 includes metal contacts 156, metal lines 158, metal vias 160, and metal pads 162. The color filters 134 and microlenses 136 (through which photons can pass to strike the light sensors (106, 108)) are arranged along the back side 104b of the first substrate 104.

[0029] The second chip 140 is on top of the first chip 138. The second chip 140 includes a second semiconductor substrate 144. The pixel transistors are arranged along the second substrate 144. For example, a first pixel transistor 146 (e.g., a reset transistor), a second pixel transistor 148 (e.g., a source follower transistor), and a third pixel transistor 150 (e.g., a select transistor) are arranged along the second substrate 144. Since the pixel transistors (146, 148, 150) are arranged along a different substrate from the light sensors (106, 108), there is more available space in the first substrate 104 for the light sensors (106, 108). Therefore, the light-sensing area of ​​the pixel 102 can be increased.

[0030] The second dielectric structure 152 is below the second substrate 144 (e.g., along the front side of the second substrate 144) and the second metal interconnect structure 154 is within the second dielectric structure 152. The second metal interconnect structure 154 includes a metal contact 164, a metal line 166, a metal via 168, and a metal pad 170. The first backside dielectric layer 142 is above the second substrate 144 (e.g., along the back side of the second substrate 144). The first chip 138 and the second chip 140 are bonded together along the dielectric structure (130, 152) and the metal interconnect structure (132, 154). For example, in some embodiments, the dielectric structure (130, 152) and the metal interconnect structure (132, 154) include a bonding interface layer (e.g., Fig.35 The first and second chips (138, 140) are bonded along the bonding interface layer.

[0031] In some embodiments, one or more metal contacts 156, one or more metal lines 158, one or more metal vias 160, and one or more metal pads 162 of the first metal interconnect structure 132 are above the transmission gates (118, 120) and coupled to the transmission gates (118, 120) for controlling the voltage of the transmission gates (118, 120). For example, a first group of metal interconnects of the first metal interconnect structure 132 is coupled to the first transmission gate 118, and a second group of metal interconnects of the first metal interconnect structure 132 is separated and isolated from the first group and coupled to the second transmission gate 120, so that the transmission transistors (122, 124) can be individually controlled to respectively access the first and second optical sensors 106, 108. The transmission gates (118, 120) are coupled to the second chip 140 through the first and second metal interconnect structures (132, 154).

[0032] The trench isolation layer 126 laterally surrounds the first light sensor 106 and the second light sensor 108 in a closed path along the boundary of the pixel 102. In addition, the trench isolation layer 126 extends directly between the first light sensor 106 and the second light sensor 108. Since the trench isolation layer 126 surrounds the first light sensor 106 and the second light sensor 108 along the boundary of the pixel 102, the trench isolation layer 126 can isolate the pixel 102 from an adjacent pixel (not shown), thereby reducing crosstalk between the pixel 102 and the adjacent pixel. In addition, since the trench isolation layer 126 extends directly between the first light sensor 106 and the second light sensor 108, crosstalk between the first and second light sensors can be reduced. In addition, using the trench isolation layer 126 to isolate pixels can improve the full well capacity (FWC) of the pixel.

[0033] The trench isolation layer 126 has an opening 128 therein. The opening 128 is defined by a pair of sidewalls 126a of the trench isolation layer 126. In some embodiments, the opening 128 is further defined by an upper surface 126b of the trench isolation layer 126. The opening 128 (e.g., the sidewalls 126a defining the opening 128) is directly located between the first light sensor 106 and the second light sensor 108. The first substrate 104 continuously extends from the first light sensor 106 and between the pair of sidewalls 126a and above the upper surface 126b of the trench isolation layer 126 to the second light sensor 108.

[0034] The first substrate 104 further includes a floating diffusion region 116. The floating diffusion region 116 is laterally spaced apart between the first light sensor 106 and the second light sensor 108. The floating diffusion region 116 has a second doping type (e.g., n-type). The floating diffusion region 116 is disposed in the opening 128. For example, the floating diffusion region 116 is directly between the pair of sidewalls 126a and directly above the upper surface 126b of the trench isolation layer 126.

[0035] Since the trench isolation layer 126 has an opening 128 therein, the floating diffusion region 116 can be disposed in the first substrate 104 directly between the first and second light sensors (106, 108). Therefore, the floating diffusion region 116 can be shared between the first and second transfer transistors (122, 124). For example, the first transfer gate 118, the gate dielectric layer 119, the first light sensor 106, and the floating diffusion region 116 form the first transfer transistor 122, and the second transfer gate 120, the gate dielectric layer 119, the second light sensor 108, and the floating diffusion region 116 form the second transfer transistor 124. Since the transfer transistors (122, 124) share the floating diffusion region 116, the performance of the integrated chip can be improved. For example, by sharing a single floating diffusion region between the transfer transistors (122, 124) (rather than the transfer transistors (122, 124) having separate floating diffusion regions), the number of separate floating diffusion regions in the first substrate 104 can be reduced. Therefore, the floating diffusion capacitance of the image sensor can be reduced and the conversion gain of the image sensor can be improved.

[0036] In some embodiments, the first photodiode region 110 and the floating diffusion region 116 form the source / drain region of the first transfer transistor 122. Similarly, the second photodiode region 112 and the floating diffusion region 116 form the source / drain region of the second transfer transistor 124. Depending on the context, the source / drain region may refer to the source or drain individually or collectively. In some embodiments, the bulk region 114 of the first substrate 104 forms the channel region of the transfer transistors (122, 124).

[0037] The metal interconnects of the first and second metal interconnect structures (132, 154) couple the source / drain region 147 of the first pixel transistor 146, the gate 149 of the second pixel transistor 148, and the floating diffusion region 116. For example, one or more metal contacts 156, one or more metal lines 158, one or more metal vias 160, and one or more metal pads 162 of the first metal interconnect structure 132 and one or more metal contacts 164, one or more metal lines 166, one or more metal vias 168, and one or more metal pads 170 of the second interconnect structure 154 couple the floating diffusion region 116 to the source / drain region 147 of the first pixel transistor 146 and to the gate 149 of the second pixel transistor 148. The second pixel transistor 148 is coupled to the third pixel transistor 150.

[0038] In some embodiments, the third chip 172 is above the second chip 140. The third chip 172 includes a third semiconductor substrate 176. The third chip 172 may be or include an application-specific integrated chip (ASIC), etc. In some embodiments, the third chip includes a circuit, such as a transistor 178 along the third substrate 176. A third dielectric structure 180 is below the third substrate 176 (e.g., along the front side of the third substrate 176) and a third metal interconnect structure 182 is within the third dielectric structure 180.

[0039] The second chip 140 and the third chip 172 are bonded together along the third dielectric structure 180, the first backside dielectric layer 142, and the second and third metal interconnect structures (154, 182). In some embodiments, the second metal interconnect structure 154 includes a metal through-substrate via (TSV) 171 extending through the second substrate 144 and the first backside dielectric layer 142 to couple the second metal interconnect structure 154 to the third metal interconnect structure 182.

[0040] In some embodiments, the third chip 172 includes a second backside dielectric layer 174 over (e.g., along the backside of) the third substrate 176. In some embodiments, the third metal interconnect structure 182 includes TSVs 184 extending through the third substrate 176 and metal bumps 186 over the second backside dielectric layer 174 and coupled to the TSVs 184.

[0041] In some embodiments, the substrate (104, 144, 176) may, for example, include silicon or some other suitable semiconductor. In some embodiments, the trench isolation layer 126 may, for example, include silicon dioxide, some other suitable dielectric, tungsten, or some other suitable metal. In some embodiments, the gate dielectric layer 119 may, for example, include silicon dioxide, some high-k dielectric, or some other suitable material. In some embodiments, the transfer gate (118, 120) may, for example, include polysilicon, metal, or some other suitable material. In some embodiments, the dielectric layers of the dielectric structure (130, 152, 180) and the backside dielectric layer (142, 174) may, for example, include silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the metal interconnect of the metal interconnect structure (132, 154, 182) may, for example, include tungsten, copper, aluminum, or some other suitable material.

[0042] Figure 4 Shows Figure 1-Figure 3 Circuit diagram 400 of some embodiments of an integrated chip.

[0043] The first chip 138 includes first and second transfer transistors (122, 124). The second chip 140 includes pixel transistors (146, 148, 150). The first transfer transistor 122 and the second transfer transistor 124 share a floating diffusion area 116. The first light sensor 106 and the second light sensor 108 are selectively coupled to the floating diffusion area 116 through the first transfer transistor 122 and the second transfer transistor 124, respectively. The floating diffusion area 116 is coupled to the source / drain area 147 of the first pixel transistor 146 and the gate 149 of the second pixel transistor 148. The second pixel transistor 148 and the third pixel transistor 150 are coupled in series. In some embodiments, the second chip 140 also includes a pixel circuit 402 coupled to the third pixel transistor 150. The pixel circuit 402 may, for example, include additional transistors, diodes, resistors, capacitors, inductors, or some other suitable circuits. In some embodiments, the pixel circuit 402 is coupled to the ASIC circuit 404 of the third chip 172. The ASIC circuit 404 may, for example, include transistors (e.g. Figure 2 transistor 178), a diode, a resistor, a capacitor, an inductor or some other suitable circuit.

[0044] Figure 5 Shows Figure 1 A top view 500 of some embodiments of an integrated chip, wherein a plurality of pixels are arranged along a first substrate 104 . Figure 6 Shows Figure 5 A cross-sectional view 600 of some embodiments of an integrated chip. In some embodiments, Figure 6 The cross-sectional view 600 may be, for example, along Figure 5The line C-C' is intercepted.

[0045] Reference Figure 5 and Figure 6 , the first pixel 102, the second pixel 502, the third pixel 504, and the fourth pixel 506 are arranged along the first substrate 104. In some embodiments, each of the pixels (102, 502, 504, 506) includes a pair of light sensor regions forming a pair of light sensors, a floating diffusion region, a pair of transfer gates forming a pair of transfer transistors sharing the floating diffusion region, a color filter, and a microlens. For example, the first pixel 102 includes first and second photodiode regions (110, 112) forming first and second light sensors (106, 108), a first floating diffusion region 116, first and second transfer gates (118, 120) forming first and second transfer transistors (122, 124), a first color filter 134, and a first microlens 136. Similarly, the second pixel 502 includes third and fourth photodiode regions (508, 510) forming third and fourth light sensors (512, 514), a second floating diffusion region 516, third and fourth transfer gates (518, 520) forming third and fourth transfer transistors (522, 524), a second color filter 526 and a second microlens 528.

[0046] In some embodiments, the transfer gates (e.g., first and second transfer gates (118, 120)) are symmetrical relative to the floating diffusion region (e.g., first floating diffusion region 116). In some embodiments, the transfer gates are asymmetrical relative to the floating diffusion region (e.g., as shown by dashed features (538, 540, 542, 544) representing offset transfer gates).

[0047] The trench isolation layer 126 surrounds each of the pixels (102, 502, 504, 506) and extends between them. The trench isolation layer 126 electrically and / or optically isolates the pixels from each other, thereby reducing crosstalk between the pixels. The trench isolation layer 126 has an opening between each pair of light sensors. For example, the first pair of sidewalls 126a of the trench isolation layer 126 defines a first opening 128 in the trench isolation layer 126, and the second pair of sidewalls 126c defines a second opening 530 in the trench isolation layer 126. In some embodiments (e.g. Figure 2 As shown in FIG. 1 , the trench isolation layer 126 extends directly below the first and second openings (128, 530), so that the first and second openings (128, 530) further extend through the upper surface (eg, Figure 2 In some other embodiments (e.g. Figure 6), the first substrate 104 further includes first and second implant regions (546, 548) in the first and second openings (128, 530), respectively (e.g., directly between the pair of sidewalls (126a, 126c) of the trench isolation layer 126 that define the first and second openings (128, 530), respectively). The implant regions have a first doping type (e.g., p-type). The implant regions provide electrical isolation between the photo sensors. For example, the first implant region 546 provides isolation between the first photo sensor 106 and the second photo sensor 108. The second implant region 548 provides isolation between the third photo sensor 512 and the fourth photo sensor 514.

[0048] The floating diffusion region is disposed in the opening. For example, the first and second floating diffusion regions (116, 516) are between the sidewalls of the trench isolation layer 126, and the sidewalls define the first and second openings (128, 530), respectively. In some embodiments, the floating diffusion region (116, 516) is disposed on the upper surface (e.g. Figure 2 In some embodiments, the floating diffusion region is above the implanted region (eg, the first and second implanted regions (546, 548)).

[0049] In some embodiments, a pixel transistor is disposed above and coupled to each transfer transistor. For example, in some embodiments, the first pixel transistor 146, the second pixel transistor 148, and the third pixel transistor 150 are above and coupled to the first floating diffusion region 116. Similarly, the fourth pixel transistor 532, the fifth pixel transistor 534, and the sixth pixel transistor 536 are above and coupled to the second floating diffusion region 516.

[0050] Figure 7 Shows Figure 1 A top view 700 of some embodiments of an integrated chip in which four pass transistors share a floating diffusion region. Figure 8 Shows Figure 7 A first cross-sectional view 800 of some embodiments of an integrated chip. Fig. 9 Shows Figure 8 A second cross-sectional view 900 of some embodiments of an integrated chip. Fig.10 Shows Figure 7-Figure 9 Circuit diagram 1000 of some embodiments of an integrated chip. In some embodiments, Figure 8 The cross-sectional view 800 may be, for example, along Figure 7 In some embodiments, Fig. 9 The cross-sectional view 900 may be, for example, along Figure 7 The line E-E' is intercepted.

[0051] Reference Figure 7-10 , the integrated chip includes a first pixel 102, a second pixel 702, a third pixel 704, and a fourth pixel 706 arranged along a first substrate 104. The first pixel 102 includes first and second photodiode regions (110, 112) forming first and second light sensors (106, 108), first and second transfer gates (118, 120) forming first and second transfer transistors (122, 124), a first color filter 134, and a first microlens 136. Similarly, the second pixel 702 includes third and fourth photodiode regions (708, 710) forming third and fourth light sensors (712, 714), third and fourth transfer gates (716, 718) forming third and fourth transfer transistors (720, 722), a second color filter 724, and a second microlens 726.

[0052] The first opening 728 is in the trench isolation layer 126 between the first pixel 102 and the second pixel 502. The first opening 728 is formed by the first pair of sidewalls 126d and the second pair of sidewalls 126e of the trench isolation layer 126. In some embodiments, the first opening 728 is further defined by the first upper surface 126f of the trench isolation layer 126. The first substrate 104 extends continuously through the first opening 728 (e.g., between the first pair of sidewalls 126d, between the second pair of sidewalls 126e, and above the first upper surface 126f of the trench isolation layer 126) between each of the light sensors (106, 108, 712, 714) of the first and second pixels (102, 702). The floating diffusion region 116 is disposed in the first opening 728 (e.g., between the first pair of sidewalls 126d, between the second pair of sidewalls 126e, and above the first upper surface 126f of the trench isolation layer 126).

[0053] The floating diffusion region 116 is shared by the first pixel 102 and the second pixel 702. For example, the first transfer transistor 122, the second transfer transistor 124, the third transfer transistor 720, and the fourth transfer transistor 722 share the floating diffusion region 116. By sharing a single floating diffusion region 116 between four transfer transistors, the number of individual floating diffusion regions in the first substrate 104 can be further reduced. Therefore, the floating diffusion capacitance of the image sensor can be further reduced and the conversion gain of the image sensor can be further improved. The first pixel transistor 146, the second pixel transistor 148, and the third pixel transistor 150 are above the first floating diffusion region 116 and coupled to the first floating diffusion region 116.

[0054] In some embodiments, the second opening 734 is in the trench isolation layer 126 between the first light sensor 106 and the second light sensor 108. The second opening 734 is defined by the third pair of sidewalls 126g of the trench isolation layer 126. In some embodiments, the second opening 734 is further defined by the second upper surface 126h of the trench isolation layer 126. The first substrate 104 extends continuously through the second opening 734 between the first and second light sensors (106, 108) (e.g., between the third pair of sidewalls 126g and above the second upper surface 126h of the trench isolation layer 126). Similarly, the third opening 736 is in the trench isolation layer 126 between the third light sensor 712 and the fourth light sensor 714. The third opening 736 is defined by the fourth pair of sidewalls 126i of the trench isolation layer 126. In some embodiments, the third opening 736 is further defined by the third upper surface (not shown) of the trench isolation layer 126. The first substrate 104 extends continuously through the third opening 736 between the third and fourth photosensors ( 712 , 714 ) (eg, between the fourth pair of sidewalls 126 i and above the third upper surface (not shown) of the trench isolation layer 126 ).

[0055] In some embodiments, the first substrate 104 includes a first implant region 730 in the second opening 734 and a second implant region 732 in the third opening 736. The first implant region 730 and the second implant region 732 have a first doping type (e.g., p-type). In some embodiments, the implant regions provide isolation between adjacent photo sensors (e.g., 106, 108 and 712, 714). In some other embodiments, the implant regions (e.g., 730, 732) are body contact regions for coupling to the bulk region 114 of the first substrate 104.

[0056] Fig.11 A top view 1100 of some other embodiments of an integrated chip including pixels 102 along a first substrate 104 is shown. Fig.12 Shows Fig.11 A cross-sectional view 1200 of some embodiments of an integrated chip. In some embodiments, Fig.12 The cross-sectional view 1200 may be, for example, along Fig.11 The line F-F' is intercepted.

[0057] The integrated chip includes a first pixel 102, a second pixel 1102, a third pixel 1104, and a fourth pixel 1106 arranged along a first substrate 104. Each pixel includes a pair of floating diffusion regions. For example, the first pixel 102 includes a first and a second floating diffusion region (1110, 1112). The first light sensor 106, the first floating diffusion region 1110, and the first transfer gate 118 form a first transfer transistor 122. The second light sensor 108, the second floating diffusion region 1112, and the second transfer gate 120 form a second transfer transistor 124.

[0058] The trench isolation layer 126 has an opening therein between each pair of photo sensors. For example, a first opening 1116 in the trench isolation layer 126 is defined by a first pair of sidewalls 126g of the trench isolation layer 126. The first substrate 104 includes an implant region in the opening. For example, a first implant region 1114 is in the first opening 1116. The implant region has a first doping type (e.g., p-type). In some embodiments, the implant region isolates the photo sensors from each other. In some other embodiments, the first implant region 1114 is a body contact region. Since the pixels share one implant region, the performance of the pixels can be improved.

[0059] In some embodiments, a first group of pixel transistors (e.g., a first pixel transistor 146, a second pixel transistor 148, and a third pixel transistor 150) are above and coupled to the first floating diffusion region 1110, and a second group of pixel transistors (not shown) are above and coupled to the second floating diffusion region 1112.

[0060] Figure 13 to Figure 36 Views (1300-3600) of some embodiments of a method for forming an integrated chip including pixels along a first semiconductor substrate are shown. Figure 13 to Figure 36 Described as relating to one method, it should be understood that Figure 13 to Figure 36 The structure disclosed in is not limited to this method, but can exist independently as a structure independent of this method.

[0061] Figure 13-Figure 30 Views ( 1300 - 3000 ) of some embodiments of a method for forming a first chip 138 including pixels 102 along a first substrate 104 are shown.

[0062] like Fig.13 Top view 1300 and Fig.14As shown in the corresponding cross-sectional view 1400 of FIG. 1 , a first light sensor 106 and a second light sensor 108 are formed in the first semiconductor substrate 104. For example, a first photodiode region 110 and a second photodiode region 112 are formed in the first substrate 104 along the front side 104a of the first substrate 104. The bulk region 114 of the first substrate 104 surrounds the photodiode regions (110, 112). The bulk region 114 of the first substrate 104 has a first doping type (e.g., p-type) and the photodiode regions (110, 112) have a second doping type (e.g., n-type) different from the first doping type. The photodiode regions (110, 112) and the bulk region 114 of the first substrate 104 form light sensors (106, 108).

[0063] In some embodiments, the photodiode regions (110, 112) are formed in the first substrate 104 by an ion implantation process, a diffusion process, or some other suitable process. In some embodiments, a mask layer 1402 is formed over the front side 104a of the first substrate 104, and the photodiode regions (110, 112) are formed in the first substrate 104 according to the openings in the mask layer 1402. In some embodiments, the mask layer 1402 may, for example, include a photoresist, a dielectric hard mask, or some other suitable material. Fig.13 The mask layer 1402 is not shown in the top view 1300 of FIG.

[0064] like Fig.15 Top view 1500 and Fig.16 As shown in the corresponding cross-sectional view 1600 of FIG. 1 , a gate dielectric layer 119 is deposited on the front side 104a of the first substrate 104, and a gate layer 1502 is deposited on the gate dielectric layer 119. In some embodiments, the gate dielectric layer 119 may, for example, include silicon, some high-k dielectric, or some other suitable material. In some embodiments, the gate layer 1502 may, for example, include polysilicon, metal, or some other suitable material. In some embodiments, the gate dielectric layer 119 and / or the gate layer 1502 may be deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

[0065] like Fig.17 Top view 1700 and Fig.18 As shown in the corresponding cross-sectional view 1800, the gate layer (eg Fig.15 and Fig.16The gate layer 1502 and the gate dielectric layer 119 are patterned to form the first transmission gate 118 and the second transmission gate 120 from the gate layer 1502. In some embodiments, the patterning includes forming a mask layer 1802 over the gate layer 1502 and etching the gate layer 1502 and the gate dielectric layer 119 according to the mask layer 1802.

[0066] In some embodiments, etching includes a dry etching process (eg, plasma etching, reactive ion etching, ion beam etching, or the like) or some other suitable etching process. In some embodiments, mask layer 1802 may include, for example, photoresist, dielectric hard mask, or some other suitable material. Fig.17 The mask layer 1802 is not shown in the top view 1700 of FIG.

[0067] like Fig.19 The top view 1900 and the corresponding Fig. 20 As shown in the cross-sectional view 2000 of FIG. 1 , a floating diffusion region 116 is formed in the first substrate 104 along the front side 104a of the first substrate 104 and between the transfer gates (118, 120). The floating diffusion region 116 has a second doping type (e.g., n-type). By forming the floating diffusion region 116 in the first substrate 104 between the transfer gates (118, 120), a first transfer transistor 122 and a second transfer transistor 124 (which share the floating diffusion region 116) are formed along the first substrate 104.

[0068] In some embodiments, the floating diffusion region 116 is formed in the first substrate 104 by an ion implantation process, a diffusion process, or some other suitable process. In some embodiments, a mask layer 2002 is formed over the first substrate 104 and over a portion of the transfer gates (118, 120). The floating diffusion region 116 is formed in the first substrate 104 according to the opening in the mask layer 2002 and according to the sidewalls of the transfer gates (118, 120). In some embodiments, the mask layer 2002 does not cover a portion of the transfer gates (118, 120), so the floating diffusion region 116 can be "self-aligned" to the transfer gates (118, 120). In some embodiments, the mask layer 2002 can include, for example, a photoresist, a dielectric hard mask, or some other suitable material. Fig.19 The mask layer 2002 is not shown in the top view 1900 of FIG.

[0069] like Fig.21As shown in the cross-sectional view 2100 of FIG. 21 , the first dielectric structure 130 and the first metal interconnect structure 132 are formed on the transfer transistors (122, 124). In some embodiments, the first dielectric structure 130 is formed by depositing a plurality of dielectric layers on the first substrate 104. In some embodiments, the first metal interconnect structure 132 is formed by forming a plurality of metal contacts 156, metal lines 158, metal vias 160, and metal pads 162 within the first dielectric structure 130. In some embodiments, the top dielectric layer of the first dielectric structure 130 and the metal pads 162 of the first metal interconnect structure 132 form a first bonding layer 2102.

[0070] In some embodiments, the dielectric layer of the first dielectric structure 130 includes silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the dielectric layer of the first dielectric structure 130 may be deposited by a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, the metal interconnection of the first metal interconnection structure 132 may include copper, aluminum, tungsten, or some other suitable material. In some embodiments, the metal interconnection of the first metal interconnection structure 132 may be formed by etching the dielectric layer of the first dielectric structure 130 and depositing metal on the etched dielectric layer.

[0071] Fig. 22 A top view 2200 of some embodiments of a first method for forming a trench 2302 in a first substrate 104 is shown and Fig.23 A corresponding cross-sectional view 2300 is shown.

[0072] like Fig. 22 The top view 2200 and the corresponding Fig.23 As shown in the cross-sectional view 2300 of FIG. 2 , the back side 104b of the first substrate 104 opposite the front side 104a is etched to form a trench 2302 in the first substrate 104. The trench 2302 is defined by the sidewalls (104c, 104d, 104e, 104f, 104h, 104i) of the first substrate 104, the bottom surface 130a of the first dielectric structure 130, and the lower surface 104g of the first substrate 104. The trench 2302 surrounds the first and second light sensors (106, 108) and extends between the first and second light sensors (106, 108). In some embodiments, the trench 2302 extends through the first substrate 104 to the first dielectric structure 130, except for directly above the floating diffusion region 116. Directly above the floating diffusion region 116, the trench 2302 extends to a depth 2306 below the back side 104b of the first substrate 104, which is less than a thickness 2308 of the first substrate 104. Thus, the trench 2302 does not extend through the floating diffusion region 116.

[0073] In some embodiments, a mask layer 2304 is formed over the back side 104b of the first substrate 104, and etching is performed according to the mask layer 2304. In some embodiments, etching includes a dry etching process (e.g., plasma etching, reactive ion etching, ion beam etching, or the like) or some other suitable etching process. In some embodiments, the mask layer 2304 may, for example, include a photoresist, a dielectric hard mask, or some other suitable material. Fig. 22 The mask layer 2304 is not shown in the top view 2200 of .

[0074] Figure 24-Figure 27 Views (2400-2700) of some embodiments of a second method for forming a trench 2502 in a first substrate 104 are shown.

[0075] like Fig.24 Top view 2400 and Fig.25 As shown in the corresponding cross-sectional view 2500 of FIG. 1 , the back side 104b of the first substrate 104 is etched to form a trench 2502 in the first substrate 104. The trench 2502 is defined by the sidewalls (104c, 104f, 104j, 104k) of the first substrate 104 and the bottom surface 130a of the first dielectric structure 130. The trench 2502 does not extend into the first substrate 104 directly above the floating diffusion region 116.

[0076] In some embodiments, a mask layer 2504 is formed over the back side 104 b of the first substrate 104 , and etching is performed based on the mask layer 2504 . Fig.24 The mask layer 2504 is not shown in the top view 2400 of FIG.

[0077] like Fig.26 The top view 2600 and the corresponding Fig. 27 As shown in the cross-sectional view 2700 of FIG. 27 , the implant region 546 is formed in the first substrate 104 along the back side 104b of the first substrate 104 and between the photo sensors (106, 108). The implant region 546 has a first doping type (e.g., p-type). In some embodiments, the implant region 546 is formed in the first substrate 104 by an ion implantation process, a diffusion process, or some other suitable process. In some embodiments, a mask layer 2702 is formed on the first substrate 104, and the implant region 546 is formed in the first substrate 104 according to the opening in the mask layer 2702.

[0078] like Fig.28 Top view 2800 and Fig.29 As shown in the cross-sectional view 2900, the trench isolation layer 126 is formed in the trench (eg Fig.23 2302 or Fig. 272502). In some embodiments, the trench isolation layer 126 is formed in the trench, including depositing the trench isolation layer 126 over the back side 104b of the first substrate 104 and in the trench, and performing a planarization process (e.g., chemical mechanical planarization (CMP) or some other suitable process) on the trench isolation layer 126. In some embodiments, the planarization process removes the trench isolation layer 126 from the back side 104b of the first substrate 104. In some other embodiments (not shown), a portion of the trench isolation layer 126 remains on the back side 104b of the first substrate 104.

[0079] In some embodiments, the trench isolation layer 126 includes silicon dioxide, tungsten, or some other suitable material. In some embodiments, the trench isolation layer 126 can be deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0080] like Fig.30 As shown in the cross-sectional view 3000 of , the color filter 134 and the microlens 136 are formed on the back side 104 b of the first substrate 104 .

[0081] Figure 31-Figure 34 Views ( 3100 - 3400 ) of some embodiments of a method for forming the second chip 140 are shown.

[0082] like Fig.31 As shown in the cross-sectional view 3100 of , a plurality of pixel transistors are formed along the second semiconductor substrate 144. For example, the first pixel transistor 146, the second pixel transistor 148, and the third pixel transistor 150 are formed along the front side of the second substrate 144.

[0083] like Fig.32 As shown in the cross-sectional view 3200 of , the second dielectric structure 152 and the second metal interconnect structure 154 are formed on the pixel transistors (146, 148, 150). In some embodiments, forming the second dielectric structure 152 includes depositing a plurality of dielectric layers on the second substrate 144. In some embodiments, forming the second interconnect structure 154 includes forming a plurality of metal contacts 164, metal lines 166, metal vias 168, and metal pads 170 in the second dielectric structure 152. In some embodiments, the top dielectric layer of the second dielectric structure 152 and the metal pads 170 of the second interconnect structure 154 form a second bonding layer 3202.

[0084] In some embodiments, the dielectric layer of the second dielectric structure 152 may include silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the dielectric layer of the second dielectric structure 152 may be deposited by a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, the metal interconnect of the second metal interconnect structure 154 may include copper, aluminum, tungsten, or some other suitable material.

[0085] like Fig.33 As shown in the cross-sectional view 3300 of , a first backside dielectric layer 142 is formed along the back side of the second substrate 144. In some embodiments, the first backside dielectric layer 142 may include silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the first backside dielectric layer 142 may be deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0086] like Fig.34 As shown in the cross-sectional view 3400 of FIG. 34 , TSV 171 is formed in the second chip 140. In some embodiments, TSV 171 is formed by etching the first backside dielectric layer 142, the second substrate 144, and the second dielectric structure 152, depositing metal over the etched layers, and planarizing the metal.

[0087] like Fig.35 As shown in the cross-sectional view 3500 of , the first chip 138 and the second chip 140 are bonded together along the first dielectric structure 130, the second dielectric structure 152, the first metal interconnect structure 132 and the second metal interconnect structure 154. For example, the first chip 138 and the second chip 140 are bonded together along the first and second bonding layers (2102, 3202). The bonding couples the metal interconnect structures (132, 154) so ​​that the floating diffusion region 116 of the first chip 138 is coupled to the pixel transistor (146, 148, 150) of the second chip 140 through the first and second metal interconnect structures (132, 154). In some embodiments, the bonding includes a fusion bonding process or some other suitable process.

[0088] like Fig.36As shown in the cross-sectional view 3600 of FIG. 36 , the third chip 172 is bonded on the back side of the second chip 140. The third chip 172 includes a third semiconductor substrate 176, a transistor 178 along the third substrate 176, a third dielectric structure 180 along the front side of the third substrate 176, a third metal interconnect structure 182 in the third dielectric structure 180, and a second backside dielectric layer 174 along the back side of the third substrate 176. In some embodiments, the third chip 172 is bonded to the second chip 140 along the first backside dielectric layer 142 and the third dielectric structure 180 of the third chip 172. In some embodiments, the bonding includes a fusion bonding process or some other suitable process.

[0089] Fig.37 A flow chart of some embodiments of a method 3700 for forming an integrated chip including pixels along a first semiconductor substrate is shown. Although method 3700 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown are required to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0090] At block 3702 , a first light sensor and a second light sensor are formed in a first semiconductor substrate along a first side of the first semiconductor substrate. Fig.13 A top view 1300 corresponding to some embodiments of block 3702 is shown and Fig.14 A corresponding cross-sectional view 1400 is shown.

[0091] At block 3704, a first transfer gate is formed over the first photosensor and a second transfer gate is formed over the second photosensor. Fig.17 A top view 1700 corresponding to some embodiments of block 3704 is shown and Fig.18 A corresponding cross-sectional view 1800 is shown.

[0092] At block 3706 , a floating diffusion region is formed in the first semiconductor substrate between the first light sensor and the second light sensor. Fig.19 A top view 1900 corresponding to some embodiments of block 3706 is shown and Fig. 20 A corresponding cross-sectional view 2000 is shown.

[0093] At block 3708 , a first metal interconnect structure is formed over the first side of the first semiconductor substrate. Fig.21 A cross-sectional view 2100 corresponding to some embodiments of block 3708 is shown.

[0094] At block 3710 , a second side of the first semiconductor substrate opposite the first side is etched to form a trench in the first semiconductor substrate. Fig. 22 and Fig.24 A top view (2200, 2400) of some embodiments corresponding to block 3710 is shown. Fig.23 and Fig.25 Cross-sectional views (2300, 2500) of some embodiments corresponding to block 3710 are shown.

[0095] At block 3712 , a trench isolation layer is deposited in the trench, the trench isolation layer having an opening between the first photosensor and the second photosensor, the first semiconductor substrate extending from the first photosensor to the second photosensor through the opening. Fig.28 A top view 2800 corresponding to some embodiments of block 3712 is shown and Fig.29 A corresponding cross-sectional view 2900 is shown.

[0096] At block 3714, a color filter and a microlens are formed directly over the first light sensor and the second light sensor. Fig.30 A cross-sectional view 3000 corresponding to some embodiments of block 3714 is shown.

[0097] At block 3716 , a first pixel transistor is formed along a first side of the second semiconductor substrate. Fig.31 A cross-sectional view 3100 corresponding to some embodiments of block 3716 is shown.

[0098] At block 3718 , a second metal interconnect structure is formed over the first side of the second semiconductor substrate. Fig.32 A cross-sectional view 3200 corresponding to some embodiments of block 3718 is shown.

[0099] At block 3720 , a second semiconductor substrate is bonded over the first side of the first semiconductor substrate such that the first metal interconnect structure is coupled to the second metal interconnect structure. Fig.35 A cross-sectional view 3500 corresponding to some embodiments of block 3720 is shown.

[0100] At block 3722 , a third semiconductor substrate is bonded over the second side of the second semiconductor substrate. Fig.36 A cross-sectional view 3600 corresponding to some embodiments of block 3722 is shown.

[0101] Therefore, the present invention relates to an integrated chip and a method for forming the integrated chip, wherein the integrated chip includes a dual light sensor pixel along a first substrate and a pixel transistor along a second substrate spaced apart from the first substrate.

[0102] Therefore, in some embodiments, the utility model relates to an integrated chip including a first semiconductor substrate. The first semiconductor substrate includes a doped region. A first photo sensor and a second photo sensor are in the first semiconductor substrate. The second photo sensor is laterally spaced apart from the first photo sensor. A trench isolation layer at least partially surrounds the first photo sensor and the second photo sensor and extends between the first photo sensor and the second photo sensor. The trench isolation layer has a first pair of sidewalls between the first photo sensor and the second photo sensor. The first semiconductor substrate extends from the first photo sensor between the first pair of sidewalls of the trench isolation layer to the second photo sensor. The doped region is between the first pair of sidewalls of the trench isolation layer. A first gate and a second gate are respectively above the first photo sensor and the second photo sensor. The first photo sensor and the first gate partially form a first transistor. The second photo sensor and the second gate partially form a second transistor. A first metal interconnect and a second metal interconnect are respectively above the first gate and the second gate. The first metal interconnect is coupled to the first gate. The second metal interconnect is coupled to the second gate. The second semiconductor substrate is above the first gate and the second gate and is spaced apart from the first gate and the second gate. A third transistor is along the second semiconductor substrate. The third transistor is coupled to the first transistor.

[0103] In an embodiment of the present invention, the first semiconductor substrate also includes: a block material region having a first doping type; a first photodiode region having a second doping type different from the first doping type, and a first floating diffusion region having the second doping type, wherein the block material region and the first photodiode region form the first photosensor, wherein the first floating diffusion region further forms the first transistor, and wherein the doping region has the first doping type.

[0104] In an embodiment of the present invention, the first metal interconnection is isolated from the second metal interconnection and the second gate.

[0105] In an embodiment of the present invention, the integrated chip further includes: a color filter and a microlens, under both the first light sensor and the second light sensor.

[0106] In an embodiment of the present invention, the first semiconductor substrate also includes: a block material region having a first doping type; and a first photodiode region having a second doping type different from the first doping type, wherein the block material region and the first photodiode region form the first light sensor, wherein the doping region is a floating diffusion region having the second doping type, wherein the floating diffusion region further forms the first transistor and the second transistor, and wherein the third transistor is coupled to the floating diffusion region.

[0107] In an embodiment of the utility model, the integrated chip further includes: a first metal contact, contacting the floating diffusion area; and a second metal contact, contacting the gate of the third transistor, wherein the second metal contact and the first metal contact couple the gate of the third transistor to the floating diffusion area.

[0108] In an embodiment of the utility model, the integrated chip further includes: a fourth transistor along the second semiconductor substrate; and a third metal contact contacting the source / drain region of the fourth transistor, wherein the third metal contact and the first metal contact couple the source / drain region of the fourth transistor to the floating diffusion region.

[0109] In an embodiment of the present utility model, the integrated chip further includes: a third photo sensor and a fourth photo sensor in the first semiconductor substrate; and a third gate and a fourth gate respectively on the third photo sensor and the third photo sensor, wherein the trench isolation layer laterally surrounds the third photo sensor and the fourth photo sensor, wherein the trench isolation layer extends between the third photo sensor and the fourth photo sensor, between the third photo sensor and the first photo sensor, and between the fourth photo sensor and the second photo sensor, wherein the first pair of side walls of the trench isolation layer are between the first photo sensor, the second photo sensor, the third photo sensor and the fourth photo sensor, wherein the first semiconductor substrate extends from the first photo sensor between the first pair of side walls of the trench isolation layer to the second photo sensor, the third photo sensor and the fourth photo sensor.

[0110] In an embodiment of the present invention, the third light sensor, the floating diffusion area and the third gate partially form a fourth transistor, and wherein the fourth light sensor, the floating diffusion area and the fourth gate partially form a fifth transistor.

[0111] In an embodiment of the present invention, the trench isolation layer has a second pair of side walls between the first photosensor and the second photosensor, the second pair of side walls being spaced apart from the first pair of side walls, wherein the first semiconductor substrate extends from the first photosensor between the second pair of side walls to the second photosensor, wherein the first semiconductor substrate also includes an implantation region between the second pair of side walls, the implantation region having the first doping type.

[0112] In an embodiment of the present invention, the integrated chip further includes: a third semiconductor substrate, which is above the second semiconductor substrate and spaced apart from the second semiconductor substrate; and a fourth transistor, which is arranged along the third semiconductor substrate and coupled to the third transistor.

[0113] In other embodiments, the utility model relates to an integrated chip including a first semiconductor substrate, the first semiconductor substrate including a shared floating diffusion region. A first light sensor and a second light sensor are in the first semiconductor substrate. The first light sensor and the second light sensor are on opposite sides of the shared floating diffusion region. A first transmission gate and a second transmission gate are respectively on the first light sensor and the second light sensor.

[0114] The first light sensor, the shared floating diffusion region, and the first transfer gate partially form a first transfer transistor.

[0115] The second photo sensor, the shared floating diffusion region, and the second transfer gate partially form a second transfer transistor. The first metal interconnect and the second metal interconnect are respectively above the first transfer gate and the second transfer gate. The first metal interconnect is coupled to the first transfer gate. The second metal interconnect is coupled to the second transfer gate. The second semiconductor substrate is above the first transfer transistor and the second transfer transistor and is spaced apart from the first transfer transistor and the second transfer transistor. The first pixel transistor is along the second semiconductor substrate. The third metal interconnect is between the first pixel transistor and the shared floating diffusion region. The third metal interconnect is coupled to the first pixel transistor and the shared floating diffusion region. The trench isolation layer laterally surrounds the first photo sensor and the second photo sensor. The trench isolation layer extends between the first photo sensor and the second photo sensor. The first pair of sidewalls of the trench isolation layer define an opening in the trench isolation layer and between the first photo sensor and the second photo sensor. The first semiconductor substrate extends from the first photo sensor between the first pair of sidewalls of the trench isolation layer to the second photo sensor. The shared floating diffusion region is between the first pair of sidewalls of the trench isolation layer.

[0116] In an embodiment of the present invention, the opening is further defined by an upper surface of the trench isolation layer.

[0117] In an embodiment of the present invention, the first semiconductor substrate also includes: a block region having a first doping type; and a first photodiode region having a second doping type different from the first doping type, wherein the block region and the first photodiode region form the first photosensor, wherein the shared floating diffusion region has the second doping type, wherein the first semiconductor substrate also includes an implant region having the first doping type, and wherein the implant region is between the first pair of side walls of the trench isolation layer and below the shared floating diffusion region.

[0118] In an embodiment of the present invention, the integrated chip further includes: a third photo sensor and a fourth photo sensor in the first semiconductor substrate; and a third transmission gate and a fourth transmission gate respectively on the third photo sensor and the fourth photo sensor, wherein the trench isolation layer laterally surrounds the third photo sensor and the fourth photo sensor, wherein the trench isolation layer extends between the third photo sensor and the fourth photo sensor, between the third photo sensor and the first photo sensor, and between the fourth photo sensor and the second photo sensor, wherein the second pair of sidewalls of the trench isolation layer further define The invention relates to a semiconductor device for transmitting the optical signal to a photosensitive element of the optical signal transmitted through the optical signal processing unit (I) and a semiconductor device for transmitting the optical signal to the photosensitive element (I) through the optical signal processing unit (I) and a semiconductor device for transmitting the optical signal to the photosensitive element (I) through the optical signal processing unit (I) at least one of the optical signal and the semiconductor device for transmitting the optical signal to the photosensitive element (I) are preferably arranged in a first position, a second position, a third position, and a fourth position.

[0119] In an embodiment of the present invention, the integrated chip further includes: a color filter and a microlens, which are directly below the first light sensor and the second light sensor.

[0120] In another embodiment, the utility model relates to a method for forming an integrated chip. The method includes forming a first photo sensor and a second photo sensor in the first semiconductor substrate along a first side of the first semiconductor substrate. A first transmission gate and a second transmission gate are formed on the first photo sensor and the second photo sensor, respectively. A floating diffusion region is formed in the first semiconductor substrate between the first photo sensor and the second photo sensor. A first metal interconnect is formed on the first transmission gate and coupled to the first transmission gate. A second metal interconnect is formed on the second transmission gate and coupled to the second transmission gate. A third metal interconnect is formed on the floating diffusion region and coupled to the floating diffusion region. A trench isolation layer is formed around the first photo sensor and the second photo sensor and extends between the first photo sensor and the second photo sensor. The trench isolation layer has an opening therein, the opening being between the first photo sensor and the second photo sensor. The first semiconductor substrate extends from the first photo sensor to the second photo sensor through the opening. A first pixel transistor is formed along the first side of the second semiconductor substrate. A fourth metal interconnect is formed on the first pixel transistor and coupled to the first pixel transistor. The second semiconductor substrate is bonded on the first side of the first semiconductor substrate so that the third metal interconnect is coupled to the fourth metal interconnect.

[0121] In another embodiment, the utility model relates to a method for forming an integrated chip, characterized in that it includes: forming a first light sensor and a second light sensor in the first semiconductor substrate along a first side of the first semiconductor substrate; forming a first transmission gate and a second transmission gate on the first light sensor and the second light sensor respectively; forming a floating diffusion region in the first semiconductor substrate between the first light sensor and the second light sensor; forming a first metal interconnection on the first transmission gate and coupled to the first transmission gate, forming a second metal interconnection on the second transmission gate and coupled to the second transmission gate, and forming a third metal interconnection on the floating diffusion region and coupled to the a floating diffusion region; forming a trench isolation layer surrounding the first light sensor and the second light sensor and extending between the first light sensor and the second light sensor, the trench isolation layer having an opening therein, the opening being between the first light sensor and the second light sensor, the first semiconductor substrate extending from the first light sensor to the second light sensor through the opening; forming a first pixel transistor along a first side of the second semiconductor substrate; forming a fourth metal interconnection over the first pixel transistor and coupled to the first pixel transistor; and bonding the second semiconductor substrate over the first side of the first semiconductor substrate so that the third metal interconnection is coupled to the fourth metal interconnection.

[0122] In an embodiment of the present invention, the floating diffusion region is in the opening in the trench isolation layer.

[0123] In an embodiment of the present invention, forming the trench isolation layer includes etching a second side of the first semiconductor substrate opposite to the first side to form a trench in the first semiconductor substrate and depositing the trench isolation layer in the trench.

[0124] In an embodiment of the present invention, the method for forming an integrated chip also includes: forming a color filter and a microlens directly above the first light sensor and the second light sensor; and bonding a third semiconductor substrate to a second side of the second semiconductor substrate, the second side being opposite to the first side of the second semiconductor substrate.

[0125] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, characterized in that: include: A first semiconductor substrate including a doped region; a first light sensor and a second light sensor, the second light sensor being laterally spaced apart from the first light sensor in the first semiconductor substrate; a trench isolation layer at least partially surrounding the first photo sensor and the second photo sensor and extending between the first photo sensor and the second photo sensor, the trench isolation layer having a first pair of sidewalls between the first photo sensor and the second photo sensor, wherein the first semiconductor substrate extends from the first photo sensor between the first pair of sidewalls of the trench isolation layer to the second photo sensor, and wherein the doped region is between the first pair of sidewalls of the trench isolation layer; A first gate and a second gate, respectively on the first light sensor and the second light sensor, the first light sensor and the first gate partially forming a first transistor, and the second light sensor and the second gate partially forming a second transistor; A first metal interconnect and a second metal interconnect are respectively on the first gate and the second gate, the first metal interconnect is coupled to the first gate, and the second metal interconnect is coupled to the second gate; a second semiconductor substrate over the first gate and the second gate and spaced apart from the first gate and the second gate; as well as A third transistor is provided along the second semiconductor substrate, wherein the third transistor is coupled to the first transistor.

2. The integrated chip according to claim 1, characterized in that: The first semiconductor substrate further comprises: a bulk region having a first doping type; a first photodiode region having a second doping type different from the first doping type, and A first floating diffusion region has the second doping type, wherein the bulk region and the first photodiode region form the first photosensor, wherein the first floating diffusion region further forms the first transistor, and wherein the doping region has the first doping type.

3. The integrated chip according to claim 1, characterized in that: The first metal interconnect is isolated from the second metal interconnect and the second gate.

4. The integrated chip according to claim 1, characterized in that: Also includes: A color filter and a microlens are below both the first light sensor and the second light sensor.

5. The integrated chip according to claim 1, characterized in that: The first semiconductor substrate further comprises: a bulk region having a first doping type; and A first photodiode region having a second doping type different from the first doping type, wherein the bulk region and the first photodiode region form the first photosensor, wherein the doping region is a floating diffusion region having the second doping type, wherein the floating diffusion region further forms the first transistor and the second transistor, and wherein the third transistor is coupled to the floating diffusion region.

6. The integrated chip according to claim 1, characterized in that: Also includes: a third semiconductor substrate on the second semiconductor substrate and spaced apart from the second semiconductor substrate; as well as A fourth transistor is arranged along the third semiconductor substrate and coupled to the third transistor.

7. An integrated chip, characterized in that: include: A first semiconductor substrate including a shared floating diffusion region; a first light sensor and a second light sensor, in the first semiconductor substrate, the first light sensor and the second light sensor being on opposite sides of the shared floating diffusion region; A first transfer gate and a second transfer gate are respectively above the first light sensor and the second light sensor, the first light sensor, the shared floating diffusion area and the first transfer gate partially forming a first transfer transistor, and the second light sensor, the shared floating diffusion area and the second transfer gate partially forming a second transfer transistor; A first metal interconnect and a second metal interconnect are respectively on the first transmission gate and the second transmission gate, the first metal interconnect is coupled to the first transmission gate, and the second metal interconnect is coupled to the second transmission gate; a second semiconductor substrate over and spaced apart from the first and second pass transistors; a first pixel transistor, along the second semiconductor substrate; a third metal interconnection between the first pixel transistor and the shared floating diffusion region, the third metal interconnection being coupled to the first pixel transistor and the shared floating diffusion region; as well as a trench isolation layer laterally surrounding the first light sensor and the second light sensor, the trench isolation layer extending between the first light sensor and the second light sensor, wherein a first pair of sidewalls of the trench isolation layer define an opening in the trench isolation layer and between the first light sensor and the second light sensor, The first semiconductor substrate extends from the first photosensor to the second photosensor between the first pair of sidewalls of the trench isolation layer, and the shared floating diffusion region is between the first pair of sidewalls of the trench isolation layer.

8. The integrated chip according to claim 7, characterized in that: The opening is further defined by an upper surface of the trench isolation layer.

9. The integrated chip according to claim 7, characterized in that: The first semiconductor substrate further comprises: a bulk region having a first doping type; and a first photodiode region having a second doping type different from the first doping type, wherein the bulk region and the first photodiode region form the first photosensor, wherein the shared floating diffusion region has the second doping type, The first semiconductor substrate further includes an implantation region having the first doping type, and the implantation region is between the first pair of sidewalls of the trench isolation layer and below the shared floating diffusion region.

10. The integrated chip according to claim 7, characterized in that: Also includes: a third light sensor and a fourth light sensor, in the first semiconductor substrate; as well as A third transmission gate and a fourth transmission gate are respectively on the third light sensor and the fourth light sensor, wherein the trench isolation layer laterally surrounds the third photosensor and the fourth photosensor, wherein the trench isolation layer extends between the third photosensor and the fourth photosensor, between the third photosensor and the first photosensor, and between the fourth photosensor and the second photosensor, wherein a second pair of sidewalls of the trench isolation layer further defines the opening in the trench isolation layer, wherein the first semiconductor substrate extends continuously from the first photosensor between the first pair of sidewalls and the second pair of sidewalls of the trench isolation layer to the second photosensor, the third photosensor, and the fourth photosensor, and wherein the shared floating diffusion region is disposed between the second pair of sidewalls of the trench isolation layer, The third light sensor, the shared floating diffusion region, and the third transfer gate partially form a third transfer transistor, and the fourth light sensor, the shared floating diffusion region, and the fourth transfer gate partially form a fourth transfer transistor.

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