Amplifier with multiple outputs

Abstract

The utility model provides an amplifier with multiple output ends, which comprises an amplifying circuit and a radio frequency switch switching circuit, and is characterized in that the amplifying circuit is configured to be a low-noise amplifying circuit with a cascode structure so as to receive a radio frequency input signal and provide the amplified radio frequency signal to the radio frequency switch switching circuit; the radio frequency switch switching circuit includes a center tap inductor and is configured to provide the amplified radio frequency signal to a plurality of output terminals of the amplifier through a center tap of the center tap inductor.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and more particularly, to an amplifier with multiple output terminals. Background Art

[0002] In the RF receiving link, the low noise amplifier (LNA) is at the forefront of the entire link, and its performance directly affects the performance of the entire receiver. In mobile terminals, such as smartphones, the receiving link may have an application scenario of single-end input and multiple-end output, and the multiple-end outputs may be turned on at the same time (for example, dual-open mode). In this case, there are also high requirements for the isolation between the output ports of the multi-end output. Therefore, the traditional output switch to achieve multi-port output is no longer applicable to this situation because of the extremely poor isolation of the output ports. In addition, the impedance of the traditional solution in the dual-open mode becomes half of the original, resulting in poor output impedance matching and reduced gain. Therefore, a low-noise amplifier with good output impedance matching and gain performance and capable of maintaining high isolation between multiple output ports is needed. Utility Model Content

[0003] An embodiment of the present disclosure provides an amplifier with multiple output terminals, including an amplifier circuit and a radio frequency switch switching circuit, characterized in that the amplifier circuit is configured as a low-noise amplifier circuit with a common source and common gate structure to receive a radio frequency input signal and provide the amplified radio frequency signal to the radio frequency switch switching circuit; the radio frequency switch switching circuit includes an intermediate tap inductor, and is configured to provide the amplified radio frequency signal to multiple output terminals of the amplifier through an intermediate tap of the intermediate tap inductor.

[0004] According to an embodiment of the present disclosure, the multiple output terminals include a first output terminal and a second output terminal, the amplifier circuit includes a first amplifier transistor and a second amplifier transistor connected in series, and is configured to amplify the RF input signal input from the first input terminal of the amplifier and output the amplified RF signal to the RF switch switching circuit; and the RF switch switching circuit includes a first selection transistor to a sixth selection transistor, and is configured to select one or more of the first selection transistor to the sixth selection transistor based on a selection signal input from a selection signal input terminal, so that the signal output from the amplifier circuit is output through at least one of the first output terminal and the second output terminal.

[0005] According to an embodiment of the present disclosure, the first input terminal of the amplifier is connected to the gate of the first amplifying transistor, the first electrode of the second amplifying transistor is connected to the RF switch switching circuit, and the second electrode of the first amplifying transistor is connected to the ground voltage; and wherein the RF switch switching circuit also includes a matching resistor, wherein the middle tap of the middle tap inductor is connected to the first electrode of the second amplifying transistor, the first end and the second end of the middle tap inductor are respectively connected to the first output terminal and the second output terminal through the first selection transistor and the second selection transistor, the third selection transistor is connected between the middle tap and the first end of the middle tap inductor, the fourth selection transistor is connected between the middle tap and the second end of the middle tap inductor, and the fifth selection transistor, the matching resistor and the sixth selection transistor are sequentially connected in series between the first end and the second end of the middle tap inductor.

[0006] According to an embodiment of the present disclosure, the selection signal input terminal includes a first selection signal input terminal and a second selection signal input terminal, and the RF switch switching circuit also includes a first inverter, a second inverter, a first AND gate, a second AND gate and a third AND gate, wherein the first selection signal input terminal is connected to the gate of the first selection transistor, the second selection signal input terminal is connected to the gate of the second selection transistor, the first selection signal input terminal is also connected to the first input terminal of the first AND gate, the second selection signal input terminal is also connected to the second input terminal of the first AND gate through the first inverter, and the output terminal of the first AND gate is connected to the gate of the third selection transistor, the first selection signal input terminal is also connected to the first input terminal of the second AND gate through the second inverter, the second selection signal input terminal is also connected to the second input terminal of the second AND gate, and the output terminal of the second AND gate is connected to the gate of the fourth selection transistor, and the first selection signal input terminal is also connected to the first input terminal of the third AND gate, the second selection signal input terminal is also connected to the second input terminal of the third AND gate, and the output terminal of the third AND gate is connected to the gates of the fifth and sixth selection transistors.

[0007] According to an embodiment of the present disclosure, the amplifier circuit also includes a first capacitor and a second capacitor, wherein the first capacitor is arranged between the first input terminal and the gate of the first amplifier transistor; and the second capacitor is arranged between the first electrode of the second amplifier transistor and the middle tap of the middle tap inductor.

[0008] According to an embodiment of the present disclosure, the amplifying circuit further includes a first resistor and a first bias voltage input terminal, wherein the first bias voltage input terminal is connected to the gate of the first amplifying transistor through the first resistor.

[0009] According to an embodiment of the present disclosure, the amplifying circuit further includes a second bias voltage input terminal, wherein the second bias voltage input terminal is connected to the gate of the second amplifying transistor.

[0010] According to an embodiment of the present disclosure, the amplifier circuit further includes a first inductor and a second inductor, wherein the first inductor is arranged between the second electrode of the first amplifier transistor and the ground voltage; and the second inductor is arranged between the first electrode of the second amplifier transistor and the power supply voltage.

[0011] According to an embodiment of the present disclosure, each of the first to second amplifying transistors and the first to sixth selection transistors is an N-type transistor, the first pole is the drain of the N-type transistor, and the second pole is the source of the N-type transistor.

[0012] According to an embodiment of the present disclosure, a first electrode of the first amplifying transistor is connected to a second electrode of the second amplifying transistor.

[0013] According to an embodiment of the present disclosure, the matching resistor is configured to provide output impedance matching when the signal output from the amplifying circuit is output simultaneously through two of the first output terminal and the second output terminal.

[0014] According to an embodiment of the present disclosure, the matching resistor is an adjustable resistor with adjustable resistance.

[0015] The present disclosure proposes a low noise amplifier that can achieve multi-port output, has two working modes, single-pass and dual-pass, and can achieve good output impedance matching and gain in the dual-pass mode, and maintain high isolation performance between multiple output ports. In addition, the solution of the present disclosure uses tapped inductors and resistors, switches, etc. to achieve single-pass and / or dual-pass mode output, without the need to switch the inductor, nor to meet the matching requirements by switching the inductor or inductor value. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of a low noise amplifier 100 supporting multiple outputs according to an embodiment of the present disclosure is shown;

[0018] Figure 2 A schematic diagram of a radio frequency path of the low noise amplifier 100 according to an embodiment of the present disclosure when the first output terminal is turned on;

[0019] Figure 3shows an example result of a performance parameter simulation of the low noise amplifier 100 according to an embodiment of the present disclosure when the first output terminal is turned on;

[0020] Figure 4 A schematic diagram of a radio frequency path of the low noise amplifier 100 according to an embodiment of the present disclosure when the second output terminal is turned on;

[0021] Figure 5 shows an example result of a performance parameter simulation of the low noise amplifier 100 according to an embodiment of the present disclosure when the second output terminal is turned on;

[0022] Figure 6 A schematic diagram of a radio frequency path of the low noise amplifier 100 according to an embodiment of the present disclosure when the first output terminal and the second output terminal are simultaneously turned on;

[0023] Figure 7 shows an example result of a performance parameter simulation of the low noise amplifier 100 according to an embodiment of the present disclosure when the first output terminal and the second output terminal are simultaneously turned on;

[0024] Figure 8 An example simulation result of the isolation between the first output terminal and the second output terminal of the low noise amplifier 100 in a dual-pass working mode according to an embodiment of the present disclosure is shown;

[0025] Figure 9a A schematic structural diagram of a low noise amplifier 900 according to an embodiment of the present disclosure is shown;

[0026] Figure 9b shows a schematic circuit diagram of a low noise amplifier 900 according to an embodiment of the present disclosure;

[0027] Fig.10 A schematic diagram of a radio frequency path of a low noise amplifier 900 according to an embodiment of the present disclosure when the first output terminal is turned on;

[0028] Fig.11 shows an example result of a performance parameter simulation of the low noise amplifier 900 according to an embodiment of the present disclosure when the first output terminal is turned on;

[0029] Fig.12 A schematic diagram of a radio frequency path of the low noise amplifier 900 according to an embodiment of the present disclosure when the second output terminal is turned on;

[0030] Fig.13 shows an example result of a performance parameter simulation of the low noise amplifier 900 according to an embodiment of the present disclosure when the second output terminal is turned on;

[0031] Fig.14A schematic diagram of a radio frequency path of a low noise amplifier 900 according to an embodiment of the present disclosure when the first output terminal and the second output terminal are simultaneously turned on;

[0032] Fig.15 shows an example result of a performance parameter simulation of the low noise amplifier 900 according to an embodiment of the present disclosure when the first output terminal and the second output terminal are simultaneously turned on; and

[0033] Fig.16 An example simulation result of the isolation between the first output terminal and the second output terminal of the low noise amplifier 900 in the dual-pass working mode according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] Before proceeding to the following detailed description, it may be advantageous to set forth the definitions of certain words and phrases used throughout this patent document. The terms "coupling", "connection" and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmission", "reception" and "communication" and their derivatives cover direct and indirect communication. The terms "include" and "comprise" and their derivatives refer to including but not limited to. The term "or" is inclusive, meaning and / or. The phrases "associated with...", "corresponding to..." and their derivatives refer to including, including within, interconnecting, including, including within, connecting or connecting with, coupling or coupling with, communicating with, cooperating, interweaving, parallel, close to, binding or binding with, having, having attributes, having a relationship or having a relationship with, etc. The term "controller" refers to any device, system or part thereof that controls at least one operation. Such a controller can be implemented with hardware, or a combination of hardware and software and / or firmware. The functions associated with any particular controller can be centralized or distributed, whether local or remote. The phrase "at least one of", when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be required. For example, "at least one of A, B, C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0035] Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0036] In this patent document, the application combination of modules and the division level of submodules are only used for illustration. Without departing from the scope of the present disclosure, the application combination of modules and the division level of submodules can have different modes. The embodiments of the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey exemplary implementation methods to those skilled in the art. The embodiments of the present disclosure can be combined to form additional embodiments.

[0037] The present disclosure will be described in detail below with reference to exemplary embodiments of the present disclosure. However, the present disclosure is not limited to the embodiments described herein, and it can be implemented in many different forms. The described embodiments are only used to make the present disclosure thorough and complete, and to fully convey the concept of the present disclosure to those skilled in the art. The features of the various embodiments described can be combined or replaced with each other, unless explicitly excluded or should be excluded according to the context.

[0038] In the present disclosure, the singular form of an element may refer to its plural form, and the plural form of an element may also refer to its singular form. For example, "element" or "an element" may refer to each other with "at least one element", "one or more elements" or "a plurality of elements" etc.

[0039] In the present disclosure, the RF path may refer to a circuit path in which a RF signal is input from one or more input terminals of an LNA, is amplified by the LNA, and then output through one or more output terminals of the LNA.

[0040] In the present disclosure, the ground voltage may also be any other low voltage or logic low voltage suitable for normal operation of circuits and devices, and the power supply voltage may also be any other high voltage or logic high voltage suitable for normal operation of circuits and devices.

[0041] In the present disclosure, in the case of an NMOS transistor (or an N-type transistor), the first electrode may be the drain of the transistor, and the second electrode may be the source of the transistor. In the case of a PMOS transistor (or a P-type transistor), the first electrode may be the source of the transistor, and the second electrode may be the drain of the transistor. In the drawings of the present disclosure, N-type transistors are used as examples for exemplary description. However, it should be understood that in other embodiments of the present disclosure, depending on the specific implementation, one or more of the amplifying transistor and the gating transistor may also be a P-type transistor, which is not limited by the present disclosure.

[0042] In the present disclosure, only a low noise amplifier (LNA) is used as an example for exemplary description. It should be understood that the technical solution of the amplifier according to the embodiment of the present disclosure can also be applied to any other type of amplifier circuit supporting or having multiple output terminals. In addition, for ease of description, in the embodiment of the present disclosure, only two output terminals are used as examples for description. It should be understood that the amplifier supporting multiple output terminals of the present disclosure can also include any other number of multiple output terminals.

[0043] In the present disclosure, a mode in which two output terminals are simultaneously selected or turned on may be referred to as a dual-on mode or a dual-pass (working) mode, and a mode in which only one of the two output terminals is selected or turned on may be referred to as a single-on mode or a single-pass (working) mode.

[0044] In the present disclosure, a gate transistor may also be referred to as a switching transistor or a switch, etc.

[0045] Figure 1 A schematic diagram of a low noise amplifier 100 supporting multiple outputs according to an embodiment of the present disclosure is shown.

[0046] like Figure 1 As shown, the low noise amplifier 100 can add two switches (e.g., switch transistors S1 and S2) at the output end of a general low noise amplifier (e.g., cascode LNA) to select the RF output end (e.g., rfout1 and rfout2), thereby selecting the signal amplified by the amplifier circuit from at least one of rfout1 and rfout2. For example, the selection can be made by connecting the gates of the switch transistors S1 and S2 respectively to the gates to perform the selection. Figure 1 In the circuit structure shown, M1 is sometimes referred to as an amplifier transistor, and M2 is sometimes referred to as a cascode transistor. In the present disclosure, for ease of description, the amplifier transistor and the cascode transistor in the low noise amplifier are collectively referred to as amplifier transistors unless otherwise specifically distinguished.

[0047] For the scheme of the low noise amplifier 100, when Vs_out1 is high and Vs_out2 is low, the switch transistor S1 is turned on and the switch transistor S2 is turned off, so that the RF path is from rfin1 to rfout1 (eg Figure 2 ). Accordingly, Figure 3 FIG. 4 shows an example result of a simulation of a performance parameter (eg, scattering parameter (S parameter)) of the low noise amplifier 100 in this state. Figure 3It can be seen that in this state, the gain (e.g., S21 parameter) of the low noise amplifier 100 corresponding to the first output terminal rfout1 is about 20.3801 dB, and the output matching (e.g., S22 parameter) is about -24.9927 dB. In the drawings related to the simulation results of the present disclosure, it is assumed that the left part of the figure is the simulation result corresponding to the first output terminal rfout1, and the right part is the simulation result corresponding to the second output terminal rfout2.

[0048] When Vs_out1 is low and Vs_out2 is high, the switch transistor S1 is turned off and the switch transistor S2 is turned on, so that the RF path is from rfin1 to rfout2 (such as Figure 4 ). Accordingly, Figure 5 FIG. 4 shows an example result of a simulation of a performance parameter (eg, S parameter) of the low noise amplifier 100 in this state. Figure 5 It can be seen that, in this state, the gain (eg, S31 parameter) of the low noise amplifier 100 corresponding to the second output terminal rfout2 is approximately 20.3801 dB, and the output matching (eg, S33 parameter) is approximately -24.9922 dB.

[0049] When Vs_out1 is high and Vs_out2 is high, both switch transistors S1 and S2 are turned on, so that the RF path is rfin1 to both rfout1 and rfout2, that is, the dual-on mode (such as Figure 6 ). Accordingly, Figure 7 FIG. 4 shows an example result of a simulation of a performance parameter (eg, S parameter) of the low noise amplifier 100 in this state. Figure 7 It can be seen that in this state, the gain of the low noise amplifier 100 corresponding to the first output terminal rfout1 (for example, the S21 parameter) is approximately 16.2752dB, and the output matching (for example, the S22 parameter) is approximately -7.39916dB; the gain of the low noise amplifier 100 corresponding to the second output terminal rfout2 (for example, the S31 parameter) is approximately 16.3797dB, and the output matching (for example, the S33 parameter) is approximately -7.68878dB.

[0050] In the dual-pass mode, the load is doubled compared to the single-channel output mode (for example, 50 ohm in single-channel mode becomes 25 ohm in dual-channel mode), so the output is matched (for example, Figure 7 The S22 and S33 shown are very poor, which will also lead to a deterioration in gain.

[0051] In addition, the isolation between the two output ports is also a very important performance indicator. For example, Figure 8FIG. 4 shows an example simulation result of the isolation between the first output terminal rfout1 and the second output terminal rfout2 of the low noise amplifier 100 in the dual-pass working mode according to an embodiment of the present disclosure. Figure 8 As shown, the isolation between the first output terminal rfout1 and the second output terminal rfout2 (eg, parameter S32) is only about 4 dB (expressed in absolute value). However, in a common application scenario, the isolation should be at least 15 dB.

[0052] In order to solve the problem of poor isolation and poor matching and gain performance in the above solution in the dual-pass working mode, the present disclosure further proposes a solution of using a tapped inductor (e.g., a middle tapped inductor) to achieve single-ended to differential conversion, thereby achieving multiple outputs, such as a low noise amplifier 900. The structural schematic diagram and circuit diagram of this solution are shown in FIG. Figure 9a and 9b As shown, the output of the amplifier circuit 910 in the low noise amplifier 900 can be connected to the middle tap of the tapped inductor D1 included in the RF switch switching circuit 920, and the other two ports of the inductor D1 are connected to rfout1 and rfout2 through the switching transistors. In addition, a matching resistor R2 is further added to the RF switch switching circuit 920 to adjust the output impedance matching, thereby achieving good output impedance matching and high RF gain, and there is also a high isolation between rfout1 and rfout2.

[0053] In this article, the circuit structure according to the embodiment of the present disclosure will be exemplified by using the intermediate tap inductor. It should be understood that in the scenario with multiple output terminals or multiple output channels, an inductor with multiple taps can also be used to achieve corresponding multi-channel output, and the present disclosure does not limit it.

[0054] Specifically, Figure 9a FIG. 1 shows a schematic diagram of the structure of a low noise amplifier 900 according to an embodiment of the present disclosure. Figure 9b FIG. 4 is a schematic circuit diagram of a low noise amplifier 900 according to an embodiment of the present disclosure.

[0055] like Figure 9a As shown, the low noise amplifier (LNA) 900 according to the embodiment of the present disclosure may have multiple output terminals. In the present disclosure, two output terminals are used as an example for exemplary description. For example, the multiple output terminals may include a first output terminal rfout1 and a second output terminal rfout2. In addition, the LNA 900 may also include one or more input terminals. In this document, one input terminal is used as an example for exemplary description, such as the first input terminal rfin1. In the implementation with multiple input terminals and / or multiple output terminals, the LNA 900 may be configured as follows: Figure 9bThe amplifier circuit shown in the figure can be duplicated and expanded in corresponding parts. In addition, as mentioned above, the LNA 900 can also include an amplifier circuit 910 and a radio frequency switch circuit 920 .

[0056] The amplifier circuit 910 may be a core circuit for the LNA 900 to implement a signal amplification function. Figure 9b As shown, the amplifier circuit 910 may include a first amplifier transistor M1 and a second amplifier transistor M2 connected in series, and may be configured to amplify a signal (e.g., an RF input signal) input from the first input terminal rfin1 of the LAN 900, and output the amplified RF signal to the RF switch switching circuit 920. In addition, the amplifier circuit 910 may also include an input terminal DC blocking capacitor C1, an output terminal capacitor C2, inductors L1, L2, a bias resistor R1, etc. It should be understood that Figure 9b The circuit shown is merely an example, and depending on the specific configuration of the circuit, one or more of the input DC blocking capacitor C1 (which may be referred to as the first capacitor in this article), the output capacitor C2 (which may be referred to as the second capacitor in this article), the inductors L1, L2, the bias resistor R1, etc. may be omitted from the amplifier circuit 910, or the amplifier circuit 910 may include other numbers of these devices.

[0057] The RF switch switching circuit 920 may include first to sixth selection transistors S1-S6, and may be a circuit configured to select one or more of the first to sixth selection transistors S1-S6 based on a selection signal input from a selection signal input terminal (for example, a first selection signal input terminal Vs_out1 and a second selection signal input terminal Vs_out2, etc.) so that the amplified signal output from the amplifier circuit 910 is output through at least one of the first output terminal rfout1 and the second output terminal rfout2.

[0058] In some embodiments, the first input terminal rfin1 of the LNA 900 is connected to the gate of the first amplifying transistor M1, the first electrode of the second amplifying transistor M2 is connected to the input terminal of the RF switch switching circuit 920 (e.g., the middle tap of the middle tap inductor D1 included therein), and the second electrode of the first amplifying transistor M1 is connected to the ground voltage (e.g., GND).

[0059] In some embodiments, as described above, the RF switch switching circuit 900 further includes an intermediate tap inductor D1 and may further include a matching resistor R2.

[0060] In some embodiments, the middle tap of the middle tap inductor D1 is connected to the first electrode of the second amplifying transistor M2, and the first and second ends of the middle tap inductor D1 are connected to the first output end rfout1 and the second output end rfout2 through the first selection transistor S1 and the second selection transistor S2, respectively. The third selection transistor S3 is connected between the middle tap and the first end of the middle tap inductor D1, and the fourth selection transistor S4 is connected between the middle tap and the second end of the middle tap inductor D1. The fifth selection transistor S5, the matching resistor R2, and the sixth selection transistor S6 can be connected in series between the first and second ends of the middle tap inductor D1, that is, between the second electrodes of the first selection transistor S1 and the second selection transistor S2. By setting the middle tap inductor D1, the LNA 900 can have a high isolation between the first output end rfout1 and the second output end rfout2 in the dual-pass mode.

[0061] In some embodiments, the selection signal input terminal may include a first selection signal input terminal Vs_out1 and a second selection signal input terminal Vs_out2. In addition, the RF switch switching circuit 900 may further include a first inverter INV1, a second inverter INV2, a first AND gate AND2_1, a second AND gate AND2_2, and a third AND gate AND2_3.

[0062] In some embodiments, the first selection signal input terminal Vs_out1 is connected to the gate of the first selection transistor S1, and the second selection signal input terminal Vs_out2 is connected to the gate of the second selection transistor S2. The first selection signal input terminal Vs_out1 is also connected to the first input terminal of the first AND gate AND2_1, the second selection signal input terminal Vs_out2 is also connected to the second input terminal of the first AND gate AND2_1 through the first inverter INV1, and the output terminal of the first AND gate AND2_1 is connected to the gate of the third selection transistor S3.

[0063] In some embodiments, the first selection signal input terminal Vs_out1 is also connected to the first input terminal of the second AND gate AND2_2 through the second inverter INV2, the second selection signal input terminal Vs_out2 is also connected to the second input terminal of the second AND gate AND2_2, and the output terminal of the second AND gate AND2_2 is connected to the gate of the fourth selection transistor S4.

[0064] In some embodiments, the first selection signal input terminal Vs_out1 is also connected to the first input terminal of the third AND gate AND2_3, the second selection signal input terminal Vs_out2 is also connected to the second input terminal of the third AND gate AND2_3, and the output terminal of the third AND gate AND2_3 is connected to the gates of the fifth selection transistor S5 and the sixth selection transistor S6.

[0065] The truth table of the logic control circuit formed by the above configuration of the first inverter INV1, the second inverter INV2, the first AND gate AND2_1, the second AND gate AND2_2 and the third AND gate AND2_3 is shown in Table 1 below.

[0066] [Table 1]

[0067]

[0068] Thus, the gate voltages of the first to sixth gating transistors can be controlled by the two gating signals input from Vs_out1 and Vs_out2 via the logic control circuit as described above, thereby controlling the on or off (or gating) of one or more of the first to sixth gating transistors. It should be understood that the logic control circuit can also be set in any other suitable configuration, which is not limited herein.

[0069] In some embodiments, the amplifier circuit 910 may further include a first capacitor C1 and a second capacitor C2. The first capacitor C1 may be disposed between the first input terminal rfin1 and the gate of the first amplifier transistor M1; and the second capacitor C2 may be disposed between the first electrode (e.g., drain) of the second amplifier transistor M2 and the middle tap of the middle tap inductor D1.

[0070] In some embodiments, the amplifier circuit 910 may further include a first resistor R1 and a first bias voltage input terminal vb1. The first bias voltage input terminal vb1 may be connected to the gate of the first amplifier transistor M1 through the first resistor R1, thereby providing the first amplifier transistor M1 with a suitable bias voltage required for normal operation of the transistor or circuit.

[0071] In some embodiments, the amplifier circuit 910 may further include a second bias voltage input terminal vb2 that may be connected to the gate of the second amplifier transistor M2 to provide the second amplifier transistor M2 with a suitable bias voltage required for normal operation of the transistor or circuit.

[0072] In some embodiments, the amplifier circuit 910 may further include a first inductor L1 and a second inductor L2. The first inductor L1 may be disposed between the second electrode of the first amplifier transistor M1 and the ground voltage; and the second inductor L2 may be disposed between the first electrode of the second amplifier transistor M2 and a power supply voltage (eg, VDD).

[0073] In some embodiments, each of the first to second amplifying transistors and the first to sixth selection transistors may be an N-type transistor, and the first electrode may be a drain of the N-type transistor, and the second electrode may be a source of the N-type transistor.

[0074] In some embodiments, a first electrode of the first amplifying transistor M1 is connected to a second electrode of the second amplifying transistor M2 .

[0075] In some embodiments, the matching resistor R2 is configured to provide output impedance matching when the signal output from the amplifier circuit 910 is output simultaneously through two of the first output terminal rfout1 and the second output terminal rfout2. For example, as shown in Table 1 above, when Vs_out1 and Vs_out2 are both high, S5 and S6 are turned on, so that the matching resistor R2 can operate normally. The matching resistor R2 can have a preset resistance value that can provide suitable output impedance matching. For example, the matching resistor R2 can have a resistance value calculated according to the load of the LNA 900. In other examples, the matching resistor R2 can also be an adjustable resistor with an adjustable resistance value. In this case, the resistance value of the matching resistor R2 can be adjusted based on different loads of the LNA 900, so that suitable output impedance matching can be provided under different load conditions.

[0076] In such Figure 9b In the example shown, when Vs_out1 is high and Vs_out2 is low, S1 and S3 are turned on, S2, S4, S5, and S6 are turned off, and the RF path is from rfin1 to rfout1 (such as Fig.10 ). Accordingly, Fig.11 FIG. 4 shows example results of simulation of performance parameters (eg, scattering parameters (S parameters)) of the LNA 900 in this state. Fig.11 It can be seen that, in this state, the gain (eg, S21 parameter) of the LNA 900 corresponding to the first output terminal rfout1 is approximately 20.5117 dB, and the output matching (eg, S22 parameter) is approximately -21.3597 dB.

[0077] When Vs_out1 is low and Vs_out2 is high, S2 and S4 are turned on, S1, S3, S5, and S6 are turned off, and the RF path is from rfin to rfout2 (such as Fig.12 ). Accordingly, Fig.13 FIG. 4 shows example results of simulation of performance parameters (eg, scattering parameters (S parameters)) of the LNA 900 in this state. Fig.13 It can be seen that, in this state, the gain (eg, S31 parameter) of the LNA 900 corresponding to the second output terminal rfout2 is approximately 20.5111 dB, and the output matching (eg, S33 parameter) is approximately -21.3841 dB.

[0078] When Vs_out1 is high and Vs_out2 is high, the gate transistors S1, S2, S5, and S6 are turned on, S2 and S4 are turned off, and the RF path is rfin to both rfout1 and rfout2 (such as Fig.14 As shown), that is, dual-pass working mode. Fig.15 FIG. 4 shows an example result of a simulation of the performance parameters (eg, scattering parameters (S parameters)) of the LNA 900 in this state. Fig.15 It can be seen that in this state, the gain of LNA 900 corresponding to the first output terminal rfout1 (for example, S21 parameter) is approximately 17.1829 dB, and the output matching (for example, S22 parameter) is approximately -10.5496 dB; the gain of LNA 900 corresponding to the second output terminal rfout2 (for example, S31 parameter) is approximately 16.9565 dB, and the output matching (for example, S33 parameter) is approximately -10.0399 dB.

[0079] also, Fig.16 FIG. 4 shows an example simulation result of the isolation between the first output terminal rfout1 and the second output terminal rfout2 of the LNA 900 in the dual-pass working mode according to an embodiment of the present disclosure. Fig.16 As shown, at this time, the isolation between the first output terminal rfout1 and the second output terminal rfout2 (for example, parameter S32 or S23) is about 20.5136 dB (expressed in absolute value).

[0080] Next, Table 2 shows a performance comparison of the LNA 100 and the LNA 900 according to the embodiment of the present disclosure obtained through simulation and experiments.

[0081] [Table 2]

[0082]

[0083] As can be seen from Table 2 above, the LNA 900 according to the embodiment of the present disclosure has comparable performance to the LNA 100 in the single-pass mode, and has better matching and gain, as well as higher isolation in the dual-pass mode.

[0084] It should be understood that the low noise amplifier 100 or the low noise amplifier 900 described above is merely illustrative, and the amplifier according to the embodiment of the present disclosure may also include one or more other devices other than those included in the low noise amplifier 100 or the low noise amplifier 900, or omit or replace any one or more of the devices, which is not limited herein. In addition, the embodiment of the present disclosure may also include any implementation method or operation method of the low noise amplifier 100 or the low noise amplifier 900 described above, and any circuit system including the low noise amplifier 100 or the low noise amplifier 900.

[0085] The hardware computing device described in the present disclosure may be implemented in its entirety or in parts thereof through various suitable hardware means, including but not limited to FPGA, ASIC, SoC, discrete gate or transistor logic, discrete hardware components, or any combination thereof.

[0086] The block diagrams of circuits, devices, apparatuses, equipment, and systems involved in the present disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these circuits, devices, apparatuses, equipment, and systems may be connected, arranged, or configured in any manner as long as the desired purpose can be achieved.

[0087] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. The present disclosure is intended to encompass such changes and modifications as fall within the scope of the appended claims.

[0088] Any description in this disclosure should not be construed as implying that any particular element, step, or function is an essential element that must be included in the claims scope. The scope of the patented subject matter is limited solely by the claims.

[0089] Exemplary embodiments according to the present disclosure have been disclosed herein, and although specific terms are employed, they are used and interpreted only in a general and descriptive sense and not for limiting purposes. In some cases, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise stated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made to the present disclosure without departing from the spirit and scope of the claims.

Claims

1. An amplifier with multiple output terminals, comprising an amplifier circuit and a radio frequency switch circuit, characterized in that: The amplifier circuit is configured as a low-noise amplifier circuit with a common-source and common-gate structure to receive a radio frequency input signal and provide the amplified radio frequency signal to the radio frequency switch circuit; The radio frequency switch circuit includes a center-tap inductor and is configured to provide the amplified radio frequency signal to multiple output terminals of the amplifier through a center tap of the center-tap inductor.

2. The amplifier according to claim 1, characterized in that The plurality of output terminals include a first output terminal and a second output terminal, The amplifier circuit includes a first amplifier transistor and a second amplifier transistor connected in series, and is configured to amplify a radio frequency input signal input from a first input terminal of the amplifier, and output the amplified radio frequency signal to the radio frequency switch circuit; and The RF switch switching circuit includes a first pass transistor, a second pass transistor, a third pass transistor, a fourth pass transistor, a fifth pass transistor and a sixth pass transistor, and is configured to select one or more of the first pass transistor, the second pass transistor, the third pass transistor, the fourth pass transistor, the fifth pass transistor and the sixth pass transistor based on a selection signal input from a selection signal input terminal, so that the signal output from the amplification circuit is output through at least one of the first output terminal and the second output terminal.

3. The amplifier according to claim 2, characterized in that The first input terminal of the amplifier is connected to the gate of the first amplifying transistor, The first electrode of the second amplifying transistor is connected to the RF switch switching circuit. A second electrode of the first amplifying transistor is connected to a ground voltage; and Wherein, the RF switch switching circuit also includes a matching resistor, wherein, The middle tap of the middle tap inductor is connected to the first electrode of the second amplifying transistor, The first end and the second end of the intermediate tap inductor are connected to the first output end and the second output end through the first gating transistor and the second gating transistor, respectively. The third selection transistor is connected between the middle tap and the first end of the middle tap inductor, and the fourth selection transistor is connected between the middle tap and the second end of the middle tap inductor. The fifth gate transistor, the matching resistor and the sixth gate transistor are sequentially connected in series between the first end and the second end of the intermediate tap inductor.

4. The amplifier according to claim 3, characterized in that The selection signal input terminal includes a first selection signal input terminal and a second selection signal input terminal, and the radio frequency switch switching circuit also includes a first inverter, a second inverter, a first AND gate, a second AND gate and a third AND gate, wherein, The first selection signal input terminal is connected to the gate of the first selection transistor, The second selection signal input terminal is connected to the gate of the second selection transistor, The first selection signal input terminal is also connected to the first input terminal of the first AND gate, the second selection signal input terminal is also connected to the second input terminal of the first AND gate through the first inverter, and the output terminal of the first AND gate is connected to the gate of the third selection transistor. The first selection signal input terminal is also connected to the first input terminal of the second AND gate through the second inverter, the second selection signal input terminal is also connected to the second input terminal of the second AND gate, and the output terminal of the second AND gate is connected to the gate of the fourth selection transistor, and The first selection signal input terminal is also connected to the first input terminal of the third AND gate, the second selection signal input terminal is also connected to the second input terminal of the third AND gate, and the output terminal of the third AND gate is connected to the gates of the fifth selection transistor and the sixth selection transistor.

5. The amplifier according to claim 3, characterized in that The amplifying circuit further includes a first capacitor and a second capacitor, wherein: The first capacitor is arranged between the first input terminal and the gate of the first amplifying transistor; and The second capacitor is arranged between the first electrode of the second amplifying transistor and the middle tap of the middle tap inductor.

6. The amplifier according to claim 3, characterized in that The amplifier circuit also includes a first resistor and a first bias voltage input terminal, wherein: The first bias voltage input terminal is connected to the gate of the first amplifying transistor through the first resistor.

7. The amplifier according to claim 3, characterized in that The amplifier circuit also includes a second bias voltage input terminal, wherein: The second bias voltage input terminal is connected to the gate of the second amplifying transistor.

8. The amplifier according to claim 3, characterized in that The amplifier circuit further includes a first inductor and a second inductor, wherein: The first inductor is arranged between the second electrode of the first amplifying transistor and the ground voltage; and The second inductor is arranged between the first electrode of the second amplifying transistor and a power supply voltage.

9. The amplifier according to claim 3, characterized in that Each of the first to second amplifying transistors and the first to sixth gate transistors is an N-type transistor, the first electrode is a drain of the N-type transistor, and the second electrode is a source of the N-type transistor.

10. The amplifier according to claim 3, characterized in that A first electrode of the first amplifying transistor is connected to a second electrode of the second amplifying transistor.

11. The amplifier according to claim 3, characterized in that The matching resistor is configured to provide output impedance matching when a signal output from the amplifying circuit is simultaneously output through both of the first output terminal and the second output terminal.

12. The amplifier according to claim 11, characterized in that The matching resistor is an adjustable resistor with adjustable resistance.

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