Watchdog system capable of configuring duration
By introducing real-time clock module and voltage comparator module into the watchdog system, combining RC circuit and communication port configuration, configurable time and high-precision timing counting are achieved, and the existing watchdog timing time fixed and reset signals are solved. The problem of unreliability improves the applicability and reliability of the system and reduces costs.
Patent Information
- Application Number
- CN202420969128.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-07
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2034-05-07
AI Technical Summary
The existing watchdog timing time is fixed and the reset signal is unreliable, which cannot meet different application needs. The timing time varies greatly in high and low temperature environments, and the cost is high.
A watchdog system including a controller, a real-time clock module, a voltage comparator module and a power-on reset module is designed. The timing time of the real-time clock module is configured through the communication port, and the RC circuit and a voltage comparator module are combined. Implement configurable watchdog circuits ranging from hundreds of milliseconds to four hours, ensuring accurate timing counts and unenvironmental impact.
It realizes a watchdog system with accurate timing counting, improved reset signal reliability, wide applicability and low cost, and can work stably in different environments.
Smart Images
Figure CN222213281U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of watchdogs, in particular to a watchdog system capable of configuring a time length. Background Art
[0002] In a microcomputer control system composed of a single-chip microcomputer and a processor, the operation of the single-chip microcomputer and the processor is often interfered by external electromagnetic fields or the software running itself has deeply hidden bugs, which may cause data confusion in various registers and memories, leading to program pointer errors, being out of the program area, taking out wrong program instructions, etc., which may lead to an infinite loop and interrupt the normal operation of the program. The system controlled by the single-chip microcomputer and the processor cannot continue to work normally, causing the entire system to stagnate and unpredictable consequences.
[0003] In the working principle of the watchdog timer, when the watchdog is started, it will start counting automatically. If the system or program is running normally and the watchdog timer is not cleared within the specified time (commonly known as "feeding the dog"), the watchdog timer will generate a reset signal to the CPU due to the overflow of the counter, causing the system to restart. This process is called "being bitten by the dog" or "dog bite reset".
[0004] In the prior art, there are watchdog circuits with fixed timing, ranging from a few hundred milliseconds to 1.6 seconds, with various models. There are also variable RC oscillator frequency watchdog circuits that configure the timing through an external RC circuit. The internal timer also uses the RC oscillator principle, and the timing varies greatly under high and low temperatures. There are also watchdogs with variable timing designed using FPGAs, which are expensive. Utility Model Content
[0005] The utility model aims to at least solve the technical problems in the prior art that the watchdog timing time is fixed and the reset signal is unreliable, and in particular innovatively proposes a watchdog system capable of configuring the duration.
[0006] In order to achieve the above-mentioned purpose of the utility model, the utility model provides a watchdog system capable of configuring the duration, including a controller, a real-time clock module, a voltage comparator module and a power-on reset module;
[0007] The controller is connected to the real-time clock module through the communication port, the output end of the real-time clock module is connected to the same-direction input end of the voltage comparator module, the output end of the voltage comparator module is connected to the power-on reset module, and the power-on reset module generates a reset signal to reset the controller.
[0008] In a preferred implementation manner of the present utility model, the communication port of the controller is based on an IIC interface or a SPI interface.
[0009] The timing duration of the real-time clock module is configured through the communication port (IIC interface or SPI interface), and the configurable duration ranges from several hundred milliseconds to four hours, thereby ensuring that the watchdog circuit has a wide range of applicability.
[0010] In a preferred embodiment of the utility model, the real-time clock module includes: the interrupt signal terminal INT of the real-time clock chip U5 is connected to one end of the capacitor C28, the other end of the capacitor C28 is connected to one end of the resistor R27, the other end of the resistor R27 is connected to the 3.3V power supply, and the other end of the capacitor C28 is also connected to the same direction input end of the voltage comparator module; one end of the resistor R27 is also connected to the positive electrode of the diode D13, and the negative electrode of the diode D13 is connected to the other end of the resistor R27;
[0011] The interrupt signal terminal INT of the real-time clock chip U5 is also connected to one end of the resistor R26, and the other end of the resistor R26 is connected to the 3.3V power supply;
[0012] The crystal input terminal OSCI of the real-time clock chip U5 is connected to one end of the crystal Y3, and the other end of the crystal Y3 is connected to the crystal output terminal OSCO of the real-time clock chip U5; one end of the crystal Y3 is also connected to one end of the capacitor C24, and the other end of the capacitor C24 is connected to the power ground;
[0013] The power supply terminal VDD of the real-time clock chip U5 is connected to one end of the capacitor C23, the other end of the capacitor C23 is connected to the power ground, one end of the capacitor C23 is also connected to one end of the capacitor C22, and the other end of the capacitor C22 is connected to the other end of the capacitor C23;
[0014] The power ground terminal VSS of the real-time clock chip U5 is connected to the power ground; the serial clock line SDL of the real-time clock chip U5 is connected to one end of the resistor R28, and the other end of the resistor R28 is connected to the 3.3V power supply; the serial clock line SDA of the real-time clock chip U5 is connected to one end of the resistor R29, and the other end of the resistor R29 is connected to the 3.3V power supply; the real-time clock chip U5 communicates with the controller through the serial clock line SDA and the serial clock line SDL.
[0015] The specific working principle of the above real-time clock module is:
[0016] The real-time clock chip U5 communicates with the controller via the serial clock line SDL and the serial clock line SDA; the real-time clock module includes an RC circuit, which includes a capacitor C28 and a resistor R27. When INT is generated, the capacitor C28 is charged, and the voltage rise time across the capacitor C28 satisfies the time constant τ=R*C (the time constant is the time required for the capacitor to charge from the initial 0V to 63.2% of the maximum voltage through the resistor). This time can be adjusted by adjusting the size of the capacitor C28 and the resistor R27.
[0017] In addition, resistor R26 and diode D13 form a discharge loop. Prepare for the next RC circuit charging. At the same time, diode D13 is a clamping diode to prevent the voltage of the interrupt signal terminal INT of the real-time clock chip U5 from being higher than 3.3V, causing damage to the chip. After the circuit is powered on, because the real-time clock signal interrupt terminal INT is an OD gate, it is pulled to a high level by resistor R26. Resistor R27 also pulls the other end of capacitor C28 to a high level, and the voltage of capacitor C28 is 0V.
[0018] In addition, the crystal oscillator Y3 is a crystal oscillator, which provides a high-precision clock for the timer in the real-time clock in the form of a crystal oscillator, so that the clock accuracy is not affected by the high and low temperature external environment.
[0019] In a preferred embodiment of the present utility model, the voltage comparator module includes: the positive input terminal VCC+ of the voltage comparison chip U6 is connected to one end of the resistor R30, the other end of the resistor R30 is respectively connected to one end of the resistor R32 and the reverse input terminal IN- of the voltage comparison chip U6, and the other end of the resistor R32 is connected to the power ground;
[0020] The output terminal OUT of the voltage comparison chip U6 is connected to one end of the resistor R31, and the other end of the resistor R31 is connected to the power-on reset module; the negative power terminal VCC- of the voltage comparison chip U6 is connected to the power ground; the positive power terminal VCC+ of the voltage comparison chip U6 is also connected to one end of the capacitor C31, and the other end of the capacitor C31 is connected to the power ground.
[0021] The working principle of the voltage comparator module is as follows: the voltage comparator module includes a voltage reference circuit, which includes resistors R30 and R32; when working normally, the voltage at the same-direction input terminal IN+ of the voltage comparison chip U6 is greater than the voltage at its reverse input terminal IN-, and the voltage comparator outputs a high level. That is, the reverse input terminal IN- of the voltage comparison chip U6 is divided by the voltage reference circuit, namely resistors R30 and R32, and finally the reverse input terminal IN- of the voltage comparison chip U6 is 1.65V, and the voltage at the same-direction input terminal IN+ of the voltage comparison chip U6 is 3.3V.
[0022] When a dog bites, the voltage at the IN+ in-phase input terminal of the voltage comparison chip U6 is lower than the voltage at its IN- inverting input terminal for a period of time; the output terminal OUT of the voltage comparison chip U6 outputs a widened low-level pulse, which is transmitted to the power-on reset module.
[0023] In a preferred embodiment of the present utility model, the power-on reset module includes:
[0024] Power-on reset chip U4 manual reset terminal Connect one end of resistor R25, and the other end of resistor R25 is connected to a 3.3V power supply;
[0025] Power-on reset chip U4 manual reset terminal Also connected to the output of the voltage comparator module;
[0026] The sensing terminal SENSE of the power-on reset chip U4 and the positive power terminal VDD of the power-on reset chip U4 are connected to one end of the capacitor C19 and one end of the capacitor C20; the other end of the capacitor C19 is connected to the other end of the capacitor C20 and the power ground, the other end of the capacitor C20 is also connected to one end of the capacitor C21, and the other end of the capacitor C21 is connected to the timing capacitor terminal CT of the power-on reset chip U4; the restart terminal of the power-on reset chip U4 Connect one end of resistor R23, and the other end of resistor R23 is connected to the 3.3V power supply, and the restart end of the power-on reset chip U4 One end of capacitor C18 is also connected, and the other end of capacitor C18 is connected to the power ground GND of power-on reset chip U4 and connected to the power ground. Output reset signal to reset the controller.
[0027] The working principle of the above scheme is: when the real-time clock chip U5 timer overflows, an INT interrupt signal is generated. The interrupt signal is transmitted through the RC circuit and the voltage comparator to extend the low-level pulse to the manual reset terminal of the power-on reset chip U4. , power-on reset chip U4 restart terminal Outputs a reset signal and resets the controller.
[0028] In a preferred implementation manner of the present invention, the controller is a single chip microcomputer, an ARM processor or other architecture processors.
[0029] In a preferred implementation manner of the present utility model, the model of the real-time clock is PCF8563T.
[0030] In a preferred implementation manner of the present utility model, the model of the voltage comparator is TS881ICT.
[0031] In a preferred implementation manner of the present utility model, the model of the power-on reset chip is TPS3808G33DBVT.
[0032] In summary, due to the adoption of the above technical solution, the beneficial effects of the utility model are:
[0033] 1. The real-time clock module counts as an independent watchdog timer, and the timing counting is accurate and is not affected by external environmental conditions such as high and low temperatures.
[0034] 2. The real-time clock module and the voltage comparator module are combined to complete the widening of the low-level pulse of the INT interrupt signal, thereby improving the reliability of triggering the power-on reset module to generate a reset signal.
[0035] 3. The controller configures the duration of the internal timer of the real-time clock through the communication port. The configurable duration ranges from several hundred milliseconds to four hours.
[0036] 4. The circuit of the utility model is simple and low in cost.
[0037] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0039] Figure 1 It is a schematic diagram of the connection relationship of the system modules of the utility model;
[0040] Figure 2 This is a schematic diagram of the connection between the real-time clock and the voltage comparator circuit of the utility model;
[0041] Figure 3 This is a schematic diagram of the power-on reset circuit of the utility model;
[0042] Figure 4 This is an operation flow chart of the watchdog system of the utility model. DETAILED DESCRIPTION
[0043] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0044] The utility model provides a watchdog system capable of configuring the duration, such as Figure 1 As shown, it includes a controller, a real-time clock module, a voltage comparator module and a power-on reset module;
[0045] The controller is connected to the real-time clock module through the communication port, the output end of the real-time clock module is connected to the same-direction input end of the voltage comparator module, the output end of the voltage comparator module is connected to the power-on reset module, and the power-on reset module generates a reset signal to reset the controller.
[0046] like Figure 2As shown, in a preferred embodiment of the utility model, the real-time clock module includes: the real-time clock interrupt signal terminal INT is connected to one end of the capacitor C28, the other end of the capacitor C28 is connected to one end of the resistor R27, the other end of the resistor R27 is connected to the 3.3V power supply, and the other end of the capacitor C28 is also connected to the same-direction input terminal IN+ of the voltage comparator module; one end of the resistor R27 is also connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the other end of the resistor R27;
[0047] The real-time clock interrupt signal terminal INT is also connected to one end of resistor C26, and the other end of resistor C26 is connected to a 3.3V power supply;
[0048] The crystal input terminal OSCI of the real-time clock chip U5 is connected to one end of the crystal Y3, and the other end of the crystal Y3 is connected to the crystal output terminal OSCO of the real-time clock chip U5; one end of the crystal Y3 is also connected to one end of the capacitor C24, and the other end of the capacitor C24 is connected to the power ground;
[0049] The power supply terminal VDD of the real-time clock chip U5 is connected to one end of the capacitor C23, the other end of the capacitor C23 is connected to the power ground, one end of the capacitor C23 is also connected to one end of the capacitor C22, and the other end of the capacitor C22 is connected to the other end of the capacitor C23;
[0050] The ground terminal VSS of the real-time clock chip U5 is connected to the power ground; the serial clock line SDL of the real-time clock chip U5 is connected to one end of the resistor R28, and the other end of the resistor R28 is connected to the 3.3V power supply; the serial clock line SDA of the real-time clock chip U5 is connected to one end of the resistor R29, and the other end of the resistor R29 is connected to the 3.3V power supply; the real-time clock chip U5 communicates with the controller through the serial clock line SDA and the serial clock line SDL.
[0051] Specifically, when the real-time clock generates an interrupt signal, capacitor C28 is charged, and the voltage rise time across capacitor C28 satisfies the time constant τ=R*C (the time constant is the time required for the capacitor to charge from the initial 0V to 63.2% of the maximum voltage through the resistor). This time can be adjusted by adjusting the size of capacitor C28 and resistor R27. The signal output by the real-time clock is connected to the same-direction input terminal of the voltage comparator.
[0052] In addition, the resistor R26 and the diode D13 are its discharge circuit. At the same time, the diode D13 is a clamping diode to prevent the voltage at the real-time clock interrupt signal terminal from being higher than 3.3V, causing damage to the chip. After the circuit is powered on, because the real-time clock interrupt signal terminal is an OD gate, the potentials at both ends of the capacitor C28 are the same, so the voltage is 0V.
[0053] In a preferred embodiment of the present utility model, the voltage comparator module includes: the positive input terminal VCC+ of the voltage comparison chip U6 is connected to one end of the resistor R30, the other end of the resistor R30 is respectively connected to one end of the resistor R32 and the reverse input terminal IN- of the voltage comparison chip U6, and the other end of the resistor R32 is connected to the power ground;
[0054] The output terminal OUT of the voltage comparison chip U6 is connected to one end of the resistor R31, and the other end of the resistor R31 is connected to the power-on reset module; the negative power terminal VCC- of the voltage comparison chip U6 is connected to the power ground; the positive power terminal VCC+ of the voltage comparison chip U6 is also connected to one end of the capacitor C31, and the other end of the capacitor C31 is connected to the power ground.
[0055] Specifically, the model of the voltage comparison chip U6 is TS881ICT. The voltage reference circuit provides a relatively accurate reference voltage for the voltage comparator. The voltage reference circuit includes resistors R30 and R32, which divide the power supply 3V3 into 1.65V. 1.65V is used as a voltage reference for the voltage comparator. The voltage reference is connected to the inverting input terminal of the voltage comparator, and the signal output by the RC circuit is connected to the same-direction input terminal of the voltage comparator.
[0056] During normal operation, the voltage at the non-inverting input of the voltage comparator is pulled up to 3.3V by resistor R27, which is greater than 1.65V at the inverting input of the voltage comparator (the reference voltage provided by the voltage reference).
[0057] Therefore, the voltage comparator outputs a high-level pulse, the power-on reset chip U4 is TPS3808G33DBVT, and the power-on reset circuit does not output a reset signal. For some controllers whose reset signals are high-level, the power-on reset chip can also use other models.
[0058] like Figure 3 As shown, in a preferred embodiment of the present utility model, the power-on reset module includes:
[0059] Power-on reset chip U4 manual reset terminal Connect one end of resistor R25, and the other end of resistor R25 is connected to a 3.3V power supply;
[0060] Power-on reset chip U4 manual reset terminal It is also connected to the output terminal OUT of the voltage comparison chip U6;
[0061] The sensing terminal SENSE of the power-on reset chip U4 and the positive terminal VDD of the power supply are connected to one end of the capacitor C19 and one end of the capacitor C20; the other end of the capacitor C19 is connected to the other end of the capacitor C20, and the other end of the capacitor C20 is also connected to one end of the capacitor C21, and the other end of the capacitor C21 is connected to the timing capacitor terminal CT of the power-on reset chip U4; the restart terminal of the power-on reset chip U4 Connect one end of resistor R23, and the other end of resistor R23 is connected to the 3.3V power supply, and the restart end of the power-on reset chip U4 One end of capacitor C18 is also connected, and the other end of capacitor C18 is connected to the power ground GND of power-on reset chip U4 and connected to the power ground. Output reset signal to reset the controller.
[0062] The working principle of the above scheme is: when the real-time clock chip U5 timer overflows, an INT interrupt signal is generated. The interrupt signal is transmitted through the RC circuit and the voltage comparator to extend the low-level pulse to the manual reset terminal of the power-on reset chip U4. , power-on reset chip U4 restart terminal Outputs a reset signal and resets the controller.
[0063] When a dead loop occurs in the system application program running on the controller or when the watchdog timer reaches a certain threshold, i.e., the dog bites, the voltage at the same-direction input terminal of the voltage comparator is a voltage waveform that rises according to a logarithmic curve within a certain period of time. Within a certain period of time, the voltage at the same-direction input terminal of the voltage comparator is less than the voltage at the reverse input terminal, and the voltage reference is 1.65V. Therefore, the output terminal of the voltage comparator outputs a low-level pulse, which is connected to the manual reset terminal of the power-on reset chip. The power-on reset circuit generates a stable reset pulse with controllable pulse width and the power-on reset chip restarts the terminal Output reset signal to reset the controller.
[0064] like Figure 4 As shown, the specific operation process of the above watchdog system is:
[0065] Step 1:
[0066] First, the system is powered on and the controller is initialized. There is a timer in the real-time clock module. The controller configures the timer duration of the real-time clock module through the IIC interface or the SPI interface. The controller is a single-chip microcomputer, an ARM processor, or a processor of other architectures, and this embodiment uses the IIC interface. When the controller runs the system application normally and the real-time clock has not reached the set threshold, the controller can reset the timer duration through the communication port, and the timer starts running from the beginning;
[0067] Step 2:
[0068] Start the real-time clock module to start timing. The model of the real-time clock chip U5 is PCF8563T. The real-time clock uses a crystal oscillator to provide a high-precision clock for the timer. The clock accuracy is not affected by the high and low temperature external environment, and the dog is periodically cleared through the IIC interface to reconfigure the timer threshold.
[0069] Step 3:
[0070] When an infinite loop occurs in the system application program running on the controller or when the watchdog timer reaches a certain threshold, i.e. the watchdog bites, the controller does not clear the watchdog. At this time, the real-time clock module generates an interrupt signal.
[0071] Capacitor C28 is charged, and the voltage rise time across capacitor C28 satisfies the time constant τ=R*C (the time constant is the time required for the capacitor to charge from the initial 0V to 63.2% of the maximum voltage through the resistor). This time can be adjusted by adjusting the size of capacitor C28 and resistor R27.
[0072] At this time, the RC circuit in the real-time clock module generates a voltage waveform that rises in a logarithmic curve. As a result, the voltage at the in-phase input of the voltage comparator is less than the voltage at its inverting input (the reference voltage provided by the voltage reference) for a period of time; the output of the voltage comparator outputs a widened low-level pulse, which is transmitted to the manual reset terminal of the power-on reset chip U4. , power-on reset chip U4 restart terminal Output reset signal to reset the controller.
[0073] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.
Claims
1. A watchdog system capable of configuring the duration, characterized in that: It includes a controller, a real-time clock module, a voltage comparator module and a power-on reset module; The controller is connected to the real-time clock module through the communication port, the output end of the real-time clock module is connected to the same-direction input end of the voltage comparator module, the output end of the voltage comparator module is connected to the power-on reset module, and the power-on reset module generates a reset signal to reset the controller.
2. The watchdog system capable of configuring the duration according to claim 1, characterized in that: The communication port of the controller is based on an IIC interface or a SPI interface.
3. The watchdog system capable of configuring the duration according to claim 1, characterized in that: The real-time clock module includes: the interrupt signal terminal INT of the real-time clock chip U5 is connected to one end of the capacitor C28, the other end of the capacitor C28 is connected to one end of the resistor R27, the other end of the resistor R27 is connected to a 3.3V power supply, and the other end of the capacitor C28 is also connected to the same-direction input end of the voltage comparator module; one end of the resistor R27 is also connected to the positive electrode of the diode D13, and the negative electrode of the diode D13 is connected to the other end of the resistor R27; The interrupt signal terminal INT of the real-time clock chip U5 is also connected to one end of the resistor R26, and the other end of the resistor R26 is connected to the 3.3V power supply; The crystal input terminal OSCI of the real-time clock chip U5 is connected to one end of the crystal Y3, and the other end of the crystal Y3 is connected to the crystal output terminal OSCO of the real-time clock chip U5; one end of the crystal Y3 is also connected to one end of the capacitor C24, and the other end of the capacitor C24 is connected to the power ground; The power supply terminal VDD of the real-time clock chip U5 is connected to one end of the capacitor C23, the other end of the capacitor C23 is connected to the power ground, one end of the capacitor C23 is also connected to one end of the capacitor C22, and the other end of the capacitor C22 is connected to the other end of the capacitor C23; The power ground terminal VSS of the real-time clock chip U5 is connected to the power ground; the serial clock line SDL of the real-time clock chip U5 is connected to one end of the resistor R28, and the other end of the resistor R28 is connected to the 3.3V power supply; the serial clock line SDA of the real-time clock chip U5 is connected to one end of the resistor R29, and the other end of the resistor R29 is connected to the 3.3V power supply; the real-time clock chip U5 communicates with the controller through the serial clock line SDA and the serial clock line SDL.
4. The watchdog system capable of configuring the duration according to claim 1, characterized in that: The voltage comparator module includes: a positive power input terminal VCC+ of a voltage comparison chip U6 is connected to one end of a resistor R30, the other end of the resistor R30 is respectively connected to one end of a resistor R32 and a negative input terminal IN- of the voltage comparison chip U6, and the other end of the resistor R32 is connected to a power ground; The output terminal OUT of the voltage comparison chip U6 is connected to one end of the resistor R31, and the other end of the resistor R31 is connected to the power-on reset module; the negative power terminal VCC- of the voltage comparison chip U6 is connected to the power ground; the positive power terminal VCC+ of the voltage comparison chip U6 is also connected to one end of the capacitor C31, and the other end of the capacitor C31 is connected to the power ground.
5. The watchdog system capable of configurable duration according to claim 1, characterized in that: The power-on reset module comprises: Power-on reset chip U4 manual reset terminal Connect one end of resistor R25, and the other end of resistor R25 is connected to a 3.3V power supply; Power-on reset chip U4 manual reset terminal Also connected to the output of the voltage comparator module; The sensing terminal SENSE of the power-on reset chip U4 and the positive power terminal VDD of the power-on reset chip U4 are connected to one end of the capacitor C19 and one end of the capacitor C20; the other end of the capacitor C19 is connected to the other end of the capacitor C20 and the power ground, the other end of the capacitor C20 is also connected to one end of the capacitor C21, and the other end of the capacitor C21 is connected to the timing capacitor terminal CT of the power-on reset chip U4; the restart terminal of the power-on reset chip U4 Connect one end of resistor R23, and the other end of resistor R23 is connected to the 3.3V power supply, and the restart end of the power-on reset chip U4 One end of capacitor C18 is also connected, and the other end of capacitor C18 is connected to the power ground GND of power-on reset chip U4 and connected to the power ground. Output reset signal to reset the controller.
6. The watchdog system capable of configurable duration according to claim 1, characterized in that: The controller is a single chip microcomputer, an ARM processor or a processor of other architectures.
7. The watchdog system capable of configuring the duration according to claim 3, characterized in that: The model of the real-time clock chip U5 is PCF8563T.
8. The watchdog system capable of configuring the duration according to claim 4, characterized in that: The model of the voltage comparison chip U6 is TS881ICT.
9. The watchdog system capable of configuring the duration according to claim 5, characterized in that: The model of the power-on reset chip U4 is TPS3808G33DBVT.