Debugging display circuit and device

Abstract

The utility model provides a debugging display circuit and device, and relates to the technical field of mainboard debugging, and the debugging display circuit comprises an EC, a display control module and a display module. The EC is used for outputting a corresponding debugging code signal to the display control module when an operation position signal formed by operation of the debugging mainboard is received; the display control module is used for forming a driving signal and outputting the driving signal to the display module when receiving the debugging code signal; and the display module is used for displaying the corresponding debugging code when receiving the driving signal. According to the utility model, the position information of a running program in the mainboard is read through the eSPI interface of the EC to form a running position signal, and then the running position information of the mainboard is displayed in a code debugging manner by controlling the display module through the SMBUS bus of the EC and the display control module comprising the SMBUS interface; the technical problem that the running position of the mainboard cannot be displayed when the mainboard of a CPU platform after 9 generations is debugged by using an existing debugging card is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of mainboard debugging, in particular to a debugging display circuit and a device. Background Art

[0002] With the rapid development of electronic technology, the central processing unit (CPU) platform is constantly being updated. In Intel's CPU platform before the 10th generation, the control chip (Embedded Controller, EC) used is a low pin count (LPC) interface. Starting from the 10th generation CPU, the EC interface is updated to the enhanced serial peripheral interface (Enhanced Serial Peripheral Interface, eSPI) interface. Due to the change in the EC interface, the display solution of the existing debug card needs to be redesigned.

[0003] The above contents are only used to assist in understanding the technical solution of the present utility model and do not constitute an admission that the above contents are prior art. Utility Model Content

[0004] The utility model provides a debugging display circuit and a device, aiming to solve the technical problem of being unable to use a debugging card in the prior art to debug a mainboard of a CPU platform using an eSPI interface of an EC to display the operating position of the mainboard.

[0005] To achieve the above-mentioned purpose, the embodiment of the utility model provides a debugging display circuit, the debugging display circuit comprising: an EC, a display control module and a display module;

[0006] The display control module is connected to the display module, and the display control module is also connected to the EC via the SMBUS bus; the EC is also connected to the mainboard via the eSPI interface;

[0007] The EC is used to output a corresponding debugging code signal to the display control module when receiving an operation position signal formed by the operation of the debugging mainboard;

[0008] The display control module is used to generate a driving signal and output it to the display module when receiving the debugging code signal;

[0009] The display module is used to display the corresponding debugging code when receiving the driving signal.

[0010] Optionally, the debugging and display circuit further includes: a voltage regulating module;

[0011] The voltage regulating module is connected to the display control module and the display module respectively;

[0012] The voltage regulating module is used to regulate the voltage of the driving signal output by the display control module, and transmit the driving signal with the regulated voltage to the display module.

[0013] Optionally, the voltage regulating module includes: a first resistor;

[0014] The first resistor is respectively connected to the output end of the display control module and the input end of the display module.

[0015] Optionally, the display module is a digital tube;

[0016] The first resistor is connected between each pin of the digital tube connected to the display control module and the output end corresponding to the display control module.

[0017] Optionally, the debugging display circuit further includes: a first capacitor;

[0018] The first end of the first capacitor is respectively connected to the power supply input end of the display control module and the power supply, and the second end of the first capacitor is grounded.

[0019] Optionally, the debugging display circuit further includes: a first connector;

[0020] The first port of the first connector connects the data input end of the display control module with the data port of the EC, and the second port of the first connector connects the clock input end of the display control module with the clock port of the EC.

[0021] Optionally, the debugging display circuit further includes: a second connector;

[0022] The first port of the second connector connects the data output end of the mainboard to the first port of the first connector, and the second port of the second connector connects the clock output end of the mainboard to the second port of the first connector.

[0023] Optionally, the display control module is a MAX6958AAEE chip.

[0024] To achieve the above object, an embodiment of the utility model further provides a debugging display device, wherein the debugging display device adopts the above-mentioned debugging display circuit.

[0025] The embodiment of the utility model proposes a debugging display circuit and device, the debugging display circuit includes: EC, display control module and display module; the display control module is connected to the display module, and the display control module is also connected to the EC through the SMBUS bus; the EC is also connected to the mainboard through the eSPI interface; the EC is used to output a corresponding debugging code signal to the display control module when receiving an operating position signal formed by debugging the mainboard operation; the display control module is used to form a driving signal and output it to the display module when receiving the debugging code signal; the display module is used to display the corresponding debugging code when receiving the driving signal. The utility model reads the location information of the running program in the mainboard through the eSPI interface of the EC to form an operating position signal, and then controls the display module to display the mainboard operating position information in the form of debugging code through the SMBUS bus of the EC and the display control module including the SMBUS interface, thereby solving the technical problem that the debugging card in the prior art cannot be used to display the mainboard operating position when debugging the mainboard of the CPU platform of the EC using the eSPI interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0027] Figure 1 It is a structural schematic diagram of the first embodiment of the debugging display circuit of the utility model;

[0028] Figure 2 It is a circuit connection diagram of the second embodiment of the debugging display circuit of the utility model;

[0029] Figure 3 It is a circuit connection diagram of the third embodiment of the debugging display circuit of the utility model;

[0030] Figure 4 This is a functional pin diagram of the MAX6958AAEE chip.

[0031] Description of Figure Numbers:

[0032] 10 EC 20 Display Control Module 30 Display Module 40 Motherboard R1 First resistor J1~J2 First to Second Connector C1 First capacitor VCC Power supply U1 Digital tube U2 MAX6958AAEE chip 50 Voltage Regulator Module

[0033] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0034] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0035] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0036] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0037] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0038] The utility model proposes a debugging display circuit, referring to Figure 1 , Figure 1 It is a structural schematic diagram of the first embodiment of the debugging display circuit of the utility model.

[0039] like Figure 1 As shown, in this embodiment, the debugging display circuit includes: EC, display control module 20 and display module 30;

[0040] The display control module 20 is connected to the display module 30, and the display control module 20 is also connected to the EC via the SMBUS bus; the EC is also connected to the mainboard 40 via the eSPI interface;

[0041] The EC is used to output a corresponding debugging code signal to the display control module 20 when receiving an operation position signal formed by the operation of the debugging mainboard 40;

[0042] The display control module 20 is used to generate a driving signal and output it to the display module 30 when receiving the debugging code signal;

[0043] The display module 30 is used to display the corresponding debugging code when receiving the driving signal.

[0044] It should be noted that the display control module 20 should have a system management bus (SMBUS) interface, the EC should have an SMBUS bus and an eSPI bus, and the motherboard 40 can be a motherboard 40 using Intel's 9th generation or later CPU platform.

[0045] It should be understood that the EC can use the interface of the SMBUS bus to connect to the interface of the SMBUS bus of the display control module 20 through a socket strip or wiring or other means. At the same time, the EC can also use the eSPI interface to connect to the mainboard 40 through a socket strip or wiring or other means, so that the mainboard 40, the EC and the display control module 20 can transmit signals about the operating information of the mainboard 40 to each other.

[0046] In a specific implementation, when debugging the main board 40, the EC can obtain a running position signal representing the running position information of the debugging main board 40 from the main board 40 through the clock line and the data line of the eSPI bus, form a corresponding debugging code signal, and transmit the debugging code signal forming the corresponding running position information of the debugging main board 40 to the display control module 20 through the clock line and the data line of the SMBUS bus. When receiving the debugging code signal, the display control module 20 forms a driving signal represented by the corresponding debugging code signal to drive the display module 30 to display the debugging code representing the running position of the debugging main board 40.

[0047] It is worth noting that when EC reads the running position signal corresponding to the running position of the mainboard 40, it can read the debugging code in the running position signal, and store the debugging code in the designated register buffer inside the EC, and set a flag bit. Whenever EC runs the internal program to the flag bit, it will send an initialization signal to the display control module 20 to initialize the display control module 20. At the same time, the debugging code stored in the designated register buffer will be sent to the designated storage address of the display control module 20 in the form of a debugging code signal, so that the display control module 20 converts the received debugging code signal into a driving signal corresponding to the debugging code, and sends it to the display module 30 to drive the display module 30 to display the corresponding debugging code.

[0048] The utility model proposes a debugging display circuit, the debugging display circuit includes: EC, display control module and display module; the display control module is connected to the display module, and the display control module is also connected to the EC through the SMBUS bus; the EC is also connected to the mainboard through the eSPI interface; the EC is used to output a corresponding debugging code signal to the display control module when receiving an operating position signal formed by debugging the mainboard operation; the display control module is used to form a driving signal and output it to the display module when receiving the debugging code signal; the display module is used to display the corresponding debugging code when receiving the driving signal. The utility model reads the location information of the running program in the mainboard through the eSPI interface of the EC to form an operating position signal, and then controls the display module to display the mainboard operating position information in the form of debugging code through the SMBUS bus of the EC and the display control module including the SMBUS interface, thereby solving the technical problem that the debugging card in the prior art cannot be used to display the mainboard operating position when debugging the mainboard of the CPU platform of the EC using the eSPI interface.

[0049] Based on the first embodiment of the above-mentioned debugging display circuit, a second embodiment of the debugging display circuit of the present utility model is proposed. Figure 2 , Figure 2 This is a circuit connection diagram of the second embodiment of the debugging display circuit of the utility model.

[0050] In this embodiment, the debugging and display circuit further includes: a voltage regulating module 50;

[0051] The voltage regulating module 50 is connected to the display control module 20 and the display module 30 respectively;

[0052] The voltage regulating module 50 is used to regulate the voltage of the driving signal output by the display control module 20 and transmit the regulated driving signal to the display module 30 .

[0053] It is easy to understand that in a specific implementation, the voltage regulating module 50 can adjust the voltage of the driving signal output by the display control module 20, so that the brightness of the debugging code displayed by the driving display module 30 changes accordingly with the voltage of the driving signal, that is, the higher the voltage of the driving signal, the brighter the brightness of the debugging code displayed by the display module 30, and the lower the voltage of the driving signal, the darker the brightness of the debugging code displayed by the display module 30.

[0054] Furthermore, the voltage regulating module 50 includes: a first resistor R1;

[0055] The first resistor R1 is connected to the output end of the display control module 20 and the input end of the display module 30 respectively.

[0056] It should be understood that the first resistor R1 can be connected in series between the output end of the display control module 20 and the input end of the display module 30 to divide the voltage with the internal resistance of the display module 30, thereby changing the voltage value obtained by changing the internal resistance of the display module 30, thereby changing the brightness of the debugging code displayed by the display module 30.

[0057] It is easy to understand that the first resistor R1 can be assembled using a package of 0402 or above according to the actual space, and the package of 0201 should be avoided as much as possible, because the resistance power of the 0201 package is only 1 / 20W. If the resistance value is set too large, the voltage value divided by the internal resistance of the display module 30 is easy to be too small, resulting in insufficient brightness of the display debugging code. If the resistance value is set too small, the current passing through the display module 30 is easy to be too large, resulting in damage to the display module 30. In a specific implementation, a resistor with a 0402 package, a resistance value of 220Ω and an accuracy within 5% can be used to meet the needs of the display module 30 in actual applications.

[0058] Furthermore, the display module 30 is a digital tube U1;

[0059] The first resistor R1 is connected between each pin of the digital tube U1 connected to the display control module 20 and the corresponding output end of the display control module 20 .

[0060] It is easy to understand that the digital tube U1 can be used as the display module 30, and the numbers or codes displayed by the digital tube U1 are used to represent the debugging code, that is, the running position of the debugging mainboard 40. In a specific implementation, the digital tube U1 can be connected in series one by one between each pin of the digital tube U1 and each output end of the display control module 20 corresponding to each pin through a plurality of first resistors R1, and the light brightness of each segment of the light emitting diode that displays the debugging code inside the digital tube U1 is controlled by the resistance value of the first resistor R1.

[0061] It should be noted that the A~G pins of the digital tube U1 are the segment code lighting control pins, which are used to select the segment code that needs to be lit; the CT pin of the digital tube U1 is the bit code circuit control pin, which is often used for the dynamic display of multi-digit digital tubes, and selects the digital tube that needs to be displayed to light up, saving power consumption by dynamic display; the COM pin of the digital tube U1 is the common pole pin, which is used to connect a high level or a low level as a reference level. If it is a common anode digital tube, the COM pin is connected to a high level, and if it is a common cathode digital tube, the COM pin is connected to a low level.

[0062] It is worth noting that if the digital tube U1 is a common cathode digital tube, the COM pin of the digital tube U1 needs to receive a low-level driving signal and the A~G pins of the digital tube U1 need to receive a high-level driving signal to light up the corresponding segments of the digital tube U1. If the digital tube U1 is a common anode digital tube, the COM pin of the digital tube U1 needs to receive a high-level driving signal and the A~G pins of the digital tube U1 need to receive a low-level driving signal to light up the corresponding segments of the digital tube U1.

[0063] Furthermore, the debugging display circuit further includes: a first capacitor C1;

[0064] The first end of the first capacitor C1 is respectively connected to the power supply input end of the display control module 20 and the power supply VCC, and the second end of the first capacitor C1 is grounded.

[0065] It is easy to understand that in a specific implementation, the display control module 20 needs to be powered by the power supply VCC to achieve a stable output drive signal. The first capacitor C1 can filter the power supply signal output by the power supply VCC to the display control module 20 to make the voltage of the power supply signal received by the display control module 20 more stable, that is, the voltage of the drive signal output by the display control module 20 is more stable.

[0066] Furthermore, the debugging display circuit further includes: a first connector J1;

[0067] The first port of the first connector J1 connects the data input end of the display control module 20 with the data port of the EC, and the second port of the first connector J1 connects the clock input end of the display control module 20 with the clock port of the EC.

[0068] It is easy to understand that in order to facilitate the installation and disassembly of the debugging display circuit, the first connector J1 is used to connect the EC and the display control module 20. In a specific implementation, the port of the SMBUS bus of the EC and the interface of the SMBUS bus of the display control module 20 can be connected by a jumper, a plug-in board or the like, so that the clock line of the SMBUS bus of the EC corresponds to the clock line of the SMBUS bus of the display control module 20, and the data line of the SMBUS bus of the EC corresponds to the data line of the SMBUS bus of the display control module 20, so that the EC can transmit the SMBUS signal data to the display control module 20 through a preset timing, so that the display control module 20 generates a drive signal corresponding to the debug code.

[0069] Furthermore, the debugging display circuit further includes: a second connector J2;

[0070] The first port of the second connector J2 connects the data output end of the mainboard 40 to the first port of the first connector J1, and the second port of the second connector J2 connects the clock output end of the mainboard 40 to the second port of the first connector J1.

[0071] It is easy to understand that in order to facilitate the installation and removal of the debugging display circuit, the second connector J2 is used to connect the mainboard 40 and the EC. In a specific implementation, the port of the eSPI bus of the mainboard 40 can be connected to the interface of the eSPI bus of the EC by using a jumper, a plug-in board, etc., so that the clock line of the eSPI bus of the mainboard 40 corresponds to the clock line of the eSPI bus of the EC, and the data line of the eSPI bus of the mainboard 40 corresponds to the data line of the eSPI bus of the EC, so that the mainboard 40 can transmit the eSPI signal data to the EC through a preset timing, so that the EC generates a debugging code signal corresponding to the running position of the debugging mainboard 40.

[0072] Based on the second embodiment of the above-mentioned debugging display circuit, a third embodiment of the debugging display circuit of the present utility model is proposed, referring to Figure 3 as well as Figure 4 , Figure 3 This is a circuit connection diagram of the third embodiment of the debugging display circuit of the utility model. Figure 4 This is a functional pin diagram of the MAX6958AAEE chip.

[0073] In this embodiment, the display control module is a MAX6958AAEE chip U2.

[0074] It is easy to understand that in a specific implementation, the display control module can be the MAX6958AAEE chip U2, which is a low-power, high-stability digital tube driver chip with an SMBUS bus. It can receive signals transmitted by the SMBUS bus, and form corresponding drive signals according to the signals transmitted by the SMBUS bus representing the need to display debug codes, thereby driving the digital tube to display the corresponding segment codes to display the corresponding debug codes.

[0075] It should be noted that, in this embodiment, the V+ pin of the MAX6958AAEE chip U2 should be connected to the power supply VCC, the SDA pin of the MAX6958AAEE chip U2 should be connected to the data line of the SMBUS bus of the EC, the SCL pin of the MAX6958AAEE chip U2 should be connected to the clock line of the SMBUS bus of the EC, the SEG0 pin of the MAX6958AAEE chip U2 is connected to the COM pin of the digital tube, the SEG1 pin of the MAX6958AAEE chip U2 is connected to the CT pin of the digital tube, and the SEG2~8 pins of the MAX6958AAEE chip U2 are connected to the A~G pins of the digital tube in sequence.

[0076] Based on all the embodiments of the above debugging display circuit, the present invention also proposes a debugging display device, which adopts the technical solutions of all the above embodiments. Since the embodiments of the present invention adopt all the above embodiments, it has at least all the beneficial effects brought by all the above technical solutions, which will not be described one by one here.

[0077] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

[0078] It is worth noting that in the actual application of the present utility model, software programs will inevitably be applied, but the applicant hereby declares that the software programs applied in the specific implementation of the technical solution are all prior art. In the present utility model, it does not involve the modification and protection of software programs, but only the protection of the hardware architecture designed to achieve the purpose of the utility model.

Claims

1. A debugging display circuit, characterized in that: The debugging display circuit comprises: EC, display control module and display module; The display control module is connected to the display module, and the display control module is also connected to the EC via the SMBUS bus; the EC is also connected to the mainboard via the eSPI interface; The EC is used to output a corresponding debugging code signal to the display control module when receiving an operation position signal formed by the operation of the debugging mainboard; The display control module is used to generate a driving signal and output it to the display module when receiving the debugging code signal; The display module is used to display the corresponding debugging code when receiving the driving signal.

2. The debugging display circuit according to claim 1, characterized in that: Also includes: Voltage regulating module; The voltage regulating module is connected to the display control module and the display module respectively; The voltage regulating module is used to regulate the voltage of the driving signal output by the display control module, and transmit the driving signal with the regulated voltage to the display module.

3. The debugging display circuit as claimed in claim 2, characterized in that: The voltage regulating module comprises: a first resistor; The first resistor is respectively connected to the output end of the display control module and the input end of the display module.

4. The debugging display circuit as claimed in claim 3, characterized in that: The display module is a digital tube; The first resistor is connected between each pin of the digital tube connected to the display control module and the output end corresponding to the display control module.

5. The debugging display circuit according to claim 1, characterized in that: The debugging display circuit further includes: a first capacitor; The first end of the first capacitor is respectively connected to the power supply input end of the display control module and the power supply, and the second end of the first capacitor is grounded.

6. The debugging display circuit according to claim 1, characterized in that: Also includes: a first connector; The first port of the first connector connects the data input end of the display control module with the data port of the EC, and the second port of the first connector connects the clock input end of the display control module with the clock port of the EC.

7. The debugging display circuit according to claim 6, characterized in that: Also includes: a second connector; The first port of the second connector connects the data output end of the mainboard to the first port of the first connector, and the second port of the second connector connects the clock output end of the mainboard to the second port of the first connector.

8. The debugging display circuit according to any one of claims 1 to 7, characterized in that: The display control module is a MAX6958AAEE chip.

9. A debugging display device, characterized in that: The debugging display device adopts the debugging display circuit as described in any one of claims 1-8.

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