Communication isolation circuit
By using digital isolators and transceivers in communication isolation circuits, combined with capacitors and filter modules, the problem of RS-485 interface circuits being easily disturbed is solved, the stable transmission of data information and the security protection of equipment are realized, and the communication system is improved reliability and stability.
Patent Information
- Application Number
- CN202420734282.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-10
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2034-04-10
AI Technical Summary
The RS-485 interface circuit is easily disturbed during data exchange, resulting in unstable communication, which may lead to data transmission loss or communication interruption. The 485 communication chip is easily damaged when the instantaneous voltage and current is too high, causing the entire circuit system to be paralyzed.
A communication isolation circuit is designed, including an isolation unit and a transceiver unit, and the data information is isolated and transmitted through a digital isolator and a transceiver. The capacitor and filter module are used to reduce interference signals, and the overvoltage protection module is used to prevent high voltage shocks.
Improve the reliability and stability of communication, prevent the instantaneous voltage and current from damaging a single unit without affecting the entire circuit, reduce signal interference, and protect the safety of the equipment.
Smart Images
Figure CN222213374U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of circuit design, and in particular relates to a communication isolation circuit. Background Art
[0002] With the development of communication technology, various communication methods have emerged. RS-485 interface circuits are widely used due to their simple design, convenient control, and convenient use. However, due to various environmental problems in the data exchange process and on-site engineering, the RS-485 interface circuits may have unstable communication and be susceptible to interference. In addition, the data output by peripheral devices through the RS-485 interface circuit may be lost or unable to communicate. Therefore, it is urgent to design an industrial control communication system with stable data communication and anti-interference.
[0003] To solve the above problems, patent CN211062040U, "A liquid supply control communication system with anti-static and anti-interference functions", proposes a technical solution to the above problems. In this technical solution, a 485 communication chip is used for data transmission. When the instantaneous voltage and current in the circuit are too large, the 485 chip may be damaged, which will directly cause the entire circuit system to be paralyzed and the effective transmission of data will not be achieved. Therefore, designing a communication isolation circuit is an important technical problem that those skilled in the art need to solve. Utility Model Content
[0004] The purpose of the utility model is to solve the above problems existing in the prior art and provide a communication isolation circuit.
[0005] The purpose of the utility model is achieved through the following technical solutions:
[0006] A communication isolation circuit is arranged between a CPU unit and a transceiver unit; the CPU unit is connected to the isolation unit, the isolation unit is connected to the transceiver unit, and the transceiver unit is connected to the CPU unit; the CPU unit outputs data information, which is sequentially converted and isolated by the isolation unit, and transmitted by the transceiver unit to the CPU unit for data processing, and after processing, is fed back to the CPU unit through the transceiver unit and the isolation unit to realize data information interaction.
[0007] Preferably, the isolation unit includes at least a first chip, a first pin VDD1 of the first chip and a capacitor C24 are arranged in parallel at the output end of the first power supply voltage; the second pin VOA of the first chip and the third pin VIB of the first chip are respectively connected to the I / O interface of the CPU unit; the capacitor C24, the fourth pin GND1 of the first chip and the fifth pin GND2 of the first chip are all grounded; the sixth pin VOB of the first chip and the seventh pin VIA of the first chip are respectively connected to the transceiver unit; the eighth pin VDD2 of the first chip outputs the second power supply voltage.
[0008] Preferably, the first power supply voltage is +3.3V voltage; the first pin VDD1 of the first chip is the isolation side power supply voltage; the eighth pin VDD2 of the first chip is the isolation side power supply voltage; the second pin V0A of the first chip is the logic output A pin, connected to the signal output interface of the CPU unit; the seventh pin VIA of the first chip is the logic input A pin; the third pin VIB of the first chip is the logic input B pin, connected to the signal input interface of the CPU unit; the sixth pin VOB of the first chip is the logic output B pin; the fourth pin GND1 of the first chip is the isolation side ground one; the fifth pin GND2 of the first chip is the isolation side ground two; the second power supply voltage is +5V voltage.
[0009] Preferably, a capacitor C26 is connected between the output end of the second power supply voltage and the fifth pin GND2 of the first chip.
[0010] Preferably, the transceiver unit includes at least a second chip; the first pin TXD of the second chip is connected to the seventh pin VIA of the first chip; the fourth pin RXD of the second chip is connected to the sixth pin VOB of the first chip; the third pin VCC of the second chip and the fifth pin VIO of the second chip are arranged in parallel at the output end of the second power supply voltage; the second pin GND of the second chip is grounded; the sixth pin CANL of the second chip and the seventh pin CANH of the second chip are connected to the output end; the eighth pin S of the second chip is connected to the output end of the second power supply voltage through a resistor R120, and the resistor R120 is arranged in parallel with the ground line of the second chip.
[0011] Preferably, the first pin TXD of the second chip is a data input pin; the second pin GND of the second chip is a ground pin; the third pin VCC of the second chip is a power supply voltage pin of the second chip; the fourth pin RXD of the second chip is a data output pin; the fifth pin of the second chip is a power supply voltage pin; the sixth pin CANL of the second chip is a low-level bus pin; the seventh pin CANH of the second chip is a high-level bus pin; and the eighth pin S of the second chip is a control input pin.
[0012] Preferably, the transceiver unit further includes a capacitor C36; the input end of the capacitor C36 is connected in parallel with the fifth pin VIO of the second chip to the output end of the second power supply voltage, and the output end of the capacitor C36 is connected in parallel with the resistor R120 and the ground line.
[0013] Preferably, at least a filtering module is arranged between the transceiver unit and the said; the filtering module includes resistors R121, R122, R123 and R124, and capacitor C79; the resistors R121 and R124 are arranged in parallel at the output end of the sixth pin CNAL of the second chip; the resistors R122 and R123 are arranged in parallel at the output end of the seventh pin CANH of the second chip; and the output ends of the resistors R121 and R122 are connected to the input end of the capacitor C79; the output end of the capacitor C79 is connected to the ground wire.
[0014] Preferably, an overvoltage protection module is also provided between the transceiver unit and the overvoltage protection module comprises two TVS tubes, wherein the input end of the first TVS tube is connected to the output end of the resistor R124; the input end of the second TVS tube is connected to the output end of the resistor 123; the output ends of the first TVS tube and the second TVS tube are connected to the ground wire.
[0015] Preferably, the device comprises three pins, wherein the first pin is connected in parallel with the second TVS tube at the output end of the resistor 123; the second pin is connected in parallel with the first TVS tube at the output end of the resistor 124; and the third pin is connected to the ground wire.
[0016] The advantages of the technical solution of the utility model are mainly reflected in:
[0017] The data information from the CPU unit and / or the processing unit is protected from interference or electrical shock by the isolation unit and the transceiver unit. When the instantaneous voltage and current are too large, only one side of one unit can be damaged at most, and the entire circuit structure will not be damaged, thereby improving the reliability and stability of communication as a whole.
[0018] The first chip and the capacitors 24 and 26 disposed on the periphery of the first chip can isolate and resist interference signals in the data during the process of receiving and transmitting data signals, thereby reducing interference during signal transmission and improving signal quality.
[0019] The data information from the first chip and / or the processing unit is filtered and transmitted through the second chip and the capacitor 36 arranged on its periphery. The second chip can effectively prevent high voltage shocks from damaging the device, thereby protecting the safety of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 : A first chip structure diagram of a preferred embodiment of the utility model;
[0021] Figure 2 : The second chip structure diagram of the preferred embodiment of the utility model. DETAILED DESCRIPTION
[0022] The purpose, advantages and features of the present invention will be illustrated and explained through the non-limiting description of the following preferred embodiments. These embodiments are only typical examples of the application of the technical solution of the present invention, and any technical solution formed by equivalent replacement or equivalent transformation falls within the scope of protection claimed by the present invention.
[0023] In the description of the scheme, it should be noted that the terms "center", "up", "down", "left", "right", "front", "back", "vertical", "horizontal", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of description and simplified description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance. Moreover, in the description of the scheme, with the operator as a reference, the direction close to the operator is the proximal end, and the direction away from the operator is the distal end.
[0024] CAN communication is a commonly used data communication protocol, which is widely used in industrial control systems, building automation, security systems and other fields. In some applications, in order to prevent electrical noise interference or electrical shock, or circuit shock of connected equipment, in order to improve system stability, safety, reliability and anti-interference ability, CAN communication is isolated. Figure 1 to Figure 2As shown, the utility model discloses a communication isolation circuit, which is arranged between the CPU unit and the processing unit 1. The communication isolation circuit at least includes an isolation unit 2 and a transceiver unit 3. The CPU unit is connected to the isolation unit 2, the isolation unit 2 is connected to the transceiver unit 3, and the transceiver unit 3 is connected to the processing unit 1. The CPU unit outputs data information, which is sequentially converted and isolated by the isolation unit 2, and transmitted by the transceiver unit 3 to the processing unit 1 for data processing, and is fed back to the CPU unit through the transceiver unit 3 and the isolation unit 2 after processing, so as to realize the interaction of data information. The isolation unit 2 reduces interference during signal transmission, thereby improving the quality of the signal. The transceiver unit 3 can effectively prevent high voltage shock from damaging the device, thereby protecting the safety of the device. The data information from the CPU unit and / or the processing unit 1 is protected from interference or electrical shock by the isolation unit 2 and the transceiver unit 3, thereby improving the reliability and stability of communication.
[0025] Specifically, Figure 1 As shown, the isolation unit 2 includes at least a first chip 21. In this application, the first chip 21 preferably adopts a digital isolator of model ADuM1281BRZ. The first pin VDD1 of the first chip 21 is the isolation side power supply voltage; it is connected in parallel with the capacitor C24 at the output end of the first power supply voltage. The first power supply voltage is +3.3V; the first chip 21 is driven to start by the first power supply voltage.
[0026] The second pin VOA of the first chip 21 and the third pin VIB of the first chip 21 are respectively connected to the I / O interface of the CPU unit. Further, the second pin V0A of the first chip 21 is a logic output A pin, connected to the signal output interface of the CPU unit; the third pin VIB of the first chip 21 is a logic input B pin, connected to the signal input interface of the CPU unit.
[0027] The output end of the capacitor C24, the fourth pin GND1 of the first chip 21 and the fifth pin GND2 of the first chip 21 are all grounded. Further, the fourth pin GND1 of the first chip 21 is the isolation side ground 1; the fifth pin GND2 of the first chip 21 is the isolation side ground 2.
[0028] The sixth pin VOB of the first chip 21 and the seventh pin VIA of the first chip 21 are respectively connected to the transceiver unit 3. The sixth pin VOB of the first chip 21 is a logic output B pin, electrically connected to the transceiver unit 3; the seventh pin VIA of the first chip 21 is a logic input A pin, electrically connected to the transceiver unit 3.
[0029] The eighth pin VDD2 of the first chip 21 is the isolation side power supply voltage, which eventually outputs the second power supply voltage; in the present application, the second power supply voltage is preferably designed as a +5V voltage. A capacitor C26 is connected between the output end of the second power supply voltage and the fifth pin GND2 of the first chip 21. The first chip 21 and the capacitors 24 and 26 arranged on the periphery of the first chip 21 can isolate and resist interference signals in the data during the process of receiving and transmitting data signals, thereby improving the stability and reliability of data transmission.
[0030] Further, such as Figure 2 As shown, the transceiver unit 3 at least includes a second chip 31; in the present application, the second chip 31 preferably adopts a TJA1051T / 3 transceiver. The first pin TXD of the second chip 31 is a data input pin, which is connected to the seventh pin VIA of the first chip 21 to realize the transmission of CPU data from the first chip 21 to the second chip 31, or the data on the processing unit 1 from the second chip 31 to the first chip 21.
[0031] The fourth pin RXD of the second chip 31 is a data output pin, which is electrically connected to the sixth pin VOB of the first chip 21 to realize the transmission of CPU data from the first chip 21 to the second chip 31, or the transmission of data on the processing unit 1 from the second chip 31 to the first chip 21.
[0032] The third pin VCC of the second chip 31 is a power supply voltage pin of the second chip 31 , and is connected in parallel with the fifth pin VIO of the second chip 31 , ie, the power supply voltage pin of the second chip 31 , at the output end of the second power supply voltage.
[0033] The second pin GND of the second chip 31 is grounded and is a ground pin. The sixth pin CANL of the second chip 31 is a low-level bus pin, and the processing unit 1 is connected to the output end of the sixth pin CANL and the seventh pin CANH (high-level bus pin) of the second chip 31 .
[0034] The eighth pin S of the second chip 31 is a control input pin, which is connected to the output end of the second power supply voltage through a resistor R120 . The resistor R120 is connected in parallel with the ground line of the second chip 31 .
[0035] Furthermore, the transceiver unit 3 further includes a capacitor C36; the input end of the capacitor C36 is connected in parallel with the fifth pin VIO of the second chip 31 and is arranged at the output end of the second power supply voltage, and the output end of the capacitor C36 is connected in parallel with the resistor R120 and the ground wire. The data information from the first chip 21 and / or the processing unit 1 is filtered and transmitted through the second chip 31 and the capacitor 36 arranged on its periphery, and the second chip 31 can effectively prevent high voltage shock from damaging the device, thereby protecting the safety of the device.
[0036] It can be seen that the first chip in the isolation unit 2 and the second chip in the transceiver unit 3 both have isolation and transceiver functions, and can realize bidirectional data transmission. Once the instantaneous voltage or current is too large, the external interference and damage can be effectively isolated and controlled on one side through the filtering modules on the periphery of the two chips and any one of the isolation sides of the isolation unit, and will not continue to extend to the CPU unit or processing unit 1, so as not to affect and cause the entire circuit structure to be paralyzed, which can buy a certain amount of time for repairing the circuit to a certain extent.
[0037] like Figure 2 As shown, at least a filtering module 41 is provided between the transceiver unit 3 and the processing unit 1. The filtering module 41 includes a resistor R121, a resistor R122, a resistor R123 and a resistor R124, and a capacitor C79. Among them, the resistor R121 and the resistor R124 are arranged in parallel at the output end of the sixth pin CNAL of the second chip 31. The resistor R122 and the resistor R123 are arranged in parallel at the output end of the seventh pin CANH of the second chip 31; and the output ends of the resistor R121 and the resistor R122 are connected to the input end of the capacitor C79. The output end of the capacitor C79 is connected to the ground wire. The data output by the transceiver unit 3 or the data output by the processing unit 1 is filtered by the filtering module 41 to isolate the interference caused by electrical noise and electrical impact on data transmission, thereby improving the reliability and stability of the system.
[0038] Furthermore, an overvoltage protection module 42 is also provided between the transceiver unit 3 and the processing unit 1. The overvoltage protection module 42 includes two TVS tubes, wherein the input end of the first TVS tube 421 is connected to the output end of the resistor R124. The input end of the second TVS tube 422 is connected to the output end of the resistor 123. The output ends of the first TVS tube 421 and the second TVS tube 422 are connected to the ground line. The two TVS tubes are used to perform overvoltage protection on the voltage exceeding 1000V in the circuit, and the overloaded voltage is transmitted to the ground line, effectively preventing the high-voltage shock from damaging the first chip or the second chip in the circuit, thereby protecting the safety of the circuit.
[0039] like Figure 2 As shown, the processing unit 1 includes three pins, the first pin of the processing unit 1 is connected in parallel with the second TVS tube 421 and arranged at the output end of the resistor 123, and the second pin of the processing unit 1 is connected in parallel with the first TVS tube 422 and arranged at the output end of the resistor 124. The third pin of the processing unit 1 is connected to the ground wire. The processing unit 1 is electrically connected to the first chip 21, the second chip 31 and the CPU unit to achieve effective data transmission and interaction.
[0040] There are many implementation methods of the utility model, and all technical solutions formed by equivalent transformation or equivalent transformation fall within the protection scope of the utility model.
Claims
1. A communication isolation circuit, provided between the CPU unit and the processing unit (1); Features: The device comprises an isolation unit (2) and a transceiver unit (3); the CPU unit is connected to the isolation unit (2), the isolation unit (2) is connected to the transceiver unit (3), and the transceiver unit (3) is connected to the processing unit (1); the CPU unit outputs data information, which is sequentially converted and isolated by the isolation unit (2), and transmitted by the transceiver unit (3) to the processing unit (1) for data processing, and after processing, is fed back to the CPU unit through the transceiver unit (3) and the isolation unit (2), thereby realizing data information interaction.
2. The communication isolation circuit according to claim 1, Features: The isolation unit (2) comprises at least a first chip (21); a first pin VDD1 of the first chip (21) and a capacitor C24 are arranged in parallel at an output end of a first power supply voltage; a second pin VOA of the first chip (21) and a third pin VIB of the first chip (21) are respectively connected to an I / O interface of the CPU unit; the capacitor C24, a fourth pin GND1 of the first chip (21) and a fifth pin GND2 of the first chip (21) are all grounded; a sixth pin VOB of the first chip (21) and a seventh pin VIA of the first chip (21) are respectively connected to the transceiver unit (3); and an eighth pin VDD2 of the first chip (21) outputs a second power supply voltage.
3. The communication isolation circuit according to claim 2, Features: The first power supply voltage is a +3.3V voltage; the first pin VDD1 of the first chip (21) is the isolation side power supply voltage; the eighth pin VDD2 of the first chip (21) is the isolation side power supply voltage; the second pin V0A of the first chip (21) is a logic output A pin, connected to the signal output interface of the CPU unit; the seventh pin VIA of the first chip (21) is a logic input A pin; the third pin VIB of the first chip (21) is a logic input B pin, connected to the signal input interface of the CPU unit; the sixth pin VOB of the first chip (21) is a logic output B pin; the fourth pin GND1 of the first chip (21) is the isolation side ground one; the fifth pin GND2 of the first chip (21) is the isolation side ground two; and the second power supply voltage is a +5V voltage.
4. The communication isolation circuit according to claim 3, Features: A capacitor C26 is connected between the output end of the second power supply voltage and the fifth pin GND2 of the first chip (21).
5. The communication isolation circuit according to claim 2, Features: The transceiver unit (3) comprises at least a second chip (31); a first pin TXD of the second chip (31) is connected to a seventh pin VIA of the first chip (21); a fourth pin RXD of the second chip (31) is connected to a sixth pin VOB of the first chip (21); a third pin VCC of the second chip (31) and a fifth pin VIO of the second chip (31) are arranged in parallel at an output end of the second power supply voltage; a second pin GND of the second chip (31) is grounded; a sixth pin CANL of the second chip (31) and a seventh pin CANH of the second chip (31) are connected to the processing unit (1) at output ends; an eighth pin S of the second chip (31) is connected to the output end of the second power supply voltage via a resistor R120, and the resistor R120 is arranged in parallel with a ground line of the second chip (31).
6. The communication isolation circuit according to claim 5, Features: The first pin TXD of the second chip (31) is a data input pin; the second pin GND of the second chip (31) is a ground pin; the third pin VCC of the second chip (31) is a power supply voltage pin of the second chip (31); the fourth pin RXD of the second chip (31) is a data output pin; the fifth pin of the second chip (31) is a power supply voltage pin; the sixth pin CANL of the second chip (31) is a low-level bus pin; the seventh pin CANH of the second chip (31) is a high-level bus pin; and the eighth pin S of the second chip (31) is a control input pin.
7. The communication isolation circuit according to claim 6, Features: The transceiver unit (3) further comprises a capacitor C36; an input end of the capacitor C36 is connected in parallel with a fifth pin VIO of the second chip (31) and arranged at an output end of the second power supply voltage, and an output end of the capacitor C36 is connected in parallel with the resistor R120 and the ground line.
8. The communication isolation circuit according to claim 5, Features: At least a filtering module (41) is arranged between the transceiver unit (3) and the processing unit (1); the filtering module (41) comprises a resistor R121, a resistor R122, a resistor R123 and a resistor R124, and a capacitor C79; the resistor R121 and the resistor R124 are arranged in parallel at the output end of the sixth pin CNAL of the second chip (31); the resistor R122 and the resistor R123 are arranged in parallel at the output end of the seventh pin CANH of the second chip (31); and the output ends of the resistor R121 and the resistor R122 are connected to the input end of the capacitor C79; and the output end of the capacitor C79 is connected to the ground line.
9. The communication isolation circuit according to claim 8, Features: An overvoltage protection module (42) is also provided between the transceiver unit (3) and the processing unit (1); the overvoltage protection module (42) comprises two TVS tubes, wherein the input end of the first TVS tube (421) is connected to the output end of the resistor R124; the input end of the second TVS tube (422) is connected to the output end of the resistor 123; and the output ends of the first TVS tube (421) and the second TVS tube (422) are connected to the ground line.
10. The communication isolation circuit according to claim 9, Features: The processing unit (1) comprises three pins, a first pin of the processing unit (1) and the second TVS tube (422) are arranged in parallel at the output end of the resistor 123; a second pin of the processing unit (1) and the first TVS tube (421) are arranged in parallel at the output end of the resistor 124; and a third pin of the processing unit (1) is connected to the ground wire.