Semiconductor device

Abstract

The utility model relates to a semiconductor device. The semiconductor device comprises a substrate of a first conductivity type, a first well region of the first conductivity type implanted on the back surface of the substrate, and a second well region of a second conductivity type implanted on the front surface of the substrate. The first well region is provided with a first doped region of a first conductive type and a second doped region of a second conductive type, and the second well region is provided with a third doped region of the second conductive type. Each of the plurality of grooves formed in the front surface of the substrate is overlapped with the polar plate in the direction perpendicular to the substrate. A transient voltage applied to the conductive material in the trench and a third doped region in the second well region is released by a bipolar transistor which is triggered and conducted and is located among the second doped region, the substrate and the third doped region under the condition that a node between the clamping region and the connection region is guided to be reversely broken down.

Description

Technical Field

[0001] The utility model mainly relates to the technical field of storage management, and more specifically, to a semiconductor device for protecting a storage hard disk during hot plugging of the storage hard disk. Background Art

[0002] Network storage, storage servers, or cloud service stations all use multiple disk slots in large quantities, so that hard disks can be easily hot-swapped at the disk slots when storage capacity expansion or storage capacity reduction is required. In a server networked with dozens or even hundreds of disk slots, the sudden hot-swapping of hard disks will increase the probability of hard disk failure and cause hard disk damage. If the hard disk data port is not properly protected during hot-swapping, the data will also be destroyed or deleted during the hot-swapping process.

[0003] For objects such as hard disk ports that are hot-plugged, the sudden voltage surge or sudden voltage drop at the port at the moment of hot-plugging can easily damage the port. The transient voltage change at the port caused by hot-plugging will not only damage the port and the electronic components connected to the port, but also seriously damage the storage particles and other components. The data lost during hot-plugging is often almost impossible to recover. This is one of the serious problems that need to be solved urgently. Utility Model Content

[0004] The present application relates to a semiconductor device, characterized in that it comprises:

[0005] A substrate of a first conductivity type, a first well region of the first conductivity type implanted on a back side of the substrate, and a second well region of a second conductivity type implanted on a front side of the substrate;

[0006] A plurality of grooves are formed on the front surface of the substrate, wherein an insulating layer is attached to the inner wall of the groove and a conductive material is filled in the groove;

[0007] A plate is arranged on the back of the substrate, and each groove overlaps with the plate in a direction perpendicular to the substrate;

[0008] a first doping region of the first conductivity type located in the first well region and disposed on the back side of the substrate and a second doping region of the second conductivity type, and a third doping region of the second conductivity type located in the second well region and disposed on the front side of the substrate;

[0009] A clamping region of the second conductivity type contacting the electrode plate disposed on the back side of the substrate, and a connecting region of the first conductivity type extending from the clamping region to the first well region;

[0010] The transient voltage applied to the conductive material and the third doped region is released by a bipolar transistor that is triggered to conduct and is located between the second doped region, the substrate and the third doped region, under the condition of inducing the node between the clamping region and the connection region to be reversely broken down.

[0011] The semiconductor device described above, wherein a top metal layer is disposed on the front side of the substrate, the top metal layer contacts the third doped region and the conductive material, and the transient voltage is connected to the top metal layer;

[0012] A bottom metal layer is disposed on the back side of the substrate, the bottom metal layer contacts the first doping region and the second doping region, and the bottom metal layer is connected to a reference ground.

[0013] The above-mentioned semiconductor device is covered with a top dielectric layer on the front side of the substrate, which exposes a local area of ​​the top metal layer to serve as a port for receiving transient voltage; and is covered with a bottom dielectric layer on the back side of the substrate, which exposes a local area of ​​the bottom metal layer to serve as a port for receiving the reference ground.

[0014] The semiconductor device mentioned above has a bottom dielectric layer covering the back side of the substrate, which exposes a partial area of ​​the plate to serve as a port for receiving the transient voltage, and the transient voltage is connected to the plate through a resistor.

[0015] The semiconductor device mentioned above is electrically connected to the plug-in terminal of the hard disk, wherein the transient voltage is the sudden change voltage that the plug-in terminal of the hard disk is subjected to during the hot plug event stage.

[0016] The semiconductor device further comprises one or more buried regions of the second conductivity type disposed on the back side of the substrate, the buried regions contacting the electrode plate and being located in the substrate region between the plurality of trenches and the electrode plate.

[0017] The above-mentioned semiconductor device also includes a fourth doped region of the first conductivity type located in the second well region and arranged on the front side of the substrate; when the bipolar transistor between the second doped region, the substrate, and the third doped region is triggered to turn on, the current under its on-condition triggers another bipolar transistor between the fourth doped region, the second well region, and the substrate to turn on.

[0018] In the above-mentioned semiconductor device, the first well region and the second well region are respectively located on different sides of a designated area of ​​the substrate for arranging multiple grooves and do not overlap each other, so that the current when any bipolar transistor is turned on has at least a lateral path that flows laterally through the gap area of ​​the substrate located between the multiple grooves.

[0019] The semiconductor device further comprises a body region of the second conductivity type disposed on the front surface of the substrate, wherein the trench penetrates downward through the body region; and

[0020] It also includes a metal plug located between adjacent grooves and disposed on the front side of the substrate, wherein a metal plug between any two adjacent grooves extends downward in the body region but does not extend to the substrate below the body region;

[0021] The transient voltage is also applied to the metal plug at the same time.

[0022] The present application also relates to a method for protecting a hard disk during hot plugging of the hard disk, characterized in that a semiconductor device is used to release the transient voltage of the plug-in terminal of the hard disk during the hot plugging event:

[0023] The semiconductor device comprises:

[0024] A substrate of a first conductivity type, a first well region of the first conductivity type implanted on a back side of the substrate, and a second well region of a second conductivity type implanted on a front side of the substrate;

[0025] A plurality of grooves are formed on the front surface of the substrate, wherein an insulating layer is attached to the inner wall of the groove and a conductive material is filled in the groove;

[0026] A plate is arranged on the back of the substrate, and each groove overlaps with the plate in a direction perpendicular to the substrate;

[0027] a first doping region of the first conductivity type located in the first well region and disposed on the back side of the substrate and a second doping region of the second conductivity type, and a third doping region of the second conductivity type located in the second well region and disposed on the front side of the substrate;

[0028] A clamping region of the second conductivity type contacting the electrode plate disposed on the back side of the substrate, and a connecting region of the first conductivity type extending from the clamping region to the first well region;

[0029] The transient voltage applied to the conductive material and the third doped region is released by a bipolar transistor that is triggered to conduct and is located between the second doped region, the substrate, and the third doped region under the condition of inducing a reverse breakdown of the node between the clamping region and the connection region;

[0030] The method includes:

[0031] Performing hot plugging on the hard disk, when the semiconductor device is connected to the hard disk, treating a surge voltage generated by a plug-in terminal of the hard disk in a hot plugging event as the transient voltage;

[0032] The transient voltage is coupled to the node between the clamping region and the connecting region by utilizing the capacitance between the electrode plate and the conductive materials in the plurality of trenches, so as to trigger the bipolar transistor to be turned on.

[0033] In the above method, a top metal layer is disposed on the front side of the substrate, which contacts the third doped region and the conductive material, and the transient voltage is connected to the top metal layer;

[0034] A bottom metal layer is disposed on the back side of the substrate, the bottom metal layer contacts the first doping region and the second doping region, and the bottom metal layer is connected to a reference ground.

[0035] In the above method, the front side of the substrate is covered with a top dielectric layer, which exposes a local area of ​​the top metal layer to serve as a port for receiving transient voltage; the back side of the substrate is covered with a bottom dielectric layer, which exposes a local area of ​​the bottom metal layer to serve as a port for receiving the reference ground.

[0036] In the above method, the back side of the substrate is covered with a bottom dielectric layer, which exposes a local area of ​​the electrode plate to serve as a port for receiving the transient voltage, and the transient voltage is connected to the electrode plate through a resistor.

[0037] In the above method, the semiconductor device is electrically connected to the plug-in terminal of the hard disk, wherein the transient voltage is the sudden change voltage borne by the plug-in terminal of the hard disk during the hot plug event stage.

[0038] The above method further includes one or more buried regions of the second conductivity type disposed on the back side of the substrate, wherein the buried regions contact the electrode plate and are located in the substrate region between the plurality of trenches and the electrode plate.

[0039] The above method also includes a fourth doped region of the first conductivity type located in the second well region and arranged on the front side of the substrate; when the bipolar transistor between the second doped region, the substrate, and the third doped region is triggered to turn on, the current under its on-condition triggers another bipolar transistor between the fourth doped region, the second well region, and the substrate to further turn on.

[0040] In the above method, the first well region and the second well region are respectively located on different sides of a designated area of ​​the substrate for arranging multiple grooves and do not overlap each other, so that the current when any bipolar transistor is turned on has at least a lateral path that flows laterally through the gap area of ​​the substrate located between the multiple grooves.

[0041] The above method further includes a body region of the second conductivity type disposed on the front side of the substrate, wherein the trench penetrates downward through the body region; and

[0042] It also includes a metal plug located between adjacent grooves and disposed on the front side of the substrate, wherein a metal plug between any two adjacent grooves extends downward in the body region but does not extend to the substrate below the body region;

[0043] The transient voltage is also applied to the metal plug at the same time.

[0044] One of the advantages of this application: For hard disks that are frequently hot-plugged, even if there is a high probability of occasional voltage increase or voltage drop in the hardware interface, since the semiconductor device of this application can generate a discharge path by triggering the bipolar transistor to be turned on when facing such voltage, the disturbance of the hardware interface by the occasional flicker voltage caused by hot plugging will be eliminated in a short time. The damage to the hot-plug interface of the hard disk or host can be prevented. The probability of data loss in the hard disk during hot plugging is also greatly reduced, for example, to avoid surge damage to storage particles.

[0045] The second advantage of the present application is that the semiconductor device is extremely sensitive to the voltage change caused by hot plugging. First, the high-speed release and pressure relief of the high-frequency flickering voltage is guaranteed in a high-priority manner, while at the same time, the low-frequency slow-changing voltage is guaranteed at a low-priority manner. In other words, the high-frequency component and the low-frequency component of the changing voltage such as the transient voltage related to hot plugging each have a reasonable and effective release path.

[0046] The third advantage of the present application is that the semiconductor device has a self-protection mechanism based on limited avalanche to activate the discharge path against the irresistible voltage caused by hot plugging. In other words, when the semiconductor device is applied with an irresistible voltage that is sufficient to damage itself and the hard disk, its protection mechanism will be triggered to avoid the occurrence or expansion of damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0048] Figure 1 A schematic diagram of the internal physical structure of a semiconductor device and the related circuit architecture is shown.

[0049] Figure 2 A discharge path for high-frequency and low-frequency components of the voltage change caused by hot plugging is reserved.

[0050] Figure 3 It is a semiconductor device that integrates a pair of bipolar transistors to serve as a current path for voltage relief.

[0051] Figure 4The semiconductor device integrates a metal plug and applies a transient voltage to the metal plug.

[0052] Figure 5 It is the effect of metal plugs on the lateral current paths of a pair of bipolar transistors.

[0053] Figure 6 It is the regulating effect of one or more buried regions of the contact plate on the capacitance value in the trench.

[0054] Figure 7 The groove cluster uses multiple rows of grooves arranged side by side and the single row of grooves is long and narrow.

[0055] Figure 8 The groove cluster uses a groove matrix distributed in multiple rows and columns and the grooves are square. DETAILED DESCRIPTION

[0056] The technical solutions disclosed in the present application will be clearly and completely described below in conjunction with specific embodiments. However, the embodiments described are only embodiments used for narrative explanation in the present application and are not all embodiments. Based on these embodiments, technicians in this field should realize that any solution obtained without creative work falls within the scope of protection of the present application.

[0057] See also Figure 1 , assuming that hot-plugging (Hot-Plug or Hot-Swap) occurs between the hot-plug terminal IO_HP and the hot-plug slot IO_SL, for example, the terminal IO_HP is inserted and docked into the slot IO_SL. Hot-plugging is powered plugging and allows the insertion, replacement or removal of components such as hard disks without shutting down the system or cutting off the power, thereby improving the scalability and flexibility of the storage system for data operations and the ability to restore data in a timely manner. For example, disk mirroring systems for complex applications basically need to be equipped with hot-plug functions for hard disks or disks. Hot-plug technology is a key technology for achieving continuous power operation and non-stop maintenance in the storage field. Hot-plugging is the most effective and stable way to improve the robustness and reliability of storage systems by performing redundant backup of key storage data, replacing failed hard disks and expanding the system without interrupting the operation of the storage system. Therefore, hard disk hot-plugging technology has received more and more attention.

[0058] See also Figure 1 For example, IO_SL (I / O Slots) represents a hot-swappable slot or jack or port or terminal or metal contact end of a computer, a computer, a supercomputing device, a server, or any similar electronic device.

[0059] See also Figure 1For example, IO_HP (I / O Hot-Plug) represents a hot-swap port or terminal or metal contact end of a storage device such as a memory card, a mobile hard disk, a solid-state drive, a mechanical hard disk, or any similar storage device.

[0060] See also Figure 1 , the traditional hot-swap circuit for storage services has many disadvantages: when a storage service such as a circuit board carrying a hard disk is hot-plugged into the entire storage system, the surge voltage generated by the hot-plugging cannot be suppressed. This instantaneous high voltage and high current will directly impact the electronic components and hard disk at the back end of the circuit board, causing direct damage to the components at the back end of the circuit board or reducing the service life of the components. Hard disks basically use flash memory storage particles. At the moment of hot-plugging the hard disk, the sudden voltage surge or sudden voltage drop at the I / O plug-in terminals such as the data port or power supply port of the hard disk can easily flow into the storage particles through the plug-in terminals and damage the storage particles.

[0061] See also Figure 1 , assuming that the terminal IO_HP is inserted and docked into the slot IO_SL, to achieve hot plugging, it is necessary to control the transient surge current on the plug-in terminal of the hard disk (taking IO_HP as an example) to a relatively low level. The plug-in terminal of the hard disk mentioned in the context of this application represents the object of the hard disk that needs to be protected, so the plug-in terminal of the hard disk mentioned here can also be replaced by the protected plug-in terminal of the hard disk, the hot plug terminal with electricity, and other terms. The protection mechanism of the plug-in terminal of the hard disk needs to be electrically connected to the semiconductor device shown in the figure, as described below.

[0062] See also Figure 1 The reason why the plug-in terminal represents the object to be protected of the hard disk is that if the voltage applied level of all the protected objects such as the hard disk power supply terminal or communication terminal, command receiving and sending terminal, bus terminal, signal terminal, data input and output terminal, address terminal, etc. is within the calibration range (i.e. tolerance range or safety specification), then there will be no accidents in the hot-swap event of the plug-in terminal. When the replaceable hard disk mode is added to the storage hot-swap design, the applied voltage of the plug-in terminal should be designed to be limited within the calibration range, which is the main function of the semiconductor device below. The transient surge current or surge voltage on the plug-in terminal is limited to a lower level, such as within the calibration range, avoiding the damage to the electronic components or data loss caused by the hot-swap process to the hard disk itself.

[0063] See also Figure 1The previous article describes the harm of hot plugging at the terminal IO_HP, that is, the hard disk. However, in fact, the impact of hot plugging is not only on the hard disk to which the terminal IO_HP belongs, but also causes a certain degree of harm to the storage system (such as cloud storage, storage server, computer, etc.) that receives the hard disk at the slot IO_SL. When the hard disk is inserted instantly, the power of the storage system will drop sharply instantly, because the hard disk and its carrier circuit board will extract the power supply for themselves from the storage system from the moment of insertion, and there is a high probability that the low voltage protection of the system will be triggered and abnormal shutdown will occur. Therefore, it is better to avoid the power fluctuation harm brought to the entire storage system by the hot plugging process to achieve the purpose of hot plugging.

[0064] See also Figure 1 In an optional embodiment, the preparation of the semiconductor device in this article is based on a wafer process such as a power semiconductor process and is prepared on an epitaxial layer or substrate PS including a first conductivity type. The first conductivity type is assumed to be a P-type semiconductor or a P conductivity type, the first and second conductivity types are relative or opposite, and the second conductivity type is assumed to be an N-type semiconductor or an N conductivity type. The first and second conductivity types can also be interchanged with each other, the first conductivity type is assumed to be an N-type semiconductor or an N conductivity type, the first and second conductivity types are relative or opposite, and the second conductivity type is assumed to be a P-type semiconductor or a P conductivity type. The aforementioned relationship between the first and second conductivity types applies to the context of this application.

[0065] See also Figure 1 In an optional embodiment, a first well region of a first conductivity type is implanted on the back side of the substrate PS, and the first well region can be represented by PW, and the implanted dopant can be based on a P-type semiconductor material. The back side implantation can adopt a conventional ion implantation process, and it can be seen that the present application can be implemented based on the existing semiconductor process in the industry, for example, the preparation process of a power metal oxide semiconductor device Power-MOSFT is one of the optional solutions.

[0066] See also Figure 1 In an optional embodiment, the second well region of the second conductivity type is implanted on the front side of the substrate PS and the second well region can be represented by NW, and the implanted dopant can be based on N-type semiconductor material. The front side implantation can adopt the conventional ion implantation process, which shows that the present application can be implemented based on the existing semiconductor process in the industry, for example, the preparation process of the power metal oxide semiconductor device Power-MOSFT is one of the optional solutions.

[0067] See also Figure 1 The semiconductor device includes a substrate PS of a first conductivity type, a first well region 20 of the first conductivity type implanted on the back side of the substrate PS, and a second well region 10 of a second conductivity type implanted on the front side of the substrate PS. In a direction perpendicular to the substrate, i.e., in a vertical direction, the first well region 20 and the second well region 10 do not overlap or overlap each other.

[0068] See also Figure 1 The semiconductor device includes a plurality of trenches 70 formed on the front surface of the substrate PS, an insulating layer 71 is attached to the inner wall of the trench 70, and a conductive material 72 is filled inside the trench 70. The insulating layer formed on the inner wall (sidewall) of the trench 70 is, for example, oxide, and the insulating layer 71 is usually made of insulating materials such as silicon dioxide, silicon nitride, or silicate glass.

[0069] See also Figure 1 In an optional embodiment, the interior of the originally hollow groove 70 formed by etching is first filled with an insulating material and then the insulating material is etched back, leaving only a thin layer of residual insulating material on the inner wall of the groove 70, and the residual insulating material is regarded as a layer of insulating layer 71 attached to the inner wall of the groove. After that, the conductive material 72 is continuously filled into the groove by deposition and the excess material is removed by etching back and only the conductive material 72 in the groove 70 is retained. The deposition method of the conductive material includes chemical vapor deposition and physical vapor deposition. The conductive material 72 can be, for example, a doped semiconductor material or doped single crystal silicon or polycrystalline silicon or even a metal material. Different grooves 70 are spaced apart, but the conductive materials 72 in each of the different grooves can have an equal potential relationship that is electrically connected to each other.

[0070] See also Figure 1 In an optional embodiment, a plurality of grooves 70 are arranged in a designated area or a predetermined area or a delimited area of ​​the substrate PS. The designated area is, for example, a relatively central area or a corner area of ​​the substrate PS. According to the conventional wafer preparation process, the substrate is usually square or rectangular, that is, the shape of the substrate PS after the wafer is diced. If the semiconductor device is an independent discrete device and is not integrated with other integrated circuits, then in the optional example, the designated area is preferably the central area of ​​the substrate. If the semiconductor device is a sub-functional module of a chip and needs to be integrated with other integrated circuits such as a flash memory with a storage transistor array, for example, the storage transistor array and the semiconductor device are prepared on a common chip or wafer, then the designated area is preferably a corner area or an edge area of ​​the substrate, because the storage transistor array and its auxiliary circuits that occupy most of the substrate area usually occupy the central area of ​​the substrate, etc.

[0071] See also Figure 1 , a plurality of trenches 70 are opened on the front side of the substrate PS inside the semiconductor device: the depth of the trench 70 extends from the front side of the substrate PS downward to close to the back side of the substrate PS but does not reach the back side of the substrate. As shown in the figure, the depth of the trench 70 is less than the thickness of the substrate PS, and a certain distance is left between the bottom of the trench and the back side of the substrate. The implantation depth of the first well region 20 and the second well region 10 in the substrate PS is much smaller than the opening depth of the trench 70.

[0072] See also Figure 1 The semiconductor device includes a plate 66 disposed on the back of the substrate PS. The position of the plate 66 is approximately the aforementioned designated area, predetermined area or demarcated area of ​​the substrate PS. The positions of the plate 66 and the groove 70 are, for example, substantially the same position of the substrate PS: such as the center area, the edge area or the corner area. The material of the plate 66 typically includes metal materials such as copper, aluminum, titanium, or semiconductor materials such as polycrystalline silicon and single crystal silicon, such as silicon alloy materials such as silicon titanium or nitrogen silicon titanium, and metal alloy materials such as aluminum copper alloy.

[0073] See also Figure 1 , each groove 70 overlaps with the electrode 66 in the direction perpendicular to the substrate PS: that is, as shown in the figure, each groove 70 and the electrode 66 overlap each other in the direction perpendicular to the substrate PS. Note that some capacitor symbols are marked in the figure, and the capacitor 73 is formed by the conductive material 72 inside the groove 70 and the electrode 66. Ways to adjust the capacitance value under less precise adjustment include: reducing the distance between the bottom of the groove 70 and the electrode 66, or increasing the tiling area of ​​the electrode 66, or increasing the number of grooves 70, or increasing the density of the distribution of the grooves 70 in a specified area, or reducing the thickness of an insulating layer 71 on the inner wall of the groove 70, and so on.

[0074] See also Figure 1, the semiconductor device includes a first doping region 25 of a first conductivity type located in the first well region 20 and arranged on the back side of the substrate PS and a second doping region 21a-21b of a second conductivity type. The first doping region 25 is implanted at the back side of the substrate PS and into a local area in the first well region 20 using a P conductivity type dopant. As shown in the figure, the implantation depth of the first doping region 25 is shallower than the implantation depth of the first well region 20. The second doping region 21a-21b is implanted at the back side of the substrate PS and into a local area in the first well region 20 using a N conductivity type dopant. As shown in the figure, the second doping region 21a-21b is divided into two parts 21a and 21b, and their doping concentrations are different. The doping concentration of the sub-part 21a is set to be much greater than the doping concentration of the sub-part 21b. The second sub-part 21b contacts and adjoins the first sub-part 21a from the substrate PS region, such as the second sub-part 21b extending from the first sub-part 21a into the substrate. In addition, the two parts of the second doping region 21a-21b, so-called 21a and 21b, can be regarded as a combined whole. In this case, the second doping regions 21a-21b directly extend from the back side of the substrate PS to the inside of the substrate PS above the first well region 20. The doping concentrations of the optional second doping regions 21a-21b, so-called 21a and 21b, are the same or similar, and in this case, the difference in doping concentrations of the second doping regions 21a-21b, 21a and 21b, is within a preset fluctuation range.

[0075] See also Figure 1 The semiconductor device has a first doping region 25 of the first conductivity type located in the first well region 20 and arranged on the back side of the substrate PS, and second doping regions 21a-21b of the second conductivity type: local portions of the second doping regions 21a-21b extend to the inside of the substrate PS region above the first well region 20. The doping regions on the back side of the substrate are based on a back side process and their doping depth is the depth seen from the back side of the substrate PS, or the depth of ion implantation from the back side.

[0076] See also Figure 1 , the semiconductor device includes a third doped region 11 of the second conductivity type located in the second well region 10 and arranged on the front side of the substrate PS. The third doped region 11 is implanted at the front side of the substrate PS and into a local area in the second well region 10 using N conductivity type dopants, and the implantation depth of the third doped region 11 is shallower than that of the second well region 10. It will be found that the second well region 10 and the first well region 20 do not overlap in the vertical direction, and the third doped region 11 implanted in the second well region 10 and the first doped region 25 and the second doped region 21a-21b implanted in the first well region 20 do not overlap. The doped regions on the front side of the substrate are based on the front side process and their doping depth is the depth seen from the front side of the substrate PS, or the depth of ion implantation from the front side.

[0077] See also Figure 1 , the semiconductor device includes a clamping region 30 of a second conductivity type, such as an N-doped type, disposed on the back side of the substrate PS and contacting the electrode plate 66. The clamping region 30 is implanted on the back side of the substrate PS. The clamping region 30 contacts the electrode plate 66, such as usually an ohmic contact. Since the groove 70 is located in a specified area of ​​the substrate PS, the clamping region 30 is approximately located near the specified area or located near the edge of the specified area, at a peripheral position. The semiconductor device includes a first conductivity type connection region 40 disposed on the back side of the substrate PS and extending from the clamping region 30 to the first well region 20. The doping concentration of the first conductivity type, such as the P-doped type connection region 40, is slightly higher than or not much different from that of the first well region 20. A local portion of the first conductivity type connection region 40 extends to the interior of the substrate PS region on the side of the first well region 20. The first conductivity type connection region 40 can also be lower in doping concentration than the first well region 20 based on the need to change the breakdown voltage. Based on the need to change the base voltage of the bipolar transistor, the first conductive type connection region 40 can also have its doping profile directly injected into the first well region 20 without extending to the substrate PS region on the side of the first well region 20, but the connection region 40 still needs to maintain an adjacent relationship with the clamping region 30.

[0078] See also Figure 1 The semiconductor device has a second conductivity type clamping region 30 disposed on the back side of the substrate PS and contacting the plate 66. The semiconductor device also has a first conductivity type connecting region 40 disposed on the back side of the substrate PS and extending from the clamping region 30, such as extending laterally to the first well region 20.

[0079] See also Figure 1In an optional embodiment, the transient voltage INV applied to the conductive material 72 inside the groove 70 and the transient voltage INV applied to the third doping region 11 is assumed to be caused by hot plugging. The figure shows that the transient voltage INV is induced at the hot plug terminal IO_HP of the hard disk and is simultaneously transmitted to the hot plug slot IO_SL. The presence of the capacitor 73 array will respond to the high-frequency transient voltage INV, and its coupling effect will guide the so-called transient voltage INV applied to the conductive material 72 and the third doping region 11 to the node (PN-junction) between the clamping region 30 and the junction region 40. If the so-called transient voltage INV is less harmful, the voltage carried by the node is not enough to reach the breakdown voltage level. If the so-called transient voltage INV is more harmful, the voltage carried by the node is sufficient to reach the breakdown voltage level. At this time, under the condition that the node between the guiding clamping area 30 and the connecting area 40 is reversely broken down, the transient voltage INV is released by the transistor that is triggered to be turned on and is located between the second doping area 21a-21b, the substrate PS, and the third doping area 11. The transistor here is, for example, an NPN bipolar transistor. The current generated when the aforementioned node is reversely broken down will flow to the base of the bipolar transistor, such as the so-called NPN, and generate a voltage drop at the base to trigger the transistor to turn on.

[0080] See also Figure 1 In an optional embodiment, for a hard disk that is frequently hot-plugged, even if its hardware interface, such as the hot-plug terminal IO_HP or the hot-plug slot IO_SL shown in the figure, has a high probability of occasional voltage increase or voltage drop, because the semiconductor device of the present application can generate a discharge path by triggering a conductive bipolar transistor, such as a conductive NPN bipolar transistor, when facing such voltage, the occasional flicker voltage of hot plugging can eliminate the negative impact on the hardware interface in a relatively short time. Prevent the hot-plug interface of the hard disk or the host from being damaged. It also greatly reduces the probability of data loss in the hard disk during hot plugging, for example, avoiding surge damage to storage particles.

[0081] See also Figure 2In an optional embodiment, the transient voltage INV applied to the conductive material 72 inside the groove 70 and the transient voltage INV applied to the third doping region 11 are also applied to the plate 66. In other words, the transient voltage INV is electrically connected to the conductive material 72, the third doping region 11, and the plate 66 at the same time. In this embodiment, it is considered that although the transient voltage INV is a high-frequency flickering voltage in most cases, it is often mixed with a low-frequency gradual voltage in a complex environment. For example, if a ripple capacitor is configured at the hot-plug terminal or the hot-plug slot, some unpredictable low-frequency voltage components will be mixed into the transient voltage INV, and the capacitance value of the ripple capacitor also affects the fluctuation of the low-frequency voltage. Even at the moment of hot plugging, the transient voltage INV has an extremely high-frequency component, but its high-frequency component is not enough to cause the node between the clamping area and the connection area to be reversely broken down, and then the low-frequency component part with a larger voltage level mixed with the transient voltage INV is sufficient to cause a severe avalanche of the semiconductor device. Note that capacitor 73 cannot pass low frequency components.

[0082] See also Figure 2 Continuing from what was said above, for semiconductor materials, when an avalanche occurs, the electrons and holes running in the crystal will constantly collide with atoms. Through such collisions, the valence electrons bound in the covalent bonds can be released by collisions, generating free electron-hole pairs. The newly generated carriers collide with other valence electrons under the action of the electric field and generate new free electron-hole pairs. Such a chain reaction causes the number of carriers to increase in an avalanche-like manner, and this kind of collision ionization leading to breakdown is called avalanche breakdown, also known as avalanche phenomenon. The transient voltage INV is the cause of the avalanche.

[0083] See also Figure 2 As mentioned in the previous example, the transient voltage INV electrically connected to the conductive material 72 inside the groove 70 and the third doped region 11 is also electrically connected to the plate 66. As shown in the figure, the transient voltage INV is directly electrically connected to the conductive material 72, the third doped region 11, etc. The transient voltage INV is electrically connected to the plate 66 through the resistor 78, or the resistor 78 can also be removed. If the transient voltage INV has a relatively large voltage value, the resistor 78 should be used. At this time, there are two paths in the semiconductor device: a coupling path where the capacitor 73 is located, and a direct connection path where the plate 66 is located. Both paths are guiding paths for guiding the transient voltage INV to the node between the clamping region 30 and the connecting region 40.

[0084] See also Figure 2 As shown in the example in the figure, the high-frequency component of the transient voltage INV can lead the node between the clamping region 30 and the connecting region 40 to be reversely broken down through the coupling path where the capacitor 73 is located, and then the transient voltage INV is released by the transistor that is triggered to be turned on and between the second doping regions 21a-21b, the substrate PS, and the third doping region 11.

[0085] See also Figure 2 As shown in the example in the figure, the low-frequency component of the transient voltage INV can lead the node between the clamping area 30 and the connecting area 40 to be reversely broken down through the direct connection path where the electrode 66 is located, and then the transient voltage INV is released by the transistor that is triggered to conduct and is located between the second doping area 21a-21b, the substrate PS, and the third doping area 11.

[0086] See also Figure 2 In an optional embodiment, the semiconductor device is more sensitive to the changing voltage of hot plugging. First, the high-speed release and pressure relief of the high-frequency flickering voltage is guaranteed in a high-priority manner. For example, the coupling path where the capacitor 73 is located can cope with the high-frequency component of the transient voltage INV. At the same time, it also takes into account the low-priority guarantee of the sub-high-speed release and pressure relief of the low-frequency slowly changing voltage. Compared with the high-frequency components, for example, the direct connection path where the plate 66 is located can cope with the low-frequency components of the transient voltage INV. In other words, the high-frequency components and low-frequency components within the changing voltage such as the transient voltage related to hot plugging each have a reasonable and effective release path. Note Figure 2 The multi-port method is only a preferred option, and other alternative implementation schemes that do not use multiple ports will be introduced below.

[0087] See also Figure 1 , a top metal layer 54 is provided on the front side of the substrate PS. The preparation method of the top metal layer 54 is, for example, to generate a thin metal covering layer on the front side of the substrate PS by deposition, and then the metal covering layer is patterned and etched to only retain the top metal layer 54 reserved on the front side of the substrate PS. The top metal layer 54 is in electrical contact with the aforementioned third doping region 11 and the conductive material 72. As shown in the figure, the top metal layer 54 is in ohmic contact with the third doping region 11 and the top metal layer 54 is in ohmic contact with the conductive material 72. In an optional embodiment, the top metal layer 54 is preferably isolated from the substrate PS using an oxide layer, but still needs to maintain electrical contact with the third doping region and the conductive material.

[0088] See also Figure 1, the transient voltage INV at the hot-swap terminal IO_HP or the hot-swap slot IO_SL can be electrically connected to the top metal layer 54 through an additional wire or the metal wiring of the semiconductor device itself. Thus, the transient voltage can be applied to the conductive material 72 and the third doped region 11. For example, if the hot-swap terminal or the slot and the semiconductor device are laid out together on a common circuit board, the metal traces or gold fingers or metal pads of the circuit board can be interconnected to the top metal layer 54 by using patch technology, such as solder balls soldered to the top metal layer 54. The hot-swap terminal or hot-swap slot basically provides metal traces or gold fingers or metal pads connected to itself.

[0089] See also Figure 1 , a bottom metal layer 64 is provided on the back of the substrate PS. The preparation method of the bottom metal layer 64 is, for example, to generate a thin metal covering layer on the back of the substrate PS by deposition, and then the metal covering layer is patterned and etched to only retain the bottom metal layer 64 reserved on the back of the substrate PS. The bottom metal layer 64 is in electrical contact with the aforementioned first doping region 25 and the second doping region 21a-21b. The bottom metal layer 64 is in ohmic contact with the first doping region 25, and the bottom metal layer 64 is in ohmic contact with the second doping region 21a-21b. In an optional example, the bottom metal layer 64 is preferably isolated from the substrate PS using an oxide layer, but still needs to maintain electrical contact with the first doping region and the second doping region.

[0090] See also Figure 1 If the electrode 66 and the bottom metal layer 64 are made of the same material, their preparation method is, for example, to generate a thin metal covering layer on the back of the substrate PS by deposition, and then the metal covering layer is patterned and etched to only retain the bottom metal layer 64 and the electrode 66 reserved on the back of the substrate PS. It is worth noting that the bottom metal layer 64 and the electrode 66 are separated and there is no direct electrical connection between them. As shown in the figure, the bottom metal layer 64 is designed to contact the first doping region 25 and the second doping region 21a-21b, and as an option, the bottom metal layer 64 is required to be electrically connected to a reference ground, such as a GND potential.

[0091] See also Figure 1, the top dielectric layer 55 is covered on the front side of the substrate PS, and the top dielectric layer 55 is required to expose a local area of ​​the top metal layer 54 to serve as a port (I / O port) for receiving the transient voltage INV. Assuming that the local area of ​​the top metal layer 54 exposed from the top dielectric layer 55 is recorded as port IO1, the transient voltage INV can be electrically connected to port IO1 by an external wire. The preparation of the top dielectric layer 55 is, for example, to generate a thinner insulating dielectric layer on the front side of the substrate PS by deposition. Thereafter, the insulating dielectric layer is subjected to patterned etching, and the small area of ​​the insulating dielectric layer on the front side of the substrate PS that overlaps with the top metal layer 54 needs to be etched and removed, thereby forming a through hole that aligns with and exposes the top metal layer 54 at the position where the small area is removed on the insulating dielectric layer on the front side of the substrate PS. Obviously, the local area of ​​the top metal layer 54 exposed from the through hole of the top dielectric layer 55 can be regarded as port IO1. The front insulating dielectric layer can use insulating films such as silicon oxide, silicon nitride, borophosphosilicate glass, and non-doped silicate glass.

[0092] See also Figure 1 , the bottom dielectric layer 65 is covered on the back of the substrate PS, and the bottom dielectric layer 65 is required to expose a local area of ​​the bottom metal layer 64 to serve as a port (I / O port) for receiving a reference ground such as GND. Assume that the local area of ​​the bottom metal layer 64 exposed from the bottom dielectric layer 65 is recorded as port IO2, and the reference ground such as GND can be electrically connected to port IO2 by an external wire. The preparation of the bottom dielectric layer 65 is, for example, to generate a thinner insulating dielectric layer on the back of the substrate PS by deposition. Thereafter, the insulating dielectric layer is patterned and etched, and a small area of ​​the insulating dielectric layer on the back of the substrate PS that overlaps with the bottom metal layer 64 needs to be etched and removed, thereby forming a through hole aligned with and exposing the bottom metal layer 64 at the position where the small area is removed on the insulating dielectric layer on the back of the substrate PS. Obviously, the local area of ​​the bottom metal layer 64 exposed from the through hole of the bottom dielectric layer 65 can be regarded as port IO2. The back insulating dielectric layer can use insulating films such as silicon oxide, silicon nitride, borophosphosilicate glass, and non-doped silicate glass.

[0093] See also Figure 1In an optional embodiment, a top metal layer 54 is provided on the front side of the substrate PS, which contacts the third doping region 11 and the conductive material 72, and the transient voltage INV is connected to the top metal layer 54. For example, IO1 can be used as the place where the top metal layer 54 is connected to the transient voltage INV. A bottom metal layer 64 is provided on the back side of the substrate PS, which contacts the first doping region 25 and the second doping region 21a-21b. The bottom metal layer 64 is connected to the reference ground GND. For example, IO2 can be used as the place where the bottom metal layer 64 is connected to the reference ground GND. In an optional example, the bottom metal layer 64 and the electrode plate 66 are preferably isolated from the substrate PS using an oxide layer, but the bottom metal layer 64 still needs to maintain an electrical contact relationship with the first doping region and the second doping region, and the electrode plate 66 still needs to maintain an electrical contact relationship with the clamping region 30.

[0094] See also Figure 1 In an optional embodiment, the front side of the substrate PS is covered with a top dielectric layer 55, which exposes a local area of ​​the top metal layer 54 to serve as a port such as IO1 for receiving the transient voltage INV. The back side of the substrate PS is covered with a bottom dielectric layer 65, which exposes a local area of ​​the bottom metal layer 64, and the exposed local area of ​​the bottom metal layer 64 serves as a port such as IO2 for receiving the reference ground such as GND.

[0095] See also Figure 2 , because the back of the substrate PS is covered with a bottom dielectric layer 65, the bottom dielectric layer 65 exposes a partial area of ​​the plate 66 as a port (I / O port) for receiving the transient voltage INV. The partial area of ​​the plate 66 exposed from the bottom dielectric layer 65 is recorded as port IO3, and the transient voltage INV can also be electrically connected to port IO3 by an external wire. The preparation of the bottom dielectric layer 65 is, for example, to first generate a thinner insulating dielectric layer on the back of the substrate PS by deposition. Thereafter, the insulating dielectric layer is patterned and etched, and the small area of ​​the insulating dielectric layer on the back of the substrate PS that overlaps with the plate 66 needs to be etched and removed, thereby forming a through hole that aligns with and exposes the plate 66 at the position where the small area is removed on the insulating dielectric layer on the back of the substrate PS, and then the partial area of ​​the plate 66 exposed from the through hole of the bottom dielectric layer 65 can be regarded as the port IO3. Ports IO3 and IO2 are etched from the same back insulating dielectric layer, so they can be prepared simultaneously.

[0096] See also Figure 2In an optional embodiment, the back of the substrate PS is covered with a bottom dielectric layer 65, and the bottom dielectric layer exposes a partial area of ​​the electrode plate 66 to serve as a port such as IO3 for receiving the transient voltage INV. As an option, the transient voltage INV is electrically connected to the electrode plate 66 at the port such as IO3 through a resistor 78. As an option, the transient voltage INV removes the aforementioned resistor 78 and is directly connected to the electrode plate 66 at the port such as IO3.

[0097] See also Figure 1 In an optional embodiment, a storage hard disk such as HDD or SSD based on an interface type such as SPI, USB, SATA, PCIE, or other interface types not listed has a hot plug terminal IO_HP, and the semiconductor device is electrically connected to the hot plug terminal IO_HP of the storage hard disk. The transient voltage INV is a voltage flicker or surge voltage that the hard disk plug terminal IO_HP withstands during the hot plug event phase. The aforementioned ports of the semiconductor device, such as IO1 or IO3, can all be electrically connected to the hot plug terminal IO_HP of the storage hard disk.

[0098] See also Figure 1 In an optional embodiment, the transient voltage INV is coupled to the node between the clamping region 30 and the junction region 40 through the capacitor 73 between the plate 66 and the conductive material 72 filled in the groove 70. The node will undergo reverse breakdown under the impact of the transient voltage INV, and the actual voltage applied to the node (PN-junction) by the transient voltage through the capacitor exceeds the reverse breakdown voltage value of the PN junction. If the actual voltage applied to the node by the transient voltage through the capacitor does not exceed the reverse breakdown voltage value of the PN junction, the node between the clamping region and the junction region will not undergo reverse breakdown.

[0099] See also Figure 1 In an optional embodiment, one or more capacitors 73 are used to isolate the low-frequency component of the transient voltage INV and ensure that the high-frequency component of the transient voltage INV can be smoothly coupled to the PN node, that is, the low-frequency component cannot be coupled to the node between the clamping area 30 and the connecting area 40 through the capacitor. On the contrary, the high-frequency component is allowed to be smoothly coupled to the node between the clamping area 30 and the connecting area 40 through the capacitor. In an optional example, the low-frequency component or component can be directly electrically connected to the plate 66 or the following alternative method can be used to replace the scheme of connecting to the plate 66.

[0100] See also Figure 1In an optional embodiment, the reverse breakdown voltage value or breakdown voltage level of the PN node between the clamping region 30 and the connecting region 40 can be adjusted by adjusting the doping concentration of the clamping region 30. However, in order to select which reverse breakdown voltage value to use to guide the PN node to be reversely broken down, a combination method can be used in the present application: changing the capacitance value of the capacitor 73 and adjusting the doping concentration of the clamping region 30. Adjusting the reverse breakdown voltage value of the PN node is actually equivalent to setting the voltage level at which the NPN bipolar transistor of the semiconductor device is turned on at the transient voltage INV. The smaller the reverse breakdown voltage is set, the easier it is for the semiconductor device to release the transient voltage INV. The larger the reverse breakdown voltage value is set, the semiconductor device needs to release the transient voltage INV smoothly under the condition of a larger transient voltage INV level. The capacitor can reasonably select its value. If the coupling capacitor is too large, it will produce a large delay or even a signal phase shift. If the coupling capacitor is too small, it will be difficult to filter out the low-frequency component. Changing parameters such as the number of grooves 70 , the size of the electrode 66 , and the distance between the bottom of the groove 70 and the back of the substrate are all optional options for adjusting the size of the capacitor 73 .

[0101] See also Figure 3 In an optional embodiment, the semiconductor device further includes a fourth doping region 12 of the first conductivity type, such as a P conductivity type, located in the second well region 10 and disposed on the front side of the substrate. The transient voltage INV applied to the conductive material 72 and the third doping region 11 is also applied to the fourth doping region 12. For example, as shown in the figure, a top metal layer 54 is disposed on the front side of the substrate PS and the top metal layer 54 contacts the third doping region 11, the conductive material 72, and the fourth doping region 12.

[0102] See also Figure 3 When the transient voltage INV applied to the conductive material 72 and the third doping region 11 is reversely broken down at the node between the guiding clamping region and the connecting region, the NPN transistor between the second doping region 21a-21b, the substrate PS and the third doping region 11 that is triggered to conduct releases INV. When the NPN bipolar transistor between the second doping region 21a-21b, the substrate PS and the third doping region 11 is triggered to conduct (turn-on), the current under the conduction condition of the NPN bipolar transistor triggers another PNP type bipolar transistor between the fourth doping region 12, the second well region 10 and the substrate PS to be further turned on (turn-on). During this period, due to the conduction of the NPN in the second well region 10, the voltage drop generated on the equivalent resistance of the second well region 10 will be applied to the base of the PNP, thereby triggering the PNP bipolar transistor to conduct. This group of bipolar transistors will generate positive feedback and promote each other's conduction to generate a larger pressure relief current path.

[0103] See also Figure 4In an optional embodiment, the semiconductor device further includes a body region NB of a second conductivity type, such as an N conductivity type, disposed on the front side of the substrate PS. The implantation depth of the body region NB is shallower than that of the second well region 10, and the doping concentration of the body region may be slightly lower than that of the second well region 10. The trench 70 penetrates downward through the body region NB, and the trench extends downward to the substrate PS region below the body region NB. The foregoing states that a plurality of trenches 70 are arranged in a designated area, a predetermined area, or a delimited area of ​​the substrate PS, and accordingly, the body region NB or the drift region is also implanted in the designated area, the predetermined area, or the delimited area. In other words, the body region NB may be implanted in a zone or peripheral position surrounding the plurality of trenches 70 on the front side of the substrate PS: the body region NB is distributed in the peripheral substrate region near the trench 70. However, in other optional embodiments, it is different from this, the body region NB is not only implanted in the zone or peripheral position surrounding the groove 70 on the front side of the substrate PS: instead, the body region NB needs to be implanted on the entire front side of the substrate PS, that is, the second conductive type dopant is implanted in all areas of the front side of the substrate to form the body region NB, but the depth of the body region NB seen from the front side of the substrate is much shallower than the groove 70 and the second well region 10.

[0104] See also Figure 4 In an optional embodiment, the semiconductor device further includes a metal plug 78 located between adjacent trenches 70 and disposed on the front side of the substrate. In the figure, a plug 78 is provided between every two adjacent trenches 70. A metal plug 78 between any two adjacent trenches 70 extends downward in the body region NB, but the plug 78 does not extend to the substrate below the body region NB. That is, the metal plug 78 is located inside the body region NB. Metal tungsten materials or tungsten alloy materials, titanium shell and tungsten core are all optional materials for the metal plug 78.

[0105] See also Figure 5 In an optional embodiment, it is known that a top metal layer 54 is provided on the front side of the substrate PS as shown in the figure, and the top metal layer 54 is in ohmic contact with the third doping region 11 and the conductive material 72. If the semiconductor device also uses the fourth doping region 12, the top metal layer 54 is also in ohmic contact with the fourth doping region 12. The purpose is to apply a transient voltage INV to the conductive material 72 and the third doping region 11, and / or to the fourth doping region 12. If the semiconductor device also uses a metal plug 78, the top metal layer 54 is also in ohmic contact with the metal plug 78. The conductive material and the third doping region and the fourth doping region and the metal plug have the same potential at this time. In an optional embodiment, the transient voltage INV is also applied to the metal plug 78 at the same time, for example, INV is applied to the metal plug 78 through the top metal layer 54.

[0106] See also Figure 5In an optional embodiment, it is mentioned above that a plurality of grooves 70 are arranged in a designated area, a predetermined area or a delimited area of ​​the substrate PS. Accordingly, the first well region 20 and the second well region 10 are respectively located on different sides of the designated area (or predetermined area, delimited area) of the substrate PS for arranging the plurality of grooves 70. For example, if the second well region 10 is deployed on the left side of the designated area, the first well region 20 is deployed on the right side of the designated area or vice versa. For example, if the second well region 10 is deployed on the front side of the designated area, the first well region 20 is deployed on the back side of the designated area or vice versa. The second well region 10 is arranged to be non-overlapping with the first well region 20, that is, non-overlapping and non-coinciding in the direction perpendicular to the substrate. Thus, the current when any bipolar transistor, such as an NPN transistor or a PNP transistor, is turned on can at least have a lateral current path that transversely penetrates the gap region (or space region) located between the plurality of grooves 70 of the substrate.

[0107] See also Figure 6 In an optional embodiment, the semiconductor device further comprises one or more buried regions 80 of a second conductivity type such as an N conductivity type disposed on the back of the substrate PS, the buried region 80 ohmically contacts the plate 66 and the buried region is located in the substrate region between the plurality of trenches 70 and the plate 66. Changing the doping concentration of the buried region 80, or changing the implantation depth of the buried region, or changing its lateral size area, etc., are all optional solutions for adjusting the size of the capacitor 73. The advantage of using the buried region and the plate in combination over using the plate alone is that the buried region 80 will form a space charge region between the buried region 80 and the substrate PS at the interface thereof. Considering the jump characteristics of the transient voltage INV and the fact that the voltage value of the transient voltage INV is not constant, the space charge region of the buried region 80 and the substrate PS will change with the change of the voltage value of the transient voltage INV. The change of the junction capacitance generated by the space charge region of the buried region 80 and the substrate PS can just meet the voltage flicker of the transient voltage INV, which is extremely important for the dynamic capacitance of the capacitor 73. Note that factors such as the size and / or doping concentration of the buried region can change the capacitance of capacitor 73. These factors cannot be changed after being set and the capacitance of capacitor 73 is fixed. These factors change the capacitance of capacitor 73 during the process of semiconductor device preparation, such as in a wafer fab, and cannot change capacitor 73 during the use of the semiconductor device. Using a buried region can adjust capacitor 73 during the use of the semiconductor device when facing different INV voltage levels.

[0108] See also Figure 7In an optional embodiment, the above mentioned multiple grooves 70 are arranged in a designated area, a predetermined area or a delimited area of ​​the substrate PS, and accordingly, the multiple grooves 70 are combined into a groove array. The groove array includes multiple rows of grooves 70 arranged side by side, and each single row of grooves 70 is strip-shaped. The transverse section AA shows the strip shape of each single row of grooves 70, and a transverse section AA is cut out in the designated area, the predetermined area or the delimited area of ​​the substrate PS as a cross-sectional view.

[0109] See also Figure 7 For example, when the collector current of the NPN transistor (between the second doping region, the substrate, and the third doping region) is turned on, it laterally penetrates the gap region (or space region) between the plurality of trenches 70 of the substrate PS. At this time, when the bipolar transistor is turned on, the current, such as the collector current, has a transverse path that flows laterally through the gap region between the plurality of trenches 70 of the substrate PS. The current path I_PAT1 shown in the cross-sectional view of the transverse cross section AA is an example of a transverse path of the collector current of the NPN bipolar transistor flowing through the gap region between the trenches 70 when the transistor is turned on.

[0110] See also Figure 8 In an optional embodiment, it is mentioned above that a plurality of grooves 70 are arranged in a designated area, a predetermined area or a delimited area of ​​the substrate PS, and accordingly, the plurality of grooves 70 are combined into a groove matrix. The groove matrix includes groove individuals distributed in multiple rows and columns, and each element position of the groove matrix (matrix) is arranged with a single groove individual and different groove individuals are spaced apart from each other. The gap area or space area between the grooves 70 individuals is still a part of the substrate PS. The cross section of each independent groove 70 individual is square. The transverse section BB shows the square cross section of each independent groove 70, and a transverse section BB is cut out as a cross-sectional view in the designated area, the predetermined area or the delimited area of ​​the substrate PS.

[0111] See also Figure 8 For example, when the PNP transistor (between the fourth doping region, the second well region, the substrate, etc.) is turned on, the collector current laterally penetrates the gap region (or space region) of the substrate PS between the multiple trenches 70. At this time, when the bipolar transistor is turned on, the current, such as the collector current, has a lateral path that flows laterally through the gap region of the substrate PS between the multiple trenches 70. The current path I_PAT2 shown in the cross-sectional view of the lateral cross section BB is an example of a lateral path for the collector current of the PNP bipolar transistor to flow through the gap region between the trenches 70 when the transistor is turned on. When the PNP bipolar transistor is turned on, the collector current, for example, flows to the base of the NPN transistor through the lateral path. Combined with Figure 3 and Figure 7 .

[0112] See also Figure 8 In an optional embodiment, in combination with Figures 1 to 7 Etc., the present application discloses a method for protecting a hard disk such as an HDD or SSD during hot plugging of the hard disk, the main scheme of which is to use a semiconductor device to release the transient voltage INV of the plug-in terminal IO_HP of the hard disk during the hot plugging event. The integrated circuit of the semiconductor device in the substrate PS has been described in detail above and will not be repeated here. The method includes: when the hard disk is hot plugged, when the semiconductor device is connected to the hard disk, which is actually a hot plug connection (hot-plug connection), the surge voltage generated by the plug-in terminal of the hard disk such as the IO_HP during the hot plugging event is regarded as a transient voltage, based on the aforementioned semiconductor device using the capacitor 73 between the plate 66 and the conductive material 72 in the plurality of grooves 70 to couple the transient voltage to the node between the clamping area 30 and the connection area 40, triggering the bipolar transistor NPN to turn on. If the semiconductor device also integrates a PNP bipolar transistor, positive feedback will be established between the NPN and PNP. In fact, transient voltage is not limited to certain flicker voltages. In complex environments, static electricity is often mixed into the plugging and unplugging process. In many cases, static electricity can be as high as hundreds of volts or thousands of volts, or even exceed tens of thousands of volts. For example, the rapid discharge of static electricity from the human body and powder static electricity can also be classified as a typical category of transient voltage.

[0113] See also Figure 8 As mentioned above, the first well region (PW) 20 and the second well region (NW) 10 are located on different sides of a designated area of ​​the substrate for arranging multiple trenches 70, and do not overlap each other. When the bipolar transistor such as NPN is turned on, the current has a lateral path ( Figure 7 and Figure 8 Examples of lateral paths shown in FIG. 1 include I_PAT2 or I_PAT1). The NPN transistor may be referred to as the first bipolar transistor.

[0114] See also Figure 7 As mentioned above, the first well region (PW) 20 and the second well region (NW) 10 are located on different sides of a designated area of ​​the substrate for arranging multiple trenches 70, and do not overlap each other. When the bipolar transistor such as PNP is turned on, the current has a lateral path (ie, a lateral path) that flows laterally through the gap region between the multiple trenches 70 of the substrate. Figure 7 and Figure 8 Examples of lateral paths shown in FIG. 1 include I_PAT2 or I_PAT1). The PNP transistor may be referred to as the second bipolar transistor.

[0115] See also Figure 8In an optional embodiment, based on the transient voltage INV mentioned above, there is a high probability that the semiconductor device will have an irreversible avalanche effect. How the semiconductor device faces and copes with the avalanche phenomenon and still has the ability to release pressure (i.e., release or release the transient voltage INV sufficient to cause avalanche) under such conditions is one of the serious problems that hot plugging needs to solve. Avalanches during hot plugging will further cause greater surge currents, etc., and functional components such as electronic components and storage particles connected to the hot plug terminals will also suffer secondary damage. Avalanches may occur between the second well region and the substrate and the first well region, or between the body region and the substrate and the first well region, between the body region and the second well region and the substrate and the first well region, or other locations. There are many possibilities for the specific location of avalanches in the semiconductor device under the transient voltage INV, and it is also related to the voltage level of the transient voltage INV. Fine-tuning the doping concentration of the substrate and each well region or each doping region will also change the avalanche location. In fact, avalanches are unpredictable. However, the present application can deal with this problem well, for example, the electric field distribution in the substrate PS can be changed by means of the groove 70, and the electric field distribution in the substrate PS can be changed by means of the combination of the metal plug 78 and the groove 70. The electric field distribution of the groove will lead the avalanche current to its vicinity, for example, near the bottom of the groove near the side wall. Under the condition of using the metal plug, the avalanche current trend can be changed more flexibly, for example, a deeper metal plug will produce a current trend at a more central position between adjacent grooves, and a shallower metal plug will produce a current trend closer to the side wall of the groove.

[0116] See also Figure 8In an optional embodiment, it is known that the current of the NPN bipolar transistor (a bipolar transistor between the second doping region and the substrate and the third doping region) when turned on has at least a lateral path that flows laterally through the substrate PS and is located in the gap region between the plurality of said grooves 70. The present application has great advantages when a semiconductor device undergoes an avalanche event due to transient voltage: the branch current between the plurality of grooves 70 induced by the avalanche event is guided to flow to the lateral path of the NPN transistor, and the avalanche event is confined to the gap region between the grooves 70 to activate the NPN transistor and inhibit further expansion of the avalanche event. Such as blocking the avalanche chain reaction. The occurrence of an avalanche event in the gap region can be understood as limiting the location where the avalanche occurs, so that the negative avalanche of the semiconductor device is only a limited avalanche, for example, only a limited and subtle trauma is generated in the gap region between the grooves. The semiconductor device based on minimally invasive is reversible, and the semiconductor device will not lose its function due to accidental transient high voltage. The avalanche branch current between the grooves 70 flows to the lateral path of the NPN transistor, for example, and also generates a voltage drop in the lateral path at the base of the NPN transistor and injects current into its collector, which is equivalent to effectively activating the NPN transistor and promoting the bipolar transistor NPN to release the transient voltage INV. The current triggered by the initial avalanche provides the carriers required for activation to the lateral path of the designated area where the groove 70 is located. Because the NPN transistor is activated and has a weaker current flowing, it is obviously different from the cut-off state. Starting and activating the NPN can undoubtedly effectively slow down or prevent the avalanche from expanding. In addition, the narrow physical space and small silicon area between any two adjacent grooves 70 will hinder the further impact of the newly generated carriers on other valence electrons. When the NPN transistor is reversely broken down at the node, it will completely enter the amplification state and have a larger current flowing. When the NPN transistor is enabled and generates a discharge current, the avalanche event will be completely suppressed and prevented from further expansion. The avalanche of the semiconductor device caused by the low-frequency component with a larger voltage level mixed with the transient voltage INV is solved. The current under the condition that the NPN transistor is turned on triggers the PNP transistor between the fourth doping region 12, the second well region 10 and the substrate PS to be turned on.

[0117] See also Figure 7In an optional embodiment, it is known that the current of the PNP bipolar transistor (another bipolar transistor between the fourth doping region and the second well region and the substrate) when turned on has at least a lateral path that flows laterally through the substrate PS and is located in the gap region between the plurality of said trenches 70. The present application has great advantages when a semiconductor device undergoes an avalanche event due to transient voltage: the branch current between the plurality of trenches 70 induced by the avalanche event is guided to flow to the lateral path of the PNP transistor, and the avalanche event is confined to the gap region between the trenches 70 to activate the PNP transistor and inhibit further expansion of the avalanche event. Such as blocking the avalanche chain reaction. The occurrence of an avalanche event in the gap region can be understood as limiting the location where the avalanche occurs, so that the negative avalanche of the semiconductor device is only a limited avalanche, for example, only a limited and subtle trauma is generated in the gap region between the trenches. The semiconductor device based on minimally invasive is reversible, and the semiconductor device will not lose its function due to accidental transient high voltage. The avalanche branch current between the grooves 70 flows to the lateral path of the PNP transistor, for example, which will also generate a voltage drop at the base of the PNP transistor that is lower than the potential of the third doping region and the fourth doping region, and the avalanche branch current pulls current from the collector of the PNP transistor. As part of the special design of the present application, its function is equivalent to effectively activating the PNP transistor and promoting the bipolar transistor PNP to release the transient voltage INV. The current triggered at the beginning of the avalanche provides the carriers required for activation to the lateral path of the designated area where the groove 70 is located. Because the PNP transistor is activated and has a weaker current flowing, it is also different from the cut-off state. Starting to activate the PNP can undoubtedly effectively slow down or prevent the avalanche from expanding. In addition, the narrow physical space and small silicon area between any two adjacent grooves 70 will hinder the further impact of the newly generated carriers on other valence electrons. When the PNP transistor is reversely broken down at the node, it will completely enter the amplification state and have a larger current flowing. When the PNP transistor is enabled and generates a discharge current, the avalanche event will be completely suppressed and prevented from further expansion. The avalanche of the semiconductor device caused by the low-frequency component with a large voltage level mixed with the transient voltage INV is solved. The current under the condition of the PNP transistor being turned on triggers the NPN transistor between the second doping region 21a-21b, the substrate PS, and the third doping region 11 to be turned on. In fact, the bipolar transistors NPN and PNP here are in a positive feedback relationship: the conduction of any one will further promote the other to enter the conduction state and make the pressure relief current for releasing the transient voltage INV have a larger value.

[0118] See also Figure 7As an option, the first well region 20 and the second well region 10 are respectively located on different sides of a designated area of ​​the substrate PS for arranging multiple grooves 70, and do not overlap each other, so that the current when the bipolar transistor is turned on has at least a lateral path that flows laterally through the gap area between the multiple grooves 70 of the substrate. When the transient voltage causes an avalanche event in the semiconductor device, the branch current between the multiple grooves 70 induced by the avalanche event is guided to flow to the lateral path of the bipolar transistor, and the avalanche event is limited to the gap area between the grooves 70 to activate the bipolar transistor and suppress the further expansion of the avalanche event. The bipolar transistor here is any one of NPN and PNP or both of them. The aforementioned design structure, such as arranging multiple grooves 70 in a designated area, can largely suppress parasitic thyristors such as parasitic PNPN that are accidentally present inside the semiconductor device. The aforementioned design structure can cope with large surge currents and high peak power consumption that occur in semiconductor devices during avalanche events. The aforementioned design structure can take both high-frequency components and low-frequency components in transient voltage into account during hot plugging. The coupling path where the capacitor 73 is located is used as a guiding path for the high-frequency component in the transient voltage INV, and the branch path where the branch current between the plurality of trenches 70 induced by the avalanche event is located is used as a guiding path for the low-frequency component in the transient voltage INV. The two types of guiding paths, the coupling path and the branch path, are used to activate or enable the bipolar transistor and suppress the further expansion of the avalanche event.

[0119] See also Figure 7 In an optional embodiment, the semiconductor device has a self-protection mechanism for hot-plug transient voltage, which activates the transient voltage discharge path based on limited avalanche. In other words, even if the semiconductor device is applied with an irresistible voltage that is sufficient to destroy the semiconductor device itself and damage the hard disk, the protection mechanism of the semiconductor device will be triggered and enabled to avoid its own damage or damage to the hard disk, and prevent the occurrence or expansion of negative avalanche.

[0120] See also Figure 7 , the electric field distribution in the substrate PS can be changed by means of the groove 70. Although the electric field distribution in the substrate PS can also be changed by means of the combination of the metal plug 78 and the groove 70, it is assumed that the groove is used alone. The electric field distribution of the groove will lead the avalanche current to its vicinity, for example, near the bottom of the groove near the sidewall.

[0121] See also Figure 7As an option, the first well region 20 and the second well region 10 are respectively located on different sides of a designated area of ​​the substrate PS for arranging multiple trenches 70 and do not overlap each other, so that the current when the bipolar transistor is turned on has at least a lateral path that flows laterally through the gap region of the substrate between the multiple trenches 70. The semiconductor device also includes a body region NB of the second conductivity type disposed on the front surface of the substrate PS, and the trenches 70 penetrate the body region NB downward, and the semiconductor device also includes a metal plug 78 disposed between adjacent trenches 70 and disposed on the front surface of the substrate PS, so that a metal plug 70 between any two adjacent trenches 70 extends downward in the body region NB, but the metal plug 70 does not extend to the substrate PS under the body region NB, and the transient voltage INV is also applied to the metal plug 70. When the transient voltage causes an avalanche event in the semiconductor device, the branch current between the multiple trenches 70 induced by the avalanche event is guided to flow to the lateral path of the bipolar transistor, and the avalanche event is confined to the gap region between the trenches 70, so as to activate the bipolar transistor and suppress the further expansion of the avalanche event. The bipolar transistor here is any one of NPN and PNP or both of them. The aforementioned design structure, arranging multiple grooves 70 in a designated area can suppress parasitic thyristors such as parasitic PNPN that accidentally exist inside the semiconductor device to a large extent. The aforementioned design structure can cope with large surge currents and high peak power consumption that occur in semiconductor devices during avalanche events. The aforementioned design structure can take both high-frequency components and low-frequency components in transient voltages into account during hot plugging. The first path where the capacitor 73 is located is used as a guide path for the high-frequency component in the transient voltage INV, and the second path where the branch current between multiple grooves 70 induced by the avalanche event is located is used as a guide path for the low-frequency component in the transient voltage INV. These two types of guide paths, the first path and the second path, are used to activate or enable bipolar transistors and suppress further expansion of avalanche events.

[0122] See also Figure 7 , the groove 70 is used to change the electric field distribution in the substrate PS. In addition, the electric field distribution in the substrate PS can be changed by means of a combination of a metal plug 78 and a groove 70, as shown in the figure. It is known that the electric field distribution of the groove will lead the avalanche current to its vicinity, such as to the bottom of the groove near the side wall. Under the condition of adding a metal plug, the avalanche current trend can be guided more flexibly, for example, a deeper metal plug will produce a current trend at a more central position between adjacent grooves, and a shallower metal plug will produce a current trend closer to the side wall of the groove.

[0123] The above description and drawings provide typical embodiments of specific structures of specific embodiments. The above application proposes existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications to the true intention and scope of the present application. Any and all equivalent scopes and contents within the scope of the claims should be considered to still be within the intention and scope of the present application.

Claims

1. A semiconductor device, It is characterized in that include: A substrate of a first conductivity type, a first well region of the first conductivity type implanted on a back side of the substrate, and a second well region of a second conductivity type implanted on a front side of the substrate; A plurality of grooves are formed on the front surface of the substrate, wherein an insulating layer is attached to the inner wall of the groove and a conductive material is filled in the groove; A plate is arranged on the back of the substrate, and each groove overlaps with the plate in a direction perpendicular to the substrate; a first doping region of the first conductivity type located in the first well region and disposed on the back side of the substrate and a second doping region of the second conductivity type, and a third doping region of the second conductivity type located in the second well region and disposed on the front side of the substrate; A clamping region of the second conductivity type contacting the electrode plate disposed on the back side of the substrate, and a connecting region of the first conductivity type extending from the clamping region to the first well region; The transient voltage applied to the conductive material and the third doped region is released by a bipolar transistor that is triggered to conduct and is located between the second doped region, the substrate and the third doped region, under the condition of inducing the node between the clamping region and the connection region to be reversely broken down.

2. The semiconductor device according to claim 1, Features: A top metal layer is disposed on the front side of the substrate, the top metal layer contacts the third doped region and the conductive material, and the transient voltage is connected to the top metal layer; A bottom metal layer is disposed on the back side of the substrate, the bottom metal layer contacts the first doping region and the second doping region, and the bottom metal layer is connected to a reference ground.

3. The semiconductor device according to claim 2, Features: A top dielectric layer is covered on the front side of the substrate, exposing a local area of ​​the top metal layer to serve as a port for receiving the transient voltage; The back side of the substrate is covered with a bottom dielectric layer, which exposes a local area of ​​the bottom metal layer to serve as a port for receiving the reference ground.

4. The semiconductor device according to claim 2, Features: The back side of the substrate is covered with a bottom dielectric layer, which exposes a local area of ​​the electrode plate to serve as a port for receiving the transient voltage. The transient voltage is connected to the electrode plate through a resistor.

5. The semiconductor device according to claim 1, Features: The semiconductor device is electrically connected to the plug-in terminal of the hard disk, wherein the transient voltage is a sudden voltage borne by the plug-in terminal of the hard disk during a hot plug event.

6. The semiconductor device according to claim 1, Features: It also includes one or more buried regions of the second conductivity type disposed on the back side of the substrate, wherein the buried regions contact the electrode plate and are located in a substrate region between the plurality of trenches and the electrode plate.

7. The semiconductor device according to claim 1, Features: It also includes a fourth doped region of the first conductivity type located in the second well region and disposed on the front side of the substrate; When the bipolar transistor between the second doping region, the substrate and the third doping region is triggered to turn on, the current under the on condition triggers another bipolar transistor between the fourth doping region, the second well region and the substrate to be further turned on.

8. The semiconductor device according to claim 1, Features: The first well region and the second well region are respectively located on different sides of a designated area of ​​the substrate for arranging the plurality of grooves and do not overlap each other, so that the current when the bipolar transistor is turned on has at least a lateral path that flows laterally through the gap region of the substrate between the plurality of grooves.

9. The semiconductor device according to claim 1, Features: It also includes a body region of the second conductivity type disposed on the front side of the substrate, wherein the trench penetrates downward through the body region; and It also includes a metal plug located between adjacent grooves and disposed on the front side of the substrate, wherein a metal plug between any two adjacent grooves extends downward in the body region but does not extend to the substrate below the body region; The transient voltage is also applied to the metal plug at the same time.

10. The semiconductor device according to claim 1, Features: The first conductivity type is a P conductivity type and the second conductivity type is an N conductivity type.

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