Semiconductor device

Abstract

A semiconductor device includes a substrate including a FinFET region formed on the substrate, where the FinFET region includes one or more fins. The semiconductor device further includes one or more device isolation structures formed on the substrate and disposed adjacent alongside the one or more fins. In addition, the semiconductor device includes an enhancement layer formed on a portion of the one or more fins.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Integrated circuits are formed on semiconductor wafers. The optical lithography patterning process uses ultraviolet light to transfer the desired mask pattern to the photoresist on the semiconductor wafer. An etching process can then be used to transfer the pattern to the layer below the photoresist. This process is repeated many times with different patterns to build different layers on the wafer substrate and manufacture semiconductor devices. For example, three-dimensional transistors such as fin-like field-effect transistors (Fin-FETs) have been introduced to replace planar transistors. In the manufacturing process of Fin-FET devices, further improvements are constantly needed to meet the performance requirements during the shrinking process. Utility Model Content

[0003] According to one embodiment of the present disclosure, a semiconductor device including a substrate is provided. The substrate includes a FinFET region formed on the substrate, wherein the FinFET region includes one or more fins. The semiconductor device further includes one or more device isolation structures formed on the substrate and disposed adjacent to the one or more fins. In addition, the semiconductor device includes a reinforcement layer formed on a portion of the one or more fins.

[0004] According to one embodiment of the present disclosure, a semiconductor device including a substrate is provided. The substrate includes a FinFET region formed on the substrate, wherein the FinFET region includes one or more fins. The semiconductor device further includes one or more device isolation structures formed on the substrate and disposed adjacent to the one or more fins, and a shallow trench isolation material deposited on the device isolation structure. In addition, the semiconductor device includes an enhancement layer formed on a portion of the one or more fins, the enhancement layer being deposited with a thickness ranging from 1A to 30A.

[0005] According to one embodiment of the present disclosure, a semiconductor device including a substrate is provided. The substrate includes a FinFET region and a trench region formed on the substrate, wherein the FinFET region includes one or more fins adjacent to the trench region. The semiconductor device further includes one or more device isolation structures formed on the substrate and disposed adjacent to the one or more fins. In addition, the semiconductor device includes a reinforcement layer formed on the sidewalls of the one or more fins. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1J various cross-sectional views illustrating intermediate stages of fabricating fins of a FinFET structure according to some embodiments;

[0008] Figures 2A to 2M Various three-dimensional views illustrating intermediate stages of fabricating fins for a FinFET structure according to some embodiments;

[0009] Figure 3 illustrates a three-dimensional representative example of a FinFET device according to some embodiments;

[0010] Figure 4 A comparative diagram illustrating the use of a reinforcement layer during fin formation according to some embodiments;

[0011] Figure 5 A comparative diagram illustrating the use of a reinforcement layer during fin formation according to some embodiments;

[0012] FIG. 6A to FIG. 6B various cross-sectional views illustrating intermediate stages of fabricating fins of a FinFET structure according to some embodiments;

[0013] Figure 7 illustrates a method of manufacturing a FinFET structure according to some embodiments;

[0014] Figure 8 A method of manufacturing a semiconductor device according to some embodiments is illustrated.

[0015]

Explanation of symbols

[0016] 102:Substrate

[0017] 104: cushion layer

[0018] 106: first insulating layer

[0019] 108: Hard Mask Layer

[0020] 110: first photoresist

[0021] 112: Fins

[0022] 113A: First side wall

[0023] 113B: Second side wall

[0024] 114: Device isolation structure

[0025] 116: Enhancement layer

[0026] 118: second photoresist layer

[0027] 120: Groove area

[0028] 122: FinFET area

[0029] 202: Top

[0030] 204:Front

[0031] 206: Rear

[0032] 208:STI Materials

[0033] 300:FinFET device

[0034] 302: Source region

[0035] 304: Drain region

[0036] 306: Gate structure

[0037] 308: Gate oxide component

[0038] 310: Channel

[0039] 312:Thickness

[0040] 400: Stage

[0041] 402: peripheral fins

[0042] 404: Stage

[0043] 406: Phase

[0044] 410: Stage

[0045] 700: Method

[0046] 800: Method

[0047] S100~S134: Steps

[0048] S200~S210: Steps DETAILED DESCRIPTION

[0049] The following disclosure provides many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0050] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The elements may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0051] The numerical values ​​in the specification and patent application range of this application should be understood to include the same numerical values ​​when reduced to the same number of significant figures, and the numerical values ​​whose difference from the numerical values ​​is less than the experimental error of the conventional measurement technology of the type described in this application for determining the value. All ranges disclosed herein include the described endpoints.

[0052] The term "about" can be used to include any numerical value, which can be changed without changing the basic function of the value. When used with a range, "about" also discloses the range defined by the absolute values ​​of the two endpoints, for example, "about 2 to about 4" also discloses the range "2 to 4". The term "about" can refer to plus or minus 10% of the indicated number.

[0053] As the semiconductor industry strives for higher device density, higher performance, and lower cost, problems involving both manufacturing and design have been encountered. One solution to these problems is the development of fin-like field effect transistors (FinFETs). FinFETs include thin vertical "fins" formed in an independent manner above the main surface of a substrate. The source, drain, and channel regions are defined within this fin. The gate of the transistor is wrapped around the channel region of the fin. This configuration allows the gate to induce current flow in the channel from three sides. Therefore, FinFET devices have the advantages of higher current and reduced short channel effects.

[0054] With the technological advancement of integrated circuit materials, the scale of FinFET and other metal oxide semiconductor field effect transistors (MOSFET) has gradually decreased. For example, high-k metal gate (HKMG) technology has been applied to FinFET. However, in low-density areas, such as in the ISO area, plasma etching can cause the edge fins of the FinFET to shrink, that is, the profile of the edge fins of the FinFET is reduced. This reduced fin profile will reduce the quality of the FinFET and cause the device to collapse. In some embodiments, the surface of the fin is nitrided before oxide deposition to form a nitride layer for use as an etch stop layer to protect the end or edge fins of the FinFET from shrinkage during the etching process.

[0055] Now go to Figures 1A to 1J , which shows various cross-sectional views of intermediate stages of manufacturing the fins of a FinFET structure according to some embodiments. In the following, various layers or films are deposited and patterned. The patterning of the layers may be performed using any suitable patterning technique, such as optical lithography patterning techniques using deposition of a photoresist layer and selective exposure of visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), or the like through a mask, followed by development of the exposed photoresist, followed by etching, deposition, or other process steps laterally delineated by the developed photoresist. In other embodiments, patterning of the electron-sensitive resist layer may be performed by electron beam exposure (electron beam lithography, i.e., e-beam lithography). Those familiar with the art will understand that the foregoing is merely illustrative.

[0056] exist Figure 1A In the embodiment of the present invention, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate. The substrate 102 may include a semiconductor material, such as an elemental semiconductor including Si and Ge; a compound or alloy semiconductor including SiC, SiGe, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaAnAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or a combination thereof. The substrate 102 may be doped or undoped.

[0057] According to one embodiment, a liner layer 104 is deposited on the substrate, such as Figure 1BIn some embodiments, the liner layer 104 may include, for example but not limited to, a suitable dielectric material, that is, an insulating material, including, for example but not limited to, silicon dioxide (SiO2) material, silicon nitride (SiN x ) material, or the like. Suitable mechanisms for depositing the liner layer 104 may include, for example but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroless plating, electrochemical plating, sputtering, ion metal plasma, another deposition process, or a suitable combination thereof.

[0058] like Figure 1C As shown in FIG. 1 , a first insulating layer 106 is formed on the liner layer 104. As will be appreciated, the first insulating layer 106 may be deposited on the liner layer 104 by, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroless plating, electrochemical plating, sputtering, ion metal plasma, another deposition process, or a suitable combination thereof. According to some embodiments, the first insulating layer 106 may include any suitable dielectric material, including, for example, but not limited to, silicon dioxide (SiO2) materials, silicon nitride (SiN x ) material, or the like. In one exemplary embodiment, the liner layer 104 and the first insulating layer 106 include different materials. In another embodiment, the first insulating layer 106 may be deposited as a silicon nitride layer.

[0059] Then, a hard mask layer 108 is formed on the first insulating layer 106. Figure 1D . According to some embodiments, the hard mask layer 108 may include, for example, but not limited to, a nitride or oxide material. As will be appreciated, deposition, such as, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroless plating, electrochemical plating, sputtering, ion metal plasma, another deposition process, or a suitable combination of the foregoing, may be used to apply the hard mask layer 108 onto the first insulating layer 106.

[0060] Next, a first photoresist 110 is applied on the hard mask layer 108 and patterned, such as Figure 1E As shown in Figure 1E As shown in FIG. 1 , the first photoresist 110 is patterned to form the fins of the FinFET structure, as will be described in Figure 1F to Figure 1J The first photoresist 110 may include a layer of photoresist material deposited on the hard mask layer 108, followed by subsequent patterning, i.e., exposure through the mask to develop portions of the photoresist material. That is, Figure 1E The diagram shows the deposition of a photoresist layer and the selective exposure to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), or the like through a mask, followed by developing the exposed photoresist. The unexposed photoresist is then removed to obtain Figure 1E The patterned first photoresist 110 is shown in FIG.

[0061] Afterwards, portions of the substrate 102, the liner layer 104, the first insulating layer 106, and the hard mask layer 108 are removed. Suitable removal processes include, for example, but not limited to, etching processes implemented as dry etching processes, plasma etching processes, RIE processes, wet etching processes, some other etching processes, or combinations thereof. That is, portions of the substrate 102, the liner layer 104, the first insulating layer 106, and the hard mask layer 108 that are not covered by the first photoresist 110 are removed. Subsequently, the first photoresist 110 is removed, resulting in Figure 1F The intermediate manufacturing stage shown in .

[0062] like Figure 1F As shown in FIG. 1 , a plurality of fins 112 are formed by the substrate 102. It should be understood that Figure 1F The number of fins 112 shown in FIG. 1 is intended to be exemplary only, and any number of fins may be used by a FinFET depending on the desired design characteristics. It should be understood that Figure 1F Each fin 112 depicted in FIG. 1 is substantially rectangular in shape and extends vertically upward from the substrate 102. Figure 1F As shown in , each fin 112 includes a first sidewall 113A and a second sidewall 113B, which are depicted as being perpendicular to the substrate 102. Those skilled in the art will appreciate that other forms, shapes, and cross-sections of the fins 112 can be implemented according to different embodiments of the subject application. In some embodiments, the thickness of the fins 112 is substantially uniform. In other embodiments, the thickness of the fins 112 can vary according to their individual locations, functions, and design requirements.

[0063] Figure 1FFurther illustrated are a plurality of device isolation structures or regions 114 formed between each of the fins 112 defined by the first sidewalls 113A and the second sidewalls 113B. According to some embodiments, the device isolation structures 114 may correspond to local oxidation of silicon (LOCOS) regions, shallow trench isolation (STI), deep trench isolation (DTI), buffer oxide (BOX) regions, deep well formation, and the like.

[0064] Now go to Figure 1G , which shows another stage of manufacturing a FinFET device according to one embodiment of the subject application. Figure 1G As shown in FIG. 1 , the enhancement layer 116 is formed on the fin 112. According to some embodiments, the enhancement layer 116 may include silicon, oxygen, nitrogen, or the like. In further embodiments, the enhancement layer 116 may include at least 1% atomic concentration of Si, O, C, N, P, As, B, and / or Ga. The enhancement layer 116 may be deposited at a thickness in the range of about 1 Å to 30 Å. As will be appreciated, the enhancement layer 116 may be deposited on a Figure 1F 114, by, for example but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), implantation, thermal diffusion, wet diffusion, post-etch refill, electroless plating, electrochemical plating, sputtering, ion metal plasma, another deposition process, or a suitable combination thereof. It should be understood that the enhancement layer 116 is deposited so as to cover the entire exposed surface of the fin 112, Figures 1A to 1J The cross-sectional view of FIG. 1 is not intended to limit the location of the reinforcement layer 116 to only the first sidewall 113A, the second sidewall 113B, and the top of the fin 112 .

[0065] about Figure 1H , a second photoresist layer 118 is deposited on portions of the enhancement layer 116 corresponding to the fins 112 and patterned for protection during subsequent processing. Figure 1H The diagram shows the deposition of a photoresist layer and the selective exposure to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), or the like through a mask, followed by developing the exposed photoresist. The unexposed photoresist is then removed to obtain Figure 1HThe patterned second photoresist layer 118 is shown in FIG.

[0066] Then Figure 1H The fins 112 that are not protected by the second photoresist layer 118 are etched at the intermediate stage shown in the figure. In some embodiments, the portion not covered by the second photoresist layer 118 is removed by etching, wherein the enhancement layer 116 is used as an etching stop layer. That is, the enhancement layer 116 includes a suitable barrier material, which is used to protect the layers and components below from damage during the subsequent etching process. It should be understood that the enhancement layer 116 corresponds to a layer of a material having etching characteristics that are significantly different from the material to be etched, thereby terminating or pausing the etching process of the layer deposited on the enhancement layer 116. According to one embodiment, the etching performed may include, for example, but not limited to plasma etching. That is, plasma etching corresponds to the use of plasma generated by exciting ions in a gas (usually oxygen and carbon tetrafluoride (CF4)) to remove silicon (or other materials). The excited ions collide with the material at the atomic level and remove the material. Other suitable plasma etching gases may include, for example, but are not limited to, octafluorocyclobutane (C4F8), argon (Ar), oxygen (O2), helium (He), trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), chlorine (Cl2), hydrogen bromide (HBr), or combinations thereof, with a pressure range of about 1 mTorr to about 5 mTorr.

[0067] In some embodiments, the etching process to remove silicon may inadvertently affect the profile of the peripheral fins, resulting in quality degradation and / or device failure. Fig. 1I As shown in , the addition of the enhancement layer 116 prevents shrinkage and allows each remaining fin 112 to have a substantially uniform thickness. That is, the enhancement layer 116 prevents the plasma etch from removing material from the first sidewalls 113A and the second sidewalls 113B of the fins 112 that are near the fins 112 to be removed, i.e., the first sidewalls 113A and the second sidewalls 113B of those fins that are near the newly formed trench regions 120 (generated from the removed fins that are not protected by the second photoresist layer 118) are protected from having material removed by the plasma etch.

[0068] therefore, Fig. 1I The diagram shows an intermediate manufacturing stage of the FinFET device after removing the uncovered fins 112. In some embodiments, the process of removing the uncovered fins 112 may be referred to as defining the fin region of the FinFET device. Fig. 1I As shown in FIG. 1 , the trench region 120 is depicted as being located adjacent to those fins 112 that are not removed. Fig. 1I Further illustrated is a FinFET region 122 on the substrate 102, as discussed in more detail below. It will be appreciated that the second photoresist layer 118 and the enhancement layer 116 retain the same Fig. 1IAs shown in , we then remove it and get Figure 1J . According to some embodiments, at least a portion of the second photoresist layer 118 and the enhancement layer 116, for example, along the first sidewall 113A and the second sidewall 113B of the remaining fin 112, are removed by a suitable removal process. Such a process may include, for example, but not limited to, plasma etching, wet etching, dry etching, or the like.

[0069] According to some embodiments, Figures 1A to 1J The FinFET device shown in the figure may be a bulk FinFET, a SOI FinFET, or the like. In some embodiments, the device isolation structure may be LOCOS, STI, DTI, BOX, deep well formation, or the like. In such embodiments, the enhancement layer 116 may have a thickness in the range of 1A to 30A. Such an enhancement layer 116 may be composed of a material including Si, O, N, etc. In addition, the enhancement layer material includes Si, Ge, O, C, N, P, As, B, Ga with an atomic concentration of at least 1%, and is formed by implantation, thermal diffusion, ALD diffusion, wet diffusion, and refilling after etching.

[0070] Now go to Figures 2A to 2M , which shows a three-dimensional illustration of a fabricated FinFET device according to some embodiments. It should be understood that Figures 2A to 2M The illustrations are not to scale, but are intended as examples to illustrate various steps of a method for fabricating a FinFET device according to embodiments disclosed herein. Thus, the height of the fins, the spacing therebetween, the placement of the source, drain, gate, etc. (as further discussed below) are intended only to illustrate and not to limit certain aspects of the embodiments disclosed herein. Figure 2A The intermediate structure shown in FIG. 1 includes a substrate 102 on which one or more layers of material are formed, such as Figure 2A Shown in the figure are a liner layer 104, a first insulating layer 106, and a hard mask layer 108. In addition, as shown in the figure, a first photoresist 110 is applied on the hard mask layer 108 and patterned.

[0071] According to one embodiment, Figure 2A An etching process is performed on the structure of , thereby removing the portion not covered by the first photoresist 110. Suitable etching may include, for example but not limited to, a dry etching process, a plasma etching process, an RIE process, a wet etching process, some other etching process, or a combination of the foregoing. Therefore, Figure 2B The initial formation of the fins 112 of the structure after such etching and removal of the first photoresist 110, and the formation of the device isolation structure 114 between each fin 112 is depicted. Figure 2BAs shown in FIG, each fin 112 includes a first sidewall 113A, a second sidewall 113B, a top 202, a front 204, and a rear 206. It should be understood that the fins 112 are illustrated as rectangular in shape for exemplary purposes only, and non-vertical sides, surfaces, fronts, rears, etc. are also contemplated herein.

[0072] Figure 2C The diagram shows the formation of a reinforcement layer 116 that seals each fin 112 and is formed on the first sidewall 113A and the second sidewall 113B, as well as the top 202, the front 204, and the back 206 of each fin 112. According to some embodiments, the reinforcement layer 116 may include silicon, oxygen, nitrogen, or the like. In further embodiments, the reinforcement layer 116 may include Si, O, C, N, P, As, B, and / or Ga at a concentration of at least 1% atomic percent. The reinforcement layer 116 may be deposited at a thickness in a range of about 1A to 30A. The reinforcement layer 116 may be deposited on the fin 112, the first sidewall 113A and the second sidewall 113B, the top 202, the front 204, the back 206, the substrate 102, and the device isolation structure 114, as shown. Figure 2C Such formation of the enhancement layer 116 may be accomplished by, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), implantation, thermal diffusion, wet diffusion, post-etch refill, electroless plating, electrochemical plating, sputtering, ion metal plasma, another deposition process, or a suitable combination of the foregoing. Figure 2C As shown in, and as mentioned above about Figure 1G As mentioned above, all exposed surfaces of the fin 112 are suitably covered by the reinforcement layer 116 .

[0073] Now go to Figure 2D , which shows the result of depositing a second photoresist layer 118 on the portion of the enhancement layer 116 corresponding to the fin 112 and patterning it for protection during subsequent processing. Figure 2D The diagram shows the deposition of a photoresist layer and the selective exposure to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), or the like through a mask, followed by developing the exposed photoresist. The unexposed photoresist is then removed to obtain Figure 2D The patterned second photoresist layer 118 is shown in FIG.

[0074] Then Figure 2D118 to remove those fins 112 that are not protected by the second photoresist layer 118. In some embodiments, the portions not covered by the second photoresist layer 118 are removed by etching, wherein the enhancement layer 116 serves as an etch stop layer, i.e., a layer of material having significantly different etching characteristics than the material to be etched, thereby terminating or pausing the etching process of the layers deposited on the enhancement layer 116. In some embodiments, the etching process to remove the extraneous fins (the fins 112 not covered by the second photoresist layer 118) is a plasma etching process, using a plasma generated by exciting ions in a gas (typically oxygen and CF4) to remove the silicon (and other materials) of the fins 112. The excited ions collide with the material at the atomic level and remove the material. As described above, this etching process to remove silicon may inadvertently affect the profile of the peripheral fins, resulting in quality degradation and / or device collapse. Therefore, the use of the enhancement layer 116 provides protection against such shrinkage of the fin profile. That is, the enhancement layer 116 reduces the etching rate in the line-end fins, thereby avoiding the phenomenon that plasma etching may cause the fin profile to shrink at the edge (ISO region) of the FinFET structure.

[0075] Figure 2E 1 provides an illustration of the advantages of utilizing the enhancement layer 116 according to some embodiments. Figure 2E As shown in , the addition of the enhancement layer 116 prevents shrinkage and allows each remaining fin 112 to have a substantially uniform thickness. That is, the enhancement layer 116 prevents the plasma etch from removing material from the first sidewalls 113A and second sidewalls 113B of the fins 112 located adjacent to the removed fins 112, i.e., those fins located adjacent to the newly formed trench regions 120 (resulting from the removal of the fins not protected by the second photoresist layer 118).

[0076] Figure 2E The diagram shows an intermediate manufacturing stage of the FinFET device after removing the uncovered fins 112. In some embodiments, the process of removing the uncovered fins 112 may be referred to as defining the fin region of the FinFET device. Figure 2E As shown in FIG. 1 , the trench region 120 is depicted as being located adjacent to those fins 112 that are not removed. Figure 2E Further illustrated is a FinFET region 122 on the substrate 102, as discussed in more detail below. It will be appreciated that the enhancement layer 116 retains the Figure 2E as shown in .

[0077] Figure 2F The diagram shows an intermediate stage in the fabrication of a FinFET device after the enhancement layer 116 has been removed from the fin 112. Figure 2FAs shown in , at least a portion of the enhancement layer 116, for example, along the first sidewall 113A and the second sidewall 113B of the remaining fin 112, the top 202, the front portion 204, and the back portion 206, is removed by a suitable removal process. Such a process may include, for example, but not limited to, plasma etching, wet etching, dry etching, or the like. Next, the hard mask layer 108 is removed by a suitable removal process. In some embodiments, the hard mask layer 108 can be removed by chemical-mechanical polishing (CMP), a dry etching process, a plasma etching process, an RIE process, a wet etching process, some other etching process, or a combination of the foregoing. Figure 2G An illustrative example of an intermediate fabrication stage of a FinFET device after removal of the hard mask layer 108 is provided.

[0078] Then, STI material 208 is deposited on the structure, such as Figure 2H As shown in Figure 2H As shown in , the STI material 208 may include any suitable shallow-trench-isolation (STI) material, including, for example, but not limited to, silicon oxide (e.g., (SiO2)), silicon nitride (SiN), silicon oxynitride (SiON), fluorosilicate glass (FSG), or low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the STI material 208 may include multiple layers of insulating material. In some embodiments, the process of depositing the insulating material may include any deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide). For example, flowable silicon oxide or silicon nitride may be deposited as the STI material 208 using a flowable CVD (FCVD) process. The FCVD process may be followed by a wet annealing process. In some embodiments, the process of depositing the insulating material may include depositing a low-k dielectric material to form a liner. In some embodiments, a liner made of another suitable insulating material may be placed between the STI material 208 and the adjacent fin 112 in the device isolation structure 114.

[0079] A chemical mechanical polishing (CMP) process is then performed to expose the first insulating layer 106 and reduce the STI material 208. Fig.2I In some embodiments, the hard mask layer 108 may remain prior to deposition of the STI material 208 and then be removed during this processing stage. Figure 2JIn the embodiment of the present invention, the STI material 208 is etched to remove a portion thereof, thereby further exposing the first insulating layer 106. Such removal may be accomplished by an electron beam (EB) operation, a wet etching process, a dry etching process, a plasma etching process, or the like.

[0080] Figure 2K The first insulating layer 106 is subsequently removed to expose the liner layer 104. The removal of the first insulating layer 106 may be accomplished by an etching operation, including, for example but not limited to, dry etching, wet etching, plasma etching, or a suitable combination thereof. Figure 2L As shown in FIG, the liner layer 104 is removed from the top 202 of the fin 112, resulting in the fin 112 being exposed within the STI material 208. It will be appreciated that the removal of the liner layer 104 may be performed by etching, ie, wet etching, dry etching, and / or plasma etching. Figure 2M The fin 112 is shown recessed relative to the STI material 208 in accordance with some embodiments. As will be appreciated, the fin recess may correspond to the definition of the fin height of the fin 112 of the FinFET device. Figure 2M One example of recessing the fin 112 so that a portion of the STI material 208 is removed is depicted. As described above, such removal of the STI material 208 may be accomplished by wet etching, dry etching, plasma etching, or the like.

[0081] Now go to Figure 3 , which shows that according to the above Figures 1A to 2M A three-dimensional representative example of a FinFET device 300 fabricated using the illustrated process. Figure 3 As shown in FIG. 1 , the FinFET device 300 includes a substrate 102, a device isolation structure 114 having an STI material 208, one or more fins 112, a source region 302, a drain region 304, a gate structure 306, a gate oxide component 308, and a channel 310. Figure 3 As shown in FIG. 1 , a FinFET device 300 is formed on a substrate 102. A device isolation structure 114 having an STI material is formed to isolate the FinFET device 300 from adjacent FinFETs and / or from adjacent active and passive components. Figure 3 As shown in FIG. 3 , each fin 112 extends vertically outward from the top surface of the substrate 102 . Based on the above-described manufacturing methods and processes (ie, the use of enhancement layer 116 during fin formation), it will be appreciated that the peripheral fins 112 of the FinFET device 300 are uniform in thickness 312 .

[0082] During operation of the FinFET device 300, current flows from the source region 302 to the drain region 304 through the channel 310 in response to a voltage applied to the gate structure 306. The source region 302 and the drain region 304 may be doped with positive-type dopants or negative-type dopants to provide a charge reservoir for the FinFET device 300. The gate structure 306 surrounds three sides of each fin 112 to control the flow of current through the channel 310. In some embodiments, the gate structure 306 is a multi-layer structure that includes (not shown) a gate electrode, a gate dielectric (e.g., a gate oxide component 308) separating the gate structure 306 from the fin 112, and sidewall spacers, as will be understood.

[0083] When the voltage applied to the gate electrode exceeds a certain threshold voltage, the FinFET device 300 turns on and current flows through the channel 310. If the applied voltage drops below the threshold voltage, the FinFET device 300 turns off and current stops flowing through the channel 310. According to some embodiments, the surrounding gate structure 306 affects the channel 310 from three sides, thereby improving the control of the conductive properties of the channel 310 relative to the planar FET. Such improved control reduces the leakage of charge from the channel 310 to the substrate 102, or from the source region 302 and the drain region 304 to the substrate 102. In addition, because the current carrying capacity of the channel 310 is much greater than the current carrying capacity of the planar conductive channel, the switching characteristics of the FinFET are also improved compared to the switching characteristics of the planar FET. The use of the above-mentioned method (i.e., applying the enhancement layer 116) achieves uniformity throughout the fin 112, especially the peripheral fin 112, thereby reducing the collapse of the FinFET device 300.

[0084] Reference now Figure 4 , which shows a comparative illustration of the use of enhancement layer 116 during fin formation. As shown at stage 400, an initial definition of fins 112 is performed. Peripheral fins 402 are circled to identify those fins 112 that are most affected by the use of enhancement layer 116. At stage 404, enhancement layer 116 is applied to fins 112. Thereafter, fin cutting is performed, i.e., plasma etching is performed to remove unwanted fins (as described above with reference to FIG. 1 ). Figures 1A to 2M As a result of the above etching, the peripheral fin 402 is shown at stage 406 to be significantly thinner than the inner fin 112. When the enhancement layer 116 is not applied, the peripheral fin 402 shown at stage 406 is significantly thinner than the inner fin 112. This is a result of the etching process, which removes a portion of the fin 112. Figure 5It also provides an illustration that the greater number of fins 112 leads to significantly thinner peripheral fins 402 than the inner fins. As a non-limiting example, if the thickness of fin 112 is designed to be 7nm, the peripheral fin 402 may be 4.2-5.2nm thick, which may cause collapse. Figure 4 , a gate liner or oxide 308 is then applied to the fins 112, as illustrated at stage 408 (without enhancement layer 116) and at stage 410 (with enhancement layer 116). In contrast, applying the enhancement layer 116 as described above maintains the thickness of each fin 112, including the peripheral fins 402, as shown at stage 408.

[0085] Fig. 6A and Figure 6B A further comparative illustration of narrowing (ie, thinning) the peripheral fin 402 without the reinforcement layer 116 is provided. It will be appreciated that Fig. 6A Corresponds to Figure 1F , as described above. Figure 6B The illustration does not include the effect of the enhancement layer 116 because, as described above, Figure 1J In contrast, the peripheral fins 402 are thinner due to silicon loss during etching.

[0086] Now go to Figure 7 , which shows a method 700 for manufacturing a FinFET structure / device according to some embodiments. The method begins at step S100, whereby a liner layer 104 is deposited on a substrate 102. The substrate 102 may include a semiconductor material, such as an elemental semiconductor including Si and Ge; a compound or alloy semiconductor including SiC, SiGe, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaAnAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or a combination thereof. In some embodiments, the liner layer 104 may include, for example but not limited to, a suitable dielectric material, i.e., an insulating material, including, for example but not limited to, a silicon dioxide (SiO2) material, a silicon nitride (SiN x ) material, or the like. Suitable mechanisms for depositing the liner layer 104 may include, for example, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroless plating, electrochemical plating, sputtering, ion metal plasma, another deposition process, or a suitable combination of the foregoing.

[0087] At step S102, a first insulating layer 106 is formed on the liner layer 104. According to some embodiments, the first insulating layer 106 may include any suitable dielectric material, including, for example but not limited to, silicon dioxide (SiO2), silicon nitride (SiN x ) material, or the like. Suitable mechanisms for depositing the first insulating layer 106 may include, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroless plating, electrochemical plating, sputtering, ion metal plasma, another deposition process, or a suitable combination of the foregoing. In an exemplary embodiment, the liner layer 104 and the first insulating layer 106 include different materials. In further embodiments, the first insulating layer 106 may be deposited as a silicon nitride layer.

[0088] Next, at step S104, a hard mask layer 108 is formed on the first insulating layer 106. According to some embodiments, the hard mask layer 108 may include, for example, but not limited to, a nitride or oxide material. As will be appreciated, deposition, such as, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroless plating, electrochemical plating, sputtering, ion metal plasma, another deposition process, or a suitable combination of the foregoing, may be used to apply the hard mask layer 108 to the first insulating layer 106.

[0089] At step S106, a first photoresist 110 is applied on the hard mask layer 108 and patterned. At step S108, a first etching process is performed to remove portions not covered by the first photoresist 110 to form a plurality of fins 112. Suitable etching may include, for example but not limited to, a dry etching process, a plasma etching process, an RIE process, a wet etching process, some other etching process, or a combination of the foregoing. As a result of the first etching process, a plurality of fins 112 are initially formed after removing the first photoresist 110.

[0090] At step S110, a reinforcement layer 116 is formed on the fin 112 and the substrate 102. According to one embodiment, the reinforcement layer 116 seals each fin 112, the first sidewall 113A and the second sidewall 113B, the device isolation structure 114, and the top 202, the front 204, and the back 206 of each fin 112. According to some embodiments, the reinforcement layer 116 may include silicon, oxygen, nitrogen, or the like. In further embodiments, the reinforcement layer 116 may include Si, O, C, N, P, As, B, and / or Ga at a concentration of at least 1% atomically. The reinforcement layer 116 may be deposited to a thickness in the range of about 1A to 30A. Such formation of the enhancement layer 116 may be accomplished by, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), implantation, thermal diffusion, wet diffusion, post-etch refill, electroless plating, electrochemical plating, sputtering, ion metal plasma, another deposition process, or a suitable combination thereof.

[0091] At step S112, a second photoresist layer 118 is applied to the portion of the enhancement layer 116 corresponding to the fins 112 and patterned for protection during subsequent processing. A second etching process is then performed at step S114 to remove those fins 112 that are not protected by the second photoresist layer 118. In some embodiments, the portions not covered by the second photoresist layer 118 are removed by etching, wherein the enhancement layer 116 is used as an etching stop layer, that is, a material layer having significantly different etching characteristics from the material to be etched, thereby terminating or pausing the etching process of the layers deposited on the enhancement layer 116. In some embodiments, the etching process for removing the irrelevant fins (fins 112 not covered by the second photoresist layer 118) is a plasma etching process, using plasma generated by exciting ions in a gas (usually oxygen and CF4) to remove silicon (and other materials) of the fins 112. The excited ions collide with the material at the atomic level and remove the material. As described above, this etching process for removing silicon may inadvertently affect the profile of the peripheral fins, resulting in quality degradation and / or device collapse. Therefore, the use of the reinforcement layer 116 provides protection against such shrinkage of the fin profile.

[0092] At step S116, a third etching process is performed to remove at least a portion of the enhancement layer 116. That is, at least a portion of the enhancement layer 116, for example, along the first sidewall 113A and the second sidewall 113B of the remaining fin 112, the top 202, the front portion 204, and the back portion 206, is removed by a suitable removal process. Such a process may include, for example, but not limited to, plasma etching, wet etching, dry etching, or the like. Thereafter, at step S118, chemical mechanical polishing is performed to remove the hard mask layer 108. At step S120, STI material 208 is then deposited. According to some embodiments, the STI material 208 may include any suitable shallow-trench-isolation (STI) material, including, for example, but not limited to, silicon oxide (e.g., (SiO2)), silicon nitride (SiN), silicon oxynitride (SiON), fluorosilicate glass (FSG), or low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the STI material 208 may include multiple layers of insulating material. In some embodiments, the process of depositing the insulating material may include any deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide). For example, flowable silicon oxide or silicon nitride may be deposited as the STI material 208 using a flowable CVD (FCVD) process. The FCVD process may be followed by a wet annealing process. In some embodiments, the process of depositing the insulating material may include depositing a low-k dielectric material to form a liner. In some embodiments, a liner made of another suitable insulating material may be placed between the STI material 208 and the adjacent fin 112 in the device isolation structure 114.

[0093] At step S122, a chemical-mechanical polishing (CMP) process is then performed to expose the first insulating layer 106 and reduce the STI material 208. At step S124, a fourth etching process is performed to remove a portion of the STI material 208 to further expose the first insulating layer 106. This removal can be accomplished by an electron beam (EB) operation, a wet etching process, a dry etching process, a plasma etching process, or the like.

[0094] Then, the first insulating layer 106 is removed by a fifth etching process at step S126, thereby exposing the pad layer 104. The removal of the first insulating layer 106 can be accomplished by an etching operation, including, for example, but not limited to, dry etching, wet etching, plasma etching, or a suitable combination thereof. At step S128, a sixth etching process is performed to remove the pad layer 104 from the top 202 of the fin 112, resulting in the fin 112 being exposed within the STI material 208. It should be understood that the removal of the pad layer 104 can be performed by etching, i.e., wet etching, dry etching, and / or plasma etching. At step S130, the fin 112 is recessed relative to the STI material 208. As will be understood, the fin recess may correspond to the definition of the fin height of the fin 112 of the FinFET device. As described above, the removal of such STI material 208 can be accomplished by wet etching, dry etching, plasma etching, or the like. At step S132, a gate oxide component 308 is formed on the fin 112 of the FinFET device. Thereafter, at step S134, a gate structure 306 is formed on the FinFET device.

[0095] Reference now Figure 8 , wherein the formation is shown to be incorporated according to the above Figure 7 The method 800 of manufacturing a semiconductor device with one or more FinFET structures / devices according to the exemplary method described herein is as follows. At step S200, a FinFET region 122 is first formed on a substrate 102. Figures 1A to 1J As shown in FIG. 1 , the FinFET region 122 includes one or more fins 112. At step S202, at least one device isolation structure 114 is formed between each of the fins 112 on the substrate 102. At step S204, a reinforcement layer 116 is formed on the fins 112 and in the device isolation structure 114. At step S206, a portion of the fins 112 is removed to form a trench region 120. At step S208, etching is performed to remove a portion of the reinforcement layer 116. Thereafter, at step S210, an STI material 208 is deposited in the device isolation structure 114.

[0096] According to a first embodiment, a method for forming a semiconductor device is provided. The method includes performing a first etching process to define one or more fins and corresponding device isolation structures on a substrate. The method further includes forming a reinforcement layer on each of the fins so that the reinforcement layer seals each fin. The method further performs a second etching process to remove one or more of the fins, and performs a third etching process to remove a portion of the reinforcement layer. The method also includes depositing STI material on the fins and the device isolation structure, and then recessing the fin relative to the STI material. In some embodiments, the reinforcement layer includes at least one of an oxide or a nitride. In some embodiments, the reinforcement layer is silicon nitride. In some embodiments, the reinforcement layer is deposited in a range of about 1 angstrom to 30 angstroms. In some embodiments, the method further includes forming a gate oxide component on at least one of the fins. In some embodiments, the method further includes forming a gate structure on the gate oxide component. In some embodiments, before performing the first etching process, it further includes depositing a liner layer on the substrate, depositing a first insulating layer on the liner layer, depositing a hard mask layer on the first insulating layer, and patterning a photoresist on the hard mask layer, wherein the first etching process is performed according to the patterned photoresist. In some embodiments, the method further includes performing a chemical mechanical polishing process to remove the hard mask layer before depositing the shallow trench isolation material. In some embodiments, the method further includes performing a chemical mechanical polishing process to expose the first insulating layer. In some embodiments, the method further includes performing a fourth etching process to remove a portion of the shallow trench isolation material. In some embodiments, the method further includes performing a fifth etching process to remove the first insulating layer. In some embodiments, the method further includes performing a sixth etching process to remove the liner layer.

[0097] According to a second embodiment, a semiconductor device including a substrate is provided. The substrate includes a FinFET region formed on the substrate, wherein the FinFET region includes one or more fins. The semiconductor device further includes one or more device isolation structures formed on the substrate and disposed adjacent to the one or more fins. In addition, the semiconductor device includes an enhancement layer formed on a portion of the one or more fins. In some embodiments, the device isolation structure includes at least one of a silicon local oxidation region, a shallow trench isolation, a deep trench isolation, a buffer oxide region, or a deep well formation. In some embodiments, the enhancement layer includes at least one of silicon, oxygen, or nitrogen. In some embodiments, the enhancement layer further includes at least one of Si, O, C, N, P, As, B, or Ga at an atomic concentration of at least 1%. In some embodiments, the enhancement layer is deposited with a thickness in the range of about 1A to 30A.

[0098] According to a third embodiment, a method for forming a semiconductor device is provided. The method includes forming a FinFET region on a substrate, wherein the FinFET region includes one or more fins. The method further includes forming one or more device isolation structures on the substrate, the one or more device isolation structures being adjacent to the one or more fins. The method also includes forming an enhancement layer on the one or more fins and the one or more device isolation structures. In addition, the method includes etching to remove at least one of the fins. In some embodiments, the method further includes depositing a shallow trench isolation material on the device isolation structure. In some embodiments, the enhancement layer includes at least 1% atomic concentration of at least one of Si, O, C, N, P, As, B, or Ga; and wherein the enhancement layer is deposited with a thickness in the range of about 1A to 30A.

[0099] According to a fourth embodiment, a semiconductor device is provided, which includes a substrate, at least one device isolation structure formed on the substrate, a shallow trench isolation material deposited on the device isolation structure, and an enhancement layer. The substrate includes a fin field effect transistor region formed on the substrate, the fin field effect transistor region includes at least one fin, and the device isolation structure is disposed adjacent to the at least one fin. The enhancement layer is formed on at least a portion of the at least one fin, and the enhancement layer is deposited with a thickness in the range of 1A to 30A. In some embodiments, the semiconductor device further includes a gate oxide component disposed on at least a portion of the at least one fin. In some embodiments, the semiconductor device further includes a gate structure disposed on the gate oxide component. In some embodiments, the semiconductor device further includes a liner disposed between the shallow trench isolation material and the at least one fin.

[0100] According to a fifth embodiment, a semiconductor device is provided, which includes a substrate, at least one device isolation structure formed on the substrate, and an enhancement layer. The substrate includes a fin field effect transistor region and a trench region formed on the substrate, and the fin field effect transistor region includes at least one fin adjacent to the trench region. The device isolation structure is disposed adjacent to the at least one fin, and the enhancement layer is formed on the sidewall of the at least one fin.

[0101] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: A substrate, the substrate comprising a FinFET region formed on the substrate, the FinFET region comprising at least one fin; at least one device isolation structure formed on the substrate, the at least one device isolation structure disposed adjacent to the at least one fin; and A reinforcement layer is formed on at least a portion of the at least one fin.

2. The semiconductor device according to claim 1, wherein The at least one device isolation structure includes at least one of a silicon local oxidation region, a shallow trench isolation, a deep trench isolation, a buffer oxide region, or a deep well formation.

3. The semiconductor device according to claim 1, wherein: The enhancement layer is deposited with a thickness ranging from 1 Å to 30 Å.

4. The semiconductor device according to claim 1, wherein: A gate oxide component is also included, which is disposed on at least a portion of the at least one fin.

5. The semiconductor device according to claim 4, wherein: The invention also comprises a gate structure which is arranged on the gate oxide component.

6. A semiconductor device, characterized in that: Include: A substrate, the substrate comprising a FinFET region formed on the substrate, the FinFET region comprising at least one fin; at least one device isolation structure formed on the substrate, the at least one device isolation structure disposed adjacent to the at least one fin; a shallow trench isolation material deposited on the at least one device isolation structure; and A reinforcement layer is formed on at least a portion of the at least one fin, the reinforcement layer being deposited with a thickness ranging from 1 Å to 30 Å.

7. The semiconductor device according to claim 6, wherein: A gate oxide component is also included, which is disposed on at least a portion of the at least one fin.

8. The semiconductor device according to claim 7, wherein: The invention also comprises a gate structure which is arranged on the gate oxide component.

9. The semiconductor device according to claim 6, wherein: A liner is also included, which is disposed between the shallow trench isolation material and the at least one fin.

10. A semiconductor device, characterized in that: Include: A substrate comprising a fin field effect transistor region and a trench region formed on the substrate, wherein the fin field effect transistor region comprises at least one fin adjacent to the trench region; at least one device isolation structure formed on the substrate, the at least one device isolation structure disposed adjacent to the at least one fin; and A reinforcement layer is formed on the sidewall of the at least one fin.

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