Clock synchronization device and network clock card

Abstract

The embodiment of the utility model provides a clock synchronization device and a network clock card, and the device comprises a plurality of clock synchronization components, and each clock synchronization component is used for determining a first clock synchronization signal and a second clock synchronization signal; the clock synchronization chip is connected with the plurality of clock synchronization components and is used for obtaining at least one first clock synchronization signal corresponding to the plurality of clock synchronization components; the processing chip is connected with the plurality of clock synchronization components and is used for obtaining at least one second clock synchronization signal corresponding to the plurality of clock synchronization components; wherein the first clock synchronization signal and the second clock synchronization signal have an association relationship.

Description

Technical Field

[0001] The present application relates to but is not limited to the field of telecommunications, and in particular to a clock synchronization device and a network clock card. Background Art

[0002] In the related art, the network clock card has fewer synchronization methods and fewer outputs after synchronization, which cannot meet the application requirements of various scenarios. Utility Model Content

[0003] In view of this, an embodiment of the present application provides a clock synchronization device and a network clock card.

[0004] The technical solution of the embodiment of the present application is implemented as follows:

[0005] On the one hand, an embodiment of the present application provides a clock synchronization device, the device comprising:

[0006] A plurality of clock synchronization components, each of the clock synchronization components is used to determine a first clock synchronization signal and a second clock synchronization signal;

[0007] A clock synchronization chip, connected to the multiple clock synchronization components, and used to obtain at least one first clock synchronization signal corresponding to the multiple clock synchronization components;

[0008] A processing chip is connected to the multiple clock synchronization components and is used to obtain at least one second clock synchronization signal corresponding to the multiple clock synchronization components; wherein the first clock synchronization signal is associated with the second clock synchronization signal.

[0009] An embodiment of the present application provides a network clock card, which includes a mainboard and any one of the above-mentioned clock synchronization devices, and the clock synchronization device is located on the mainboard.

[0010] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application.

[0012] Figure 1 A schematic diagram of the structure of a clock synchronization device provided in an embodiment of the present application;

[0013] Figure 2 A schematic diagram of the structure of a network clock card provided in this application;

[0014] Figure 3A schematic diagram of the structure of a network clock card provided in this application. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0016] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0017] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are merely to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0018] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the general understanding of those skilled in the art in the field to which the embodiments of the present application belong. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0019] In modern communication networks, most telecommunication services require that the frequency or time differences between devices in the entire network remain within a reasonable error level, that is, network clock synchronization. In related technologies, most network clock cards only have 1588 or 1588 and Synchronous Ethernet (SyncE) synchronization methods, and a few have Global Navigation Satellite System (GNSS) synchronization methods. The output after synchronization is very small, which cannot meet the application requirements of various scenarios.

[0020] An embodiment of the present application provides a clock synchronization device. On the one hand, it determines the clock synchronization signals emitted by different clock synchronization components through multiple clock synchronization components, and can support multiple synchronization modes. Compared with a clock synchronization device that only supports one synchronization mode, it can meet the needs of various application scenarios. On the other hand, it uses a clock synchronization chip and a processing chip to respectively process different clock synchronization signals with related relationships, thereby improving the stability of the processed clock synchronization signals.

[0021] Figure 1 A schematic diagram of the structure of a clock synchronization device provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the clock synchronization device 100 includes a plurality of clock synchronization components 101, a clock synchronization chip 102 and a processing chip 103, wherein:

[0022] A plurality of clock synchronization components 101, each of the clock synchronization components is used to determine a first clock synchronization signal and a second clock synchronization signal;

[0023] A clock synchronization chip 102, connected to the multiple clock synchronization components, and configured to obtain at least one first clock synchronization signal corresponding to the multiple clock synchronization components;

[0024] The processing chip 103 is connected to the multiple clock synchronization components and is used to obtain at least one second clock synchronization signal corresponding to the multiple clock synchronization components; wherein the first clock synchronization signal is associated with the second clock synchronization signal.

[0025] Here, multiple clock synchronization components 101 may include but are not limited to satellite timing synchronizers, precise time sources, external clock sources, etc. The satellite timing synchronizer may receive standard time from a specified satellite, and further determine the first clock synchronization signal and the second clock synchronization signal through the standard time. The precise time source may extract the clock synchronization signal (including the first clock synchronization signal and the second clock synchronization signal) from the 1588 message through the Precision Time Protocol (PTP). In some embodiments, PTP is also referred to as the 1588 protocol. The external clock source is connected to an external higher-level clock through the Ethernet interface of the device to determine the first clock synchronization signal and the second clock synchronization signal.

[0026] The clock synchronization signal (including the first clock synchronization signal and the second clock synchronization signal) can be any suitable signal. For example, the first clock synchronization signal can be a periodic pulse signal, where the period can be any suitable period, for example, seconds. In this case, the periodic pulse signal is a pulse per second signal (Pulse Per Second, 1PPS). For another example, the first clock synchronization signal can be a periodic clock signal, which can be used for counting and synchronizing time. For another example, the first clock synchronization signal can be a time of day (TOD) signal, which is used to indicate the date and time of the current moment.

[0027] In some implementations, the first clock synchronization signal and the second clock synchronization signal may be different signals. In implementation, the first clock synchronization signal and the second clock synchronization signal appear in pairs.

[0028] In some implementations, when the first clock synchronization signal may be a second pulse signal, the second clock synchronization signal may be a time and date signal. In implementation, the first clock synchronization signal may provide an absolute time, and the second clock synchronization signal may provide a relative time. The combination of the first clock synchronization signal and the second clock synchronization signal may achieve accurate time synchronization, thereby obtaining more accurate time information.

[0029] The clock synchronization chip can be any suitable chip, for example, a phase-locked loop chip (Phase Locked Loop, PPL), a network time chip (Network Time Protocol, NTP), etc. The phase-locked loop chip has the functions of clock multiplication, division, phase shift and programmable duty cycle, and can realize clock management and offset control. During implementation, the input pin of the clock synchronization chip is connected to the output interface of the clock synchronization component, and the first clock synchronization signal sent by the clock synchronization component connected to the input pin is obtained through the input pin of the clock synchronization chip.

[0030] The processing chip can be any suitable chip, for example, a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), etc. The Field Programmable Gate Array chip is composed of a programmable input and output unit, a basic programmable logic unit, a complete clock management, an embedded block random access memory (RAM), abundant wiring resources, an embedded bottom functional unit, and an embedded dedicated hardware module. During implementation, the input pin of the processing chip is connected to the output interface of the clock synchronization component, and the second clock synchronization signal sent by the clock synchronization component connected to the input pin is obtained through the input pin of the clock synchronization chip.

[0031] In the embodiments of the present application, on the one hand, through multiple clock synchronization components, clock synchronization signals emitted by different clock synchronization components can be obtained, thereby being able to support multiple synchronization modes. Compared with the clock synchronization device that supports a single synchronization mode, it can meet a variety of application scenarios; on the other hand, clock synchronization chips and processing chips are used to respectively process different clock synchronization signals with related relationships, thereby improving the stability of the processed clock synchronization signals.

[0032] In some embodiments, the clock synchronization component 101 includes a satellite timing synchronizer; the satellite timing synchronizer is connected to a satellite timing receiver, and the satellite timing receiver is used to receive standard time from a designated satellite; the satellite timing synchronizer is used to determine the first clock synchronization signal and the second clock synchronization signal according to the standard time.

[0033] Here, the designated satellite is a satellite selected by the satellite timing receiver based on factors such as the signal strength of multiple satellites, the position of the satellite, the visibility of the satellite, and the position of the satellite timing receiver. The satellite timing receiver is used to receive the standard time from the designated satellite, and the satellite timing synchronizer synchronously generates a timing signal, and decodes the received standard time of the designated satellite to obtain the first clock synchronization signal and the second clock synchronization signal. In some embodiments, the first clock synchronization signal and the second clock synchronization signal can be output through different output interfaces of the satellite timing synchronizer. For example, the satellite timing synchronizer can output the first clock synchronization signal and the second clock synchronization signal through a serial port interface or a network port interface. In some embodiments, the first clock synchronization signal output by the satellite timing synchronizer can be a second pulse signal, and the second clock synchronization signal can be a time and date signal.

[0034] In an embodiment of the present application, a clock synchronization signal composed of the standard time of a specified satellite is synchronized by a satellite timing synchronizer, which can meet the synchronization requirements of application scenarios for the standard time of the specified satellite.

[0035] In some implementations, the clock synchronization component 101 includes a specific input interface, where the specific input interface is used to connect to an external clock synchronization component, where the external clock synchronization component is used to determine the first clock synchronization signal and the second clock synchronization signal.

[0036] Here, the specific input interface can be any suitable interface, for example, an RJ45 input interface, an RJ11 input interface, etc. The RJ45 input interface is a connector for an Ethernet cable, and is mainly used to connect various external clock synchronization components. External clock synchronization components may include, but are not limited to, a communication building integrated timing supply system clock synchronization component (Building Integrated Timing Supply System, BITS), a line clock synchronization component, and a precision time protocol clock synchronization component (Precise Time Protocol, PTP), etc. During implementation, the specific input interface is connected to the output interface of the external clock synchronization component, and through the output interface of the external clock synchronization component, the specific input interface can obtain the first clock synchronization signal and the second clock synchronization signal sent by the output interface of the external clock synchronization component to which the input interface is connected.

[0037] In some implementations, the first clock synchronization signal and the second clock synchronization signal, after passing through a specific input interface, will pass through a level conversion chip and then be input to the clock synchronization chip and the processing chip respectively. The level conversion chip is mainly used to convert the level so that the clock synchronization chip and the processing chip can adapt to the level of the specific input interface so that they can communicate with each other.

[0038] In an embodiment of the present application, an external clock synchronization component is connected through a specific input interface to receive information from the external clock synchronization component, so as to facilitate the subsequent use of multiple synchronization methods to achieve synchronization and meet the synchronization requirements of various application scenarios.

[0039] In some embodiments, the clock synchronization device 100 also includes a specific output interface, which is connected to the device to be clock synchronized, and is used to output the first clock synchronization signal processed by the clock synchronization chip and the second clock synchronization signal processed by the processing chip to the device to be clock synchronized.

[0040] Here, the specific output interface can be any suitable interface, for example, an RJ45 output interface, an RJ11 output interface, etc. The devices to be clock synchronized can include but are not limited to routers, communication equipment, etc. During implementation, after a device to be clock synchronized receives the processed first clock synchronization signal and the second clock synchronization signal, the device to be clock synchronized can be synchronized with other devices to be clock synchronized. During implementation, the specific output interface is connected to the input interface of the device to be clock synchronized, and the specific output interface can first obtain the first clock synchronization signal processed by the clock synchronization chip and the second clock synchronization signal processed by the processing chip, and then send the first clock synchronization signal and the second clock synchronization signal to the device to be clock synchronized corresponding to the specific output interface.

[0041] In some implementations, the first clock synchronization signal processed by the clock synchronization chip and the second clock synchronization signal processed by the processing chip will pass through the level conversion chip and then be output to the device to be clock synchronized through a specific output interface. The level conversion chip is mainly used to enable the clock synchronization chip and the processing chip to adapt to the level of the specific output interface so that they can communicate with each other.

[0042] In the embodiment of the present application, the processed clock synchronization signal is output to the device to be clock synchronized through a specific output interface, thereby ensuring that the device to be clock synchronized can achieve synchronization and meet the synchronization requirements of the device to be clock synchronized.

[0043] In some implementations, the clock synchronization device 100 further includes a bus input interface, where the bus input interface is used to connect to an external device, and the external device is used to determine the first clock synchronization signal and the second clock synchronization signal.

[0044] Here, the bus input interface (Peripheral Component Interconnect Express, PCI-E) is any suitable interface, for example, PCI-E x4, PCI-E x8, PCI-E x16, etc. The bus input interface belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, allocates exclusive channel bandwidth for the connected device, does not share the bus bandwidth, and mainly supports active power management, error reporting, end-to-end reliability transmission, hot plug and service quality and other functions. The external device may include but is not limited to a global positioning system (Global Positioning System, GPS) receiver, a network service server (Network Time Protocol, NTP), other clock synchronization interface input (Other Timing Interface Input, OTII), etc. For example, when the external device is a global positioning system receiver, the bus input interface receives the time signal from the GPS through the global positioning system receiver, and further determines the first clock synchronization signal and the second clock synchronization signal. In implementation, the bus input interface is connected to the output interface of the external device, and the bus input interface can obtain the first clock synchronization signal and the second clock synchronization signal sent by the output interface of the external device corresponding to the bus input interface.

[0045] In the embodiment of the present application, the clock synchronization signal is determined by connecting an external device through a bus input interface, which further enriches the application scenarios of the clock synchronization device.

[0046] In some embodiments, the clock synchronization component 101 includes a precise time source, which includes a first interface; the processing chip includes an auxiliary clock, and the first interface is connected to the auxiliary clock, and is used to determine the first clock synchronization signal and the second clock synchronization signal according to the auxiliary clock when the precise time source is configured as an auxiliary mode.

[0047] Here, the precise time source may include but is not limited to a first synchronization source and a second synchronization source, wherein the first synchronization source indicates that the synchronization source has a 1588 synchronization function. The second synchronization time source indicates that the synchronization source has a 1588 and synchronous Ethernet synchronization function. The 1588 protocol (also known as the Precision Time Protocol) is a precision time synchronization protocol standard for network measurement and control systems, which is used to achieve high-precision time synchronization between devices, and can also be used for frequency synchronization between devices. Synchronous Ethernet is used for frequency synchronization between Ethernet devices. The 1588 synchronization source refers to a synchronization signal source provided only by the 1588 protocol, which achieves clock synchronization through mutual communication and calibration between master and slave clock devices in the network. The 1588 and synchronous Ethernet synchronization sources are synchronization signal sources provided by synchronous Ethernet and the 1588 protocol, which have high accuracy and stability, and can meet application scenarios with high requirements for clock synchronization, such as communication operators, data centers, etc.

[0048] The auxiliary clock may be used to receive time data input from the first interface, and perform operations such as parsing, packaging, and checking the time data. In implementation, the auxiliary clock may be any suitable clock, such as a media access controller (MAC).

[0049] The first interface can be any suitable interface. For example, a small form-factor pluggable optical module interface (SFP), a quad small form-factor pluggable optical module interface (QSFP), etc. The first interface is mainly composed of optoelectronic devices, functional circuits, optical interfaces, etc., and its main function is to realize photoelectric conversion and electro-optical conversion functions. The auxiliary mode characterizes that the priority of the first interface of the precise time source is lower than the priority of the second interface. At this time, the first interface of the precise time source is used as the input interface. The precise time source receives the time data sent by the external time server (for example, GPS, NTP, etc.) through the first interface, and synchronously sends the time data to the auxiliary clock, so that the auxiliary clock parses the time data to determine the first clock synchronization signal and the second clock synchronization signal.

[0050] In the embodiment of the present application, the clock synchronization signal is determined by a precise time source and an auxiliary clock, which can meet the synchronization requirements of the clock synchronization device in the application scenario under the precise time source.

[0051] In some embodiments, the precise time source includes a second interface; the second interface is used to output the first clock synchronization signal processed by the clock synchronization chip and the second clock synchronization signal processed by the processing chip to the device to be clock synchronized when the precise time source is configured as a main mode.

[0052] Here, the second interface can be any suitable interface, for example, a small package hot-swappable optical module interface, a four-channel small package hot-swappable optical module interface, etc. The master mode indicates that the priority of the second interface of the precise time source is higher than the priority of the first interface. At this time, the second interface of the precise time source is used as an output interface to output the first clock synchronization signal processed by the clock synchronization chip and the second clock synchronization signal processed by the processing chip to the device to be clock synchronized, thereby enabling the device to be clock synchronized to be synchronized. The device to be clock synchronized may include but is not limited to routers, communication equipment, etc.

[0053] In the embodiment of the present application, the processed clock synchronization signal is output to the device to be clock synchronized through the second interface of the precise time source, which can meet the synchronization requirements of the device to be clock synchronized in the application scenario under the precise time source.

[0054] In some implementations, the clock synchronization apparatus 100 further includes a connector for outputting the first clock synchronization signal processed by the clock synchronization chip and the second clock synchronization signal processed by the processing chip to the device to be clock synchronized.

[0055] Here, the connector can be any suitable connector, for example, a coaxial cable connector (Bayonet Neill-Concelman, BNC), a high-frequency signal connector (Sub Miniature version A, SMA), etc. The coaxial cable connector is used for low-frequency, low-rate signal transmission. The high-frequency signal connector is used for high-frequency, high-rate signal transmission. During implementation, the input interface of the connector is connected to the output interface of the clock synchronization chip, and the input interface of the connector can obtain the processed first clock synchronization signal sent by the output interface of the clock synchronization chip corresponding to the input interface of the connector, and obtain the processed second clock synchronization signal sent by the output interface of the processing chip corresponding to the input interface of the connector.

[0056] In an embodiment of the present application, the processed clock synchronization signal is output to the device to be clock synchronized through a connector, which can meet the synchronization requirements of the device to be clock synchronized in different scenarios.

[0057] In some implementations, the clock synchronization chip further includes a priority configuration component, and the priority configuration component is used to configure the priorities between different clock synchronization components.

[0058] Here, priority is a specified attribute of each clock source. In some embodiments, the smaller the priority value of the clock synchronization component, the higher the priority of the clock synchronization component. In some embodiments, the larger the priority value of the clock synchronization component, the higher the priority of the clock synchronization component. During implementation, the priority can be configured for each clock synchronization component through the priority configuration component, or the system can automatically configure the priority for each clock synchronization component.

[0059] In the embodiment of the present application, by configuring different priorities for the clock synchronization components, switching of different clock synchronization components can be achieved according to different application scenarios.

[0060] Based on the above embodiments, the present application also provides a network clock card. Figure 2 A schematic diagram of the structure of a network clock card provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the network clock card 20 includes a mainboard 21 and a clock synchronization device 22 , and the clock synchronization device 22 is located on the mainboard 21 .

[0061] Here, the clock synchronization device may be any of the above-mentioned clock synchronization devices. In some implementations, the clock synchronization chip and the processing chip may also be located on the mainboard.

[0062] In the embodiment of the present application, by adapting the network clock card of the clock synchronization device, multiple synchronization modes can be supported to meet the needs of various application scenarios.

[0063] The following describes the application of the clock synchronization device provided in an embodiment of the present application in a practical scenario.

[0064] In modern communication networks, most telecommunication services require that the frequency or time differences between devices in the entire network remain within a reasonable error level, that is, network clock synchronization. In related technologies, most network clock cards only have 1588, or 1588 and synchronous Ethernet synchronization methods, and a few have satellite timing synchronization methods. The output after synchronization is very small, which cannot meet the application requirements of various scenarios.

[0065] An embodiment of the present application provides a clock synchronization device. On the one hand, it determines the clock synchronization signals emitted by different clock synchronization components through multiple clock synchronization components, and can support multiple synchronization modes. Compared with a clock synchronization device that only supports one synchronization mode, it can meet the needs of various application scenarios. On the other hand, it adopts a clock synchronization chip and a processing chip to respectively process different clock synchronization signals with related relationships, thereby improving the processed clock synchronization signal and stability.

[0066] Figure 3 A schematic diagram of the structure of a network clock card provided in this application, such as Figure 3 As shown, the network clock card 20 includes a mainboard (not shown in the figure) and a clock synchronization device 22, the clock synchronization device 22 includes a PLL chip 25 (corresponding to the aforementioned clock synchronization chip), an FPGA chip 24 (corresponding to the aforementioned processing chip), multiple clock synchronization components 23, a connector 26, a bus input interface 27, a first level conversion chip 28, an RJ45 output interface 29 (corresponding to the aforementioned specific output interface), a second level conversion chip 210 and a bus output interface 211, the FPGA chip 24 includes an ARM unit 241, a first auxiliary clock 242 and a second auxiliary clock 243, the ARM unit 241 includes a TOD module 2411 and a PTP module 2412, and the multiple clock synchronization components 23 include: a satellite timing synchronization source 231 (corresponding to the aforementioned satellite timing synchronizer) and a precise time source 232, wherein:

[0067] The PLL chip 25 is respectively connected to the FPGA chip 24, the satellite timing synchronization source 231, the first level conversion chip 28, the second level conversion chip 210, the bus input interface 27, the bus output interface 211 and the connector 26, and is used to obtain at least one first clock synchronization signal corresponding to the multiple clock synchronization components 23, the external clock synchronization components and the external device, and process the obtained first clock synchronization signal, and output the processed first clock synchronization signal;

[0068] The FPGA chip 24 is respectively connected to the PLL chip 25, the satellite timing synchronization source 231, the first level conversion chip 28, the second level conversion chip 210, the bus input interface 27, the bus output interface 211 and the connector 26, and is used to obtain at least one second clock synchronization signal corresponding to multiple clock synchronization components 23, external clock synchronization components and external devices, and process the obtained second clock synchronization signal to output the processed second clock synchronization signal; wherein the first auxiliary clock 242 of the FPGA chip 24 is configured as an auxiliary mode, for receiving the time data sent by the first SFP interface 2321, determining the first clock synchronization signal and the second clock synchronization signal, and sending the first clock synchronization signal to the PLL chip 25, and receiving the processed first clock synchronization signal output by the PLL chip 25; the TOD module 2411 and the PTP module 2412 in the ARM unit 241 are used to process the second clock synchronization signal; the second auxiliary clock 243 is configured as a main mode, for receiving the processed first clock synchronization signal and the processed second clock synchronization signal, and outputting the above signals to the second SFP interface 2322;

[0069] The connector 26 is connected to the PLL chip 25 and the FPGA chip 24, and is used to output the first clock synchronization signal processed by the PLL chip 25 and the second clock synchronization signal processed by the FPGA chip 24 to the device to be clock synchronized; in some embodiments, the connector 26 is also used to receive the frequency configurable signal sent by the PLL chip 25, and output the first clock synchronization signal and the frequency configurable signal processed by the PLL chip 25 and the second clock synchronization signal processed by the FPGA chip 24 to the device to be clock synchronized;

[0070] The bus input interface 27 is connected to the PLL chip 25 and the FPGA chip 24, and is used to connect an external device, and the external device is used to determine the first clock synchronization signal and the second clock synchronization signal;

[0071] The bus output interface 211 is connected to the PLL chip 25 and the FPGA chip 24, and is used to receive the first clock synchronization signal processed by the PLL chip 25 and the second clock synchronization signal processed by the FPGA chip 25, and output the above signals to an external device;

[0072] The first level conversion chip 28 is connected to the RJ45 input interface 233, the PLL chip 25 and the FPGA chip 24 respectively, and is used to achieve level adaptation between the PLL chip 25 and the RJ45 input interface 233 and level adaptation between the FPGA chip 24 and the RJ45 input interface 233, so that the RJ45 input interface 233 and the PLL chip 25, and the RJ45 input interface 233 and the FPGA chip 24 can communicate with each other;

[0073] The second level conversion chip 210 is connected to the RJ45 output interface 29, the PLL chip 25 and the FPGA chip 24 respectively, and is used to achieve level adaptation between the PLL chip 25 and the RJ45 output interface 29, and level adaptation between the FPGA chip 24 and the RJ45 output interface 29, so that the RJ45 output interface 29 and the PLL chip 25, and the RJ45 output interface 29 and the FPGA chip 24 can communicate with each other;

[0074] The RJ45 output interface 29 is connected to the second level conversion chip 210, and is used to output the first clock synchronization signal processed by the PLL chip 25 and the second clock synchronization signal processed by the FPGA chip 24 to the device to be clock synchronized;

[0075] The satellite timing synchronization source 231 is connected to the PLL chip 25 and the FPGA chip 24 respectively, and is used to determine the first clock synchronization signal and the second clock synchronization signal according to the standard time;

[0076] The first SFP interface 2321 of the precise time source 232 is connected to the first auxiliary clock 242 of the FPGA chip 24, and is used to send time data received from a precise time server (not shown in the figure) of the precise time source 232 to the first auxiliary clock 242; the second SFP interface 2322 is connected to the second auxiliary clock 243 of the FPGA chip 24, and is used to receive the first clock synchronization signal processed by the PLL chip 25 and the second clock synchronization signal processed by the FPGA chip 24 sent by the second auxiliary clock 243, and output the above signals to the device to be synchronized with the clock;

[0077] The multiple clock synchronization components 23 also include an RJ45 input interface 233 (corresponding to the aforementioned specific input interface), which is connected to the first level conversion chip 28 and is used to connect an external clock synchronization component, which is used to determine the first clock synchronization signal and the second clock synchronization signal.

[0078] In this way, firstly, by configuring the master-slave mode through the precise time source, the clock synchronization between devices can be realized and the cost can be reduced; secondly, through the bus input and output mode of the Open Telecom IT Infrastructure (OTII) standard clock, the time synchronization of the external device can be realized, which reduces the cost and increases the reliability compared with the use of clock synchronization cables; further, through the input mode of the RJ45 input interface, the synchronization of the external clock synchronization component can be realized; finally, a variety of clock synchronization modes can be provided, so that the configuration of the network clock card is more flexible and can meet a variety of application scenarios, and a variety of synchronization modes can adopt the master-slave mode, making the network clock card more stable.

[0079] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The serial numbers of the embodiments of the present application mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0080] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0081] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0082] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0083] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0084] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0085] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A clock synchronization device, characterized in that: The device comprises: A plurality of clock synchronization components, each of the clock synchronization components is used to determine a first clock synchronization signal and a second clock synchronization signal; A clock synchronization chip, connected to the multiple clock synchronization components, and used to obtain at least one first clock synchronization signal corresponding to the multiple clock synchronization components; a processing chip connected to the plurality of clock synchronization components, and configured to obtain at least one second clock synchronization signal corresponding to the plurality of clock synchronization components; The first clock synchronization signal and the second clock synchronization signal are associated with each other.

2. The device according to claim 1, characterized in that The clock synchronization component includes a satellite timing synchronizer; The satellite timing synchronizer is connected to a satellite timing receiver, and the satellite timing receiver is used to receive the standard time from a designated satellite; The satellite timing synchronizer is used to determine the first clock synchronization signal and the second clock synchronization signal according to the standard time.

3. The device according to claim 1, characterized in that The clock synchronization component includes a specific input interface, and the specific input interface is used to connect to an external clock synchronization component, and the external clock synchronization component is used to determine the first clock synchronization signal and the second clock synchronization signal.

4. The device according to claim 3, characterized in that The device also includes a specific output interface connected to the device to be clock synchronized, and used to output the first clock synchronization signal processed by the clock synchronization chip and the second clock synchronization signal processed by the processing chip to the device to be clock synchronized.

5. The device according to claim 1, characterized in that The device further comprises a bus input interface, wherein the bus input interface is used to connect an external device, and the external device is used to determine the first clock synchronization signal and the second clock synchronization signal.

6. The device according to claim 1, characterized in that The clock synchronization component includes a precise time source, and the precise time source includes a first interface; The processing chip includes an auxiliary clock, and the first interface is connected to the auxiliary clock, and is used to determine the first clock synchronization signal and the second clock synchronization signal according to the auxiliary clock when the precise time source is configured in the auxiliary mode.

7. The device according to claim 6, characterized in that The precise time source comprises a second interface; The second interface is used to output the first clock synchronization signal processed by the clock synchronization chip and the second clock synchronization signal processed by the processing chip to the device to be clock synchronized when the precise time source is configured in the master mode.

8. The device according to claim 1, characterized in that The device also includes a connector for outputting the first clock synchronization signal processed by the clock synchronization chip and the second clock synchronization signal processed by the processing chip to the device to be clock synchronized.

9. The device according to any one of claims 1 to 8, characterized in that The clock synchronization chip also includes a priority configuration component, and the priority configuration component is used to configure the priorities between different clock synchronization components.

10. A network clock card, characterized in that: The network clock card comprises a mainboard and the clock synchronization device according to any one of claims 1 to 9, and the clock synchronization device is located on the mainboard.

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