Groove type semiconductor device

Abstract

The utility model discloses a groove type semiconductor device. The device comprises a substrate; the channel layer is arranged on one side of the substrate, the channel layer comprises a downward concave part, and the width of the downward concave part is gradually increased in the direction vertically pointing to the channel layer along the substrate; wherein the side wall of the lower concave part is a semi-polar crystal face of the channel material; the barrier layer is located on the side, away from the substrate, of the channel layer, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer. By adopting the scheme, the forming effect of the two-dimensional electron gas on the side wall of the groove can be ensured, the concentration of the two-dimensional electron gas on the side wall of the groove is enhanced, the on resistance of the device is further reduced, the forward conduction rate is improved, and meanwhile, the breakdown voltage of the device is considered. Besides, the side wall of the groove is arranged to be a semi-polar crystal face, the epitaxial growth quality of the upper film layer on the channel layer is improved, the flatness of the connecting face of the channel layer and the barrier layer is guaranteed, lattice scattering in the two-dimensional electron gas transmission process is further reduced, and the overall performance of the device is improved.

Description

Technical Field

[0001] The embodiment of the utility model relates to the technical field of semiconductor devices, and in particular to a trench-type semiconductor device. Background Art

[0002] Traditional high electron mobility transistors (HEMTs) are all horizontal structures, that is, the two-dimensional electron gas is on the same plane. Taking gallium nitride-based semiconductor devices as an example, horizontal gallium nitride-based semiconductor devices are generally epitaxially grown on the C-plane of the gallium nitride crystal as the substrate.

[0003] With the development of semiconductor technology, the channel-type current aperture structure vertical field effect transistor (CAVET) was proposed. However, in the channel-type CAVET structure, the heterogeneous interface at the channel sidewall is no longer the crystal C plane, but may become the A plane or M plane that deviates greatly from the C plane. Since the C plane is a polar crystal plane, and the A plane and M plane are non-polar crystal planes, the spontaneous polarization effect on the non-polar crystal plane is weaker than that on the polar crystal plane, resulting in poor formation of the two-dimensional electron gas near the sidewall, affecting the overall performance of the device. Utility Model Content

[0004] The utility model provides a trench-type semiconductor device to improve the two-dimensional electron gas formation effect at the trench sidewall, enhance the two-dimensional electron gas concentration, and improve the overall performance of the device.

[0005] The trench semiconductor device provided by the embodiment of the utility model comprises:

[0006] substrate;

[0007] A channel layer is arranged on one side of the substrate, the channel layer comprises a concave portion, and the width of the concave portion gradually increases along the direction perpendicular to the substrate and pointing to the channel layer; wherein the sidewall of the concave portion is a semi-polar crystal plane of the channel material;

[0008] The barrier layer is located on a side of the channel layer away from the substrate, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer.

[0009] Optionally, the channel material is GaN;

[0010] The side wall of the concave portion is at least one of the GaN crystal planes 1 (10-12), 2 (11-23), 3 (11-22), 4 (10-11), 5 (11-21), 6 (20-21) and equivalent crystal planes of the above crystal planes.

[0011] Optionally, a first angle θ1 is formed between the sidewall of the concave portion and the first virtual plane, and the first virtual plane is perpendicular to the plane where the substrate is located;

[0012] Among them, θ1=23.39°, or θ1=21.33°, or θ1=15.78°, or θ1=14.00°, or θ1=8.54°, or θ1=7.54°.

[0013] Optionally, the trench-type semiconductor device further includes a drift layer, the drift layer is disposed on a surface of one side of the substrate, and the channel layer is located on a side of the drift layer facing away from the substrate;

[0014] The drift layer includes a groove, a concave portion is located in the groove, a sidewall of the concave portion is parallel to a sidewall of the groove, a second angle θ2 is formed between the sidewall of the groove and a first virtual plane, and the first virtual plane is perpendicular to a plane where the substrate is located;

[0015] Among them, θ2=23.39°, or θ2=21.33°, or θ2=15.78°, or θ2=14.00°, or θ2=8.54°, or θ2=7.54°.

[0016] Optionally, the trench semiconductor device further comprises a drift layer and an electron blocking layer, wherein the drift layer is disposed on one side surface of the substrate, the electron blocking layer is located on a side surface of the drift layer away from the substrate, and the channel layer covers a portion of the electron blocking layer;

[0017] The electron blocking layer includes an opening, where a portion of the drift layer is exposed, a concave portion is located in the opening, a sidewall of the concave portion is parallel to a sidewall of the opening, a third angle θ3 is formed between the sidewall of the opening and a first virtual plane, and the first virtual plane is perpendicular to a plane where the substrate is located;

[0018] Among them, θ3=23.39°, or θ3=21.33°, or θ3=15.78°, or θ3=14.00°, or θ3=8.54°, or θ3=7.54°.

[0019] Optionally, the electron blocking layer includes a GaN layer and a GaN:C layer which are sequentially stacked in a direction perpendicular to the channel layer from the substrate.

[0020] Optionally, a spacer layer is further included between the channel layer and the barrier layer.

[0021] Optionally, the trench semiconductor device further includes a gate, and the gate is located on a side of the barrier layer away from the channel layer.

[0022] Optionally, a p-type doped GaN layer is further included between the gate and the barrier layer.

[0023] Optionally, the trench-type semiconductor device further includes a source and a drain; the source is located on a side of the substrate away from the channel layer, and the drain is in contact with the two-dimensional electron gas layer.

[0024] The trench-type semiconductor device provided by the embodiment of the utility model includes: a substrate; a channel layer arranged on one side of the substrate, the channel layer includes a concave portion, and the width of the concave portion gradually increases along the direction of the substrate perpendicular to the channel layer; wherein the side wall of the concave portion is a semi-polar crystal plane of the channel material; a barrier layer, the barrier layer is located on the side of the channel layer away from the substrate, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer. The above scheme can ensure the formation effect of the two-dimensional electron gas at the side wall of the groove, enhance the concentration of the two-dimensional electron gas at the side wall of the groove, thereby reducing the on-resistance of the device, improving the forward conduction rate, and taking into account the breakdown voltage of the device at the same time, ensuring that the device has better performance. In addition, setting the side wall of the groove as a semi-polar crystal plane is also conducive to improving the epitaxial growth quality of the film layer above the channel layer, ensuring the flatness of the interface between the channel layer and the barrier layer, and thereby reducing the lattice scattering of the two-dimensional electron gas transmission process, so that the device as a whole achieves the purpose of low impedance and high frequency response. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic structural diagram of a trench-type semiconductor device provided by an embodiment of the utility model;

[0026] Figure 2 A schematic diagram of a GaN crystal structure provided in an embodiment of the utility model;

[0027] Figure 3 A schematic structural diagram of another trench-type semiconductor device provided by an embodiment of the utility model;

[0028] Figure 4 A schematic structural diagram of another trench-type semiconductor device provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0029] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0030] In view of the problems in the above background technology, the present application proposes a trench type semiconductor device. Figure 1 A schematic diagram of the structure of a trench-type semiconductor device provided by an embodiment of the utility model is shown in FIG. Figure 1As shown in the figure, the trench-type semiconductor device includes: a substrate 1; a channel layer 2 disposed on one side of the substrate 1, the channel layer 2 including a concave portion 20, and the width of the concave portion 20 gradually increasing along the direction perpendicular to the substrate 1 and pointing to the channel layer 2; wherein, the side wall 201 of the concave portion 20 is a semi-polar crystal plane of the channel material; a barrier layer 3, the barrier layer 3 is located on the side of the channel layer 2 away from the substrate 1, and a two-dimensional electron gas layer 4 is formed between the channel layer 2 and the barrier layer 3.

[0031] Among them, the substrate 1 can be selected from semiconductor materials of group III-V or group II-IV, such as GaN, GaAs, InP, and Ga2O3, etc., but not limited thereto. In the embodiments of the present invention, the substrate 1 is taken as a GaN substrate as an example for introduction, and semiconductor devices of other material systems can be adjusted based on the embodiments of this application, which will not be described in detail here.

[0032] Continue to refer to Figure 1 , a channel layer 2 is disposed on one side of the substrate 1, and a barrier layer 3 is disposed on the side of the channel layer 2 away from the substrate 1. The channel layer 2 can be an unintentionally doped GaN layer, and the barrier layer 3 can be an Al x Ga 1-x N layer, 0 < x < 1, but not limited thereto. The channel layer 2 includes a concave portion 20 and an extension portion 21, and the extension portion 21 is located on the left and right sides of the concave portion 20. The extension portion 21 extends in the horizontal direction, and the concave portion 20 extends downward to form a trench 5, and the side wall of the trench 5 is the side wall 201 of the concave portion 20. Among them, the direction perpendicular to the substrate 1 and pointing to the channel layer 2 can be defined as the direction from bottom to top. As Figure 1 shown, from bottom to top, the width of the concave portion 20 gradually increases, that is, the trench 5 has a shape with a wider top and a narrower bottom.

[0033] A two-dimensional electron gas layer 4 is formed at the heterointerface between the channel layer 2 and the barrier layer 3 above it for generating a two-dimensional electron gas. Among them, the two-dimensional electron gas layer 4 is formed on the side of the channel layer 2 close to the barrier layer 3. It is worth noting that in the embodiments of the present invention, the side wall 201 of the concave portion 20 of the channel layer 2 is controlled to be a semi-polar crystal plane of the channel material. Compared with the non-polar crystal plane, the spontaneous polarization effect of the semi-polar crystal plane is higher, which can ensure the formation effect of the two-dimensional electron gas at the side wall of the trench 5, enhance the concentration of the two-dimensional electron gas at the side wall of the trench 5, thereby reducing the on-resistance of the device, increasing the forward conduction rate, and at the same time taking into account the breakdown voltage of the device to ensure that the device has better performance. In addition, setting the side wall of the trench 5 as a semi-polar crystal plane is also beneficial to improving the epitaxial growth quality of the film layer above the channel layer 2, ensuring the flatness of the interface between the channel layer 2 and the barrier layer 3, and thus reducing the lattice scattering during the transmission of the two-dimensional electron gas, so that the overall device achieves the purpose of low impedance and high-frequency response.

[0034] The cross-sectional shape of the concave portion 20 may be a U-shaped shape, and the bottom surface of the concave portion 20 may be a C-plane of GaN. Those skilled in the art will know that GaN crystals include multiple semi-polar crystal planes, and the embodiment of the utility model does not limit which semi-polar crystal plane the sidewall of the groove 5 is, and those skilled in the art may set it according to actual conditions.

[0035] In the embodiment of the utility model, the trench-type semiconductor device includes: a substrate; a channel layer arranged on one side of the substrate, the channel layer includes a concave portion, and the width of the concave portion gradually increases along the direction of the substrate perpendicular to the channel layer; wherein the side wall of the concave portion is a semi-polar crystal plane of the channel material; a barrier layer, the barrier layer is located on the side of the channel layer away from the substrate, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer. The above scheme can ensure the formation effect of the two-dimensional electron gas at the side wall of the groove, enhance the concentration of the two-dimensional electron gas at the side wall of the groove, thereby reducing the on-resistance of the device, improving the forward conduction rate, and taking into account the breakdown voltage of the device at the same time, ensuring that the device has better performance. In addition, setting the side wall of the groove as a semi-polar crystal plane is also conducive to improving the epitaxial growth quality of the film layer above the channel layer, ensuring the flatness of the interface between the channel layer and the barrier layer, thereby reducing the lattice scattering of the two-dimensional electron gas transmission process, so that the device as a whole achieves the purpose of low impedance and high frequency response.

[0036] Exemplarily, in a possible embodiment, when the channel material is GaN, the sidewall of the recessed portion is at least one of crystal planes 1 (10-12), 2 (11-23), 3 (11-22), 4 (10-11), 5 (11-21), 6 (20-21) of GaN, and equivalent crystal planes of the above crystal planes.

[0037] Specifically, Figure 2 A schematic diagram of a GaN crystal structure provided in an embodiment of the utility model is shown in FIG. Figure 2 As shown, the semipolar crystal planes of GaN crystal include Figure 2 The multiple crystal planes shown in Figures (a) to (f) and the equivalent crystal planes of each crystal plane, Figure 2 The crystal planes filled with patterns in the figure represent semi-polar crystal planes. Figure 2 The figure (a) shows the crystal plane 2 (11-23), Figure 2 The figure (b) shows the crystal planes 3 (11-22), Figure 2 Figure (c) shows (11-21), Figure 2 The figure (d) shows the crystal plane 1 (10-12), Figure 2 The figure (e) shows the crystal planes 4 (10-11), Figure 2 The figure (f) shows crystal plane six (20-21). Figure 2 In (a) to (c), the direction perpendicular to the paper plane is the [1-100] crystal direction. Figure 2 In the middle (d) to (f), the direction perpendicular to the paper plane is the [1-210] crystal direction. In the embodiment of the utility model, the sidewall of the groove of the channel layer can be set to any of the above crystal planes.

[0038] Furthermore, the sidewall crystal plane can be regulated by adjusting the angle of the trench sidewall. Figure 1 , there is a first angle θ1 between the side 201 of the recess 20 and the first virtual plane 6, and the first virtual plane 6 is perpendicular to the plane where the substrate 1 is located; θ1=23.39°, or, θ1=21.33°, or, θ1=15.78°, or, θ1=14.00°, or, θ1=8.54°, or, θ1=7.54°.

[0039] Specifically, the first virtual plane 6 is a plane perpendicular to the substrate 1, or it can also be understood that the first virtual plane 6 is perpendicular to the C-plane (polar crystal plane) of GaN. The inventors of the present application found that when the angle θ1 between the sidewall 201 of the lower recess 20 and the first virtual plane 6 is 23.39°, the sidewall of the channel layer corresponds to the crystal plane one (10-12) of GaN and its equivalent crystal plane. When the angle θ1 between the sidewall 201 of the lower recess 20 and the first virtual plane 6 is 21.33°, the sidewall of the channel layer corresponds to the crystal plane two (11-23) of GaN and its equivalent crystal plane. When the angle θ1 between the sidewall 201 of the lower recess 20 and the first virtual plane 6 is 15.78°, the sidewall of the channel layer corresponds to the crystal plane three (11-22) of GaN and its equivalent crystal plane. When the angle θ1 between the sidewall 201 of the lower recess 20 and the first virtual plane 6 is 8.54°, the sidewall of the channel layer corresponds to the crystal plane 5 (11-21) of GaN and its equivalent crystal plane. When the angle θ1 between the sidewall 201 of the lower recess 20 and the first virtual plane 6 is 7.54°, the sidewall of the channel layer corresponds to the crystal plane 6 (20-21) of GaN and its equivalent crystal plane.

[0040] Therefore, when preparing the channel layer 2, the first angle θ1 between the sidewall 201 of the recess 20 and the first virtual plane 6 can be controlled to be any of the above angles to ensure that the sidewall of the channel layer is a semi-polar crystal plane.

[0041] Optional, you can continue to refer to Figure 1In some embodiments, the trench semiconductor device further includes a drift layer 7, which is disposed on one side surface of the substrate 1, and the channel layer 2 is located on the side of the drift layer 7 away from the substrate 1; the drift layer 7 includes a groove 70, the recessed portion 20 is located in the groove 70, the sidewall 201 of the recessed portion 20 is parallel to the sidewall 701 of the groove 70, and a second angle θ2 is formed between the sidewall 701 of the groove 70 and the first virtual plane 6, and the first virtual plane 6 is perpendicular to the plane where the substrate 1 is located; wherein, θ2=23.39°, or, θ2=21.33°, or, θ2=15.78°, or, θ2=14.00°, or, θ2=8.54°, or, θ2=7.54°.

[0042] like Figure 1 As shown, in this embodiment, a drift layer 7 is provided on one side surface of the substrate 1, and the presence of the drift layer 7 is beneficial to improving the conductivity and switching speed of the device. The drift layer 7 may be an unintentionally doped GaN layer or an n-type doped GaN layer, but is not limited thereto. A groove 70 is provided in the drift layer 7, and the groove 70 extends downward to a certain depth from the surface of the side of the drift layer 7 away from the substrate 1, and the groove 70 is in a shape of being wide at the top and narrow at the bottom. The channel layer 2 is formed on the side of the drift layer 7 away from the substrate 1, and the concave portion 20 of the channel layer 2 is located in the groove 70, and the concave portion 20 is in contact with the inner wall of the groove 70, and the angle θ2 between the side wall 701 of the groove 70 and the first virtual plane 6 is equal to the angle θ1 between the side wall 201 of the concave portion 20 and the first virtual plane 6.

[0043] The angle θ2 between the sidewall 701 of the groove 70 in the drift layer 7 and the first virtual plane 6 can be set to 23.39°, 21.33°, 15.78°, 14.00°, 8.54° or 7.54°. In this way, based on the sidewall angle of the groove 70 in the drift layer 7, when the channel layer 2 is prepared on the drift layer 7, the sidewall angle of the concave portion 20 of the channel layer 2 can be more accurately controlled, thereby ensuring that the heterogeneous interface between the channel layer 2 and the barrier layer 3 is a semi-polar crystal plane.

[0044] Optionally, the groove 5 is generally formed by an etching process, and the sidewall angle of the groove 5 can be controlled by adjusting the etching process parameters, which is not described in detail or limited in the embodiments of the present invention. In addition, when the channel layer 2 is deposited on the drift layer 7, the sidewall angle of the channel layer 2 can also be ensured to meet the above angle requirements by adjusting the process parameters.

[0045] Optional, Figure 3 A schematic diagram of another trench semiconductor device provided by an embodiment of the present utility model, referring to Figure 3In another possible embodiment, the trench semiconductor device may further include a drift layer 7 and an electron blocking layer 8, the drift layer 7 is arranged on one side surface of the substrate 1, the electron blocking layer 8 is located on the side surface of the drift layer 7 facing away from the substrate 1, and the channel layer 2 covers a portion of the electron blocking layer 8; the electron blocking layer 8 includes an opening 80, and a portion of the drift layer 7 is exposed at the opening 80, the recess 20 is located in the opening 80, the side wall 201 of the recess 20 is parallel to the side wall 801 of the opening 80, and a third angle θ3 is formed between the side wall 801 of the opening 80 and the first virtual plane 6, and the first virtual plane 6 is perpendicular to the plane where the substrate 1 is located; wherein, θ3=23.39°, or, θ3=21.33°, or, θ3=15.78°, or, θ3=14.00°, or, θ3=8.54°, or, θ3=7.54°.

[0046] Figure 3 In the illustrated embodiment, a drift layer 7 is disposed on one surface of the substrate 1, and the drift layer 7 may be an unintentionally doped GaN layer or an n-type doped GaN layer. An electron blocking layer 8 is also disposed on the side of the drift layer 7 facing away from the substrate 1, and the presence of the electron blocking layer 8 may prevent reverse leakage current and improve device performance. The material of the electron blocking layer 8 is not limited, for example, AlGaN, GaN, AlInN or AlInGaN may be selected, but is not limited thereto.

[0047] Continue to refer Figure 3 In this embodiment, an opening 80 is provided in the electron blocking layer 8. The opening 80 extends downward from the surface of the electron blocking layer 8 facing away from the substrate 1 to the upper surface of the drift layer 7. The opening 80 is wide at the top and narrow at the bottom. The channel layer 2 is formed on the side of the electron blocking layer 8 facing away from the substrate 1. The concave portion 20 of the channel layer 2 is located in the opening 80. The concave portion 20 is in contact with the inner wall of the opening 80. The angle θ3 between the side wall 801 of the opening 80 and the first virtual plane 6 is equal to the angle θ1 between the side wall 201 of the concave portion 20 and the first virtual plane 6.

[0048] The angle θ3 between the sidewall 801 of the opening 80 and the first virtual plane 6 can be set to 23.39°, 21.33°, 15.78°, 14.00°, 8.54° or 7.54°. In this way, based on the sidewall angle of the opening 80 in the electron blocking layer 8, when the channel layer 2 is prepared above the electron blocking layer 8, the sidewall angle of the concave portion 20 of the channel layer 2 can be more accurately controlled, thereby ensuring that the heterogeneous interface between the channel layer 2 and the barrier layer 3 is a semi-polar crystal plane.

[0049] Optional, you can continue to refer to Figure 3 In some embodiments, the electron blocking layer 8 may include a GaN layer 81 and a GaN:C layer 82 stacked in sequence along a direction perpendicular to the substrate 1 and pointing toward the channel layer 2. The opening 80 penetrates the GaN layer 81 and the GaN:C layer 82.

[0050] Among them, the GaN layer 81 can be a p-type doped GaN layer, and the GaN:C layer 82 is a deliberately carbon-doped GaN layer. The thicknesses of the GaN layer 81 and the GaN:C layer 82 are not limited and can be set by those skilled in the art according to actual situations. Using the stacked GaN layer 81 and GaN:C layer 82 as the electron blocking layer 8 can reduce device leakage and lower device power consumption.

[0051] Optionally, in the above Figure 1 and Figure 3 In the illustrated embodiment, the channel layer 2 is adjacent to the barrier layer 3 and they are in contact with each other. In embodiments not shown in the drawings of the present invention, the channel layer 2 and the barrier layer 3 are not necessarily adjacent, and a spacer layer may be included therebetween.

[0052] Among them, the spacer layer can be an Al y Ga 1-y N spacer layer, where 0 < y < 1, but it is not limited thereto. Among them, the contents of the Al component and the Ga component in the Al y Ga 1-y N spacer layer may be different from the contents of the Al component and the Ga component in the Al x Ga 1-x N barrier layer. The values of x and y can be set by those skilled in the art according to actual situations, and the embodiments of the present invention do not limit this. By setting an appropriate spacer layer, the two-dimensional electron gas concentration between the channel layer 2 and the barrier layer 3 can be increased, further improving the device performance. When a spacer layer is provided between the channel layer 2 and the barrier layer 3, the two-dimensional electron gas layer 4 is still formed on the side of the channel layer 2 close to the barrier layer 3.

[0053] Optionally, Figure 4 is a schematic structural diagram of another trench-type semiconductor device provided by the embodiments of the present invention, which can be referred to Figure 1 or Figure 4 . The trench-type semiconductor device further includes a gate 9, and the gate 9 is located on the side of the barrier layer 3 facing away from the channel layer 2.

[0054] Figure 4 shows an optional setting manner of the gate 9. Figure 4 In the illustrated embodiment, the gate 9 is in direct contact with the barrier layer 3 to form a Schottky gate structure. The trench-type semiconductor device can be a trench-type Schottky diode. Along the direction perpendicular to the plane of the substrate 1, the gate 9 covers the concave portion 20 and a part of the extending portion 21 of the channel layer 2, increasing the carrier movement rate of the forward conduction by means of the two-dimensional electron gas, and accelerating the switching speed of the Schottky diode by means of the confined two-dimensional electron gas channel.

[0055] It can be further referred to Figure 1 , Figure 1Another optional arrangement of the gate 9 is shown. Figure 1 In the illustrated embodiment, a p-type doped GaN layer 10 is further included between the gate 9 and the barrier layer 3 .

[0056] Specifically, the gate 9 and the barrier layer 3 may be separated by a p-type doped GaN layer 10 to form a PN junction gate structure. In the direction perpendicular to the plane where the substrate 1 is located, the p-type doped GaN layer 10 may cover the concave portion 20 and part of the extension portion 21 of the channel layer 2, the gate 9 may overlap the concave portion 20, and the area of ​​the gate 9 may be set to be smaller.

[0057] Optionally, in an embodiment not shown in the present invention, a gate oxide layer may be further included between the gate 9 and the barrier layer 3 to form a MIS gate structure, which will not be described in detail in the embodiment of the present invention.

[0058] You can continue to refer to Figure 1 , Figure 3 or Figure 4 The trench-type semiconductor device further includes a source 11 and a drain 12 ; the source 11 is located on a side of the substrate 1 away from the channel layer 2 , and the drain 12 is in contact with the two-dimensional electron gas layer 4 .

[0059] Specifically, Figure 1 , Figure 3 or Figure 4 As shown, the trench-type semiconductor device may be a vertical structure, with the drain 12 and the source 11 respectively located on the upper and lower sides of the substrate 1. The source 11 may be formed on the side of the substrate 1 away from the channel layer 2, and the source 11 may be located on the left and right sides of the channel layer 2 and the barrier layer 3, and connected to the edges of the channel layer 2 and the barrier layer 3, so that the drain 12 is in contact with the two-dimensional electron gas layer 4.

[0060] Of course, the configuration of the gate 9, source 11 and drain 12 in the above-mentioned trench-type semiconductor device are all examples. In actual application, technicians in this field can adjust the positions of the gate 9, source 11 and drain 12 according to actual needs.

[0061] The trench semiconductor device provided in the embodiment of the present utility model may also include any film layer structure known to those skilled in the art, and the embodiment of the present utility model does not elaborate on this and does not limit this.

[0062] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A trench semiconductor device, characterized in that: include: substrate; A channel layer is disposed on one side of the substrate, the channel layer comprises a concave portion, and the width of the concave portion gradually increases along the direction perpendicular to the substrate and pointing to the channel layer; wherein the sidewall of the concave portion is a semi-polar crystal plane of the channel material; A barrier layer is located on a side of the channel layer away from the substrate, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer.

2. The trench semiconductor device according to claim 1, wherein: The channel material is GaN; The side wall of the recessed portion is at least one of the crystal planes 1 (10-12), 2 (11-23), 3 (11-22), 4 (10-11), 5 (11-21), 6 (20-21) of GaN and the equivalent crystal planes of the above crystal planes.

3. The trench semiconductor device according to claim 2, wherein: There is a first angle θ1 between the sidewall of the concave portion and a first virtual plane, and the first virtual plane is perpendicular to the plane where the substrate is located; Among them, θ1=23.39°, or θ1=21.33°, or θ1=15.78°, or θ1=14.00°, or θ1=8.54°, or θ1=7.54°.

4. The trench type semiconductor device according to claim 1, wherein: The trench-type semiconductor device further comprises a drift layer, wherein the drift layer is disposed on a surface of one side of the substrate, and the channel layer is located on a side of the drift layer away from the substrate; The drift layer comprises a groove, the concave portion is located in the groove, the sidewall of the concave portion is parallel to the sidewall of the groove, a second angle θ2 is formed between the sidewall of the groove and a first virtual plane, and the first virtual plane is perpendicular to the plane where the substrate is located; Among them, θ2=23.39°, or θ2=21.33°, or θ2=15.78°, or θ2=14.00°, or θ2=8.54°, or θ2=7.54°.

5. The trench semiconductor device according to claim 1, wherein: The trench semiconductor device further comprises a drift layer and an electron blocking layer, wherein the drift layer is disposed on one side surface of the substrate, the electron blocking layer is located on one side surface of the drift layer away from the substrate, and the channel layer covers a portion of the electron blocking layer; The electron blocking layer comprises an opening, wherein a portion of the drift layer is exposed at the opening, the concave portion is located in the opening, a sidewall of the concave portion is parallel to a sidewall of the opening, a third angle θ3 is formed between the sidewall of the opening and a first virtual plane, and the first virtual plane is perpendicular to a plane where the substrate is located; Among them, θ3=23.39°, or θ3=21.33°, or θ3=15.78°, or θ3=14.00°, or θ3=8.54°, or θ3=7.54°.

6. The trench semiconductor device according to claim 5, characterized in that: The electron blocking layer includes a GaN layer and a GaN:C layer which are sequentially stacked in a direction perpendicular to the substrate and directed toward the channel layer.

7. The trench type semiconductor device according to claim 1, characterized in that: A spacer layer is further included between the channel layer and the barrier layer.

8. The trench type semiconductor device according to claim 1, wherein: The trench semiconductor device further includes a gate, which is located at a side of the barrier layer away from the channel layer.

9. The trench type semiconductor device according to claim 8, characterized in that: A p-type doped GaN layer is also included between the gate and the barrier layer.

10. The trench type semiconductor device according to claim 1, wherein: The trench-type semiconductor device further comprises a source and a drain; the source is located at a side of the substrate away from the channel layer, and the drain is in contact with the two-dimensional electron gas layer.

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