Metal oxide thin film transistor memory device
By designing a metal oxide thin film transistor memory device including buffer layer, insulating layer, gate, source and drain, the problems of high power consumption, limited life and cumbersome manufacturing processes of traditional memory devices are solved, and the structure is simple , cost savings and suitable for mass production.
Patent Information
- Application Number
- CN202420920829.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-29
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2034-04-29
AI Technical Summary
Traditional memory devices have problems such as high power consumption, limited life, and slow reading and writing speed, especially the high risk of mechanical failures, and the manufacturing process of metal oxide thin film transistor memory devices is cumbersome and has high cost.
Design a metal oxide thin film transistor memory device, including substrate, buffer layer, insulating layer, gate, source and drain, and prepare channel layers by sputtering, atomic layer deposition or solution method, using indium, gallium, zinc, etc. As a storage medium, the gate electrode is formed by photolithography and evaporation processes. The insulating layer is a silicon oxide film. The anodization treatment is carried out at normal temperature and pressure.
It simplifies structure and process, reduces production costs, is suitable for large-scale production, and is suitable for the manufacturing of memory devices for electronic devices, and has high practical value.
Smart Images
Figure CN222233643U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic devices, in particular to a metal oxide thin film transistor memory device. Background Art
[0002] Traditional storage devices have problems such as high power consumption, limited life, high density, and relatively slow read and write speeds. For HDDs, the movement of the mechanical arm and the rotation of the disk result in low data access speeds, which increases the risk of mechanical failure, especially for SSD flash memory chips. Flash memory storage cells have a limited number of erase and write times. After multiple erase and write operations, the storage cells may become unreliable or unable to write data.
[0003] In recent years, metal oxide thin film transistor memory devices have attracted widespread attention as a new type of storage technology. They have the advantages of non-volatility, high density, and low power consumption, and are widely studied for use in the fields of sensors, memory, and processors. However, there are also problems with the manufacturing process being relatively complicated and the cost being relatively high. Utility Model Content
[0004] The utility model aims to provide a metal oxide thin film transistor memory device to solve the problems raised in the above background technology.
[0005] In order to solve the above technical problems, the utility model provides the following technical solutions: a metal oxide thin film transistor memory device, comprising a substrate, on which a buffer layer, an insulating layer, a gate, a source and a drain are sequentially arranged, the buffer layer is arranged between the substrate and the insulating layer, and contacts the substrate and the insulating layer respectively, a source contact region is arranged between the source and the insulating layer, the source contact region contacts the insulating layer and the source, a drain contact region is arranged between the drain and the insulating layer, and the drain contact region contacts the insulating layer and the drain.
[0006] Preferably, a channel layer is formed between the source and the drain.
[0007] Preferably, the channel layer is obtained by a preparation process selected from the group consisting of sputtering, atomic layer deposition, and solution method.
[0008] Preferably, a storage medium is formed between the channel layer and the source and drain.
[0009] Preferably, the storage medium is at least two elements of indium, gallium, zinc and aluminum.
[0010] Preferably, the gate is formed into a desired shape and size by one of photolithography and evaporation processes.
[0011] Preferably, the insulating layer is a silicon oxide film.
[0012] Beneficial effects of the utility model: The metal oxide thin film transistor memory device provided by the scheme has a simpler structure, and the anodizing process only needs to be carried out at room temperature and pressure, which is simple to operate and highly controllable, suitable for large-scale production, and saves production costs. It has high practical value and can be widely used in the manufacture and application of memory devices in the field of electronic equipment. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 This is a schematic diagram of manufacturing a buffer layer on a substrate according to the utility model;
[0014] Figure 2 This is a schematic diagram of the utility model for making a grid;
[0015] Figure 3 This is a schematic diagram of the utility model for making an insulating layer;
[0016] Figure 4 It is a schematic diagram of the overall structure of the memory of the utility model.
[0017] The reference numerals in the figures are: substrate 1 , buffer layer 2 , insulating layer 3 , gate 4 , source contact region 501 , drain contact region 502 , source 601 , drain 602 , channel layer 7 , storage medium 8 . DETAILED DESCRIPTION
[0018] In the following description, a large number of specific details are given to provide a more thorough understanding of the utility model. However, it is obvious to those skilled in the art that the utility model can be implemented without one or more of these details. In other examples, in order to avoid confusion with the utility model, some technical features known in the art are not described.
[0019] Embodiment 1,
[0020] Reference Figures 1 to 4, metal oxide thin film transistor memory, substrate 1 is made of glass material, a buffer layer 2 is deposited on the upper surface, indium tin oxide (ITO) is deposited on the buffer layer 2 as a gate 4, the gate 4 can be formed into a desired shape and size by photolithography, a silicon dioxide (SiO2) insulating layer 3 is deposited above the gate 4 to isolate the gate 4 from the channel layer 7, the channel layer 7 is a metal oxide thin film indium gallium zinc oxide (IGZO) deposited on the insulating layer 3, the IGZO thin film can be obtained by atomic layer deposition (ALD) preparation process, located between the source 601 and the drain 60 2, the source 601 and the drain 602 are located on both sides of the gate 4, which are made of aluminum metal and are formed into the required shape and size through a photolithography process. The source 601 is connected to the insulating layer 3 through a source contact region 501, and the drain 602 is connected to the insulating layer 3 through a drain contact region 502. A non-volatile storage medium 8 is introduced between the channel layer and the source and drain. The storage medium 8 is an indium gallium zinc oxide (IGZO) metal oxide material. Finally, a protective polymer encapsulation layer is covered on the surface of the device to protect the transistor structure and prevent it from being affected by the external environment.
[0021] Embodiment 2,
[0022] Metal oxide thin film transistor memory, substrate 1 is made of glass material, a buffer layer 2 is deposited on the upper surface, indium tin oxide (ITO) is deposited on the buffer layer 2 as a gate 4, the gate 4 can be formed into a desired shape and size by evaporation, a silicon dioxide (SiO2) insulating layer 3 is deposited on the gate 4 to isolate the gate 4 from the channel layer 7, the channel layer 7 is a metal oxide thin film indium gallium zinc oxide (IGZO) deposited on the insulating layer 3, the IGZO thin film can be obtained by a solution preparation process, and is located between the source 601 and the drain 602, the source The source 601 and the drain 602 are located on both sides of the gate 4 and are made of aluminum metal. The required shape and size are formed by photolithography. The source 601 is connected to the insulating layer 3 through the source contact region 501, and the drain 602 is connected to the insulating layer 3 through the drain contact region 502. A non-volatile storage medium 8 is introduced between the channel layer and the source and drain. The storage medium 8 is an indium aluminum zinc oxide (IAZO) metal oxide material. Finally, a protective silicon dioxide encapsulation layer is covered on the surface of the device to protect the transistor structure and prevent it from being affected by the external environment.
[0023] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be interpreted as limiting the present invention itself. Various changes can be made to it in form and detail without departing from the spirit and scope of the present invention defined in the appended claims.
Claims
1. A metal oxide thin film transistor memory device, characterized in that: The invention comprises a substrate, on which a buffer layer, an insulating layer, a gate, a source electrode and a drain electrode are sequentially arranged, the buffer layer is arranged between the substrate and the insulating layer and contacts the substrate and the insulating layer respectively, a source contact region is arranged between the source electrode and the insulating layer, the source contact region contacts the insulating layer and the source electrode, a drain contact region is arranged between the drain electrode and the insulating layer, the drain contact region contacts the insulating layer and the drain electrode.
2. The metal oxide thin film transistor memory device according to claim 1, characterized in that: A channel layer is formed between the source electrode and the drain electrode.
3. The metal oxide thin film transistor memory device according to claim 2, characterized in that: The channel layer is obtained by a preparation process of atomic layer deposition or solution method.
4. The metal oxide thin film transistor memory device according to claim 2, characterized in that: A storage medium is formed between the channel layer and the source and drain.
5. The metal oxide thin film transistor memory device according to claim 4, characterized in that: The storage medium is at least two elements of indium, gallium, zinc and aluminum.
6. The metal oxide thin film transistor memory device according to claim 1, characterized in that: The gate is formed into a desired shape and size by one of photolithography and evaporation processes.
7. The metal oxide thin film transistor memory device according to claim 1, characterized in that: The insulating layer is a silicon oxide film.