Array substrate and display panel
By setting a composite reflective layer between the silicon nitride buffer layer and the silicon dioxide buffer layer, the laser utilization rate and external ultraviolet light reflectivity are improved, the problem of high energy consumption during excimer laser annealing is solved, and low-temperature polycrystalline silicon is realized Efficient production and stability improvement.
Patent Information
- Application Number
- CN202323368405.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-06
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2033-12-06
Smart Images
Figure CN222235416U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art
[0002] In recent years, AMOLED (Active-Matrix Organic Light Emitting Diode) has become the development trend of flat panel displays due to its advantages such as no need for backlight, thinness, high luminous efficiency, low power consumption, high color saturation and wide viewing angle.
[0003] AMOLED is usually composed of a low-temperature polysilicon (LTPS) driving backplane and an electroluminescent layer to form a self-luminous component. Low-temperature polysilicon has a high electron mobility. For AMOLED, the use of low-temperature polysilicon material has the advantages of high resolution, fast response speed, high brightness, high aperture ratio, and low energy consumption.
[0004] Currently, excimer laser annealing (ELA) is the most widely used method for making low-temperature polysilicon and has been mass-produced. However, the use of excimer laser annealing to make low-temperature polysilicon still has the problem of high production energy consumption. Utility Model Content
[0005] The main purpose of the utility model is to provide an array substrate and a display panel, aiming to solve the problem of high production energy consumption in the process of preparing the array substrate by excimer laser annealing.
[0006] In order to achieve the above object, the utility model provides an array substrate, which includes:
[0007] A substrate, and a silicon nitride buffer layer, a composite reflective layer, a silicon dioxide buffer layer, a semiconductor layer, a first insulating layer, a first gate electrode, a second insulating layer, a second gate electrode, a third insulating layer, an electrode data line, a fourth insulating layer, an organic planarization layer, an anode electrode, and a pixel definition layer sequentially deposited on the substrate;
[0008] The electrode data line passes through the third insulating layer and the second insulating layer, avoids the first gate electrode and the second gate electrode, enters the first insulating layer and contacts the semiconductor layer;
[0009] The anode electrode passes through the organic planar layer, enters the fourth insulating layer and contacts the electrode data line.
[0010] Optionally, the composite reflective layer includes a stack of alternately arranged titanium dioxide atomic layers and silicon dioxide atomic layers.
[0011] Optionally, the thickness of the composite reflective layer is 160-300 nm.
[0012] Optionally, in the composite reflective layer, the film layer in contact with the silicon dioxide buffer layer is the silicon dioxide atomic layer.
[0013] Optionally, the thickness of the semiconductor layer is
[0014] Optionally, the thickness of the silicon nitride buffer layer is
[0015] Optionally, the thickness of the silicon dioxide buffer layer is
[0016] Optionally, the thickness of the organic planar layer is 1.8-2.5 μm.
[0017] Optionally, the thickness of the third insulating layer is The thickness of the fourth insulating layer is
[0018] In addition, to achieve the above-mentioned purpose, the utility model further provides a display panel, and the display panel includes the array substrate as described above.
[0019] The array substrate provided by the utility model comprises: a substrate, and a silicon nitride buffer layer, a composite reflective layer, a silicon dioxide buffer layer, a semiconductor layer, a first insulating layer, a first gate electrode, a second insulating layer, a second gate electrode, a third insulating layer, an electrode data line, a fourth insulating layer, an organic flat layer, an anode electrode, and a pixel definition layer which are sequentially deposited on the substrate; the electrode data line passes through the third insulating layer and the second insulating layer, avoids the first gate electrode and the second gate electrode, enters the first insulating layer and contacts the semiconductor layer; the anode electrode passes through the organic flat layer, enters the fourth insulating layer and contacts the electrode data line. By setting a composite reflective layer between the silicon dioxide buffer layer and the silicon nitride buffer layer, during the excimer laser annealing process, when the laser penetrates the amorphous silicon and the silicon dioxide buffer layer in the semiconductor layer and irradiates the composite reflective layer, the composite reflective layer can reflect the laser back to the amorphous silicon, thereby improving the utilization rate of the laser. Even if the output energy of the emitted laser is reduced, the conversion of amorphous silicon into polycrystalline silicon can be guaranteed, thereby reducing the production energy consumption of low-temperature polycrystalline silicon. In addition, the composite reflective layer can also reflect out ultraviolet light entering from the outside through the substrate, thereby improving the stability of the polycrystalline silicon array substrate device. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 is a structural schematic diagram of an array substrate in the related art;
[0021] Figure 2 A schematic diagram of the structure of an array substrate provided by an embodiment of the utility model;
[0022] Figure 3 It is a schematic diagram of the structure of the composite reflective layer involved in the embodiment of the utility model.
[0023] Description of Reference Numerals
[0024] 101 Substrate 102 Silicon nitride buffer layer 103 Composite reflective layer 103a Titanium dioxide atomic layer 103b Silicon dioxide atomic layer 104 Silicon dioxide buffer layer 105 First insulation layer 106 Second insulation layer 107 The third insulating layer 108 Fourth insulation layer 109 Organic flat layer 110 Pixel Definition Layer 201 Semiconductor layer 202 First gate 203 The second gate 204 Electrode data line 205 Anode electrode
[0025] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0026] In order to facilitate the understanding of the present invention, a more comprehensive description will be given below with reference to the relevant drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0027] In the description of the present utility model, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features; "plurality" means two or more. The term "including" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may exist or be added.
[0028] In addition, terms indicating orientation or positional relationships, such as “center,” “lateral,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are described based on the orientation or relative positional relationships shown in the accompanying drawings and are merely simplified descriptions for the convenience of describing the present application. They do not indicate that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limitations on the present invention.
[0029] Figure 1 is a schematic diagram of the structure of an array substrate in the related art, such as Figure 1As shown, a silicon nitride buffer layer 102, a silicon dioxide buffer layer 104, a semiconductor layer 201, a first insulating layer 105, a first gate electrode 202, a second insulating layer 106, a second gate electrode 203, a third insulating layer 107, an electrode data line 204, a fourth insulating layer 108, an organic planarization layer 109, an anode electrode 205, and a pixel definition layer 110 are sequentially arranged on a substrate 101; the electrode data line 204 passes through the third insulating layer 107 and the second insulating layer 106, and avoids the first gate electrode 202 and the second gate electrode 203, enters the first insulating layer 105 and contacts the semiconductor layer 201; the anode electrode 205 passes through the organic planarization layer 109, enters the fourth insulating layer 108 and contacts the electrode data line 204. In the process of preparing the semiconductor layer 201, a silicon nitride buffer layer 102 and a silicon dioxide buffer layer 104 are first prepared on the substrate 101, amorphous silicon is deposited on the silicon dioxide buffer layer 104, and the amorphous silicon is melted and crystallized into polycrystalline silicon in the ELA process. In the ELA process, the laser will penetrate from the amorphous silicon to the silicon dioxide buffer layer 104, and may be emitted from the silicon nitride buffer layer 102 and the substrate 101, resulting in the loss of laser energy, so the energy consumption is relatively high.
[0030] The utility model embodiment provides an array substrate, such as Figure 2 As shown, the array substrate includes: a substrate 101, and a silicon nitride buffer layer 102, a composite reflective layer 103, a silicon dioxide buffer layer 104, a semiconductor layer 201, a first insulating layer 105, a first gate electrode 202, a second insulating layer 106, a second gate electrode 203, a third insulating layer 107, an electrode data line 204, a fourth insulating layer 108, an organic planar layer 109, an anode electrode 205, and a pixel definition layer 110 arranged in sequence on the substrate 101; the electrode data line 204 passes through the third insulating layer 107 and the second insulating layer 106, and avoids the first gate electrode 202 and the second gate electrode 203, enters the first insulating layer 105 and contacts the semiconductor layer 201; the anode electrode 205 passes through the organic planar layer 109, enters the fourth insulating layer 108 and contacts the electrode data line 204.
[0031] The substrate 101 can be made of glass and has light transmittance. The silicon nitride buffer layer 102 is disposed on the substrate 101. The silicon nitride material has good water vapor insulation, and the silicon nitride buffer layer 102 can effectively protect the device. The thickness of the silicon nitride buffer layer can be For example, The silicon dioxide buffer layer 102 can reduce the heat diffusion rate and make the polysilicon in the semiconductor layer 201 fully crystallized. The thickness of the silicon dioxide buffer layer can be For example,
[0032] Figure 3 is a schematic diagram of the structure of the composite reflective layer, such as Figure 3 As shown, the composite reflective layer 103 disposed on the silicon nitride buffer layer 102 may include a stack of titanium dioxide atomic layers 103a and silicon dioxide atomic layers 103b alternately disposed. The combination of a titanium dioxide atomic layer 103a and a silicon dioxide atomic layer 103b is regarded as a stack. Figure 3 FIG. 4 shows a case where the number of stacking layers is 3, and the actual number of stacking layers can be adjusted.
[0033] In some feasible embodiments, the number of titanium dioxide atomic layers 103a in the composite reflective layer 103 can be 800-1500, for example, 800, 1000, 1200, 1500, and the number of silicon dioxide atomic layers 103b can be 800-1500, for example, 800, 1000, 1200, 1500. The thickness of the composite reflective layer 103 can be 160-300nm, for example, 160nm, 200nm, 240nm, 260nm, 300nm. The titanium dioxide atomic layer 103a can reflect the laser back to the semiconductor layer 201 after the laser penetrates the silicon dioxide buffer layer 102, thereby improving the utilization rate of the laser, and the external ultraviolet light from the substrate 101 side can also be reflected by the composite reflective layer 103, thereby improving the stability of the polysilicon device. The alternating arrangement of silicon dioxide atomic layers 103b and titanium dioxide atomic layers 103a can reduce the stress of the glass substrate 101 and prevent excessive bending. Silicon dioxide and titanium dioxide are both oxides. When the titanium dioxide atomic layer 103a is deficient in oxygen, oxygen can be supplemented from the silicon dioxide atomic layer 103b.
[0034] In some feasible implementations, in the composite reflective layer 103, the film layer in contact with the silicon dioxide buffer layer 104 is a silicon dioxide atomic layer 103b. The silicon dioxide buffer layer 104 is disposed on the composite reflective layer 103. By alternately arranging the film layers, the topmost layer of the final composite reflective layer 103 can be controlled to be the silicon dioxide atomic layer 103b, which is similar in material to the silicon dioxide buffer layer, and is conducive to the bonding between the layers.
[0035] The composite reflective layer 103 can be prepared by ALD (Atomic Layer Deposition). ALD technology forms a thin film by alternately passing gaseous precursor pulses into the reaction chamber and causing chemical adsorption reaction on the surface of the deposition substrate. The film layer deposited by ALD has obvious advantages in terms of uniformity, density, step coverage and thickness control.
[0036] In the process of preparing the titanium dioxide atomic layer, the temperature of the atomic deposition chamber can be set to 150-250°C and the pressure can be set to 0.01-0.5 Torr, and tetrakis(dimethylamino)titanium or titanium chloride precursor is introduced into the atomic layer deposition chamber at a rate of 5ml / min-30ml / min for a time of 0.02s; after staying in the chamber for 2 seconds to 5 seconds, the reaction chamber is purged with inert gas Ar or He for 3 seconds to 30 seconds to remove the residual titanium precursor; an oxygen precursor, i.e. oxygen, is introduced into the atomic layer deposition reaction chamber for a time of 0.2s; after 2 seconds to 20 seconds, the reaction chamber is purged with inert gas Ar or He for 3 seconds to 30 seconds to remove the residual oxygen; the above steps are represented by cycle a, and each time cycle a is repeated once, one layer of titanium dioxide atomic layer can be controlled to be generated.
[0037] In the process of preparing the silicon dioxide atomic layer, the same temperature and pressure parameter settings as those for the above-mentioned titanium dioxide atomic layer preparation can be adopted, and ethyl orthosilicate or methyl orthosilicate precursor is introduced into the atomic layer deposition chamber at a rate of 5ml / min-30ml / min and an introduction time of 0.02s; after a preset stay in the chamber for 2 seconds to 5 seconds, the reaction chamber is purged with an inert gas Ar or He for 3 seconds to 30 seconds to remove residual silicon precursor; an oxygen precursor, i.e., oxygen, is introduced into the atomic layer deposition reaction chamber for an introduction time of 0.2s; after 2 seconds to 5 seconds, the reaction chamber is purged with an inert gas Ar or He for 3 seconds to 30 seconds to remove residual oxygen; the above steps are represented by cycle b, and each repetition of cycle b can control the generation of one layer of silicon dioxide atomic layer.
[0038] The above cycle a and cycle b are performed alternately, and the number of cycles can be set to be the same to generate an overlapping composite film layer of titanium dioxide and silicon dioxide. The preset number of cycles a and cycle b can be set to between 800 and 1500 times. If it is determined that the composite reflective layer needs to be 200 nanometers thick, the number of cycles can be set to about 1000 times.
[0039] The semiconductor layer 201 may include amorphous silicon or polycrystalline silicon. During the preparation of the array substrate, a silicon dioxide buffer layer 104 and amorphous silicon may be deposited on the composite reflective layer 103 in sequence. At this time, the component in the semiconductor layer 201 is amorphous silicon. The ELA process is used to melt and crystallize the amorphous silicon into polycrystalline silicon. The component in the semiconductor layer 201 gradually changes from amorphous silicon to polycrystalline silicon. The wavelength of the ultraviolet laser may be set to 308nm. Part of the laser will penetrate the amorphous silicon and silicon dioxide buffer layer 104, and be reflected by the composite reflective layer 103 to the semiconductor layer 201, thereby improving the utilization rate of the laser in the ELA. The polycrystalline silicon formed in the semiconductor layer 201 is then patterned to produce a designed shape. The thickness of the semiconductor layer 201 may be For example,
[0040] After the components in the semiconductor layer 201 are converted into polysilicon through the ELA process, a first insulating layer 105 can be deposited on the semiconductor layer 201, and a first gate layer material is deposited on the first insulating layer 105 and patterned to form a first gate 202. A second insulating layer 106 and a second gate layer material are then deposited on the first gate 202, and a second gate layer material is patterned to form a second gate 203.
[0041] The third insulating layer 107 is deposited on the second gate 203, and the third insulating layer 107 is patterned to open a hole. The formed hole passes through the third insulating layer 107 and the second insulating layer 106 and enters the first insulating layer 105. The opening position avoids the first gate 202 and the second gate 203. Then, the electrode data line material is deposited on the third insulating layer 107, and the electrode data line material enters the position of the opening. After patterning, the electrode data line 204 is formed. The thickness of the third insulating layer 107 can be For example, The third insulating layer 107 covers the second gate 203 , and the thickness of the third insulating layer 107 is thicker than that of the second gate 203 .
[0042] A fourth insulating layer 108 is deposited on the electrode data line 204, and a hole is patterned, and the position of the hole corresponds to the position of the electrode data line 204. The thickness of the fourth insulating layer 108 can be For example, The fourth insulating layer 108 covers the electrode data line 204, and the thickness of the fourth insulating layer 108 is thicker than the electrode data line 204. The film layer and pattern of the organic planar layer 109 can be made on the fourth insulating layer 108 by using a photo process. The thickness of the organic planar layer 109 can be 1.8-2.5 μm, for example, 1.8 μm, 2.0 μm, 2.2 μm, 2.3 μm, 2.5 μm. The thickness of the organic planar layer 109 is thicker than other film layers, and can better support the anode electrode 205.
[0043] Anode electrode material is deposited on the organic planar layer 109 and patterned to form an anode electrode 205, which passes through the organic planar layer 109 and enters the fourth insulating layer 108 to contact the electrode data line 204. A photo process can be used on the film layer of the anode electrode 205 to produce the film layer and pattern of the pixel definition layer 110.
[0044] The array substrate structure proposed by the utility model deposits a composite film layer of TiO2 and SiO2 between the silicon nitride buffer layer and the silicon dioxide buffer layer by atomic layer deposition to form a composite reflective layer. When the laser penetrates the amorphous silicon layer and the silicon dioxide buffer layer and irradiates the composite reflective layer, the composite reflective layer can reflect the laser back to the amorphous silicon layer, thereby improving the utilization rate of the laser. In addition, the external ultraviolet light from the glass substrate side will also be reflected by the composite reflective layer, thereby improving the stability of the polysilicon device.
[0045] The embodiment of the utility model also provides a display panel, which includes the array substrate as described in the above embodiment. On the basis of reducing the production energy consumption of the array substrate, due to the improvement of the laser utilization rate in the ELA process, even if the output energy of the ELA machine is reduced, it can ensure that amorphous silicon is converted into polycrystalline silicon and forms an active layer, so the production cost can also be reduced, and thus the production cost of the display panel is also reduced. In addition, the composite reflective layer in the array substrate can also reflect ultraviolet rays entering from the substrate side, and the high stability of the polycrystalline silicon device provides favorable conditions for the application of AMOLED type display panels. In addition to the array substrate, the display panel may also include necessary components such as an electroluminescent layer.
[0046] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. An array substrate, characterized in that: The array substrate comprises: A substrate, and a silicon nitride buffer layer, a composite reflective layer, a silicon dioxide buffer layer, a semiconductor layer, a first insulating layer, a first gate electrode, a second insulating layer, a second gate electrode, a third insulating layer, an electrode data line, a fourth insulating layer, an organic planarization layer, an anode electrode, and a pixel definition layer sequentially deposited on the substrate; The electrode data line passes through the third insulating layer and the second insulating layer, avoids the first gate electrode and the second gate electrode, enters the first insulating layer and contacts the semiconductor layer; The anode electrode passes through the organic planar layer, enters the fourth insulating layer and contacts the electrode data line.
2. The array substrate according to claim 1, characterized in that: The composite reflective layer includes a stack of alternately arranged titanium dioxide atomic layers and silicon dioxide atomic layers.
3. The array substrate according to claim 2, characterized in that: The thickness of the composite reflective layer is 160-300 nm.
4. The array substrate according to claim 2, characterized in that: In the composite reflective layer, the film layer in contact with the silicon dioxide buffer layer is the silicon dioxide atomic layer.
5. The array substrate according to claim 1, wherein: The thickness of the semiconductor layer is 6. The array substrate according to claim 1, characterized in that: The thickness of the silicon nitride buffer layer is 7. The array substrate according to claim 1, wherein: The thickness of the silicon dioxide buffer layer is 8. The array substrate according to claim 1, wherein: The thickness of the organic planar layer is 1.8-2.5 μm.
9. The array substrate according to claim 1, wherein: The thickness of the third insulating layer is The thickness of the fourth insulating layer is 10. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 9.