Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device. The semiconductor device comprises a first joint layer; a first layer of a silazane-based compound or a silazane-based compound between the first bonding layer and the first integrated circuit, where the first integrated circuit is associated with the first integrated circuit die; a second bonding layer bonded to the first bonding layer; and a second layer of a silazane-based compound or a silazane-based compound between the second bonding layer and a second integrated circuit, where the second integrated circuit is associated with a second integrated circuit die. The bonded structure may include enhanced adhesion performance and enhanced vibration damping performance. Reducing lateral stresses, enhancing adhesive properties, and damping properties can reduce the likelihood of bond interface cracking or peeling during thinning operations that thin two integrated circuit dies.

Description

Technical Field

[0001] An embodiment of the utility model relates to a semiconductor device, and in particular to a semiconductor device including a sealant layer structure. Background Art

[0002] A three-dimensional integrated circuit (3DIC) assembly may include two or more integrated circuit (IC) dies stacked vertically and bonded along bonding wires. A 3DIC assembly may be formed by stacking two or more semiconductor substrates including two or more IC dies using a wafer bonding operation such as a wafer-on-wafer (WoW) bonding operation. After the bonding operation, a 3DIC assembly including two or more IC dies may be cut out of the stack of two or more semiconductor substrates and encapsulated in a semiconductor die package. Utility Model Content

[0003] An embodiment of the utility model provides a semiconductor device comprising: a first bonding layer; a silazane-based compound or a first layer of a silazane-based compound, between the first bonding layer and a first integrated circuit, wherein the first integrated circuit is associated with a first integrated circuit die; a second bonding layer, bonded to the first bonding layer; and a silazane-based compound or a second layer of a silazane-based compound, between the second bonding layer and a second integrated circuit, wherein the second integrated circuit is associated with a second integrated circuit die.

[0004] Based on the above, relative to another bonding interface structure that does not include layers of sealant material, the layered structure can reduce the lateral stress of the entire bonding interface to reduce the possibility of warping of the two integrated circuit dies. In addition, relative to another bonding interface structure that does not include layers of sealant material, the layered structure can include enhanced adhesion and / or enhanced vibration damping properties. Reducing lateral stress, enhancing adhesion and / or vibration damping properties can reduce the possibility of cracking or peeling of the bonding interface during a thinning operation that thins one or more of the two integrated circuit dies.

[0005] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented.

[0007] Figure 2is a diagram of an example embodiment of forming a stacked die product as described herein.

[0008] Figure 3 is a diagram of an embodiment of an example semiconductor die package including a stacked die product described herein.

[0009] Figures 4A-4C is a diagram of an example embodiment of a supporting layered structure based on an example semiconductor substrate including an encapsulant layer as described herein.

[0010] Figures 5A-5C is a diagram of an example embodiment of a supporting layered structure based on an example semiconductor die including an encapsulant layer as described herein.

[0011] Figure 6 is a diagram of an example implementation of an example stress relief structure described herein.

[0012] Figures 7A-7F is a diagram of an example embodiment of forming a layered structure including a sealant layer as described herein.

[0013] Figure 8 This article describes Figure 1 A diagram of example components of one or more devices.

[0014] Fig. 9 and Fig.10 is a flow chart of an example process associated with forming a support encapsulant layer for stacked die applications.

[0015] Description of Reference Numerals

[0016] 100: example environment; 102: deposition tool; 104: exposure tool; 106: etching tool; 108: bonding tool; 110: dispensing tool; 112: planarization tool; 114: connection tool; 116: automatic test equipment / ATE tool; 118: singulation tool; 120: transfer tool; 200, 300: implementation scheme; 202a, 202b, 208: semiconductor substrate; 204a, 204b, 304 : integrated circuit die; 206: bonding operation; 210: thinning operation; 212: bumping operation; 214: operation; 216: stacked die product; 302: semiconductor die package; 306: interposer; 308: substrate; 312: connection structure 316: bonding interface structure; 318: bonding interface; 320a, 320b: sealant layer; 322a, 322b: stress relief structure; 324a, 324b: dielectric layer; 3 26a, 326b: bonding layer; 328a, 328b: interconnect structure; 330a, 330b: substrate layer; 332a, 332b: integrated circuit; 400, 500, 600, 700: example implementation scheme; 402, 404, 406, 412, 414, 416, 420, 422, 424, 502, 504, 506, 512, 514, 516, 518, 520, 522, 52 4: example; 408, 508: overall width; 410, 510: bevel area; 702: stress relief cavity; 800: device; 810: bus; 820: processor; 830: memory; 840: input component; 850: output component; 860: communication component; 900, 1000: process; 910, 920, 930, 1010, 1020, 1030, 1040, 1050: block; D1: thickness. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clearly describing the present disclosure, rather than for defining the relationship between various embodiments and / or configurations.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein may be interpreted in a similar manner.

[0019] In some cases, a stacked die product (e.g., a wafer-on-wafer (WoW) product) may include a single material (e.g., a silicon oxynitride (SiON) material) that is shared along a bonding interface between co-facing surfaces of two integrated circuit dies bonded together. In some cases, lateral stresses across such a bonding interface may cause the stacked die product to warp. In addition, such a bonding interface may have stiffness characteristics that may not adequately suppress vibrations and / or reduce stresses along the bonding interface during operations to thin the stacked die product. In such cases, during the thinning operation, the bonding interface may crack or delaminate, resulting in separation of the two integrated circuit dies and rendering the stacked die product unusable. In addition, to mitigate such warping, cracking, and / or delamination, one or more additional processing operations may be performed, such as trimming operations along the perimeter of two or more semiconductor substrates bonded as part of forming the stacked die product.

[0020] Some embodiments described herein provide technology and equipment to form a stacked die product including two or more integrated circuit dies. The bonding interface between the two integrated circuit dies included in the stacked die product includes a layered structure. As part of the layered structure, each layer of the sealant material is directly on the coplanar surface of the two integrated circuit dies. The layered structure further includes one or more bonding layers between each sealant material layer located on the coplanar surface of the two integrated circuit dies. With respect to another bonding interface structure that does not include each layer of the sealant material, the layered structure can reduce the lateral stress of the entire bonding interface to reduce the possibility of warping of the two integrated circuit dies. In addition, with respect to another bonding interface structure that does not include each layer of the sealant material, the layered structure may include enhanced bonding performance and / or enhanced vibration reduction performance. Reducing lateral stress, enhancing bonding performance and / or vibration reduction performance can reduce the possibility of cracking or peeling of the bonding interface during the thinning operation that thins one or more of the two integrated circuit dies.

[0021] In this manner, the yield of stacked die products is increased relative to the yield of stacked die products formed using a bonding interface that does not include a layered structure. Additionally or alternatively, in some embodiments, trimming operations along the perimeter of the connected semiconductor substrate as part of forming the stacked die product can be eliminated. By increasing the yield of the stacked die product and eliminating trimming operations, resource consumption (e.g., semiconductor manufacturing process tools, raw materials, manpower, and / or computing resources) used to manufacture a large number of stacked die products can be reduced.

[0022] Figure 1 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, environment 100 includes a combination of semiconductor processing tools, including a deposition tool 102, an exposure tool 104, an etching tool 106, a bonding tool 108, a dispensing tool 110, a planarization tool 112, a connection tool 114, an automated test equipment (ATE) tool 116, a singulation tool 118, and a transfer tool 120. The semiconductor processing tools (102-118) of example environment 100 may be included in one or more facilities, such as semiconductor cleaning or semiconductor clean rooms, semiconductor foundries, semiconductor processing facilities, outsourced assembly and test (OSAT) facilities, and / or manufacturing facilities.

[0023] Deposition tool 102 is a semiconductor processing tool capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or other types of CVD tools. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some embodiments, example environment 100 includes multiple types of deposition tools 102.

[0024] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet light (UV) light source (e.g., deep UV light, extreme UV (EUV) light, and / or the like), an X-ray source, an electron beam source, and / or other types of radiation sources. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for various portions of etching of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0025] The etching tool 106 is a semiconductor processing tool capable of etching various types of material substrates, wafers or semiconductor devices. For example, the etching tool 106 may include a wet etching tool, a dry etching tool and / or other types of etching tools. The wet etching tool may include a chemical etching tool or other types of wet etching tools including a chamber filled with etching liquid. The substrate may be placed in the chamber for a specific period of time to remove one or more portions of a specific amount of the substrate. The dry etching tool may include a plasma etching tool, a laser etching tool, a reactive ion etching tool or a vapor phase etching tool, etc. The dry etching tool may use sputtering technology, plasma-assisted etching technology (e.g., plasma sputtering technology or plasma sputtering technology or other types of technology involving the use of ionized gas to etch one or more portions isotropically or directionally) or other types of dry etching technology to remove one or more portions of the substrate.

[0026] The bonding tool 108 is a semiconductor processing tool capable of bonding two or more wafers (or two or more semiconductor substrates or two or more semiconductor devices) together. For example, the bonding tool 108 may include a eutectic bonding tool capable of forming a eutectic bond between the two or more wafers. In these examples, the bonding tool 108 may heat the two or more wafers to form a eutectic system between the materials of the two or more wafers.

[0027] The dispensing tool 110 may dispense one or more materials during the fabrication of semiconductor devices. For example, as part of a multi-semiconductor substrate stacking process, the dispensing tool 110 may include a pressurized nozzle that dispenses a polymer material between bevel edges of a semiconductor substrate (eg, a wafer).

[0028] The planarization tool 112 is a semiconductor processing tool capable of polishing or planarizing individual layers of a wafer or semiconductor device. For example, the planarization tool 112 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools that can polish or planarize layers or surfaces of deposited or plated materials. The planarization tool may use a combination of chemical and mechanical forces (e.g., chemical etching and freeabrasive polishing) to polish or planarize the surface of the semiconductor device. The planarization tool 112 may use abrasives and corrosive chemical slurries as well as a polishing pad and a retaining ring (e.g., typically larger in diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head may rotate with different rotation axes to remove material and level any irregular topography of the semiconductor device, thereby making the semiconductor device flat or planar.

[0029] The connection tool 114 is a semiconductor processing tool that can form a connection structure (e.g., an electrically conductive structure). The connection structure formed by the connection tool 114 may include a metal wire, a stud, a column, a bump, or a solder ball. The connection structure formed by the connection tool 114 may include materials such as gold (Au) material, copper (Cu) material, silver (Ag) material, nickel (Ni) material, tin (Sn) material, or palladium (Pd) material. The connection tool 114 may include a bump tool, a wire bonding tool, or a plating tool.

[0030] ATE tool 116 is a semiconductor processing tool capable of testing the quality and reliability of one or more integrated circuit dies and / or semiconductor packages (e.g., one or more integrated circuit dies after encapsulation). ATE tool 116 may perform wafer test operations, known good die (KGD) test operations, and / or semiconductor die package test operations, etc. ATE tool 116 may include parameter test tools, speed test tools, and / or burn-in tools, etc. Additionally or alternatively, ATE tool 116 may include probe tools and / or probe card tools, etc.

[0031] The singulation tool 118 is a semiconductor processing tool that can singulate (eg, separate, remove) a wafer into one or more integrated circuit dies. For example, the singulation tool 118 may include a cutting tool, a sawing tool, and / or a laser tool that cuts one or more integrated circuit dies from a wafer.

[0032] The transport tool 120 is a semiconductor processing tool capable of transporting work-in-process (WIP) between semiconductor processing tools (102-118). The transport tool 120 can be configured to accommodate one or more transport carriers, such as a wafer transport carrier (such as a wafer cassette or a front opening unified pod (FOUP), etc.), a tube core carrier transport carrier (such as a film frame, etc.) and / or a package transport carrier (such as a joint electron device engineering council (JEDEC) tray or a carrier tape reel, etc.). The transport tool 120 can also be configured to transport and / or combine WIPs between transport carriers. The transport tool 120 can include a pick-and-place tool, a conveyor belt tool, a robot arm tool, an overhead hoist transport (OHT) tool, an automated materially handling system (AMHS) tool, and / or other types of tools. In some embodiments, the example environment 100 includes multiple types of such tools as part of the transport tool 120.

[0033] As combined Figure 2-10 As described in greater detail elsewhere herein, one or more of the semiconductor processing tools (102-118) and / or the transfer tool 120 may perform a series of manufacturing operations associated with a support encapsulant structure for stacked die applications. For example, the series of operations includes forming a siloxane-based compound layer on a first semiconductor substrate. The series of operations includes forming a first bonding layer over the siloxane-based compound layer. The series of operations includes bonding the first bonding layer to a second bonding layer associated with a second semiconductor substrate.

[0034] Additionally or alternatively, the sequence of manufacturing operations includes forming a first layer of a siloxane-based compound over a portion of a first integrated circuit die. The method includes forming a first dielectric layer over the first layer of the siloxane-based compound. The sequence of manufacturing operations includes forming a second layer of a siloxane-based compound over a portion of a second integrated circuit die. The sequence of manufacturing operations includes forming a second dielectric layer over the second layer of the siloxane-based compound. The sequence of manufacturing operations includes bonding the first dielectric layer and the second dielectric layer.

[0035] Figure 1 The number and arrangement of semiconductor processing tools shown are provided as one or more examples. In practice, there may be additional semiconductor processing tools, different semiconductor processing tools, or Figure 1 Different semiconductor processing tools are shown. In addition, Figure 1 Two or more of the semiconductor processing tools shown may be implemented in a single tool cluster, or Figure 1 The illustrated set of tools may be implemented as a plurality of distributed semiconductor processing tools. Additionally or alternatively, one or more semiconductor processing tools of environment 100 may perform one or more functions described as being performed by another set of tools of environment 100.

[0036] Figure 2 2 is a diagram of an example embodiment 200 for forming a stacked die product as described herein. Embodiment 200 may correspond to a "wafer-on-wafer" (WoW) technology, etc., for forming a three-dimensional integrated circuit die (3DIC) product. Example embodiment 200 may use Figure 1 One or more semiconductor processing tools (102-118) and / or a transfer tool 120 are used to form a stacked die product.

[0037] As shown, semiconductor substrate 202a may include integrated circuit die 204a and semiconductor substrate 202b may include integrated circuit die 204b. Integrated circuit dies 204a and 204b may be formed by deposition tool 102 using a series of deposition operations, by exposure tool 104 using a series of patterning operations, and by etching tool 106 using a series of etching operations, etc.

[0038] The bonding operation 206 (e.g., a bonding operation of the bonding tool 108, etc.) may align the integrated circuit dies 204a and 204b and bond the semiconductor substrates 202a and 202b to form a stack of semiconductor substrates 208. As a result of the bonding operation 206, the integrated circuits of the integrated circuit dies 204a and 204b may be electrically connected for signal transmission (e.g., input / output signal transmission, clock or timing signal transmission, and / or power signal transmission, etc.). The bonding operation 206 may include a eutectic bonding operation, a hybrid bonding operation, and / or other types of bonding operations.

[0039] To save space in the final semiconductor die package, a thinning operation 210 (e.g., a thinning operation of a planarization tool 112) may be performed on the top substrate of the stack of semiconductor substrates 208 (e.g., semiconductor substrate 202a including integrated circuit die 204a). In some embodiments, such as in combination with Figure 3-10As described in greater detail elsewhere herein, a supporting encapsulant structure may be formed on semiconductor substrate 202a and semiconductor substrate 202b prior to thinning operation 210. The supporting encapsulant structure may improve the robustness of the stack of semiconductor substrates 208 during thinning operation 210 and / or subsequent operations performed on the stack of semiconductor substrates 208. For example, by improving the robustness of the stack of semiconductor substrates, the likelihood of defects and / or yield loss within the stack of semiconductor substrates 208 due to trim loss inherent to trim operations, trim wall exposure, and / or trim delamination may be reduced. Additionally or alternatively, in some implementations, such trim operations are eliminated.

[0040] Bumping operation 212 (e.g., bumping operation performed by connection tool 114) can form connection structures (e.g., solder balls, etc.) on pads of the integrated circuit die of the top semiconductor substrate (e.g., integrated circuit die 204a of semiconductor substrate 202a). This connection structure can be used for testing operations and / or packaging operations to encapsulate stacked die products from the stack of semiconductor substrate 208.

[0041] The downstream series of operations 214 may include testing operations and cutting operations to test the stacked die product 216 (e.g., the integrated circuit die 204a is bonded to the integrated circuit die 204b) and extract the stacked die product 216 from the stack of semiconductor substrates. The testing operations (e.g., testing operations performed by the ATE tool 116, etc.) may ensure the quality of the bonding operation 206 and / or the quality of the integrated circuit dies (e.g., the integrated circuit die 204a and / or the integrated circuit die 204b, etc.) included in the stack of semiconductor substrates 208. The testing operations may include functional testing, parametric testing, and / or reliability testing, etc. The cutting operation to extract the stacked die product 216 from the stack of semiconductor substrates 208 may be performed by the singulation tool 118, etc.

[0042] As mentioned above, Figure 2 Other examples may be found in relation to Figure 2 The content described is different.

[0043] Figure 3is a diagram of an embodiment 300 of an example semiconductor die package 302 including a stacked die product as described herein. Semiconductor die package 302 includes stacked die product 216 (e.g., integrated circuit die 204a bonded to integrated circuit die 204b) and integrated circuit die 304. For example, integrated circuit die 204a may correspond to a first system on chip (SoC) integrated circuit die, and integrated circuit die 204b may correspond to a second SoC integrated circuit die. Additionally or alternatively, integrated circuit die 304 may correspond to a high bandwidth memory (HBM) die, such as a dynamic random access memory (DRAM) IC die.

[0044] Semiconductor die package 302 may include an interposer 306 having one or more layers of electrically conductive traces. The electrically conductive traces of interposer 306 may include one or more materials, such as gold (Au) material, copper (Cu) material, silver (Ag) material, nickel (Ni) material, tin (Sn) material, or palladium (Pd) material, etc. Interposer 306 may also include one or more layers of dielectric material (such as ceramic material or silicon material, etc.). In some embodiments, interposer 306 corresponds to a PCB including glass reinforced epoxy laminate material and / or prepreg material layers (such as composite fiber / resin / epoxy material), etc. Additionally or alternatively, one or more layers of interposer 306 may include a build-up film material.

[0045] The semiconductor die package 302 may also include a substrate 308 having one or more layers of electrically conductive traces. The electrically conductive traces of the substrate 308 may include one or more materials, such as a gold (Au) material, a copper (Cu) material, a silver (Ag) material, a nickel (Ni) material, a tin (Sn) material, or a palladium (Pd) material, etc. The substrate 308 may also include one or more layers of a dielectric material, such as a ceramic material or a silicon material, etc. In some implementations, the substrate corresponds to a PCB including a glass-reinforced epoxy laminate material and / or a prepreg material layer, such as a composite fiber / resin / epoxy material, etc. Additionally or alternatively, one or more layers of the substrate 308 may include a build-up film material.

[0046] The semiconductor die package 302 may further include a connection structure 312 and an underfill 314. Examples of the connection structure 312 include a nail head, a pillar, a bump, and / or a solder ball. The connection structure 312 may include one or more materials, such as a gold (Au) material, a copper (Cu) material, a silver (Ag) material, a nickel (Ni) material, a tin (Sn) material, a lead (Pb) material, or a palladium (Pd) material. In some embodiments, one or more materials may be lead-free (e.g., Pb-free).

[0047] A portion of the connection structures 312 may connect the stacked die product 216 and / or the integrated circuit die 304 to the interposer (e.g., the stacked die product 216 and / or the integrated circuit die 304 may be attached to the interposer 306 using one or more of the connection structures 312). Additionally or alternatively, another portion of the connection structures 312 may connect the interposer to the substrate 308. Additionally or alternatively, another portion of the connection structures 312 may be included to connect the substrate to a system level PCB. In some embodiments, the connection structures 312 provide one or more electrical connections for transmitting and / or exchanging signals within the semiconductor die package 302. Additionally or alternatively, in some embodiments, the connection structures 312 provide one or more mechanical connections for connection purposes and / or spacing purposes). Additionally or alternatively, in some embodiments, one or more connection structures 312 provide both electrical and mechanical connections.

[0048] As shown in the detailed enlarged view of the embodiment 300, the stacked die product 216 includes a bonding interface structure 316. The bonding interface structure 316 bonds the integrated circuit die 204a and the integrated circuit die 204b along a bonding interface 318.

[0049] In some embodiments, as shown, the bonding interface structure 316 includes a sealant layer 320a and a sealant layer 320b. The sealant layer 320a can be included as part of (e.g., on, above, or associated with) the integrated circuit die 204a, and the sealant layer 320b can be included as part of (e.g., on, below, or associated with) the integrated circuit die 204b.

[0050] The sealant layers 320a and 320b may include siloxane-based or silazane-based compounds. Examples of compounds that may be included in the sealant layers 320a and 320b include dimethyldiethoxysilane (DMDEOS) compounds, tetraethylorthosilicate (TEOS) compounds, polydimethylsiloxane (PDMS) and / or polysilazanes (PHPS) compounds. In some embodiments, the physical properties (e.g., elasticity, hardness) of the compounds may provide a degree of compliance within the bonding interface structure 316, thereby reducing the likelihood of warping of the integrated circuit die 204a and / or 204b.

[0051] Additionally or alternatively, the sealant layer 320a and / or the sealant layer 320b may include composite filler particles. Examples of composite filler particles include silicon carbide (SiC) composite filler particles, aluminum dioxide (Al2O3) composite filler particles, zirconium tungsten phosphate (Zr2WP2O3) composite filler particles, and silicon carbide (SiC) composite filler particles. 12 The encapsulant layers 320a and / or 320b may be provided with ZWP (ZrO2) composite filler particles, SiO2 composite filler particles, and / or ceramic composite particles. Such composite particles may strengthen the encapsulant layers 320a and / or 320b to reduce the possibility of tearing and / or peeling of the encapsulant layers 320a and / or 320b during the thinning operation of the integrated circuit die 204a and / or the integrated circuit die 204b.

[0052] In some embodiments, such as Figure 3 As further shown in the enlarged view of , the integrated circuit die 204a includes a stress-relief structure 322a filled with a portion of the encapsulant layer 320a. Additionally or alternatively, in some embodiments, the integrated circuit die 204b includes a stress-relief structure 322b filled with a portion of the encapsulant layer 320b. The stress relief structures 322a and / or 322b can relieve lateral stress near or within the bonding interface structure 316 to reduce the likelihood of warping of the integrated circuit die 204a and / or 204b.

[0053] In some embodiments, as further shown, the bonding interface structure 316 includes a dielectric layer 324a and a dielectric layer 324b. The dielectric layer 324a can be included as part of (e.g., on, above, or associated with) the integrated circuit die 204a, and the dielectric layer 324b can be included as part of (e.g., on, below, or associated with) the integrated circuit die 204b. In addition, in some embodiments, the dielectric layers 324a and / or 324b are referred to as passivation layers.

[0054] The dielectric layers 324a and 324b may include a dielectric material. Examples of dielectric materials that may be included in the dielectric layers 324a and 324b include silicon dioxide (SiO2) materials, silicon oxycarbide (SiOC) materials, aluminum dioxide (Al2O3) materials, undoped silicon glass materials, and / or phosphosilicate glass materials. In some implementations, the dielectric layers 324a and 324b protect the integrated circuit die 204a and / or 204b from damage during operations to connect the integrated circuit die 204a and / or 204b.

[0055] In some embodiments, as further shown, the bonding interface structure 316 includes a bonding layer 326a and a bonding layer 326b. The bonding layer 326a can be included as part of (e.g., on, above, or associated with) the integrated circuit die 204a, and the bonding layer 326b can be included as part of (e.g., on, below, or associated with) the integrated circuit die 204b.

[0056] The bonding layers 326a and 326b may include silicon oxynitride (SiON) materials. Additionally or alternatively, the bonding layers 326a and / or 326b may include silicon dioxide (SiO2) materials, silicon oxycarbide (SiOC) materials, aluminum dioxide (Al2O3) materials, undoped silicon glass materials, and / or phosphosilicate glass materials, etc. In some embodiments, the bonding layers 326a and 326b partially couple (e.g., facilitate bonding) the integrated circuit dies 204a and 204b along the bonding interface 318.

[0057] In some embodiments, as further shown, the bonding interface structure 316 includes a set of interconnect structures 328a and a set of interconnect structures 328b. The set of interconnect structures 328a can be included as part of (e.g., on, above, or associated with) the integrated circuit die 204a, and the set of interconnect structures 328b can be included as part of (e.g., on, below, or associated with) the integrated circuit die 204b. In some embodiments, the set of interconnect structures 328a is interspersed in the bonding layer 326a and the sealant layer 320a. In some embodiments, the set of interconnect structures is interspersed in the bonding layer 326b and the sealant layer 320b.

[0058] The set of interconnect structures 328a and / or 328b may include copper (Cu) material. Additionally or alternatively, the set of interconnect structures 328a and / or 328b may include gold (Au) material, silver (Ag) material, nickel (Ni) material, or tin (Sn) material, etc. In some embodiments, the set of interconnect structures 328a and / or 328b partially couples (e.g., facilitates bonding) the integrated circuit dies 204a and 204b along the bonding interface 318.

[0059] In some embodiments, such as Figure 3As shown, the integrated circuit device 204a includes a substrate layer 330a (a layer of silicon (Si) material, etc.). One or more portions of the bonding interface structure 316 (e.g., the encapsulant layer 320a, the dielectric layer 324a, the bonding layer 326a, and / or the set of interconnect structures 328a) can be interposed between the substrate layer 330a and the bonding interface 318. In some implementations, an integrated circuit 332a can be associated with the integrated circuit device 204a (e.g., on or within the integrated circuit device 204a), wherein the substrate layer 330a is interposed between the integrated circuit 332a and the bonding interface structure 316.

[0060] In some embodiments, such as Figure 3 As shown, the integrated circuit die 204b includes a substrate layer 330b (a layer of silicon (Si) material, etc.). One or more portions of the bonding interface structure 316 (e.g., the encapsulant layer 320b, the dielectric layer 324b, the bonding layer 326b, and / or the set of interconnect structures 328b) can be interposed between the substrate layer 330b and the bonding interface 318. In some embodiments, an integrated circuit 332b can be associated with the integrated circuit die 204b (e.g., on or within the integrated circuit die 204b), wherein the substrate layer 330b is interposed between the integrated circuit 332b and the bonding interface structure 316.

[0061] like Figure 3 As shown, the device (e.g., stacked die product 216) includes a first bonding layer (e.g., bonding layer 326a). The device further includes a first layer of a siloxane-based compound or a silazane-based compound (e.g., sealant layer 320a) between the first bonding layer and a first integrated circuit (e.g., integrated circuit 332a), wherein the first integrated circuit is associated with a first integrated circuit die (e.g., integrated circuit die 204a). The device includes a second bonding layer (e.g., bonding layer 326b) bonded to the first bonding layer. The device includes a second layer of a siloxane-based compound or a silazane-based compound (e.g., sealant layer 320b) between the second bonding layer and a second integrated circuit (e.g., integrated circuit 332b), wherein the second integrated circuit is associated with a second semiconductor die (e.g., integrated circuit die 204b).

[0062] Using the bonding interface structure 316, the yield of the stacked die product 216 is increased relative to the yield of the stacked die product formed using the bonding interface structure that does not include the sealant layer 320a and / or 320b. By increasing the yield of the stacked die product 216, the resource consumption (e.g., semiconductor manufacturing processing tools, raw materials, manpower and / or computing resources) of manufacturing a large number of stacked die products 216 can be reduced.

[0063] Figure 3The number and arrangement of structures and layers shown in the figure are provided as one or more examples. In practice, there may be additional structures and layers, different structures and layers, or different Figure 3 Different structures and layers are shown.

[0064] Figures 4A-4C is a diagram of an example embodiment 400 of an example semiconductor substrate-based layered structure including an encapsulant layer as described herein. The semiconductor substrate-based layered structure may include encapsulant layers 320a and 320b and semiconductor substrates 202a and 202b bonded along a bonding interface 318.

[0065] Figure 4A An example of a semiconductor substrate-based layered structure including encapsulant layers 320a and 320b, dielectric layers 324a and 324b, and bonding layers 326a and 326b is shown. Figure 4A Examples 402 , 404 , and 406 are included regarding an overall width 408 of the semiconductor substrates 202 a and 202 b and regarding a beveled edge region 410 (eg, a beveled peripheral region) between the semiconductor substrates 202 a and 202 b .

[0066] As shown in example 402, the bonding interface 318 spans the entire width 408 of the semiconductor substrates 202a and 202b. In addition, as shown in example 402, the sealant layers 320a and 320b span the entire width 408 of the semiconductor substrates 202a and 202b. In some embodiments, the semiconductor substrate-based layered structure of example 402 is referred to as a layered structure "under the bonding interface". In this embodiment, one or more layers of the bonding interface structure can be located (e.g., interposed) between the sealant layers 320a and 320b spanning the entire width 408.

[0067] As shown in example 404, the bonding interface 318 spans the entire width 408 of the semiconductor substrates 202a and 202b. In addition, as shown in example 404, the sealant layers 320a and 320b are included in the bevel region 410 of the semiconductor substrates 202a and 202b (e.g., not spanning the entire width 408). In some embodiments, the semiconductor substrate-based layered structure of example 404 is referred to as a "bevel supporting under bond interface" layered structure. In this embodiment, one or more layers of the bonding interface structure may be located between the sealant layers 320a and 320b in the bevel region 410.

[0068] As shown in example 406, the bonding interface 318 spans a portion of the overall width 408 of the semiconductor substrates 202a and 202b (e.g., the bonding interface 318 is excluded from the bevel region 410). In addition, as shown in example 406, the sealant layers 320a and 320b are bonded within the bevel region 410 of the semiconductor substrates 202a and 202b (e.g., there is no intermediate layer between the sealant layers 320a and 320b). In some embodiments, the semiconductor substrate-based layered structure of example 406 is referred to as a "bevel supporting only" layered structure.

[0069] In example 406 and some embodiments, dielectric layers 324a and 324b are formed on and / or over semiconductor substrates 202a and 202b using a deposition operation. Deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, Figure 1 The dielectric layers 324a and 324b are deposited in other types of deposition operations as described and / or other suitable deposition operations. In some implementations, after the deposition tool 102 deposits the dielectric layers 324a and 324b, the planarization tool 112 planarizes the dielectric layers 324a and 324b.

[0070] In example 406, bonding layers 326a and 326b may be formed over and / or on dielectric layers 324a and 324b. To form bonding layers 326a and 326b, deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, Figure 1 The bonding layers 326a and 326b may be deposited in other types of deposition operations described in and / or other suitable deposition operations. In some embodiments, after the deposition tool 102 deposits the bonding layers 326a and 326b, the planarization tool 112 planarizes the bonding layers 326a and 326b.

[0071] In example 406, after formation, bonding layers 326a and 326b may be bonded. To bond bonding layers 326a and 326b, bonding tool 108 may perform a eutectic bonding operation, Figure 1 Other types of bonding operations described in and / or another bonding operation to bond the bonding layers 326a and 326b along the bonding interface 318.

[0072] After bonding the bonding layers 326a and 326b, a gap may exist in the bevel region 410. In this case, the deposition tool 102 may deposit the sealant layers 320a and 320b in the bevel region 410 to fill the gap. The deposition tool 102 may be used in a dispensing operation, a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, Figure 1The sealant layers 320a and / or 320b may be deposited in other types of deposition operations described in and / or other suitable deposition operations.

[0073] Figure 4B An example of a semiconductor substrate layer structure including sealant layers 320a and 320b, dielectric layers 324a and 324b, and the set of interconnect structures 328a and 328b is shown. Figure 4B In the embodiment, the bonding interface 318 is bonded to the dielectric layers 324a and 324b. Figure 4B As shown, the bonding interface 318 is bonded to the interconnect structures 328a and 328b.

[0074] As shown in example 412, the bonding interface 318 spans the entire width 408 of the semiconductor substrates 202a and 202b. In addition, as shown in example 412, the sealant layers 320a and 320b span the entire width 408 of the semiconductor substrates 202a and 202b. In some embodiments, the semiconductor substrate-based layered structure of example 412 is referred to as a layered structure "below the bonding interface." In this embodiment, one or more layers of the bonding interface structure can be located between the sealant layers 320a and 320b across the entire width 408.

[0075] As shown in example 414, the bonding interface 318 spans the entire width 408 of the semiconductor substrates 202a and 202b. In addition, as shown in example 414, the sealant layers 320a and 320b are contained within the bevel region 410 of the semiconductor substrates 202a and 202b (e.g., not spanning the entire width 408). In some embodiments, the semiconductor substrate-based layered structure of example 414 is referred to as a "bevel support below the bonding interface" layered structure. In this embodiment, one or more layers of the bonding interface structure may be located between the sealant layers 320a and 320b within the bevel region 410.

[0076] As shown in example 416, the bonding interface 318 spans a portion of the overall width 408 of the semiconductor substrates 202a and 202b (e.g., the bonding interface 318 is excluded from the bevel region 410). In addition, as shown in example 416, the sealant layers 320a and 320b are bonded within the bevel region 410 (e.g., there is no intermediate layer of bonding interface structure between the sealant layers 320a and 320b). In some embodiments, the semiconductor substrate-based layered structure of example 416 is referred to as a "bevel-only support" layered structure.

[0077] Figure 4C An example of a semiconductor substrate layer structure including sealant layers 320a and 320b, dielectric layers 324a and 324b, bonding layers 326a and 326b, and the set of interconnect structures 328a and 328b is shown. Figure 4CIn the embodiment, the bonding interface 318 is bonded to the bonding layers 326a and 326b. Figure 4C As shown, the bonding interface 318 is bonded to the interconnect structures 328a and 328b.

[0078] As shown in example 420, the bonding interface 318 spans the entire width 408 of the semiconductor substrates 202a and 202b. In addition, as shown in example 420, the sealant layers 320a and 320b span the entire width 408 of the semiconductor substrates 202a and 202b. In some embodiments, the semiconductor substrate-based layered structure of example 420 is referred to as a layered structure "below the bonding interface." In this embodiment, one or more layers of the bonding interface structure can be located between the sealant layers 320a and 320b across the entire width 408.

[0079] As shown in example 422, the bonding interface 318 spans the entire width 408 of the semiconductor substrates 202a and 202b. In addition, as shown in example 422, the sealant layers 320a and 320b are contained within the bevel region 410 of the semiconductor substrates 202a and 202b (e.g., do not span the entire width 408). In some embodiments, the semiconductor substrate-based layered structure of example 422 is referred to as a "bevel-supported below the bonding interface" layered structure.

[0080] As shown in example 424, the bonding interface 318 spans a portion of the overall width 408 of the semiconductor substrates 202a and 202b (e.g., the bonding interface 318 is excluded from the bevel region 410). In addition, as shown in example 424, the sealant layers 320a and 320b are bonded within the bevel region 410 of the semiconductor substrates 202a and 202b (e.g., there is no intermediate layer between the sealant layers 320a and 320b). In some embodiments, the semiconductor substrate-based layered structure of example 424 is referred to as a "bevel-only support" layered structure.

[0081] As mentioned above, Figures 4A-4C Provided as an example. Other examples may be related to Figures 4A-4C Different than described.

[0082] Figures 5A-5C is a diagram of an example embodiment 500 of an example integrated circuit die based layered structure including an encapsulant layer as described herein. The integrated circuit die based layered structure may include encapsulant layers 320a and 320b and integrated circuit dies 204a and 204b bonded along bonding interface 318.

[0083] Figure 5A An example of an integrated circuit die based layered structure including encapsulant layers 320a and 320b, dielectric layers 324a and 324b, and bonding layers 326a and 326b is shown. Figure 5A Examples 502 , 504 , and 506 are included regarding an overall width 508 of the integrated circuit dies 204 a and 204 b and regarding a beveled edge region 510 (eg, a sloped edge region) between the integrated circuit dies 204 a and 204 b .

[0084] As shown in example 502, the bonding interface 318 spans the entire width 508 of the integrated circuit dies 204a and 204b. In addition, as shown in example 502, the sealant layers 320a and 320b span the entire width 508 of the integrated circuit dies 204a and 204b. In some embodiments, the layered structure based on the integrated circuit die of example 502 is referred to as a layered structure "below the bonding interface". In this embodiment, one or more layers of the bonding interface structure can be located between the sealant layers 320a and 320b across the entire width 508.

[0085] As shown in example 504, the bonding interface 318 spans the entire width 508 of the integrated circuit dies 204a and 204b. In addition, as shown in example 504, the sealant layers 320a and 320b are contained within the bevel region 510 of the integrated circuit dies 204a and 204b (e.g., not spanning the entire width 508). In some embodiments, the layered structure based on the integrated circuit die of example 504 is referred to as a layered structure of "bevel support below the bonding interface". In this embodiment, one or more layers of the bonding interface structure can be located between the sealant layers 320a and 320b within the bevel region 510.

[0086] As shown in example 506, the bonding interface 318 spans a portion of the overall width 508 of the integrated circuit dies 204a and 204b (e.g., the bonding interface 318 is excluded from the bevel region 510). In addition, as shown in example 506, the encapsulant layers 320a and 320b are bonded within the bevel region 510 of the integrated circuit dies 204a and 204b (e.g., there is no intermediate layer between the encapsulant layers 320a and 320b). In some embodiments, the integrated circuit die-based layered structure of example 506 is referred to as a "bevel-only support" layered structure.

[0087] Figure 5B An example of a semiconductor substrate layer structure including sealant layers 320a and 320b, dielectric layers 324a and 324b, and the set of interconnect structures 328a and 328b is shown. Figure 5B In the embodiment, the bonding interface 318 is bonded to the dielectric layers 324a and 324b. Figure 5B As shown, the bonding interface 318 is bonded to the interconnect structures 328a and 328b.

[0088] As shown in example 512, the bonding interface 318 spans the entire width 508 of the integrated circuit dies 204a and 204b. In addition, as shown in example 512, the encapsulant layers 320a and 320b span the entire width 508 of the semiconductor dies 204a and 204b. In some embodiments, the layered structure based on the integrated circuit die of example 512 is referred to as a layered structure "below the bonding interface". In this embodiment, one or more layers of the bonding interface structure can be located between the encapsulant layers 320a and 320b across the entire width 508.

[0089] As shown in example 514, the bonding interface 318 spans the entire width 508 of the integrated circuit dies 204a and 204b. In addition, as shown in example 514, the sealant layers 320a and 320b are contained within the bevel region 510 of the integrated circuit dies 204a and 204b (e.g., not spanning the entire width 508). In some embodiments, the layered structure based on the integrated circuit die of example 514 is referred to as a layered structure of "bevel support below the bonding interface". In this embodiment, one or more layers of the bonding interface structure can be located between the sealant layers 320a and 320b within the bevel region 510.

[0090] As shown in example 516, the bonding interface 318 spans a portion of the overall width 508 of the integrated circuit dies 204a and 204b (e.g., the bonding interface 318 is excluded from the bevel region 510). In addition, as shown in example 516, the sealant layers 320a and 320b are bonded within the bevel region 510 (e.g., there is no intermediate layer between the sealant layers 320a and 320b). In some embodiments, the integrated circuit die-based layered structure of example 516 is referred to as a "bevel-only support" layered structure.

[0091] Figure 5C An example of a semiconductor substrate layer structure including sealant layers 320a and 320b, dielectric layers 324a and 324b, bonding layers 326a and 326b, and the set of interconnect structures 328a and 328b is shown. Figure 5C In the embodiment, the bonding interface 318 is bonded to the bonding layers 326a and 326b. Figure 5C As shown, the bonding interface 318 is bonded to the interconnect structures 328a and 328b.

[0092] As shown in example 518, the bonding interface 318 spans the entire width 508 of the integrated circuit dies 204a and 204b. In addition, as shown in example 520, the sealant layers 320a and 320b span the entire width 508 of the integrated circuit dies 204a and 204b. In some embodiments, the layered structure based on the integrated circuit die of example 520 is referred to as a layered structure "below the bonding interface". In this embodiment, one or more layers of the bonding interface structure can be located between the sealant layers 320a and 320b across the entire width 508.

[0093] As shown in example 520, the bonding interface 318 spans the entire width 508 of the integrated circuit dies 204a and 204b. In addition, as shown in example 522, the sealant layers 320a and 320b are contained within the bevel region 510 of the integrated circuit dies 204a and 204b (e.g., not spanning the entire width 508). In some embodiments, the layered structure based on the integrated circuit die of example 522 is referred to as a layered structure of "bevel support below the bonding interface". In this embodiment, one or more layers of the bonding interface structure can be located between the sealant layers 320a and 320b within the bevel region 510.

[0094] As shown in example 522, the bonding interface 318 spans a portion of the overall width 508 of the integrated circuit dies 204a and 204b (e.g., the bonding interface 318 is excluded from the bevel region 510). In addition, as shown in example 524, the sealant layers 320a and 320b are bonded within the bevel region 510 of the integrated circuit dies 204a and 204b (e.g., there is no intermediate layer between the sealant layers 320a and 320b). In some embodiments, the integrated circuit die-based layered structure of example 524 is referred to as a "bevel-only support" layered structure.

[0095] As mentioned above, Figures 5A-5C Provided as an example. Other examples may be related to Figures 5A-5C Different than described.

[0096] Figure 6 is a diagram of an example implementation 600 of an example stress relief structure described herein. The stress relief structure may correspond to stress relief structure 322b.

[0097] like Figure 6 As shown, integrated circuit dies 204a and 204b use corresponding Figure 5C The example 518 of the integrated circuit die based layered structure is bonded together. Figure 6 In FIG. 2 , the stress relief structure 322 b penetrates into the integrated circuit die 204 b and includes a portion of the encapsulant layer 320 b. Figure 6 The integrated circuit die 204a does not include a stress relief structure.

[0098] The choice of including stress relief structures or excluding stress relief structures in the integrated circuit die may depend on a variety of factors, including a projected stress profile along the bonding interface 318, a projected warpage of the stacked die product (including the integrated circuit dies 204a and 204b), and / or properties of one or more materials included in the stacked die product, etc. Additionally or alternatively, the degree of stress relief (and / or warpage of the stacked die structure including the integrated circuit dies 204a and 204b) may be adjusted by adjusting the size, pattern, or spacing of the stress relief structures 322b.

[0099] As mentioned above, Figure 6 Provided as an example. Other examples may be related to Figure 6 The content described is different.

[0100] Figures 7A-7F is a diagram of an example embodiment 700 for forming a layered structure including an encapsulant layer as described herein. In some embodiments, one or more of the semiconductor processing tools (102-118) and / or the transfer tool 120 can perform one or more operations described in conjunction with the example embodiment 700. In some embodiments, one or more operations described in conjunction with the embodiment 700 can be performed by another semiconductor processing tool. In addition, although the example embodiment 700 is described in forming a layered structure as part of bonding two semiconductor substrates, one or more aspects of the example embodiment 700 can be applicable to forming a layered structure as part of bonding two integrated circuit dies.

[0101] Turn to refer to Fig. 7A , a stress relief cavity 702 may be formed in the semiconductor substrate 202a. For example, one or more of the semiconductor processing tools (102-118) may perform photolithography patterning operations, etching operations, CMP operations, and / or other types of operations to form the stress relief cavity in the semiconductor substrate 202a.

[0102] like Figure 7B As shown, the sealant layer 320a can be formed over the semiconductor substrate 202a. For example, one or more of the semiconductor processing tools (102-114) can perform a dispensing operation, a curing operation, a CMP operation, and / or other types of operations to form the sealant layer 320a over the semiconductor substrate 202a. As part of forming the sealant layer 320a over the semiconductor substrate 202a, the stress relief cavity 702 can be filled to form a stress relief structure 322a.

[0103] In some embodiments, after formation, the thickness D1 of the sealant layer 320a may be included in the range of about 1 micron to about 20 microns. If the thickness D1 is less than about 1 micron, the bonding interface structure including the sealant layer 320a may not have sufficient rigidity and / or strength to prevent the semiconductor substrate 202a from warping during subsequent bonding operations. If the thickness D1 is greater than about 20 microns, it may result in increased costs and / or low manufacturing efficiency. However, other values ​​and ranges of thickness D1 are also within the scope of the present disclosure.

[0104] like Figure 7C As shown, dielectric layer 324a is formed over sealant layer 320a. For example, one or more of the semiconductor processing tools (102-118) may perform deposition operations, CMP operations, and / or other types of operations to form dielectric layer 324a over sealant layer 320a.

[0105] like Fig.7D As shown, bonding layer 326a is formed over dielectric layer 324a. For example, one or more of the semiconductor processing tools (102-118) may perform a deposition operation, a CMP operation, and / or other types of operations to form bonding layer 326a over dielectric layer 324a.

[0106] Turn to refer to Fig. 7E , the set of interconnect structures 328a is formed through the bonding layer 326a, the dielectric layer 324a, and the sealant layer 320a. For example, as part of forming the set of interconnect structures 328a, one or more semiconductor processing tools (102-118) may perform photolithography patterning operations, etching operations, deposition operations, plating operations, CMP operations, and / or other types of operations to form the set of interconnect structures 328a through the bonding layer 326a, the dielectric layer 324a, and the sealant layer 320a.

[0107] like Figure 7F As shown, semiconductor substrate 202a and semiconductor substrate 202b are bonded together. For example, as part of bonding semiconductor substrate 202a and semiconductor substrate 202b, one or more semiconductor processing tools (102-118) (e.g., bonding tool 108) may perform a eutectic bonding operation that bonds bonding layers 326a and 326b along a bonding interface 318. Additionally or alternatively, one or more of semiconductor processing tools (102-118) (e.g., bonding tool 108) may perform a eutectic bonding operation that bonds the set of interconnect structures 328a and 328b along a bonding interface 318. In some embodiments, bonding semiconductor substrate 202a and semiconductor substrate 202b includes forming a bonding interface structure 316.

[0108] As mentioned above, Figures 7A-7FProvided as an example. Other examples may be related to Figures 7A-7F Different than described.

[0109] Figure 8 8 is a diagram of example components of an apparatus 800 associated with forming a support encapsulant layer structure for stacked die applications. The apparatus 800 may correspond to one or more of the semiconductor processing tools (102-118) and / or the transfer tools 120. In some embodiments, one or more of the semiconductor processing tools (102-118) and / or the transfer tools 120 may include one or more apparatuses 800 and / or one or more components of the apparatus 800. Figure 8 As shown, device 800 may include a bus 810 , a processor 820 , a memory 830 , an input component 840 , an output component 850 , and / or a communication component 860 .

[0110] The bus 810 may include one or more components that enable wired and / or wireless communication between components of the device 800. The bus 810 may include one or more components that enable wired and / or wireless communication between components of the device 800. Figure 8 Two or more components of a processor 820 are coupled together, for example, via an operable coupling, a communication coupling, an electronic coupling, and / or an electrical coupling. For example, bus 810 may include an electrical connection (e.g., a wire, a trace, and / or a lead) and / or a wireless bus. Processor 820 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit, and / or other types of processing components. Processor 820 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 820 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0111] The memory 830 may include volatile and / or non-volatile memory. For example, the memory 830 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 830 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 830 may be a non-transitory computer-readable medium. The memory 830 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the device 800. In some embodiments, the memory 830 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 820), such as via bus 810. The communicatively coupled between the processor 820 and the memory 830 may enable the processor 820 to read and / or store process information in the memory 830 and / or store information in the memory 830.

[0112] Input components 840 may enable device 800 to receive input, such as user input and / or sensed input. For example, input components 840 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, an angular velocity sensor, and / or a brake. Output components 850 may enable device 800 to provide output, such as through a display, a speaker, and / or a light emitting diode. Communication components 860 may enable device 800 to communicate with other devices through wired connections and / or wireless connections. For example, communication components 860 may include a receiver, a transmitter, a transceiver, a modem, a network adapter, and / or an antenna.

[0113] Device 800 can perform one or more operations or processes described herein. For example, a non-temporary computer-readable medium (e.g., memory 830) can be executed by processor 820 to store a set of instructions (e.g., one or more instructions or program codes). Processor 820 can execute a set of instructions to perform one or more operations or processes described herein. In some embodiments, the set of instructions is executed by one or more processors 820, so that one or more processors 820 and / or device 800 perform one or more operations or processes described herein. In some embodiments, hard-wired circuits can be used instead of instructions or in combination with instructions to perform one or more operations or processes described herein. Additionally or alternatively, processor 820 can be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuits and software.

[0114] Figure 8The number and arrangement of components in FIG. 8 are provided as examples. Apparatus 800 may include additional components, fewer components, different components, or components that are different from the components in FIG. Figure 8 Additionally or alternatively, one or more components of the device 800 (eg, one or more components) may perform one or more functions described as being performed by another set of components of the device 800.

[0115] Fig. 9 is a flow chart of an example process 900 associated with forming a support encapsulant layer structure for stacked die applications. In some embodiments, Fig. 9 One or more process blocks are performed by one or more semiconductor processing tools (e.g., one or more semiconductor processing tools (102-118) and / or a transfer tool 120). Additionally or alternatively, Fig. 9 One or more process blocks may be performed by one or more components of the apparatus 800 , such as a processor 820 , a memory 830 , an input component 840 , an output component 850 , and / or a communication component 860 .

[0116] like Fig. 9 As shown, the process 900 may include forming a siloxane-based compound layer on a first semiconductor substrate (block 910). For example, as described herein, one or more of the semiconductor processing tools (102-118) and / or the transfer tool 120 may form a siloxane-based compound layer (e.g., the sealant layer 320a) on a first semiconductor substrate (e.g., the semiconductor substrate 202a).

[0117] like Fig. 9 As further shown, process 900 may include forming a first bonding layer over the siloxane-based compound layer (block 920). For example, as described herein, one or more of the semiconductor processing tools (102-118) and / or the transfer tool 120 may form the first bonding layer (e.g., bonding layer 326a) over the siloxane-based compound layer.

[0118] like Fig. 9 As further shown, the process 900 may include bonding the first bonding layer to a second bonding layer associated with the second semiconductor substrate (block 930). For example, as described herein, one or more of the semiconductor processing tools (102-118) and / or the transfer tool 120 may bond the first bonding layer to a second bonding layer (e.g., bonding layer 326b) associated with the second semiconductor substrate (e.g., semiconductor substrate 202b).

[0119] Process 900 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or in conjunction with any combination of one or more other processes described elsewhere herein.

[0120] In the first embodiment, forming a siloxane-based compound layer on a first semiconductor substrate includes dispensing the siloxane-based compound layer on the first semiconductor substrate and curing the siloxane-based compound layer.

[0121] In a second embodiment, alone or in combination with the first embodiment, process 900 includes forming a dielectric layer (eg, dielectric layer 324a) over the siloxane-based compound layer and then forming a first bonding layer over the sealant layer.

[0122] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 900 includes forming a first set of interconnect structures (e.g., the set of interconnect structures 328b) through a first bonding layer and a siloxane-based compound layer, and bonding the first set of interconnect structures to a second set of interconnect structures associated with a second semiconductor substrate.

[0123] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 900 includes forming one or more stress relief cavities (eg, stress relief cavity 702 ) in the first semiconductor substrate before forming a siloxane-based compound layer on the first semiconductor substrate.

[0124] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, forming a siloxane-based compound layer on the first semiconductor substrate includes filling one or more stress relief cavities with the siloxane-based compound layer.

[0125] although Fig. 9 Example blocks of process 900 are shown, but in some embodiments, process 900 includes Fig. 9 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those described in 900. Additionally or alternatively, two or more of the blocks or process 900 may be performed in parallel.

[0126] Fig.10 is a flow chart of an example process 1000 associated with forming a support encapsulant layer structure for stacked die applications. In some embodiments, Fig.10 One or more process blocks of are performed by one or more semiconductor processing tools and / or wafer die transfer tools (e.g., one or more of the semiconductor processing tools (102-118) and / or transfer tools 120). Additionally or alternatively, Fig.10 One or more process blocks may be performed by one or more components of the apparatus 800 , such as a processor 820 , a memory 830 , an input component 840 , an output component 850 , and / or a communication component 860 .

[0127] like Fig.10As shown, process 1000 may include forming a first layer of a silazane-based compound over a portion of a first integrated circuit die at block 1010. For example, as described herein, one or more of the semiconductor processing tools (102-118) and / or transfer tools may form a first layer of a silazane-based compound (e.g., encapsulant layer 320a) over a portion of a first integrated circuit die (e.g., integrated circuit die 204a).

[0128] like Fig.10 As further shown, the process 1000 may include forming a first dielectric layer over the first layer of the silazane-based compound (block 1020). For example, as described herein, one or more of the semiconductor processing tools (102-118) and / or the transfer tool 120 may form the first dielectric layer (e.g., dielectric layer 324a) over the first encapsulant layer.

[0129] like Fig.10 As further shown, the process 1000 may include forming a second layer of a silazane-based compound over a portion of the second integrated circuit die (block 1030). For example, as described herein, one or more of the semiconductor processing tools (102-118) and / or the transfer tool 120 may form the second layer of a silazane-based compound (e.g., encapsulant layer 320b) over a portion of the second integrated circuit die (204b).

[0130] like Fig.10 As further shown, the process 1000 may include forming a second dielectric layer over the second layer of the silazane-based compound (block 1040). For example, as described herein, one or more semiconductor processing tools (102-118) may form the second dielectric layer (e.g., dielectric layer 324b) over the second layer of the silazane-based compound.

[0131] like Fig.10 As further shown, process 1000 may include bonding the first dielectric layer and the second dielectric layer (block 1050). For example, one or more of the semiconductor processing tools (102-118) and / or transfer tools may bond the first dielectric layer and the second dielectric layer as described herein.

[0132] Process 1000 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or in conjunction with any combination of one or more other processes described elsewhere herein.

[0133] In a first embodiment, forming a first layer of a silazane-based compound over the portion of the first integrated circuit die includes forming the first layer of the silazane-based compound to a thickness (eg, thickness D1 ) included in a range of about 1 micron to about 20 microns.

[0134] In a second embodiment, alone or in combination with the first embodiment, forming the first layer of the silazane-based compound over the portion of the first integrated circuit die includes forming the first layer of the silazane-based compound only on the bevel edge (e.g., bevel edge region 510) of the first integrated circuit die.

[0135] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming the first layer of the silazane-based compound over the portion of the first integrated circuit die includes forming the first layer of the silazane-based compound over an entire width (e.g., entire width 508) of the first integrated circuit die.

[0136] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, bonding the first dielectric layer and the second dielectric layer includes bonding the first dielectric layer and the second dielectric layer using a eutectic bonding process.

[0137] although Fig.10 Example blocks of process 1000 are shown, but in some embodiments, process 1000 includes Fig.10 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those described in. Additionally or alternatively, two or more of the blocks or process 1000 may be performed in parallel.

[0138] Some embodiments described herein provide technology and equipment to form a stacked die product including two or more integrated circuit dies. The bonding interface between the two integrated circuit dies included in the stacked die product includes a layered structure. As part of the layered structure, each layer of the sealant material is directly on the coplanar surface of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the layers of the sealant material, and the sealant material is located on the coplanar surface of the two integrated circuit dies. Relative to another bonding interface structure that does not include each layer of the sealant material, the layered structure can reduce the lateral stress of the entire bonding interface to reduce the possibility of warping of the two integrated circuit dies. In addition, relative to another bonding interface structure that does not include each layer of the sealant material, the layered structure may include enhanced bonding performance and / or enhanced vibration reduction performance. The reduction of lateral stress, the improvement of bonding performance and / or vibration reduction performance can reduce the possibility of cracking or peeling of the bonding interface during the thinning operation of thinning one or more of the two integrated circuit dies.

[0139] In this way, the yield of the stacked die product is increased relative to the yield of a stacked die product having a bonding interface that does not include a layered structure. Additionally or alternatively, in some embodiments, trimming operations along the perimeter of the semiconductor substrates that are bonded to form the stacked die product can be eliminated. By increasing the yield of the stacked die product and eliminating trimming operations, resource consumption (e.g., semiconductor manufacturing processing tools, raw materials, manpower, and / or computing resources) to manufacture a large number of stacked die products can be reduced.

[0140] As described in more detail above, some embodiments described herein provide a method. The method includes forming a siloxane-based compound layer on a first semiconductor substrate. The method includes forming a first bonding layer above the siloxane-based compound layer. The method includes bonding the first bonding layer to a second bonding layer associated with a second semiconductor substrate.

[0141] In some embodiments, forming the siloxane-based compound layer on the first semiconductor substrate includes: dispensing the siloxane-based compound layer on the first semiconductor substrate; and curing the siloxane-based compound layer. In some embodiments, the method further includes forming a dielectric layer over the siloxane-based compound layer before forming the first bonding layer over the siloxane-based compound layer. In some embodiments, the method further includes forming a first group of interconnect structures through the first bonding layer and the siloxane-based compound layer; and bonding the first group of interconnect structures to a second group of interconnect structures associated with the second semiconductor substrate. In some embodiments, the method further includes forming one or more stress relief cavities in the first semiconductor substrate before forming the siloxane-based compound layer on the first semiconductor substrate. In some embodiments, forming the siloxane-based compound layer on the first semiconductor substrate includes filling the one or more stress relief cavities with the siloxane-based compound layer.

[0142] As described in more detail above, some embodiments described herein provide a method. The method includes forming a first layer of a silazane-based compound over a portion of a first integrated circuit die. The method includes forming a first dielectric layer over a first sealant layer. The method includes forming a second layer of a silazane-based compound over a portion of a second integrated circuit die. The method includes forming a second dielectric layer over the second layer of the silazane-based compound. The method includes bonding the first dielectric layer and the second dielectric layer.

[0143] In some embodiments, forming the first layer of the silazane-based compound over the portion of the first integrated circuit die includes forming the first layer of the silazane-based compound to a thickness ranging from about 1 micron to about 20 microns. In some embodiments, forming the first layer of the silazane-based compound over the portion of the first integrated circuit die includes forming the first layer of the silazane-based compound only on the hypotenuse of the first integrated circuit die. In some embodiments, forming the first layer of the silazane-based compound on the portion of the first integrated circuit die includes forming the first layer of the silazane-based compound over the entire width of the first integrated circuit die. In some embodiments, bonding the first dielectric layer and the second dielectric layer includes bonding the first dielectric layer and the second dielectric layer using a eutectic bonding process.

[0144] As described in more detail above, some embodiments described herein provide a device. The device includes a first bonding layer. The device includes a first layer of a siloxane-based compound or a silazane-based compound between the first bonding layer and a first integrated circuit, wherein the first integrated circuit is associated with a first integrated circuit die. The device includes a second bonding layer bonded to the first bonding layer. The device includes a second layer of a siloxane-based compound or a silazane-based compound between the second bonding layer and a second integrated circuit, wherein the second integrated circuit is associated with a second integrated circuit die.

[0145] In some embodiments, the device further comprises a first set of connection structures interspersed in the first bonding layer and the first layer of the silazane-based compound or the silazane-based compound, and a second set of connection structures interspersed in the second bonding layer and the first layer of the silazane-based compound or the silazane-based compound, wherein the second set of connection structures is bonded to the first set of connection structures. In some embodiments, the device further comprises one or more stress relief structures in the first integrated circuit die. In some embodiments, the first layer of the silazane-based compound or the silazane-based compound and the second layer of the silazane-based compound or the silazane-based compound comprise composite filler particles. In some embodiments, the device further comprises a bevel region, wherein the first layer of the silazane-based compound or the silazane-based compound and the second layer of the silazane-based compound or the silazane-based compound are directly bonded within the bevel region. In some embodiments, the device further comprises an interposer, wherein a stacked die structure is attached to the interposer, the stacked die structure comprising the first bonding layer, the first layer of the silazane-based compound or the silazane-based compound, the second bonding layer, and the second layer of the silazane-based compound or the silazane-based compound. In some embodiments, the device further comprises a bevel region, wherein a bonding interface structure is located within the bevel region between the first layer of the silazane-based compound or the silazane-based compound and the second layer of the silazane-based compound or the silazane-based compound. In some embodiments, the bonding interface structure comprises the first bonding layer directly bonding the second bonding layer. In some embodiments, the device further comprises a dielectric layer within the bevel region between the first layer of the silazane-based compound or the silazane-based compound and the second layer of the silazane-based compound or the silazane-based compound.

[0146] As used herein, the term "and / or", when used with multiple items, is intended to cover each of the multiple items individually and any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A but not B", and "B but not A".

[0147] As used herein, "satisfies a threshold" may refer to greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc., depending on the context.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: a first bonding layer; a silazane-based compound or a first layer of a silazane-based compound between the first bonding layer and the first integrated circuit, wherein the first integrated circuit is associated with a first integrated circuit die; a second bonding layer bonded to the first bonding layer; as well as a silazane-based compound or a second layer of a silazane-based compound between the second bonding layer and the second integrated circuit, Wherein the second integrated circuit is associated with a second integrated circuit die.

2. The semiconductor device according to claim 1, wherein: Also includes: a first set of connecting structures interspersed in the first bonding layer and the silazane-based compound or the first layer of the silazane-based compound, and a second set of connecting structures, interspersed in the second bonding layer and the silazane-based compound or the first layer of the silazane-based compound, The second set of connection structures is coupled to the first set of connection structures.

3. The semiconductor device according to claim 1, wherein: Also includes: One or more stress relief structures in the first integrated circuit die.

4. The semiconductor device according to claim 1, wherein: wherein the silazane-based compound or the first layer of the silazane-based compound and the silazane-based compound or the second layer of the silazane-based compound include: Composite filler particles.

5. The semiconductor device according to claim 1, wherein: Also includes: A bevel region, wherein the silazane-based compound or the first layer of the silazane-based compound and the silazane-based compound or the second layer of the silazane-based compound are directly bonded within the bevel region.

6. The semiconductor device according to claim 1, wherein: Also includes: An interposer, wherein a stacked die structure is attached to the interposer, the stacked die structure comprising the first bonding layer, the silazane-based compound or the first layer of the silazane-based compound, the second bonding layer, and the silazane-based compound or the second layer of the silazane-based compound.

7. The semiconductor device according to claim 1, wherein: Also includes: A bevel region, wherein a bonding interface structure is located within the bevel region between the silazane-based compound or the first layer of the silazane-based compound and the silazane-based compound or the second layer of the silazane-based compound.

8. The semiconductor device according to claim 7, wherein: Wherein the bonding interface structure comprises: The first bonding layer is directly bonded to the second bonding layer.

9. The semiconductor device according to claim 8, wherein: Also includes: A dielectric layer is within the bevel region between the silazane-based compound or the first layer of the silazane-based compound and the second layer of the silazane-based compound or the silazane-based compound.

10. The semiconductor device according to claim 1, wherein: The thickness of the first layer of the silazane-based compound is in a range of 1 μm to 20 μm.

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