Interconnection structure

Abstract

The embodiment of the utility model relates to an interconnection structure. The interconnect structure includes a first metal line and a second metal line surrounded by an abutment dielectric and disposed on the substrate. The first dielectric layer is disposed on the first metal line, and has a through hole extending through the first dielectric layer and overlying a first contact region of the first metal line. The second dielectric layer is disposed on the first dielectric layer, the first metal line and the second metal line, and has a first via hole and a second via hole extending through the second dielectric layer, the first via hole being connected to the through hole and overlying the first contact region, and the second via hole overlying the second contact region of the second metal line. The first through hole is arranged on the first contact area and extends along the through hole, the first via hole and the first upper surface of the second dielectric layer. The second through hole is arranged on the second contact area and extends along the second via hole and the second upper surface of the second dielectric layer. The first via includes a first flange lined on an upper surface of the first dielectric layer and connecting sidewalls of the first dielectric layer and the second dielectric layer.

Description

Technical Field

[0001] The embodiment of the utility model relates to an interconnection structure. Background Art

[0002] Interconnect structures include conductive features that electrically connect two or more circuit components (e.g., transistors, power supplies, signal inputs, etc.) together. Interconnect structures include on-chip interconnects for integrated circuits and off-chip interconnects in heterogeneous system integration. In interconnect design, geometry (width, thickness, spacing, aspect ratio, pitch), materials, process control, and design layout are critical for proper interconnect functionality, performance, power efficiency, reliability, and manufacturing yield. Utility Model Content

[0003] In some embodiments, the utility model relates to an interconnection structure. The interconnection structure includes a first metal line and a second metal line surrounded by an adjacent dielectric and arranged on a substrate. A first dielectric layer is arranged on the first metal line, and has a through hole extending through the first dielectric layer and overlying a first contact area of ​​the first metal line. A second dielectric layer is arranged on the first dielectric layer, the first metal line and the second metal line, and has a first via hole and a second via hole extending through the second dielectric layer, the first via hole connecting the through hole and overlying the first contact area, and the second via hole overlying the second contact area of ​​the second metal line. A first through hole is arranged on the first contact area and extends along the first upper surface of the through hole, the first via hole and the second dielectric layer. A second through hole is arranged on the second contact area and extends along the second via hole and the second upper surface of the second dielectric layer. The first through hole includes a first flange, and the first flange is lined on the upper surface of the first dielectric layer and connects the sidewalls of the first dielectric layer and the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noteworthy that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion.

[0005] Figures 1A-1D A series of layout and cross-sectional views illustrating some embodiments of a method of forming an interconnect structure with staggered vias in a two-step process.

[0006] Figure 2 A process flow diagram of some embodiments of a method for forming an interconnect structure with staggered vias in a two-step process is shown.

[0007] Figure 3A-3B Layout and cross-sectional views of some embodiments of an interconnect structure with staggered vias are shown.

[0008] Figure 4A-4B Layouts and cross-sectional views of some additional embodiments of interconnect structures having staggered vias disposed on boundary regions of underlying metal lines are shown.

[0009] Figure 5A-5B Layout and cross-sectional views of some additional embodiments of an interconnect structure having a plurality of staggered vias of different heights are shown.

[0010] Figure 6A-6B Layouts and cross-sectional views of some additional embodiments of interconnect structures having staggered vias and second vias of smaller height and aligned upper surfaces are shown.

[0011] Figures 7A-11B A series of layout and cross-sectional views illustrating some embodiments of a method of forming an interconnect structure with staggered vias in a two-step process.

[0012] Figures 12A-15B A series of layout diagrams and cross-sectional views illustrating some embodiments of a method for forming an interconnect structure having staggered vias at corner regions of metal lines by a two-step process. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and settings are described below to simplify the utility model. Of course, these are only examples and are not restrictive. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features can be formed between the first and second features, so that the first feature and the second feature may not be in direct contact. In addition, the utility model may repeat reference numerals and / or letters for similar features in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another component or feature, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] Fabricating semiconductor devices involves depositing and patterning various materials, such as semiconductors, dielectrics, and metals, to form circuit components. The circuit components then need to be electrically connected to function properly. Interconnect structures include conductive features that connect two or more circuit components (such as transistors, power supplies, signal inputs, etc.) together. Interconnect structures can be on-chip interconnects for integrated circuits or off-chip interconnects in heterogeneous system integration. In interconnect design, geometric dimensions (width, thickness, spacing, aspect ratio, pitch), materials, process control, and design layout are critical for proper interconnect functionality, performance, power efficiency, reliability, and manufacturing yield.

[0016] In some applications, the thickness of the semiconductor device is not uniform, or multiple semiconductor devices of different thicknesses are integrated on a single substrate. For example, a MEMS device may contain gaps of multiple heights; an acoustic device may require different distances from the corresponding flexible board and fixed board, or an optical device may have cavities of different lengths. One method of forming a multi-thickness structure is to form and pattern a first dielectric layer on a first area that requires a greater thickness, and then fully form a second dielectric layer. Nevertheless, it can be challenging to form an interconnect structure to connect metal lines from the bottom to the top of a multi-thickness structure. Deeper vias may result in reduced connection reliability and greater contact resistance with the underlying metal. In addition, a separate mask and patterning process may be required to form deeper vias to reduce excessive etching damage to other via areas with smaller dimensions.

[0017] Therefore, some embodiments of the utility model relate to a new method for forming an interconnect structure for a multi-thickness semiconductor device, and an associated interconnect structure. In the method, a first through hole can be formed by a two-step process, wherein the lower portion of the first through hole is formed when the first dielectric layer is patterned to increase the height of the first zone, and then the upper portion of the first through hole is formed by forming and patterning the second dielectric layer. The second dielectric layer is overlying the patterned first dielectric layer and simultaneously forms a second through hole in the second zone lacking the first dielectric layer. Therefore, no additional patterning process is required to form the first through hole and the second through hole with different thicknesses. In some embodiments, the first through hole is formed so that the bottom lateral dimension of the upper portion is greater than the top lateral dimension of the lower portion, thereby resulting in a staggered through hole shape with a ledge between the upper and lower portions. Since the step height for filling the first through hole is reduced by having a staggered through hole shape with a protrusion in the middle, the reliability and contact resistance of the first through hole can be improved.

[0018] Figures 1A-1D A series of layout diagrams and cross-sectional views of some embodiments of a method of forming an interconnect structure with staggered vias by a two-step process are shown. Figures 1A-1D It is described in relation to a method, but it should be understood that Figures 1A-1D The structure disclosed in is not limited to this method, but can exist independently as a structure independent of this method.

[0019] like Figure 1A As shown in the layout diagram and cross-sectional view, a first metal line 106A and a second metal line 106B are provided. In some embodiments, the first metal line 106A and the second metal line 106B may be arranged side by side or in a repeated array. In order to form a larger height above the first metal line 106A, in some embodiments, a first dielectric layer 108 is first deposited over the first metal line 106A and the second metal line 106B, and then patterned to be removed from the second metal line 106B. A through-hole 110 is formed by a patterning process, exposing a first contact region of the first metal line 106A. In some embodiments, from the layout diagram, the through-hole 110 may have a square shape as shown, or another polygonal or circular shape. The through-hole 110 may be disposed at one or more different positions above the first metal line 106A, for example Figures 1A-1D In some alternative embodiments, the through hole 110 may be disposed in one or more of a central region, a corner region, or other applicable locations.

[0020] like Figure 1B As shown in the layout diagram and cross-sectional view of , a second dielectric layer 112 is formed on the first dielectric layer 108, overlying the first metal line 106A and also overlying the second metal line 106B lacking the first dielectric layer 108. Therefore, the first dielectric layer 108 and the second dielectric layer 112 together construct a higher height directly above the first metal line 106A than directly above the second metal line 106B. The second dielectric layer 112 may extend into the through hole 110 to reach the first contact area of ​​the first metal line 106A. In some embodiments, the second dielectric layer 112 may be deposited in its entirety. In some alternative embodiments, the second dielectric layer 112 may also be patterned but still remain to cover at least a portion of the first dielectric layer 108 and the second dielectric layer 112.

[0021] like Figure 1C As shown in the layout diagram and cross-sectional view of FIG. 1 , the second dielectric layer 112 is then patterned to simultaneously form a first via-hole 116A and a second via-hole 116B, wherein the first via-hole 116A is directly located above the lower through-hole 110 and the second via-hole 116B exposes the second contact region of the second metal line 106B. The through-hole 110 and the first via-hole 116A together form a first through-hole 118A (see FIG. 1 ). Figure 1D The second via hole is used for a second through hole 118B (see FIG. 1 ) with a depth smaller than that of the first through hole 118A. Figure 1D). In some embodiments, from the layout diagram, the first via 116A or the second via 116B may have a square shape as shown, or another polygonal shape or a circular shape. The first via 116A may be disposed concentrically with the through hole 110. In some embodiments, the bottom lateral dimension of the first via 116A is greater than the top lateral dimension of the through hole 110, thereby resulting in a staggered shape with a flange between the first via 116A and the through hole 110. The second via 116B may be disposed at one or more different positions above the second metal line 106B, for example Figure 1C-1D In some alternative embodiments, the second via 116B may be disposed in one or more of a central region, a side region within the boundary of the second metal line 106B, a corner region, or other suitable locations, as will be discussed in more detail later. In some embodiments, the second via 116B may have a top or bottom lateral dimension, such as a diameter or side length, between the first via 116A and the through hole 110.

[0022] like Figure 1D As shown in the layout diagram and cross-sectional view of FIG, a first via 118A and a second via 118B are formed in the first via 116A and the through hole 110 and the second via 116B, respectively. In some embodiments, the first via 118A extends along the first upper surface 112u1 of the second dielectric layer 112, and the second via 118B extends along the second upper surface 112u2 of the second dielectric layer 112. The first device 128 can be formed on the first via 118A above the first upper surface 112u1 and electrically connected to the first metal line 106A. Similarly, the second device 130 can be formed on the second via 118B above the second upper surface 112u2 and electrically connected to the second metal line 106B. As an example, a control signal can be provided from a logic circuit to the first device 128 and the second device 130 through the first metal line 106A and the second metal line 106B, respectively. A first vertical distance from the bottom surface of the first device 128 to the first metal line 106A is greater than a second vertical distance from the bottom surface of the second device 130 to the second metal line 106B.

[0023] By forming the through hole 110 while patterning the first dielectric layer 108, and then forming the first via hole 116A and the second via hole 116B together by patterning the second dielectric layer 112, no additional patterning process is required to pattern the first through hole 118A and the second through hole 118B of different thicknesses. In addition, since the step height for filling the first through hole 118A is reduced by having a staggered shape with a protrusion in the middle, the reliability and contact resistance of the first through hole 118A are improved.

[0024] Figure 2A process flow chart of some embodiments of a method for forming an interconnect structure having staggered through-holes formed by a two-step process is shown. Although method 200 is illustrated and described below as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be interpreted as limiting. For example, some actions may occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, all illustrated actions may not be required to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0025] At act 202, in some embodiments, a first metal line and a second metal line are provided overlying a substrate. A first dielectric layer is formed on the first metal line and the second metal line. Figure 7A-7B Some examples corresponding to action 202 are illustrated.

[0026] At act 204, in some embodiments, a first dielectric layer is patterned overlying the first metal line and absent from the second metal line. When the first dielectric layer overlying the first metal line is patterned, a lower through hole is patterned in the first region. Figure 1A , 8A -8B and 12A-12B illustrate some examples corresponding to action 204.

[0027] At action 206, a second dielectric layer is formed on the first dielectric layer in the first region and the second dielectric layer also overlies the second metal line in the second region lacking the first dielectric layer. The second dielectric layer can extend into the through hole to the first contact region of the first metal line. The second dielectric layer can be formed directly on the second metal line. Figure 1B , 9A -9B and 13A-13B illustrate some examples corresponding to action 206.

[0028] The second dielectric layer is then patterned to simultaneously form a first via and a second via in the second region, the first via being directly above the lower through hole in the first region, in action 208. Thus, the lower through hole and the first via together form a via that exposes a first contact region for the first through hole, and the second via exposes a second contact region for the second through hole, the second through hole having a depth less than the depth of the first through hole. Figure 1C , 10A -10B and 14A-14B illustrate some examples corresponding to action 208.

[0029] At act 210, a first via is formed on the first contact region, the first via extending along the first via, and a second via is formed on the second contact region, the second via extending along the second via. The first via and the second via may extend along the first upper surface and the second upper surface of the second dielectric layer, respectively. Figure 1D , 11A -11B and 15A-15B illustrate some examples corresponding to action 210.

[0030] Figure 3A-3B Layout diagram 300A and cross-sectional view 300B of some embodiments of an interconnect structure having a first via 118A disposed in a first region 132 and a second via 118B disposed in a second region 134 are shown. The first via 118A may be a via disposed staggered on a first contact region 106c1 of a first metal line 106A, and the second via 118B may be disposed on a second contact region 106c2 of a second metal line 106B.

[0031] The first metal line 106A and the second metal line 106B may be surrounded by the adjacent dielectric 104 and disposed on the substrate 102. In some embodiments, the first metal line 106A and the second metal line 106B are respectively connected to a semiconductor device (not shown) disposed within the substrate 102 through one or more additional interconnect features including metal lines and vias. As an example, the first metal line 106A and the second metal line 106B may be connected to a logic circuit within the substrate 102 to transmit control signals to the first device 128 and the second device 130, respectively.

[0032] In some embodiments, the first dielectric layer 108 is disposed on the first metal line 106A. The through hole 110 extends through the first dielectric layer 108 and overlies the first contact area 106c1 of the first metal line 106A. The second dielectric layer 112 can be disposed on the first dielectric layer 108 and the first metal line 106A and the second metal line 106B. The first via 116A and the second via 116B extend through the second dielectric layer 112. The first via 116A is connected to the through hole 110 and overlies the first contact area 106c1. The second via 116B overlies the second contact area 106c2 of the second metal line 106B. The first through hole 118A extends along the through hole 110, the first via 116A, and the first upper surface 112u1 of the second dielectric layer 112. The second through hole 118B extends along the second via 116B and the second upper surface 112u2 of the second dielectric layer 112.

[0033] In some embodiments, the bottom lateral dimension of the first via 116A is greater than the top lateral dimension of the through hole 110. The first through hole 118A may include a flange 1181 lining the upper surface of the first dielectric layer 108 and connecting the sidewalls of the first dielectric layer 108 and the second dielectric layer 112. In some embodiments, the first via 116A has an entire sidewall 116s extending smoothly from the second dielectric layer 112 to the first dielectric layer 108.

[0034] The first device 128 may be disposed on a first lateral portion of the first through-hole 118A and electrically connected to the first metal line 106A through the first through-hole 118A. Similarly, the second device 130 may be disposed on a second lateral portion of the second through-hole 118B and electrically connected to the second metal line 106B through the second through-hole 118B. A first vertical distance t1 from the bottom surface of the first device 128 to the first metal line 106A is greater than a second vertical distance t2 from the bottom surface of the second device 130 to the second metal line 106B, so that gaps or cavities of different lengths may be provided between the first metal line 106A and the first device 128 and between the second metal line 106B and the second device 130.

[0035] See also Figure 3A , in some embodiments, the second via 116B is a square having a side length between the side length of the through hole 110 and the side length of the first via 116A. The through hole 110 and the first via 116A may also both be square. In some alternative embodiments, the through hole 110, the first via 116A, or the second via 116B may have another polygonal or circular shape. The first via 116A may be arranged concentrically with the through hole 110. As an example, the through hole 110 may have a side length of about 50nm to about 300nm, the first via 116A may have a side length of about 300nm to about 1000nm, and the second via 116B may have a side length of about 50nm to about 1000nm (200nm to about 500nm). In some embodiments, the second via 116B may have a top or bottom lateral dimension, such as a diameter or side length, between the first via 116A and the through hole 110. The lateral dimension of the first via 116A may be offset by a constant value from the lateral dimension of the first via 116A. By setting the layout shape and size as described above, the layout area can be utilized to the maximum extent while providing sufficient contact area and ledge for better via filling.

[0036] In various embodiments, the substrate 102 may include any type of semiconductor body (e.g., silicon / CMOS bulk, SiGe, etc.), such as a semiconductor wafer or one or more grains on a wafer, and any other type of semiconductor and / or epitaxial layer formed thereon and / or otherwise associated therewith. The adjacent dielectric 104 may include, for example, silicon dioxide and / or other low-k dielectric materials. The first metal line 106A and the second metal line 106B may include a conductive material, such as aluminum (Al), copper (Cu), titanium nitride (e.g., TiN), tantalum nitride (e.g., TaN), platinum (e.g., Pt), titanium (e.g., Ti), tantalum (e.g., Ta), tungsten (e.g., W), iron (e.g., Fe), nickel (e.g., Ni), some other suitable metal, or any alloy or combination of the foregoing. For example, the first metal line 106A and the second metal line 106B have a thickness of about 15 nanometers, about 15-500 nanometers, or other suitable thicknesses, respectively. The first dielectric layer 108 or the second dielectric layer 112 may include a dielectric material, such as silicon dioxide, silicon nitride, and / or aluminum oxide. The first and second vias 118A and 118B may include TiN or other suitable conductive materials.

[0037] Figure 4A-4B Layout diagram 400A and cross-sectional view 400B of some additional embodiments of interconnect structures having first vias 118A disposed in first region 132 and second vias 118B disposed in second region 134 are shown. First vias 118A may be staggered vias disposed on first contact region 106c1 of first metal line 106A, and second vias 118B may be disposed on second contact region 106c2 of second metal line 106B. In some alternative Figure 3A-3B In the illustrated embodiment, the first through hole 118A and the second through hole 118B may be disposed at corner regions of the first metal line 106A and the second metal line 106B, respectively (eg, Figure 4A-4B as shown) or at the boundary region of the first metal line 106A and the second metal line 106B (eg Figures 1A-1D shown).

[0038] In some embodiments, the first metal line 106A and the second metal line 106B each include a barrier layer 120 surrounding the bottom and sidewall surfaces of the metal body 122. The first through hole 118A and the second through hole 118B are in contact with the barrier layer 120 and the metal body 122, respectively. In some embodiments, the barrier layer 120 includes a material that forms less native oxide on the top, so it is easier to clean and provide better contact resistance for the first through hole 118A and the second through hole 118B. For example, the barrier layer 120 may include TaN, and the metal body may include AlCu. The native oxide TaO of the barrier layer 120 is easier to remove than aluminum oxide. Therefore, by forming the first contact area 106c1 and the second contact area 106c2 in contact with the barrier layer 120 at the corner area of ​​the first metal line 106A and the second metal line 106B, the interconnection reliability and contact resistance are improved.

[0039] In some embodiments, for example, Figure 4A-4B As shown, when the first via hole 116A is patterned, the first dielectric layer 108 may be removed from one or more sides of the first via hole 116A. Therefore, the first sidewall portion 116s-1 smoothly extends from the second dielectric layer 112 to the first dielectric layer 108. The second sidewall portion 116s-2 near the second region 134 may be lower than the first sidewall portion 116s-1. The first through hole 118A may include a first ridge 118l-1 lining the upper surface of the first dielectric layer 108. In some embodiments, the first through hole 118A also includes a second ridge 118l-2 lining the upper surface of the barrier layer 120 and connecting the surface of the first metal line 106A and the upper surface of the recess adjacent to the dielectric 104. Similarly, the second through hole 118B includes a ridge lining the upper surface of the barrier layer 120 and connecting the surface of the second metal line 106B and the upper surface of the recess adjacent to the dielectric 104.

[0040] Figure 5A-5BLayouts and cross-sectional views of some additional embodiments of an interconnect structure having multiple staggered vias of different heights are shown. For example, the interconnect structure may have a first via 118A disposed in a first region 132 connecting a first metal line 106A, a second via 118B disposed in a second region 134 connecting a second metal line 106B, and a third via 118C disposed in a third region 136 connecting a third metal line 106C. The vias 118A, 118B, 118C are formed by a series of upper via patterning processes. In some embodiments, the vias may have a square shape as shown, or another polygonal or circular shape as an alternative in the layout diagram. The lateral dimensions of the vias may be offset by a constant value to maximize the use of the layout area while providing sufficient contact area and flanges for easier via filling. For example, the first dielectric layer 108 may be patterned directly above the first metal line 106A, with the through hole 110 disposed therethrough. The second dielectric layer 112 may be patterned directly over the first metal line 106A and the second metal line 106B, with the first via 116A and the second via 116B disposed therethrough. The third dielectric layer 124 may be patterned directly over the first metal line 106A, the second metal line 106B, and the third metal line 106C, with the first upper via 126A, the second upper via 126B, and the third upper via 126C disposed therethrough.

[0041] Thus, first via 118A may be a staggered via arranged along three concentric holes connected by flanges between each other: first upper via 126A extending from third dielectric layer 124 to the first upper surface of second dielectric layer 112, first via 116A extending from second dielectric layer 112 to the upper surface of first dielectric layer 108, through via 110 connected to first via 116A through the upper surface of first dielectric layer 108. Second via 118B may be a staggered via arranged along two concentric holes: second via 116B and second upper via 126B connected by flanges on the second upper surface of second dielectric layer 112. The second upper surface is lower than the first upper surface of second dielectric layer 112. Finally, third via 118C is arranged along third upper via 126C to reach third metal line 106C.

[0042] See also Figure 5A In the layout diagram of FIG. 1 , in some embodiments, the first upper via 126A and the first via 116A can be arranged concentrically with the through hole 110. In some embodiments, the second via 116B can be arranged concentrically with the second upper via 126B. By setting the layout shape and size as described above, the layout area can be maximized while providing sufficient contact area and flange for better through-hole filling.

[0043] Figure 6A-6B Layouts and cross-sectional views of some additional embodiments of interconnect structures with staggered vias and second vias of smaller height are illustrated. In lieu of all of the above discussion, in some embodiments, the upper surface of the second metal line 106B can be disposed above the upper surface of the first metal line 106A, so that even if the first via 118A and the second via 118B have aligned upper lateral portions, there can be a smaller height between the second metal line 106B and the second dielectric layer 112. The upper lateral portions of the first via 118A and the second via 118B can both be disposed on the flat upper surface of the second dielectric layer 112. Similar to the above, the first via 118A and the second via 118B can be formed by forming the through hole 110 when patterning the first dielectric layer 108, and then forming the first via 116A and the second via 116B together by patterning the second dielectric layer 112. Therefore, no additional patterning process is required to form the first via 118A having a thickness greater than the second via 118B. Additionally, the through hole 110 and the first via 116A may have a lateral dimension offset at the junction, thereby forming a ledge therebetween. As a result, the step height for filling the first via 118A is reduced by having a staggered via shape, thereby improving the reliability and contact resistance of the first via 118A.

[0044] Figures 7A-11B A series of layout diagrams and cross-sectional views of some embodiments of a method of forming an interconnect structure with staggered vias by a two-step process are shown. Figures 7A-11B It is described in relation to a method, but it should be understood that Figures 7A-11B The structure disclosed in is not limited to such a method, but can stand alone as a structure independent of the method.

[0045] like Figure 7A-7B As shown in the layout diagram 700A and the cross-sectional diagram 700B of FIG. 1 , in some embodiments, a first metal line 106A and a second metal line 106B are provided. A first dielectric layer 108 is formed on the first metal line 106A and the second metal line 106B. The process of forming the first dielectric layer 108 may be or include depositing an oxide or other applicable dielectric layer by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), some other suitable deposition process, or any combination of the foregoing.

[0046] like Figures 8A-8BAs shown in the layout diagram 800A and the cross-sectional view 800B of FIG. 1 , in some embodiments, the first dielectric layer 108 is patterned to be removed from the second metal line 106B. The patterning can be performed, for example, by a photolithography / etching process and / or by some other suitable process. During the patterning, a through hole 110 is formed, exposing the first contact region in the first metal line 106A. In some embodiments, from the layout diagram, the through hole 110 can have a square shape as shown, or another polygonal or circular shape. The through hole 110 can be disposed at one or more different positions above the first metal line 106A, for example Figures 1A-1D In some optional embodiments, the through hole 110 can be disposed in one or more of the central area, the corner area or other applicable positions.

[0047] like Figures 9A-9B As shown in the layout diagram 900A and the cross-sectional view 900B of FIG. 1 , in some embodiments, the second dielectric layer 112 is formed on the first dielectric layer 108 overlying the first metal line 106A and also overlying the second metal line 106B lacking the first dielectric layer 108. The process of forming the second dielectric layer 112 may be or include depositing an oxide or other applicable dielectric layer by PVD, CVD, ALD, some other suitable deposition process, or any combination of the foregoing. Therefore, the first dielectric layer 108 and the second dielectric layer 112 together construct a higher height directly above the first metal line 106A than directly above the second metal line 106B. The second dielectric layer 112 may extend into the through hole 110 to reach the first contact area 106c1 of the first metal line 106A. In some embodiments, the second dielectric layer 112 may be deposited in its entirety. In some alternative embodiments, the second dielectric layer 112 may also be patterned but still retained to cover at least a portion of the first dielectric layer 108 and the second dielectric layer 112.

[0048] like Figures 10A-10B As shown in the layout diagram 1000A and the cross-sectional diagram 1000B of FIG. 1 , in some embodiments, the second dielectric layer 112 is then patterned to simultaneously form a first via 116A and a second via 116B, wherein the first via 116A is directly above the lower through hole 110 and exposes the first contact region 106c1 of the first metal line 106A, and the second via 116B exposes the second contact region 106c2 of the second metal line 106B. The through hole 110 and the first via 116A together form a first through hole 118A (see FIG. 1 ). Figures 11A-11B The second via hole is used for a second through hole 118B (see Figures 11A-11B ). In some embodiments, from Fig. 10A From the layout diagram of FIG. 1 , the first via 116A or the second via 116B may have the following structure: Fig. 10AThe first via 116A may be arranged concentrically with the through hole 110. In some embodiments, the bottom lateral dimension of the first via 116A is greater than the top lateral dimension of the through hole 110, thereby resulting in a staggered shape with a flange 118l between the first via 116A and the through hole 110. In some embodiments, the second via 116B may have a top or bottom lateral dimension, such as a diameter or side length, between the first via 116A and the through hole 110.

[0049] In some embodiments, hard mask layer 114 may be formed on second dielectric layer 112 and used as a mask for patterning second dielectric layer 112 accordingly. Hard mask layer 114 may be formed by one or more deposition or spin coating processes of various polymer, dielectric and / or metal materials. Hard mask layer 114 may include, for example, TiN. Although hard mask layer 114 is not shown in some figures (e.g., Figures 10A-11B , 14A-15B), and in other figures (e.g., Figure 1A-6B ), but it should be understood that for various embodiments, the hard mask layer 114 may be used or omitted, and may or may not remain in the final device above the second dielectric layer 112.

[0050] like Figures 11A-11B As shown in the layout diagram 1100A and the cross-sectional view 1100B, in some embodiments, the first through hole 118A and the second through hole 118B are formed in the first via 116A and the through hole 110 and the second via 116B, respectively. In some embodiments, a pre-cleaning process is performed to prepare the first contact area 106c1 and the second contact area 106c2. For example, an ion bombardment process such as an Ar bombardment process can be performed to remove native oxide (e.g., aluminum oxide). Then, a conductive feature is formed along the first via 116A, the through hole 110, and the second via 116B, and the conductive feature extends along the first upper surface 112u1 of the second dielectric layer 112 and the second upper surface 112u2 of the second dielectric layer 112 that is lower than the first upper surface 112u1. For example, the conductive feature can be conformally formed by DC sputtering, PVD, CVD, ALD, some other suitable deposition process, or any combination of the foregoing. As an example, the conductive features may be formed to have a thickness in the range of 10 nm to 50 nm to balance low line resistance and reliable electrical connections with process cost.

[0051] Then, the conductive features are patterned to form a first through hole 118A having a first lateral portion extending along the first upper surface 112u1 and a second through hole 118B having a second lateral portion extending along the second upper surface 112u2. The hard mask layer 114 may be patterned together with the conductive features. In this case, the hard mask layer 114 may have sidewalls that are vertically aligned with the sidewalls of the first through hole 118A and the second through hole 118B. In some embodiments, the hard mask layer 114 may include the same metal material as the conductive features and may thus be merged into a seamless whole of the first through hole 118A and the second through hole 118B in the final device. The first device 128 may be formed on the first lateral portion of the first through hole 118A and electrically connected to the first metal line 106A. Similarly, the second device 130 may be formed on the second lateral portion of the second through hole 118B and electrically connected to the second metal line 106B. As an example, control signals may be provided from the logic circuit in the substrate 102 to the first device 128 and the second device 130 through the first metal line 106A and the second metal line 106B, respectively. A first distance from the bottom surface of the first device 128 to the first metal line 106A is greater than a second distance from the bottom surface of the second device 130 to the second metal line 106B, so cavities of different lengths (e.g., different vertical distances t1, t2) may be provided between the first metal line 106A and the first device 128 and between the second metal line 106B and the second device 130, respectively.

[0052] Figures 12A-15B A series of layout diagrams and cross-sectional views of some embodiments of a method for forming an interconnect structure having staggered vias formed at corners or border regions by a two-step process are shown. Figures 12A-15B It is described in relation to a method, but it should be understood that Figures 12A-15B The structure disclosed in is not limited to this method, but can exist independently as a structure independent of this method.

[0053] like Figures 12A-12BAs shown in the layout diagram 1200A and the cross-sectional view 1200B of , in some embodiments, a first dielectric layer 108 having a through hole 110 is formed on the first metal line 106A, and the through hole 110 exposes the first contact area 106c1 of the first metal line 106A. In some embodiments, the process of forming the first dielectric layer 108 may include depositing an oxide or other applicable dielectric layer by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), some other suitable deposition process, or any combination of the foregoing. Then, the first dielectric layer 108 is patterned to be removed from the second metal line 106B and the first contact area 106c1 of the first metal line 106A. The patterning can be performed, for example, by a lithography / etching process and / or by some other suitable process. In some embodiments, from the layout diagram, the through hole 110 can have a square shape as shown, or another polygonal or circular shape. The through hole 110 may be disposed at one or more different locations above the first metal line 106A, such as a corner region, wherein one or more sides of the interface of the first metal line 106A, the second metal line 106B, and the adjacent dielectric 104 are exposed. In some embodiments, the first metal line 106A and the second metal line 106B each include a barrier layer 120 surrounding the bottom and sidewall surfaces of the metal body 122. The through hole 110 exposes the barrier layer 120 and the metal body 122. As an example, the barrier layer 120 may include TaN, and the metal body may include AlCu.

[0054] like Figures 13A-13B As shown in the layout diagram 1300A and the cross-sectional view 1300B of FIG. 1300A, in some embodiments, the second dielectric layer 112 is formed on the first dielectric layer 108 overlying the first metal line 106A and also overlying the second metal line 106B lacking the first dielectric layer 108. The process of forming the second dielectric layer 112 may be or include depositing an oxide or other applicable dielectric layer by PVD, CVD, ALD, some other suitable deposition process, or any combination of the foregoing. Therefore, the first dielectric layer 108 and the second dielectric layer 112 together construct a higher height directly above the first metal line 106A than directly above the second metal line 106B. The second dielectric layer 112 may extend to the barrier layer 120 and the portion of the metal body 122 in the through hole 110. In some embodiments, the second dielectric layer 112 may be deposited all over. In some alternative embodiments, the second dielectric layer 112 may also be patterned but still remain to cover at least a portion of the first dielectric layer 108 and the second dielectric layer 112.

[0055] like Figures 14A-14BAs shown in the layout diagram 1400A and the cross-sectional diagram 1400B of FIG. 1400A, in some embodiments, the second dielectric layer 112 is then patterned to simultaneously form a first via 116A and a second via 116B, wherein the first via 116A is directly above the lower through hole 110 and exposes the first contact region 106c1 of the first metal line 106A, and the second via 116B exposes the second contact region 106c2 of the second metal line 106B. The through hole 110 and the first via 116A together form a first through hole 118A (see FIG. 140A ). Figures 15A-15B ) a via hole. In some embodiments, as shown, the second dielectric layer 112 is completely removed from the sidewalls of the first dielectric layer 108. In some alternative embodiments, the second dielectric layer 112 may have a remaining portion disposed on the sidewalls of the first dielectric layer 108. The second via hole is used to form a second through hole 118B (see Figures 15A-15B In some embodiments, the first via 116A or the second via 116B may have a Fig.14A The square shown in , or from Fig.14A Alternatively, the layout diagram of the first via 116A may have another polygonal or circular shape. The first via 116A may be arranged concentrically with the through hole 110. In some embodiments, the bottom lateral dimension of the first via 116A is greater than the top lateral dimension of the through hole 110, thereby resulting in a staggered shape with a ledge between the first via 116A and the through hole 110 (see below). Figures 15A-15B In some embodiments, the second via 116B may have a top or bottom lateral dimension, such as a diameter or side length, between that of the first via 116A and the through hole 110 .

[0056] like Figures 15A-15B As shown in the layout diagram 1500A and the cross-sectional view 1500B, in some embodiments, the first through hole 118A and the second through hole 118B are formed in the first via 116A and the through hole 110 and the second via 116B, respectively. In some embodiments, a pre-cleaning process is performed to prepare the first contact area 106c1 and the second contact area 106c2. For example, an ion bombardment process such as an Ar bombardment process can be performed to remove native oxides (e.g., TaO, Al2O3). By using the layout design of the first through hole 118A and the second through hole 118B at the corners of the metal lines 106A and 106B, the barrier layer 120 is located at least a portion of the contact areas 106c1 and 106c2. The barrier layer 120 may have a native oxide that is softer and easier to etch than the metal body 122. In this way, the pre-cleaning process takes less time and is completed more completely, thereby improving interconnect reliability and contact resistance.

[0057] Then, conductive features are formed along the first via 116A, the through hole 110, and the second via 116B, and the conductive features extend along the first upper surface 112u1 of the second dielectric layer 112 and the second upper surface 112u2 of the second dielectric layer 112 that is lower than the first upper surface 112u1. For example, the conductive features can be conformally formed by DC sputtering, PVD, CVD, ALD, some other suitable deposition process, or any combination of the foregoing. As an example, the conductive features can be formed to have a thickness in the range of 10nm to 50nm to strike a balance between low line resistance and reliable electrical connection and process cost.

[0058] Then, the conductive features are patterned to form a first through hole 118A having a first lateral portion extending along the first upper surface 112u1 and a second through hole 118B having a second lateral portion extending along the second upper surface 112u2. In some embodiments, the first sidewall portion 116s-1 smoothly extends from the second dielectric layer 112 to the first dielectric layer 108. The second sidewall portion 116s-2 near the second region 134 may be lower than the first sidewall portion 116s-1. The first through hole 118A may include a first ledge 118l-1 lined on the upper surface of the first dielectric layer 108. In some embodiments, the first through hole 118A also includes a second ledge 118l-2, which lines the upper surface of the barrier layer 120 and connects the surface of the first metal line 106A and the recessed upper surface adjacent to the dielectric 104. Similarly, the second via 118B includes a ledge that lines the upper surface of the barrier layer 120 and connects the surface of the second metal line 106B and the recessed upper surface adjacent to the dielectric 104. The hard mask layer 114 can be patterned together with the conductive features. In this case, the hard mask layer 114 can have sidewalls that are vertically aligned with the sidewalls of the first via 118A and the second via 118B. In some embodiments, the hard mask layer 114 can include the same metal material as the conductive features and can therefore be merged into a seamless whole with the first via 118A and the second via 118B in the final device.

[0059] Therefore, the present invention relates to a new method for forming an interconnect structure, which eliminates a separate deep via patterning process to simplify the manufacturing process, thereby forming staggered vias to provide improved connection reliability and contact resistance.

[0060] Therefore, in some embodiments, the utility model relates to a method for forming an interconnect structure for a semiconductor device. The method includes depositing a first dielectric layer on a first metal line and a second metal line overlying a substrate, and the first dielectric layer is patterned to be removed from the second metal line and form a through hole exposing a first contact area of ​​the first metal line. The method also includes depositing a second dielectric layer on both the first metal line and the second metal line, the second dielectric layer extending into the through hole to reach the first contact area of ​​the first metal line and located on the second metal line. The method also includes patterning the second dielectric layer to form a first via and a second via, the first via being vertically connected to the through hole and concentric with the through hole, the first via and the through hole exposing the first contact area of ​​the first metal line, and the second via exposing the second contact area of ​​the second metal line. The method also includes extending along the through hole, the first via, and the first upper surface of the second dielectric layer to form a first through hole on the first contact area, and extending along the second via and the second upper surface of the second dielectric layer to form a second through hole on the second contact area.

[0061] In some embodiments, the first via is formed to have a bottom lateral dimension greater than a top lateral dimension of the through hole, and a first ledge is formed between the first via and the through hole. In some embodiments, the second via is formed to have a top lateral dimension between the top lateral dimension of the first via and the top lateral dimension of the through hole. In some embodiments, the method further comprises forming a hard mask layer after depositing the second dielectric layer, wherein the second dielectric layer is patterned according to the hard mask layer. In some embodiments, the first via has an entire sidewall extending smoothly from the second dielectric layer to an upper portion of the first dielectric layer. In some embodiments, the through hole and the first via are directly overlying a corner region of the first metal line. In some embodiments, the first through hole contacts the barrier layer and the metal body of the first metal line, and wherein the second through hole contacts the barrier layer and the metal body of the second metal line. In some embodiments, the first via is formed to have a first sidewall portion and a second sidewall portion, the first sidewall portion extending smoothly from the second dielectric layer to the first dielectric layer, and the second sidewall portion being lower than the first sidewall portion. In some embodiments, the second via is formed to directly overlie a corner region of the second metal line, and the second through hole contacts the barrier layer and the metal body of the second metal line. In some embodiments, a first device is formed on the first upper surface having a first vertical distance to the first metal line and a second device is formed on the second upper surface having a second vertical distance to the second metal line, wherein the first vertical distance is greater than the second vertical distance.

[0062] In other embodiments, the utility model relates to a method for forming an interconnect structure for a semiconductor device. The method includes forming a first metal line and a second metal line on a substrate, and forming a first dielectric layer on the first metal line while the first dielectric layer does not exist on the second metal line. A through hole is patterned in the first dielectric layer to expose a first contact area of ​​the first metal line. The method also includes forming a second dielectric layer on both the first metal line and the second metal line. The second dielectric layer is patterned with a first via hole, the first via hole is connected to the through hole and exposes the first contact area of ​​the first metal line, and the second dielectric layer is simultaneously patterned with a second via hole, the second via hole exposes the second contact area of ​​the second metal line. The method also includes extending along the through hole, the first via hole and the first upper surface of the second dielectric layer to form a first through hole on the first contact area, and extending along the second via hole and the second upper surface of the second dielectric layer to form a second through hole on the second contact area. The first upper surface is higher than the second upper surface.

[0063] In other embodiments, the first through hole is formed with a first flange, the first flange is lined on the upper surface of the first dielectric layer and connects the sidewalls of the first dielectric layer and the second dielectric layer. In other embodiments, the through hole is formed to directly overlie the corner area of ​​the first metal line, and wherein the first via hole exposes the first metal line and the adjacent dielectric. In other embodiments, the first metal line and the second metal line are formed with a barrier layer surrounding the bottom and sidewall surfaces of the metal body, and wherein the first through hole and the second through hole contact the barrier layer and the metal body. In other embodiments, the first through hole is formed with a second flange, the second flange is lined on the upper surface of the barrier layer and connects the first metal line and the surface of the adjacent dielectric.

[0064] In some other embodiments, the utility model relates to an interconnect structure for a semiconductor device. The interconnect structure includes a first metal line and a second metal line surrounded by an adjacent dielectric and arranged on a substrate. A first dielectric layer is arranged on the first metal line, and has a through hole extending through the first dielectric layer and overlying a first contact area of ​​the first metal line. A second dielectric layer is arranged on the first dielectric layer, the first metal line and the second metal line, and has a first via hole and a second via hole extending through the second dielectric layer, the first via hole connecting the through hole and overlying the first contact area, and the second via hole overlying the second contact area of ​​the second metal line. A first through hole is arranged on the first contact area and extends along the through hole, the first via hole and the first upper surface of the second dielectric layer. A second through hole is arranged on the second contact area and extends along the second via hole and the second upper surface of the second dielectric layer. The first through hole includes a first flange, and the first flange is lined on the upper surface of the first dielectric layer and connects the sidewalls of the first dielectric layer and the second dielectric layer.

[0065] In yet other embodiments, the first via has a bottom lateral dimension that is greater than a top lateral dimension of the through hole. In yet other embodiments, from a layout view, the second via is a square having a side length between a side length of the through hole and a side length of the first through hole. In yet other embodiments, each of the first metal line and the second metal line includes a barrier layer surrounding a bottom and sidewall surface of a metal body, and wherein the first through hole and the second through hole contact the barrier layer and the metal body. In yet other embodiments, the first through hole includes a second flange, the second flange lining an upper surface of the barrier layer and connecting the first metal line and the surface of the adjacent dielectric.

[0066] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present invention.

Claims

1. An interconnect structure, characterized in that: include: A first metal line and a second metal line, surrounded by an adjacent dielectric and disposed on a substrate; A first dielectric layer disposed on the first metal line and having a through hole extending through the first dielectric layer and overlying a first contact region of the first metal line; a second dielectric layer disposed on the first dielectric layer, the first metal line and the second metal line, having a first via and a second via extending through the second dielectric layer, the first via connecting the through hole and overlying the first contact region, and the second via overlying the second contact region of the second metal line; and A first through hole is disposed on the first contact region and extends along the through hole, the first via hole and the first upper surface of the second dielectric layer; as well as A second through hole is disposed on the second contact region and extends along the second via hole and the second upper surface of the second dielectric layer; The first through hole includes a first flange, which is lined on the upper surface of the first dielectric layer and connects the side walls of the first dielectric layer and the second dielectric layer.

2. The interconnect structure according to claim 1, characterized in that: The first via has a bottom lateral dimension that is greater than a top lateral dimension of the through hole.

3. The interconnect structure according to claim 1, characterized in that: From the layout diagram, the second via hole is a square, and the side length of the second via hole is between the side length of the through hole and the side length of the first through hole.

4. The interconnect structure according to claim 1, characterized in that Each of the first metal line and the second metal line includes a barrier layer surrounding a bottom and sidewall surfaces of a metal body, and wherein the first via and the second via contact the barrier layer and the metal body.

5. The interconnection structure according to claim 4, characterized in that: The first via includes a second ledge lining an upper surface of the barrier layer and connecting the first metal line and the adjacent dielectric surface.

6. The interconnection structure according to claim 4, characterized in that The adjacent dielectric has a concave upper surface.

7. The interconnect structure according to claim 1, characterized in that The first through hole is disposed in a central area, a corner area or a boundary area of ​​the first metal line.

8. The interconnect structure according to claim 1, characterized in that The second through hole is disposed in a central area, a corner area or a border area of ​​the second metal line.

9. The interconnect structure according to claim 1, characterized in that: Also includes: A hard mask layer is located on the second dielectric layer and has sidewalls vertically aligned with sidewalls of the first through hole and the second through hole.

10. The interconnect structure according to claim 1, characterized in that The second through holes are staggered through holes.

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