Chip input and output corner unit with ESD (Electro-Static Discharge) protection function

Abstract

The utility model relates to a chip input and output corner unit with an ESD (Electro-Static Discharge) protection function, which is characterized by comprising a corner transition oblique line connected with a lead and used for enabling the lead to transit from one direction to another direction; an ESD protection circuit, which is connected to the lead wire to be protected; and pad openings connected to the leads through the conductive vias. By introducing the ESD protection circuit and placing the bonding pad to be connected to the power line or the ground line, the IC circuit can be protected, the ESD current can be released, the ESD protection circuit can be used as a binding lead of a power supply or the ground, and the chip power supply connection can be enhanced.

Description

Technical Field

[0001] The utility model generally relates to the field of chip IO, and in particular to a chip input / output corner unit (CORENR cell) with ESD protection function and capable of being bound. Background Art

[0002] In the field of integrated circuit design, chip input and output (IO) pin pads are distributed at different locations on the chip according to design requirements and are interconnected through wiring.

[0003] Chinese patent CN106783775B discloses a three-dimensional integrated circuit chip and a power wiring method thereof. Figure 1 The schematic diagram of the chip shows the overall power wiring method. The top power network is made of a layer of metal to form several power rings. The power ring is used as the chip IO power connection unit, which only connects the IO power ring line into a ring. It only has the metal layer power line to form the steering and bridging function of the IO power ring. There is no embedded circuit device inside and no PAD opening is added. Therefore, there is no ESD protection unit and the lead cannot be bound. Utility Model Content

[0004] In order to at least partially solve the above problems in the prior art, the utility model proposes a chip input and output corner unit with ESD protection function, which is characterized by comprising:

[0005] A corner transition oblique line, which is connected to the lead wire and is used to make the lead wire transition from one direction to another direction;

[0006] An ESD protection circuit connected to the lead to be protected; and

[0007] The pad opening is connected to each lead through a conductive through hole.

[0008] In an embodiment of the present invention, the ESD protection circuit is located below the lead layer and is connected to the lead through an interlayer conductive structure.

[0009] In one embodiment of the present invention, the ESD protection circuit is connected between the protected power line and the ground line.

[0010] In one embodiment of the present invention, the ESD protection circuit is an RC clamp circuit.

[0011] In one embodiment of the present utility model, the RC clamping circuit comprises:

[0012] An RC circuit, comprising a resistor R and a first capacitor C connected in series, one end of the resistor R is connected to a power line, the other end of the resistor R is connected to a first node, one end of the first capacitor C is connected to the first node, and the other end of the first capacitor C is connected to a ground line;

[0013] an inverter, wherein an input terminal of the inverter is connected to the first node;

[0014] an NMOS transistor, wherein the gate of the NMOS transistor is connected to the output terminal of the inverter, the source of the NMOS transistor is connected to the ground line, and the drain of the NMOS transistor is connected to the power line; and

[0015] The second capacitor CVDD is connected between the power line and the ground line.

[0016] In an embodiment of the present invention, the pad opening is connected to a power line.

[0017] In one embodiment of the present invention, when the chip is packaged, the pad is led out as a power packaging line.

[0018] In an embodiment of the present invention, the pad opening is connected to a ground line.

[0019] In one embodiment of the present invention, when the chip is packaged, the pad is led out as a ground line.

[0020] In one embodiment of the present invention, the number and positions of the pad openings are determined according to the space resources of the corner unit.

[0021] The utility model introduces an ESD protection circuit based on the original corner unit's function as a power connection steering, and places a PAD connected to a power line or a ground line, which can not only protect the IC circuit and release the ESD current, but also serve as a binding lead for the power supply or the ground to strengthen the chip power connection.

[0022] The utility model has at least the following beneficial effects: the utility model can effectively solve the problem of increasing the ESD protection circuit by utilizing the space under the corner unit without increasing the chip area, thereby improving the reliability of the chip system; the utility model can also solve the problem of increasing the number of power output lines in the packaging project without occupying the GPIO digital model, thereby reducing the chip IR-drop and providing chip power supply capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To further illustrate the advantages and features of the various embodiments of the present invention, a more detailed description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding components will be represented by identical or similar reference numerals.

[0024] Figure 1 An overall schematic diagram of the chip showing the power wiring method.

[0025] Figure 2 A schematic diagram of a chip input-output corner unit 200 with ESD protection function according to an embodiment of the utility model is shown.

[0026] Figure 3 FIG. 4 is a schematic circuit diagram of an RC clamp circuit 300 according to an embodiment of the present invention.

[0027] Figure 4 A schematic diagram of a chip input-output corner unit 400 with ESD protection function according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0028] It should be noted that the components in the figures may be shown exaggeratedly for the sake of illustration and are not necessarily true to scale. In the figures, identical or functionally identical components are provided with the same reference numerals.

[0029] In the present invention, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate object between the two. In addition, "arranged on or above..." only indicates the relative positional relationship between two components, and in certain circumstances, such as after reversing the product direction, it can also be converted into "arranged under or below...", and vice versa.

[0030] In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be understood as limiting.

[0031] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of multiple elements.

[0032] It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the components or assemblies may be shown, but those of ordinary skill in the art will understand that under the teachings of the present invention, the required components or assemblies may be added according to the needs of the specific scenario. In addition, unless otherwise specified, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a feature in the first embodiment that corresponds to or has the same or similar functions, and the resulting embodiment also falls within the disclosure scope or recorded scope of the present application.

[0033] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the values ​​of the two are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to", etc. indicating directions also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0034] In addition, the numbering of the steps of the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps can be executed in different orders.

[0035] The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

[0036] In view of the problems existing in the prior art, the utility model proposes to introduce an ESD protection circuit at the position where the lead connection turns, and place a PAD to connect to the power line or the ground line, which can not only protect the IC circuit and release the ESD current, but also serve as a binding lead for the power supply or the ground to strengthen the chip power connection.

[0037] Figure 2 A schematic diagram of a chip input-output corner unit 200 with ESD protection function according to an embodiment of the utility model is shown.

[0038] like Figure 2 As shown, a plurality of leads turn at a corner unit 200, and each lead includes a corner transition oblique line 201 for transitioning the lead from one direction to another.

[0039] In the chip input / output corner unit 200 with ESD protection function, a lower layer ESD protection circuit 202 is introduced. That is, the ESD protection circuit 202 is located below the lead layer and is connected to the lead through the interlayer conductive structure. In one embodiment of the utility model, the ESD protection circuit 202 can be connected between the power line and the ground line to be protected. For example, Figure 2 In the embodiment, the ESD protection circuit 202 is connected between the VSIO line and the VDIO line.

[0040] The ESD protection circuit 202 may be an RC clamp circuit. Figure 3 FIG. 2 shows a schematic circuit diagram of an RC clamp circuit 300 according to an embodiment of the present invention. Figure 3 As shown, the RC clamp circuit 300 includes: an RC circuit, including a resistor R and a first capacitor C connected in series, one end of the resistor R is connected to the power line VDIO, the other end of the resistor R is connected to the first node 301, one end of the first capacitor C is connected to the first node 301, and the other end of the first capacitor C is connected to the ground line VSIO; an inverter 302, the input end of the inverter 302 is connected to the first node 301; an NMOS transistor, the gate of the NMOS transistor is connected to the output end of the inverter 302, the source is connected to the ground line VSIO, and the drain is connected to the power line VDIO; a second capacitor CVDD is connected between the power line VDIO and the ground line VSIO.

[0041] In other embodiments of the present invention, the ESD protection circuit may adopt other similar electrostatic discharge protection circuits.

[0042] The chip input / output corner unit 200 with ESD protection function further includes one or more pad (PAD) openings 203. The pad openings 203 can be connected to various leads through conductive vias.

[0043] In the practical application of the present invention, the number and position of the pad openings 203 can be determined according to the space resources of the corner unit. Usually, 1 to 2 pads can be placed. The placed pads can be used as ground lead packaging leads when the chip is packaged (such as Figure 2 as shown) or the power package lead (as shown Figure 4 As shown), the power supply capability of the chip is enhanced.

[0044] Figure 4 A schematic diagram of a chip input-output corner unit 400 with ESD protection function according to another embodiment of the present invention is shown. Figure 4 The corner unit 400 shown is Figure 2 The corner unit 200 is similar to the one shown, except that the pad opening 403 is connected to the power line VDIO through a conductive through hole. The placed pad can be used as a power packaging line when the chip is packaged.

[0045] The chip input and output corner unit with ESD protection function provided by the utility model can mainly form three benefits: 1. The introduction of the ESD protection circuit RC-CLAMP unit strengthens the density of the chip ESD network device, which is very helpful for improving the chip reliability; 2. The introduction of PAD opening, the number of PADs that can be introduced depends on the CORENR space resources, and generally 1 to 2 PADs can be placed; the placed PAD can be used as a ground lead package lead when the chip is packaged ( Figure 3 ) or power package lead ( Figure 4 ), strengthen the power supply capacity of the chip; 3. Introducing the ESD protection circuit inside the CORNER unit can reduce the ESD protection units that must be placed in other positions of the chip to meet the reliability design, thus saving on-chip space resources and reducing chip costs.

[0046] The utility model can effectively solve the problem of increasing the ESD protection circuit by using the space under the chip input and output corner unit with ESD protection function without increasing the chip area, thereby improving the reliability of the chip system. The chip input and output corner unit with ESD protection function provided by the utility model can also solve the problem of increasing the number of power output lines in the packaging project without occupying the GPIO digital model, reducing the chip IR-drop, and improving the chip power supply capacity.

[0047] The corner unit of the utility model has been successfully applied to the design of M041 M042 C031 products.

[0048] Although various embodiments of the utility model are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the utility model. Therefore, the breadth and scope of the utility model disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A chip input and output corner unit with ESD protection function, characterized in that: include: A corner transition oblique line, which is connected to the lead wire and is used to make the lead wire transition from one direction to another direction; An ESD protection circuit connected to the lead to be protected; and The pad opening is connected to each lead through a conductive through hole.

2. The chip input-output corner unit with ESD protection function according to claim 1, characterized in that: The ESD protection circuit is located below the lead layer and is connected to the lead through an interlayer conductive structure.

3. The chip input-output corner unit with ESD protection function according to claim 1, characterized in that: The ESD protection circuit is connected between the power line and the ground line to be protected.

4. The chip input-output corner unit with ESD protection function according to claim 3, characterized in that: The ESD protection circuit is an RC clamp circuit.

5. The chip input-output corner unit with ESD protection function according to claim 4, characterized in that: The RC clamp circuit comprises: An RC circuit, comprising a resistor R and a first capacitor C connected in series, one end of the resistor R is connected to a power line, the other end of the resistor R is connected to a first node, one end of the first capacitor C is connected to the first node, and the other end of the first capacitor C is connected to a ground line; an inverter, wherein an input terminal of the inverter is connected to the first node; an NMOS transistor, wherein the gate of the NMOS transistor is connected to the output terminal of the inverter, the source of the NMOS transistor is connected to the ground line, and the drain of the NMOS transistor is connected to the power line; and The second capacitor CVDD is connected between the power line and the ground line.

6. The chip input-output corner unit with ESD protection function according to claim 1, characterized in that: The pad opening is connected to a power line.

7. The chip input-output corner unit with ESD protection function according to claim 6, characterized in that: When the chip is packaged, the pad is led out as the power packaging line.

8. The chip input-output corner unit with ESD protection function according to claim 1, characterized in that: The pad opening is connected to a ground line.

9. The chip input-output corner unit with ESD protection function according to claim 8, characterized in that: When the chip is packaged, the pad is used as the ground wire.

10. The chip input-output corner unit with ESD protection function according to claim 1, characterized in that: The number and positions of the pad openings are determined according to the space resources of the corner unit.

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