System for realizing multichannel AD amplitude calibration and phase compensation

Abstract

The utility model relates to a system for realizing multichannel AD amplitude calibration and phase compensation. The system comprises a signal source, an AD acquisition card and an FPGA board, the signal source is connected with the AD acquisition card and the FPGA board and is used for outputting a calibration signal; the AD acquisition card is connected with the FPGA board, comprises a plurality of AD chips and is used for outputting original signal data; and the FPGA board is used for carrying out calibration synchronization on the original signal data according to the calibration signal. According to the scheme of the invention, multichannel AD synchronous acquisition can be realized by using the FPGA board, the precision is high, and the efficiency is good.

Description

Technical Field

[0001] The present application relates to the field of AD synchronization technology, and in particular to a system for realizing multi-channel AD amplitude calibration and phase compensation. Background Art

[0002] With the rapid development of science and technology and the development of sensor technology and communication technology, data acquisition systems have been widely used in various fields such as aerospace, military, industry, and medical treatment, especially in the detection and monitoring projects of high-precision products. In the digital processing system of the scatterometer, a multi-channel ADC circuit is required to sample the data. In this system, the data collected by the ADC needs to be processed by digital down-conversion, pulse compression, and beamforming. However, due to the large number of sampling circuits, the ADC channels are affected by environmental factors such as wiring differences and clock errors, which leads to consistency problems between ADC channels. Especially when there are multiple ADC chips working in parallel, there will be two different channel differences: one is the difference between the two acquisition circuits of the same ADC, and the other is the difference between the acquisition circuits of different ADC chips. This difference will increase the error of the later signal processing and reduce the accuracy of the entire system. Therefore, the consistency of the sampling channel is a very important issue.

[0003] In actual engineering applications, the acquisition system is required to have the characteristics of high speed, high precision, real-time processing, good system stability and a large number of channels. However, most traditional data acquisition solutions use ARM processors (Advanced RISCMachine, ARM) or digital signal processors (Digital Signal Processing, DSP) as the control core, which cannot effectively solve the technical problems of real-time and synchronization in high-speed data acquisition and processing, and it is difficult to achieve multi-channel AD synchronous acquisition.

[0004] In view of the above problems, those skilled in the art have been seeking solutions. Utility Model Content

[0005] The technical problem to be solved by the present application is to provide a system for realizing multi-channel AD amplitude calibration and phase compensation in view of the defects of the above-mentioned prior art.

[0006] In order to achieve the above objectives, this application is implemented through the following technical solutions:

[0007] The present application provides a system for implementing multi-channel AD amplitude calibration and phase compensation, comprising:

[0008] Signal source for outputting calibration signal,

[0009] AD acquisition card for outputting raw signal data,

[0010] An FPGA board for calibrating the raw signal data according to the calibration signal;

[0011] The signal source is electrically connected to the AD acquisition card and the FPGA board;

[0012] The AD acquisition card is arranged on the FPGA board, and includes a plurality of AD chips, and the AD chips are connected to the FPGA board via an IO interface;

[0013] The FPGA board is used to calibrate and synchronize the original signal data according to the calibration signal;

[0014] Wherein, the FPGA board includes at least two processing units, and the processing units include a second data distributor, an FFT algorithm module, an AD data operation module, an AD data processing module, and an AD packaging module;

[0015] The second data distributor is used for outputting the original signal data into a plurality of the original signal data;

[0016] The FFT algorithm module is used to output a calibration coefficient according to the original signal data and the calibration signal;

[0017] The AD data operation module is used to assign the calibration coefficient to the original signal data of the corresponding AD channel to obtain amplitude calibration data;

[0018] The AD data processing module is used to obtain phase compensation parameters according to the amplitude calibration data;

[0019] The AD packaging module is used to reorder and align the multiple amplitude calibration data according to the phase compensation parameters to obtain multiple synchronous data, and process the synchronous data into packet data and output it.

[0020] Optionally, the signal source includes a phase calibration signal source, a first data distributor, a plurality of sensors, and a plurality of data selectors;

[0021] The phase calibration signal source is electrically connected to the first data distributor, and the sensor is electrically connected to the corresponding data selector;

[0022] The phase calibration signal source is used to output a calibration signal;

[0023] The first data distributor is used for outputting the calibration signal into a plurality of calibration signals;

[0024] The sensor is used to collect a voltage analog signal and output the voltage analog signal to the corresponding data selector;

[0025] The data selector is used to select and output any one of the calibration signal and the voltage analog signal to the AD acquisition card.

[0026] Optionally, the FPGA board further includes a calibration switching control circuit and a multi-channel signal simulation circuit, wherein the calibration switching control circuit is used to control the phase calibration signal source to be connected to the signal simulation circuit;

[0027] The signal simulation circuit is used to transform the analog signal output by the signal source into a plurality of change data;

[0028] The AD acquisition card is also used to convert the plurality of change data into a plurality of original signal data;

[0029] The FFT algorithm module is also used to obtain the calibration coefficient according to the calibration signal and the original signal data.

[0030] Optionally, the signal simulation circuit includes an impedance conversion circuit, a signal conditioning and filtering circuit;

[0031] The impedance conversion circuit is electrically connected to the signal source and the signal conditioning and filtering circuit, and the signal conditioning and filtering circuit is electrically connected to the AD chip;

[0032] The impedance conversion circuit is used to change the input impedance of the signal entering the circuit into a high impedance state;

[0033] The signal conditioning and filtering circuit is used to adjust the amplitude and noise of the signal entering the circuit.

[0034] Optionally, the calibration switching control circuit includes a plurality of switches connected in parallel;

[0035] One end of the switch is connected to the phase calibration signal source, and the other end of the switch is electrically connected to the impedance conversion circuit.

[0036] Optionally, the FPGA board also includes a RAM controller; the RAM controller is electrically connected to the second data distributor, and is used to convert the AD clock domain of the original signal data into the FPGA clock domain.

[0037] Optionally, the processing unit also includes a second secondary data distributor, an input end of the second secondary data distributor is electrically connected to the second data distributor, a first output end of the second secondary data distributor is electrically connected to the RAM controller, and a second output end of the second secondary data distributor is connected to the FFT algorithm module.

[0038] Optionally, the FPGA board further includes a DDR controller and an RGMII controller, and the DDR controller is electrically connected to the RGMII controller;

[0039] The DDR controller is used to store the packet data in an external DDR chip and output the packet data to the RGMII controller;

[0040] The RGMII controller includes an RGMII interface, and the RGMII interface is used to output the packet data to an external communication chip.

[0041] Optionally, the system also includes an ARM processor and a display; the ARM processor is electrically connected to the FPGA board and the display, and is used to unpack the packet data output by the FPGA board into multiple synchronous data, and output the synchronous data to the display for display.

[0042] Optionally, the AD chip includes a reset pin, an AD analog-to-digital conversion start pin, and an AD analog-to-digital conversion end pin, and the FPGA board also includes a crystal oscillator;

[0043] The crystal oscillator is used to provide an FPGA input clock source, and the FPGA board is also used to control the reset pin, the AD analog-to-digital conversion start pin, and the AD analog-to-digital conversion end pin for timing synchronization according to the crystal oscillator.

[0044] The present application provides a system for realizing multi-channel AD amplitude calibration and phase compensation, and multi-channel AD synchronous acquisition can be realized by using FPGA with high precision and good efficiency.

[0045] In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specifically cites preferred embodiments and describes them in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The present application is described in detail below with reference to the accompanying drawings and specific implementation methods;

[0047] Figure 1 It is a schematic diagram of a system for implementing multi-channel AD amplitude calibration and phase compensation provided by an embodiment of the present application.

[0048] Figure 2 It is a schematic diagram of a signal source provided in an embodiment of the present application.

[0049] Figure 3 It is a structural schematic diagram of an FPGA board provided in one embodiment of the present application.

[0050] Figure 4 It is a functional block diagram of amplitude calibration provided by an embodiment of the present application.

[0051] Figure 5a It is a schematic diagram of a sequence of original signal data provided by an embodiment of the present application.

[0052] Figure 5b It is a sequence diagram of amplitude calibration data provided by an embodiment of the present application.

[0053] Figure 5c It is a sequence diagram of synchronization data provided by an embodiment of the present application.

[0054] Figure 6 This is a schematic diagram of synchronous acquisition between different models of ADs provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0056] Figure 1 is a schematic diagram of a system for implementing multi-channel AD amplitude calibration and phase compensation provided by an embodiment of the present application, please refer to Figure 1 The present application provides a system for realizing multi-channel AD amplitude calibration and phase compensation, including: a signal source, an AD acquisition card, an FPGA board, an ARM processor, and a display.

[0057] The signal source is electrically connected to the AD acquisition card and the FPGA board to output a calibration signal.

[0058] Figure 2 is a schematic diagram of a signal source provided by an embodiment of the present application, please refer to Figure 2 The signal source includes a phase calibration signal source, a first data distributor DMUX, two sensors, and two data selectors MUX1 and MUX2.

[0059] The first data distributor DMUX includes a signal input interface and two signal output interfaces; the data selector includes two signal input interfaces and one signal output interface.

[0060] The phase calibration signal source is electrically connected to the signal input interface of the first data distributor DMUX, the two signal output interfaces of the first data distributor DMUX are respectively connected to the signal input interfaces of the data selectors MUX1 and MUX2, the sensor is electrically connected to another signal input interface of the data selector, and the signal output interfaces of the data selectors MUX1 and MUX2 are connected to the AD acquisition card.

[0061] The phase calibration signal source is used to output a calibration signal.

[0062] The first data distributor is used to output the single calibration signal into multiple calibration signals.

[0063] The sensor is used to collect analog signals and output the analog signals to the corresponding data selector.

[0064] The data selector is used to select any one of the output calibration signal and analog signal to be output to the AD acquisition card.

[0065] In one embodiment, in actual product applications, sensors are used to collect analog signals sent by voltage sensors; in the test phase, phase calibration signal sources are used to perform phase calibration on multiple AD channels.

[0066] Specifically, in the embodiment of the present application, DMUX is the first data distributor, which outputs the single calibration signal generated by the phase calibration signal source as two calibration signals. MUX is a data selector, which selects the sensor signal or the phase calibration signal. The phase calibration signal is selected during multi-channel AD phase calibration, and the sensor signal is selected during actual application. Generally, before the product is launched, phase calibration is performed first, and then the actual sensor signal is selected.

[0067] DMUX is a data distributor. It has one input terminal and multiple output terminals. Its logical function is to send the signal of one input terminal to one of multiple output terminals.

[0068] The AD acquisition card is arranged on the FPGA board, and includes a plurality of AD chips, which are connected to the FPGA board through an IO interface for outputting raw signal data. Among them, the plurality of AD chips can be chips of the same model or chips of different models. In this embodiment, two AD7606 chips are selected for example.

[0069] In the embodiment of the present application, the AD acquisition card is composed of multiple AD chips and AD board types. The AD board type is for different AD chips, and the AD acquisition card needs to be identified, which is equivalent to an ID number;

[0070] Among them, the AD board type is implemented using 4 IO PINs, and different AD chips have different phase calibration reference parameters.

[0071] AD board types are shown in the following table:

[0072]

[0073] The FPGA board is used to calibrate and synchronize the raw signal data according to the calibration signal.

[0074] Figure 3 This is a schematic diagram of the structure of the FPGA board provided in one embodiment of the present application. Figure 3The FPGA board includes at least two processing units, a calibration switching control circuit, and a multi-channel signal simulation circuit. In this embodiment, only two processing units and their data processing principles are illustrated. The following is a brief description of the A-channel and B-channel processing units as examples:

[0075] The single-channel processing unit includes an AD acquisition module, a second data distributor, a second secondary data distributor, a RAM controller, an FFT algorithm module, an AD data operation module, an AD data processing module, a FIFO module, an AD packet module, a DDR controller, and an RGMII controller. The two-channel processing units share the same AD packet module, the same DDR controller, and the same RGMII controller.

[0076] In one embodiment, the FPGA board may further include a master controller, which may be a microprocessor, which is disposed on the FPGA board via an IO interface. The microprocessor is used to execute the logic functions of modules such as an AD acquisition module, an FFT algorithm module, an AD data operation module, an AD data processing module, a FIFO module, and an AD packaging module.

[0077] In other embodiments, the FPGA board may also include multiple analog circuits, and the implementation of modules such as the AD acquisition module, FFT algorithm module, AD data calculation module, AD data processing module, FIFO module, and AD packet module may be completed by the internal analog circuit of the FPGA board.

[0078] The AD acquisition module is connected to the AD acquisition card and is used to write a driver for the AD chip to enable it to perform data sampling at a rate of 50 Kbps, and to receive the original signal data collected by the AD chip and send it to the second data distributor for processing.

[0079] The second data distributor is used to output a single original signal data into two original signal data. For example, DMUXA outputs the original signal data A into two original signal data A1 and A2, and DMUXB outputs the original signal data B into two original signal data B1 and B2.

[0080] The input end of the second secondary data distributor is electrically connected to the second data distributor, the first output end of the second secondary data distributor is electrically connected to the RAM controller, and the second output end of the second secondary data distributor is connected to the FFT algorithm module. The second secondary data distributor is used to output a single original signal data into two original signal data. For example, DMUX1 outputs the original signal data A1 as two paths of original signal data AD1 at the same time, and DMUX2 outputs the original signal data B1 as two paths of original signal data AD1 at the same time.

[0081] The RAM controller is connected to the second secondary data distributor and the AD data operation module, and is used to write the data output by the second secondary data distributor into the corresponding external RAM chip, and convert the AD clock domain of the signal into the 100MHz clock domain inside the FPGA.

[0082] Figure 4 This is a functional block diagram of amplitude calibration provided by an embodiment of the present application. Figure 4 The calibration switching control circuit is used to control the phase calibration signal source to output the calibration signal, and the signal simulation circuit is used to transform the analog signal output by the signal source into a plurality of change data. The AD acquisition card is also used to transform the plurality of change data into a plurality of original signal data.

[0083] Among them, the signal simulation circuit includes an impedance conversion circuit, a signal conditioning and filtering circuit, the impedance conversion circuit is electrically connected to the signal source, the signal conditioning and filtering circuit, and the signal conditioning and filtering circuit is electrically connected to the AD chip.

[0084] The impedance conversion circuit is used to change the input impedance of the signal entering the circuit into a high impedance state, and the signal conditioning and filtering circuit is used to adjust the signal amplitude and noise entering the circuit. Specifically, the impedance conversion circuit changes the signal input impedance into a high impedance state, reducing the impact on the signal source and improving the acquisition accuracy; the signal conditioning and filtering circuit amplifies or attenuates the amplitude of the collected signal to within the ADC's acquisition range to improve the acquisition dynamic range, and attenuates the signal out-of-band noise to improve the signal-to-noise ratio.

[0085] The calibration switching control circuit includes a plurality of switches connected in parallel, one end of the switch is connected to the phase calibration signal source, and the other end of the switch is electrically connected to the impedance conversion circuit. In this embodiment, the switch can be a MOS tube or a triode, and the FPGA board controls the calibration switching control circuit to be closed / opened by outputting a high / low voltage signal.

[0086] The multi-channel analog signal inputs are all the same source signal Asin(ωt+φ0). After passing through each signal simulation circuit, the signals are respectively transformed into A1sin(ωt+φ1), A2sin(ωt+φ2)…Ansin(ωt+φn). That is, after the multi-channel analog signals enter the signal simulation circuit respectively, different amplitude and phase deviations appear. The present application calibrates the original signal data output by the AD chip according to the amplitude and phase deviations to achieve AD chip synchronization.

[0087] The FFT algorithm module is used to output the calibration coefficient according to the original signal data and the calibration signal. For example, in the A-channel processing unit, the FFT algorithm module is used to receive the original signal data AD1, process the original signal data AD1 and the calibration signal accordingly, and obtain the calibration coefficient K1; similarly, the calibration coefficient K2 of the B-channel processing unit is obtained.

[0088] Specifically, the present application uses an FPGA board for calibration: the FPGA controls the calibration switching control circuit to be closed so that the phase calibration signal source outputs a calibration signal, and uses the FFT algorithm module to perform FFT transformation on the multiple original signal data obtained respectively to obtain the amplitudes A1, A2...An of the multiple original signal data at the calibration signal source frequency. The obtained amplitude is divided by the source amplitude of the calibration signal to obtain the calibration coefficients K1, K2...Kn of each signal, and the calculation formula is: Kn=An / A.

[0089] The AD data operation module is connected to the RAM controller and the FFT algorithm module, and is used to use the 100MHz clock inside the FPGA board to read the original signal data AD1 from the RAM chip, and to assign the calibration coefficient K to the corresponding original signal data AD1 to obtain the amplitude calibration data AD1*K1 of the A-channel processing unit. Similarly, the amplitude calibration data AD1*K2 of the B-channel processing unit can be obtained.

[0090] The AD data processing module is connected to the AD data operation module and is used to obtain the phase compensation parameter according to the amplitude calibration data. Optionally, the AD data processing module is also used to obtain the maximum value sequence number in the amplitude calibration data of multiple AD channels, and to determine the difference between the maximum value sequence number of other channels and the first channel as the phase compensation parameter.

[0091] Exemplarily, in the sequence of amplitude calibration data AD1*K1, the maximum value of the data is found, and the serial number corresponding to the maximum value is marked; for example, for the A-channel processing unit, starting from the first data AD1*K1, the maximum value in AD1*K1 ~AD100*K1 is found, and when the serial number cnt=5, the maximum value is AD5*K1; similarly, the corresponding maximum value serial number in the B-channel processing unit is cnt=7. In this way, it can be seen that the synchronization phase of the A-channel data and the B-channel data differs by two, so the A-channel data is delayed by 2 phases, A-channel_AD_delay2, so that the A-channel_AD_delay2 is aligned with the B-channel data phase. In other words, the A-channel data is delayed by 2 phase cycles, and the phase compensation parameters of the A-channel data are written into the external ROM chip. When the system is actually used, the A-channel phase compensation parameters, that is, 2 phases, are read from the external ROM chip when it is powered on, and the A-channel data can be aligned with the B-channel data; similarly, the B-channel data does not need to be aligned, and the B-channel phase compensation parameters, that is, 0 phases, are read.

[0092] Figure 5a is a schematic diagram of a sequence of original signal data provided by an embodiment of the present application, Figure 5b is a schematic diagram of a sequence of amplitude calibration data provided by an embodiment of the present application, Figure 5c This is a schematic diagram of a sequence of synchronization data provided by an embodiment of the present application. Please also refer to Figure 5a , Figure 5b , Figure 5c , here is a data example for phase calibration:

[0093] like Figure 5a As shown, it is the original signal data output by multiple AD chips, each channel data sequence represents an AD chip, and this embodiment includes n AD chips, where n is greater than or equal to 2.

[0094] like Figure 5b As shown in the figure, it is the amplitude calibration data obtained after assigning the calibration coefficient K to the corresponding original signal data, and marks the data maximum value in the sequence of the amplitude calibration data AD1*K1 (as shown in the dotted box). The marked sequence is shown in the figure. The maximum values ​​in the channel 1 data sequence to the channel n data sequence are: K1*DATAn, K2*DATA(n-1)...Kn*DATA(n+1), and their maximum value marked sequence numbers are M1=n, M2=n-1...Mn=n+1 respectively; the difference calculation is performed based on this marked sequence number, and the maximum value mark M1=n in channel 1 is taken as the benchmark, and the remaining channel sequence number data are compared and the difference is calculated (such as the channel 2 maximum value sequence number difference is M1-M2= m2=1), and the sequence number difference set is obtained, that is, the above-mentioned phase compensation parameters {m2, m3...mn}.

[0095] like Figure 5c As shown, it is a reordered and aligned data sequence. The data sequences from channel 1 to channel n are reordered and aligned using the above-mentioned phase compensation parameters {m2, m3…mn} (for example, data K1*DATAn, K2*DATA(n-1)…Kn*DATA(n+1) are already under the same sequence number). The aligned data sequence can be output as synchronous data.

[0096] The calibration parameters and phase compensation parameters of each signal are saved in the FPGA non-volatile storage unit, and the calibration values ​​and phase compensation parameters are used for data processing during the normal signal acquisition process to achieve the purpose of high-precision synchronous acquisition of amplitude and phase.

[0097] The FIFO module is connected to the second data distributor, and is used for receiving the original signal data A2 and the original signal data B2, and converting the AD clock domain of the original signal data into the 100 MHz clock domain inside the FPGA.

[0098] The AD packetization module is used to reorder and align multiple amplitude calibration data according to phase compensation parameters to obtain multiple synchronous data, and process the synchronous data into packet data and output it. Specifically, the AD packetization module reorders and aligns the amplitude calibration data AD1*K1 of the A-way processing unit and the amplitude calibration data AD1*K2 of the B-way processing unit according to the phase compensation parameters stored in the external ROM chip, so that the synchronous data of the A-way processing unit and the B-way processing unit can be obtained; after the data is aligned, the AD packetization module merges the synchronous data of the A-way processing unit and the B-way processing unit into packet data, for example, merging the A-way synchronous data and the B-way synchronous data into packet data C={A, B}, where the A-way and B-way synchronous data are single-byte, and the packet data C is double-byte.

[0099] The DDR controller is connected to the AD packet module to receive packet data and store it in an external DDR chip. When the external DDR chip stores enough data for one frame (equivalent to 1s of data), the DDR controller reads the packet data in the DDR chip and sends it to the RGMII controller.

[0100] The RGMII controller is electrically connected to the DDR controller, and is used to send packet data to an external communication chip, namely an Ethernet PHY chip (the Ethernet PHY chip is set on the FPGA board and connected through the IO interface) using the Ethernet interface RGMII interface, and then send it to the lower-level processor using the Ethernet PHY chip.

[0101] In the system of this embodiment, the ARM processor is electrically connected to the FPGA board and the display, and is used to unpack the packet data output by the AD packet module into multiple synchronous data, and output the synchronous data to the display for display. Specifically, the ARM processor receives the packet data C sent by the Ethernet chip, and then unpacks the packet data C into A-way synchronous data and B-way synchronous data through the RGMII driver, and then performs algorithm processing on the A-way synchronous data and the B-way synchronous data respectively, and processes them into display data A and display data B, and finally displays the display data A and display data B on the display.

[0102] Figure 6 This is a schematic diagram of synchronous acquisition between different types of ADs provided in an embodiment of the present application. Figure 6 The schematic diagram of realizing synchronous acquisition of different types of AD based on FPGA is shown in the figure. Examples of different types of AD include AD7606, AD7768, and ADS1274.

[0103] AD data acquisition mainly relies on FPGA and AD IO pins for data acquisition. The IO pins related to AD synchronous acquisition are: reset pin (RESET), AD analog-to-digital conversion start pin (CONVST A / B), and AD analog-to-digital conversion completion pin (BUSY).

[0104] The FPGA board also includes a crystal oscillator, which is used to provide the FPGA input clock source. The FPGA board is also used to perform timing synchronization based on the crystal oscillator to control the reset pin, the AD analog-to-digital conversion start pin, and the AD analog-to-digital conversion end pin.

[0105] The following is an example of its synchronization scheme:

[0106] First, source clock synchronization: The FPGA board uses the same crystal oscillator clock to drive multiple different AD chip IO pins (reset pin, AD analog-to-digital conversion start pin, AD analog-to-digital conversion end pin, etc.). Multiple AD chip IO control pins all use the same clock for timing control, which means that the control pin timing of multiple AD chips is synchronized, achieving the first level of synchronization.

[0107] Second, source reset synchronization: After the FPGA board is powered on, it outputs a reset signal. Multiple AD chips receive the reset signal through the reset pin. The reset signal is used to control multiple AD chips to work simultaneously, achieving the second level of synchronization.

[0108] Third, digital-to-analog conversion start synchronization: The FPGA board generates an analog-to-digital conversion start signal according to the user's sampling rate requirements. Multiple AD chips receive the analog-to-digital conversion start signal through the analog-to-digital conversion start signal pin, and use the analog-to-digital conversion start signal to simultaneously control multiple AD chips to start digital-to-analog conversion at the same time, achieving the third level of synchronization.

[0109] Fourth, digital-to-analog conversion time synchronization: Due to differences in AD conversion time, according to the AD analog-to-digital conversion time difference, delay control of multiple AD analog-to-digital conversion start signals is used here to achieve precise synchronization between boards.

[0110] The FPGA-based AD synchronous acquisition solution for different models mainly includes source clock synchronization, source reset synchronization, conversion start synchronization and conversion time synchronization. Through the four-level synchronization strategy, the synchronization accuracy of three different types of AD chips can be achieved within 100ns.

[0111] The solution of this application is a multi-channel real-time, high-speed, and high-precision synchronous data acquisition system with FPGA as the main processor. The sampling frequency range of this solution in the actual monitoring project is 1-200 kHz. FPGA is used to reasonably control and coordinate the transmission of data streams between various modules, thereby realizing the real-time, synchronous, and high-speed acquisition functions required by the system, and can solve the problem of real-time high-speed data acquisition and precise synchronization between multi-channel AD boards.

[0112] The solution of this application has the following advantages:

[0113] (1) The solution of implementing multi-channel AD synchronous acquisition based on FPGA board will not produce phase error. For example, in the field of power measurement, power measurement usually requires the simultaneous acquisition of voltage and current data. If there is a phase error, it will cause errors in power calculation. Therefore, synchronous acquisition is required.

[0114] (2) Multi-channel AD synchronous acquisition is realized based on FPGA board, which has good real-time performance and can meet both synchronous acquisition and real-time acquisition requirements.

[0115] (3) FPGA is widely used in data acquisition and processing scenarios due to its high speed and parallel processing characteristics. For the synchronous acquisition and processing of multiple signals, it is necessary to ensure the amplitude and phase accuracy of the acquired signals before subsequent data processing and analysis can be performed. Signal acquisition requires a series of impedance transformation, filtering, and A / D conversion. Since the circuit parameters of multiple signals cannot be highly consistent, the signal conditioning and conversion process will produce certain amplitude and phase deviations. This patent proposes to use FPGA to achieve amplitude calibration and phase compensation, which can calibrate the amplitude and compensate the phase of different channels to achieve the purpose of high-precision phase synchronization and provide an accurate data source for subsequent data processing and analysis.

[0116] Obviously, those skilled in the art can make various changes and modifications to the utility model without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these changes and variations. The technical features of the above-described embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions or improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A system for realizing multi-channel AD amplitude calibration and phase compensation, characterized in that: include: Signal source for outputting calibration signal, AD acquisition card for outputting raw signal data, An FPGA board for calibrating the raw signal data according to the calibration signal; The signal source is electrically connected to the AD acquisition card and the FPGA board; The AD acquisition card is arranged on the FPGA board, and includes a plurality of AD chips, and the AD chips are connected to the FPGA board via an IO interface; The FPGA board is used to calibrate and synchronize the original signal data according to the calibration signal; Wherein, the FPGA board includes at least two processing units, and the processing units include a second data distributor, an FFT algorithm module, an AD data operation module, an AD data processing module, and an AD packaging module; The second data distributor is used for outputting the original signal data into a plurality of the original signal data; The FFT algorithm module is used to output a calibration coefficient according to the original signal data and the calibration signal; The AD data operation module is used to assign the calibration coefficient to the original signal data of the corresponding AD channel to obtain amplitude calibration data; The AD data processing module is used to obtain phase compensation parameters according to the amplitude calibration data; The AD packaging module is used to reorder and align the multiple amplitude calibration data according to the phase compensation parameters to obtain multiple synchronous data, and process the synchronous data into packet data and output it.

2. The system according to claim 1, characterized in that The signal source includes a phase calibration signal source, a first data distributor, a plurality of sensors, and a plurality of data selectors; The phase calibration signal source is electrically connected to the first data distributor, and the sensor is electrically connected to the corresponding data selector; The phase calibration signal source is used to output a calibration signal; The first data distributor is used for outputting the calibration signal into a plurality of calibration signals; The sensor is used to collect a voltage analog signal and output the voltage analog signal to the corresponding data selector; The data selector is used to select and output any one of the calibration signal and the voltage analog signal to the AD acquisition card.

3. The system according to claim 2, characterized in that The FPGA board further comprises a calibration switching control circuit and a multi-channel signal simulation circuit, wherein the calibration switching control circuit is used to control the phase calibration signal source to be connected to the signal simulation circuit; The signal simulation circuit is used to transform the analog signal output by the signal source into a plurality of change data; The AD acquisition card is also used to convert the plurality of change data into a plurality of original signal data; The FFT algorithm module is also used to obtain the calibration coefficient according to the calibration signal and the original signal data.

4. The system according to claim 3, characterized in that The signal simulation circuit includes an impedance conversion circuit, a signal conditioning and filtering circuit; The impedance conversion circuit is electrically connected to the signal source and the signal conditioning and filtering circuit, and the signal conditioning and filtering circuit is electrically connected to the AD chip; The impedance conversion circuit is used to change the input impedance of the signal entering the circuit into a high impedance state; The signal conditioning and filtering circuit is used to adjust the amplitude and noise of the signal entering the circuit.

5. The system according to claim 4, characterized in that The calibration switching control circuit includes a plurality of switches connected in parallel; One end of the switch is connected to the phase calibration signal source, and the other end of the switch is electrically connected to the impedance conversion circuit.

6. The system according to claim 1, wherein: The FPGA board also includes a RAM controller; the RAM controller is electrically connected to the second data distributor and is used to convert the AD clock domain of the original signal data into the FPGA clock domain.

7. The system according to claim 6, characterized in that The processing unit also includes a second secondary data distributor, an input end of the second secondary data distributor is electrically connected to the second data distributor, a first output end of the second secondary data distributor is electrically connected to the RAM controller, and a second output end of the second secondary data distributor is connected to the FFT algorithm module.

8. The system of claim 1, wherein: The FPGA board also includes a DDR controller and an RGMII controller, and the DDR controller is electrically connected to the RGMII controller; The DDR controller is used to store the packet data in an external DDR chip and output the packet data to the RGMII controller; The RGMII controller includes an RGMII interface, and the RGMII interface is used to output the packet data to an external communication chip.

9. The system according to claim 8, characterized in that The system also includes an ARM processor and a display; the ARM processor is electrically connected to the FPGA board and the display, and is used to unpack the packet data output by the FPGA board into multiple synchronous data, and output the synchronous data to the display for display.

10. The system according to claim 1, wherein: The AD chip includes a reset pin, an AD analog-to-digital conversion start pin, and an AD analog-to-digital conversion end pin, and the FPGA board also includes a crystal oscillator; The crystal oscillator is used to provide an FPGA input clock source, and the FPGA board is also used to control the reset pin, the AD analog-to-digital conversion start pin, and the AD analog-to-digital conversion end pin for timing synchronization according to the crystal oscillator.

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