PLC communication module aging test equipment

Abstract

The utility model discloses an aging test device for a PLC communication module, which comprises a touch screen, an FPGA chip, a first detection unit, a second detection unit, a power supply module and a plurality of groups of test channels, and the test channels comprise a first detection channel, a second detection channel,..., and an nth detection channel. Each detection channel comprises a first low-pass filter, a tested module, an attenuator, a test module and a second low-pass filter which are electrically connected in sequence, the tested modules are electrically connected with the first detection unit and the FPGA chip respectively, the test modules are electrically connected with the second detection unit and the FPGA chip respectively, the FPGA chip is electrically connected with the touch screen, and the touch screen is electrically connected with the attenuator. The power supply module is electrically connected with the touch screen, the FPGA chip, the first low-pass filter, the tested module, the testing module and the second low-pass filter, the tested module is a module needing aging testing, and the testing module is a standard module used for being compared with the tested module.

Description

Technical Field

[0001] The utility model belongs to the technical field of centralized meter reading equipment for low-voltage power users, and in particular relates to an aging test device for a PLC communication module. Background Art

[0002] In low-voltage power line carrier communication, the carrier communication function has been solidified into the carrier module. During the production process of the module, the enterprise needs to perform aging test on the module to ensure product quality. The development of module aging equipment in production has become an indispensable link.

[0003] The current aging equipment can build a test environment for a single module and perform periodic testing according to the set working time. However, if there are a large number of modules, the timeliness cannot be guaranteed. There are two main reasons: 1) This is because multiple groups of modules need to reuse the same power line when communicating; 2) Multiple groups of RS232 serial ports need to be aggregated and reused before communicating with the PC software. Therefore, in the current aging, a polling method is used to perform aging tests on multiple groups of modules, which will inevitably reduce the aging intensity and fail to screen out some modules with hidden problems. Therefore, it is necessary to develop a new type of aging test equipment. Utility Model Content

[0004] The utility model aims to solve the problems of the prior art and provides a PLC communication module aging test device.

[0005] In order to solve the technical problem, the technical solution of the utility model is: a PLC communication module aging test device, including a touch screen, an FPGA chip, a first detection unit, a second detection unit, a power module and several groups of test channels, the test channels include a first detection channel, a second detection channel, ..., an nth detection channel, the first detection channel, the second detection channel, ..., the nth detection channel all include a first low-pass filter, a module under test, an attenuator, a test module and a second low-pass filter electrically connected in sequence, a plurality of the modules under test are respectively electrically connected to the first detection unit and the FPGA chip, a plurality of the test modules are respectively electrically connected to the second detection unit and the FPGA chip, the FPGA chip is electrically connected to the touch screen, the power module is respectively electrically connected to the touch screen, the FPGA chip, the first low-pass filter, the module under test, the test module and the second low-pass filter, the module under test is a module that needs to be subjected to an aging test, and the test module is a standard module for comparison with the module under test.

[0006] Preferably, the range of n in the nth detection channel is 1-10.

[0007] Preferably, the touch screen is connected to the FPGA chip via an RS232 interface, and the touch screen sends commands and test data to corresponding registers inside the FPGA chip via the RS232 interface.

[0008] Preferably, the FPGA chip includes a test serial port transceiver and a communication serial port transceiver, the test serial port transceiver includes a test serial port Dx and a tested serial port Tx, the range of x is 1 to 10, the test serial port Dx is electrically connected to the corresponding test module, the tested serial port Tx is electrically connected to the corresponding tested module, and the communication serial port transceiver is electrically connected to the RS232 interface of the touch screen.

[0009] Preferably, the first low-pass filter and the second low-pass filter are both third-order π-type LC filters, with a cut-off frequency of 20 KHz and an input impedance of 50Ω.

[0010] Preferably, the attenuator is a π-type fixed amplitude attenuator with an attenuation value of 50dB; the first detection unit and the second detection unit both include a 74LVC4245A chip, the first detection unit is respectively connected to multiple tested serial ports Tx and tested modules, and the second detection unit is respectively connected to multiple test serial ports Dx and test modules.

[0011] Preferably, the power supply module includes AC220V, VHH, 5V and 3.3V voltages, AC220V is electrically connected to the first low-pass filter and the second low-pass filter of each test channel respectively, VHH is electrically connected to the VHH pins of the tested module and the test module respectively, VHH is 18-24V, 5V is electrically connected to the VCC pins of the tested module and the test module respectively, and 3.3V is electrically connected to the touch screen and the FPGA chip respectively.

[0012] Preferably, the PLC communication module aging test equipment also includes an upper cover, a circuit board, an O-ring and a shell, the touch screen is embedded in the upper cover, the upper cover and the shell are sealed and connected by an O-ring, the circuit board is installed in a sealed space formed by the upper cover and the shell, the FPGA chip, the first detection unit, the second detection unit, the power supply module and several groups of test channels' first low-pass filters, attenuators and second low-pass filters are installed on the PCB board of the circuit board, and several groups of the tested modules and test modules are installed on the upper cover.

[0013] Preferably, the upper cover is provided with a plurality of locking seats, and a plurality of tested modules and testing modules are respectively locked and installed on the upper cover through the plurality of locking seats.

[0014] Compared with the prior art, the advantages of the utility model are:

[0015] (1) The utility model provides a PLC communication module aging test device, including a touch screen, an FPGA chip, a first detection unit, a second detection unit, a power module and a plurality of test channels. The tested modules of each test channel are respectively connected to the first detection unit and the FPGA chip, the test modules of each test channel are respectively connected to the second detection unit and the FPGA chip, and the FPGA chip is connected to the touch screen. The operator only needs to set the aging test cycle duration and the test duration through the touch screen interface to start the aging test project. After the test is completed, a sound alarm is reported to prompt the user that the test is completed;

[0016] (2) The utility model uses a first low-pass filter and a second low-pass filter to isolate 10 test channels for the test module and the module under test. Each test channel independently transmits and receives data without causing interference. The communication rate, duration, and state (start, pause, stop) of each test channel can be set separately, thereby improving the test efficiency. 10 groups of tests can be performed simultaneously, ensuring the timeliness of the test.

[0017] (3) After the test module and the tested module are plugged in, the first detection unit and the second detection unit of the utility model will check their status to see if the device is powered on normally, and report the inspection results to the touch screen. The tester can find the fault in the first place, thus improving the efficiency of fault module detection;

[0018] (4) The test channel of the utility model includes a first low-pass filter, a module under test, an attenuator, a test module and a second low-pass filter. The module under test and the test module are respectively connected to the low-pass filters. The low-pass filters are connected to AC220V, and the power carrier is 50HZ, which effectively avoids interference between test channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 , a structural block diagram of a PLC communication module aging test device of the utility model;

[0020] Figure 2 , schematic diagram of the principle of the FPGA chip of the utility model;

[0021] Figure 3 , a schematic diagram of the structure of a PLC communication module aging test device of the utility model;

[0022] Figure 4 , the circuit principle diagram of the low-pass filter of the utility model.

[0023] Description of reference numerals:

[0024] 1. Touch screen, 2. FPGA chip, 3. First detection unit, 4. Second detection unit, 5. Power module, 6. Test channel, 7. First low-pass filter, 8. Module under test, 9. Attenuator, 10. Test module, 11. Second low-pass filter, 12. Upper cover, 13. Circuit board, 14. O-ring, 15. Housing;

[0025] 6-1, first detection channel, 6-2, second detection channel, 6-n, nth detection channel;

[0026] 12-1. Locking seat. DETAILED DESCRIPTION

[0027] The following describes the specific implementation of the utility model in conjunction with embodiments:

[0028] It should be noted that the structures, proportions, sizes, etc. shown in this specification are only used to match the contents disclosed in the specification so that people familiar with this technology can understand and read them, and are not used to limit the conditions under which the present invention can be implemented. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0029] Example 1

[0030] like Figure 1 As shown, the utility model discloses a PLC communication module aging test device, including a touch screen 1, an FPGA chip 2, a first detection unit 3, a second detection unit 4, a power module 5 and a plurality of test channels 6, the test channel 6 includes a first detection channel 6-1, a second detection channel 6-2, ..., an nth detection channel 6-n, the first detection channel 6-1, the second detection channel 6-2, ..., the nth detection channel 6-n all include a first low-pass filter 7, a module under test 8, an attenuator 9, a test module 10 and a second low-pass filter 11 electrically connected in sequence, a plurality of the modules under test 8 are electrically connected to the first detection unit 3 and the FPGA chip 2, respectively, a plurality of the test modules 10 are electrically connected to the second detection unit 4 and the FPGA chip 2, the FPGA chip 2 is electrically connected to the touch screen 1, the power module 5 is electrically connected to the touch screen 1, the FPGA chip 2, the first low-pass filter 7, the module under test 8, the test module 10 and the second low-pass filter 11, respectively, the module under test 8 is a module that needs to be subjected to an aging test, and the test module 10 is a standard module for comparison with the module under test 8.

[0031] Example 2

[0032] Preferably, the range of n in the nth detection channel is 1-10.

[0033] like Figure 1 As shown, preferably, the touch screen 1 is connected to the FPGA chip 2 via an RS232 interface, and the touch screen 1 sends commands and test data to corresponding registers inside the FPGA chip 2 via the RS232 interface.

[0034] like Figure 1 , 2 As shown, preferably, the FPGA chip 2 includes a test serial port transceiver and a communication serial port transceiver, the test serial port transceiver includes a test serial port Dx and a tested serial port Tx, the range of x is 1 to 10, the test serial port Dx is electrically connected to the corresponding test module 10, the tested serial port Tx is electrically connected to the corresponding tested module 8, and the communication serial port transceiver is electrically connected to the RS232 interface of the touch screen 1.

[0035] The FPGA chip 2 adopts the new Altera (Intel) IV series FPGA device EP4CE22E22C8N, it has the following main functions and features:

[0036] Logic resources: The EP4CE22E22C8N has a high logic density, providing 22,320 logic elements (LEs), which can be used to implement a variety of complex logic functions and algorithms.

[0037] Storage resources: EP4CE22E22C8N provides 594Kbits of embedded memory (M9K memory block), which can be used to implement storage functions such as data cache, FIFO, RAM, ROM, etc.

[0038] I / O resources: EP4CE22E22C8N provides 154 programmable I / O pins and supports multiple I / O standards, such as LVTTL, LVCMOS, PCI, etc. These pins can be used for communication and data transmission with external devices and systems.

[0039] PLLs (Phase Locked Loops): EP4CE22E22C8N has 4 PLLs that can be used to implement high-performance clock management and frequency synthesis functions.

[0040] Support hardware-accelerated configuration and remote upgrade: EP4CE22E22C8N supports hardware-accelerated configuration and remote upgrade functions, and can be configured and upgraded through JTAG, AS (Active Serial) or PS (Passive Serial) interface.

[0041] Low power consumption: Cyclone IV E series FPGAs have excellent low power consumption characteristics and can meet the needs of various low power applications.

[0042] EP4CE22E22C8N Development Environment

[0043] EP4CE22E22C8N is developed using Quartus II software. Quartus II is a comprehensive CPLD / FPGA development software launched by Altera. The software supports multiple design input forms such as schematics, VHDL, VerilogHDL and AHDL (Altera Hardware Support Description Language), and has its own built-in synthesizer and simulator, which can complete the complete PLD design process from design input to hardware configuration.

[0044] FPGA configuration memory chip

[0045] The FPGA configuration memory core uses W9825G6KH-6I, which is a high-speed synchronous dynamic random access memory (SDRAM) with an organizational structure of 4M words × 4 banks × 16 bits. Speed ​​grade: -6I; components meet the 166MHz / CL3 specification (-6I industrial grade is guaranteed to support -40℃≤TA≤85℃, and -6J industrial grade is guaranteed to support -40℃≤TA≤105℃).

[0046] The power supply is 3.3V;

[0047] Interface: LVTTL;

[0048] Self-refresh modes: standard and low power;

[0049] Refresh cycle / 16mS;

[0050] Available in TSOP II 54-pin package.

[0051] Example 3

[0052] Preferably, the first low-pass filter 7 and the second low-pass filter 11 are both third-order π-type LC filters, with a cut-off frequency of 20 KHz and an input impedance of 50Ω.

[0053] The groups of first low-pass filters 7 and second low-pass filters 11 adopt third-order π-type LC filters with a cut-off frequency of 20 KHz and an input impedance of 50Ω.

[0054] like Figure 4 As shown, C1, C2 are capacitance: 160nF; polypropylene film capacitor (CBB); rated voltage: 400V plug-in type

[0055] L1 line number: 2; withstand voltage: 250V@AC; rated current: 3.5A; inductance: 800uH.

[0056] The main purpose of the filter is to prevent the carrier signal at the input of the attenuator from leaking to the output, so as not to affect the output.

[0057] Preferably, the attenuator 9 is a π-type fixed amplitude attenuator with an attenuation value of 50 dB; the first detection unit 3 and the second detection unit 4 both include a 74LVC4245A chip, the first detection unit 3 is respectively connected to multiple tested serial ports Tx and tested modules 8, and the second detection unit 4 is respectively connected to multiple test serial ports Dx and test modules 10.

[0058] The attenuator 9 is a π-type fixed amplitude attenuator with an attenuation value of 50 dB. The specific parameters are: R1, R2 resistance values ​​are 50Ω; R3 is 8KΩ.

[0059] Main functions of the detection module:

[0060] Check whether the module is online and the indication. If the indicator light (green) next to the module locking seat is not on, the module loading is unsuccessful; if the indicator light (green) is on, it means that the module is online; if the indicator light (green) flashes (0.5 on, 9.5 seconds on), the module is being tested. At the same time, on the touch screen,

[0061] Level adaptation: The product uses the 74LVC4245A chip to convert between 3.3V and 5V levels. The Tx pin and RX pin of each test serial port are connected to two 74LVC4245A chips with different configurations to achieve level conversion in two transmission directions. For example: / OE, DIR is: low, low level, 3.3V to 5V level conversion is achieved; / OE, DIR is: low, high level, 5V to 3.3V level conversion is achieved.

[0062] Example 4

[0063] Preferably, the power supply module 5 includes AC220V, VHH, 5V and 3.3V voltages, AC220V is electrically connected to the first low-pass filter 7 and the second low-pass filter 11 of each test channel 6, VHH is electrically connected to the VHH pins of the tested module 8 and the test module 10, VHH is 18-24V, 5V is electrically connected to the VCC pins of the tested module 8 and the test module 10, and 3.3V is electrically connected to the touch screen 1 and the FPGA chip 2.

[0064] The power module 5 is powered by 220V internally, and the AC power is converted to 24V (VHH signal) by the LM200-22B24R2 module of Jinshengyang. The power supply has three main uses. (1) The power supply is used as the VHH power supply for the test and tested modules; (2) The VHH power supply is converted to +5V power supply for the Vcc pin of the test and tested modules by the XL1509-ADJE1 chip; (3) VHH is converted to 3.3V voltage by the LM317 chip for use by the touch screen and FPGA chip 2.

[0065] According to the system design, LM200-22B24R2 is a 200W power module that can support 10 channels and 20 modules working at the same time.

[0066] The VHH to 5V conversion uses XL1509-5.0. XL1509-5.0 is a high-efficiency step-down voltage regulator chip that can achieve step-down conversion with an input voltage range of 4.5V to 40V. It can output a constant voltage of 5V and a maximum output current of 3A. The chip uses a built-in N-channel MOSFET switch tube with a conversion efficiency of up to 96%, which can provide reliable power stability for various electronic devices. In addition, XL1509-5.0E1 also has a variety of protection functions, such as input undervoltage protection, overtemperature protection and short-circuit protection, which can effectively ensure the stable operation of the equipment.

[0067] The performance indicators are as follows:

[0068] Input voltage range: 4.5V-40V;

[0069] Output voltage range: 5.0V;

[0070] Output current: 3A;

[0071] Quiescent current: ≤5mA;

[0072] Switching frequency: 150kHz;

[0073] Efficiency: Up to 96%;

[0074] Working temperature range: -40℃-85℃;

[0075] Package type: SOP8.

[0076] The 24V to 3.3V circuit uses the LM317 chip, which is an integrated three-terminal voltage regulator with variable output voltage. The output voltage of the voltage regulator can be calculated using the following formula: Vo = 1.25 (1 + R2 / R1). Just from the formula itself, the resistance values ​​of R1 and R2 can be set at will. The 317 voltage regulator has a minimum stable operating current, which is generally 1.5mA. To ensure that the output current is at least 1.5mA, 1.25 / 1.5*1000 gives the maximum value of R1 as R1≈0.83KΩ. After calculation, we can get the R2 value of 1.5KΩ.

[0077] Example 5

[0078] like Figure 3 As shown, preferably, the PLC communication module aging test equipment also includes an upper cover 12, a circuit board 13, an O-ring 14 and a shell 15, the touch screen 1 is embedded in the upper cover 12, the upper cover 12 and the shell 15 are sealed and connected by the O-ring 14, the circuit board 13 is installed in the sealed space formed by the upper cover 12 and the shell 15, the FPGA chip 2, the first detection unit 3, the second detection unit 4, the power supply module 5 and several groups of test channels 6 The first low-pass filter 7, the attenuator 9 and the second low-pass filter 11 are installed on the PCB board of the circuit board 13, and several groups of the tested modules 8 and the test modules 10 are installed on the upper cover 12.

[0079] Preferably, the upper cover 12 is provided with a plurality of locking seats 12 - 1 , and a plurality of tested modules 8 and testing modules 10 are respectively locked and installed on the upper cover 12 through the plurality of locking seats 12 - 1 .

[0080] The pin spacing of the locking seat 12-1PINDIP package test seat is 2.54MM.

[0081] The upper cover and the shell are made of ABS resin, which is easy to process, stable in size, and has excellent impact resistance, heat resistance, low temperature resistance, chemical resistance and electrical properties.

[0082] The O-shaped sealing ring is made of silicone rubber, which has excellent heat resistance, cold resistance, ozone resistance, and atmospheric aging resistance. It has good insulation performance and is non-toxic and pollution-free. It can reach IP65 protection level when combined with the upper cover and the shell.

[0083] The PCB board of the circuit board adopts a multi-layer circuit design to ensure uniform current distribution on the circuit board, good heat dissipation, prevent color blocks from appearing under low grayscale conditions, and enhance anti-electromagnetic interference capabilities.

[0084] Touch screen: adopts the serial port screen of DC64480EW056_1VX1_0X model from Dacai Technology. The core processor capacity of this serial port screen is 800MHz, 32-bit dual-core processor; the operating system is an embedded real-time operating system. Screen size, 5.6 inches; resolution 480*640 storage space: 1Gbit; color 65K colors, 16-bit RGB; communication mode is RS232 / TTL, and the typical baud rate is 115200bps.

[0085] Main functions of touch screen:

[0086] Set the test cycle, test times, and test duration of the test channel;

[0087] Status display of the tested module and the testing module (offline, online, testing, testing completed);

[0088] Display of test completion times and test status (normal test, abnormal test);

[0089] Test data editing;

[0090] Report and display test alarms and information;

[0091] Start, pause and stop the test channel;

[0092] 232 serial port and FPGA chip are used for communication, and the baud rate (9600, 14400, 38400, 115200bps) can be set.

[0093] The working principle of the utility model is as follows:

[0094] like Figures 1 to 4 As shown, the utility model discloses a PLC communication module aging test device, including a touch screen, an FPGA chip, a first detection unit, a second detection unit, a power module and several groups of test channels, the tested modules of each group of test channels are respectively connected to the first detection unit and the FPGA chip, the test modules of each group of test channels are respectively connected to the second detection unit and the FPGA chip, the FPGA chip is connected to the touch screen, the operator only needs to set the aging test cycle duration and the test duration through the touch screen interface, the touch screen can send commands and test data to the FPGA chip, the FPGA chip sends the corresponding test command to the corresponding test channel, performs aging test on the test module 10 of the test channel, and performs aging test items, the two low-pass filters of each group of test channels avoid interference between channels, improve the test accuracy, and after the test is completed, report a sound alarm to prompt the user that the test is completed.

[0095] The utility model adopts a first low-pass filter and a second low-pass filter to isolate 10 test channels for the test module and the module under test. Each test channel independently sends and receives data without causing interference. The communication rate, duration, and state (start, pause, stop) of each test channel can be set separately, which improves the test efficiency. 10 groups of tests can be carried out at the same time, ensuring the timeliness of the test.

[0096] The first detection unit and the second detection unit of the utility model will check the status of the test module and the tested module after they are plugged in to check whether the equipment is powered on normally, and report the inspection result to the touch screen, so that the test personnel can find the fault in the first time, thereby improving the efficiency of fault module detection.

[0097] The test channel of the utility model comprises a first low-pass filter, a module under test, an attenuator, a test module and a second low-pass filter. The module under test and the test module are respectively connected to the low-pass filters. The low-pass filters are connected to AC220V, and the power carrier is 50HZ, which effectively avoids interference between the test channels.

[0098] The utility model makes it more convenient to save and export the test data. The test data can be saved in the memory inside the device, and can also be exported to a PC or other memory through a serial port, which is convenient for customers to manage their data.

[0099] Scalability: The utility model adopts FPGA chip 2, which provides abundant programmable IO pins, and the device can be upgraded by upgrading the software and replacing the card holder panel.

[0100] The main technical parameters of this utility model:

[0101] 1. Maximum number of channels: 10 (one test module (T) and one tested module (D) constitute one channel);

[0102] 2. Test duration and test cycle settings;

[0103] 3. Display the status (online, offline) of the test module and the module under test;

[0104] 4. Test result presentation (sending data, receiving data) and data export;

[0105] 5. Sound alarm function (test completion alarm, test abnormality alarm)

[0106] 6. Working temperature: -20 to +65 °C

[0107] 7. Working power supply: AC220V

[0108] The workflow of this utility model is as follows:

[0109] 1. The device has 10 test channels, each of which is divided into a test module 10 and a tested module 8. Place the test module 10 and the tested module 8 in the locking seat 12-1 of the instrument in the correct direction, lock them, and power on the device.

[0110] 2. The status of each test channel test module 10 and the tested module 8 is displayed on the touch screen 1. When both are online, the data transmission cycle, test duration, and data transmission can be set on the touch screen 1 (if this item is not set, the system default value is used). Click the start button and the channel starts working.

[0111] 3. Touch screen 1 sends commands and test data to the corresponding registers inside FPGA chip 2 (EP4CE22E22C8N) through the RS232 interface.

[0112] 4. Two types of serial port transceivers are implemented inside FPGA chip 2: test serial port transceiver (test serial port Dx, test serial port Tx, x is the channel number) and communication serial port transceiver (communication serial port). The test serial port consists of a total of 10 channels. Each test channel is divided into test serial port Dx and test serial port Tx, x is the channel number, and there are a total of 20 UART serial ports. Serial port numbering: test serial port D1 and test serial port T1; test serial port D2 and test serial port T2; test serial port D3 and test serial port T3; test serial port D4 and test serial port T4; test serial port D5 and test serial port T5; test serial port D6 and test serial port T6; test serial port D7 and test serial port T7; test serial port D8 and test serial port T8; test serial port D9 and test serial port T9; test serial port D10 and test serial port T10; the communication serial port is the UART serial port that communicates with touch screen 1.

[0113] The test serial transceiver is equipped with:

[0114]

[0115]

[0116] Communication UART serial transceiver matching

[0117] Re_Temp_DataBuffer Send data register Trans_Temp_DataBuffer Receive data register

[0118] After receiving the data sent by touch screen 1, the receiving data register Re_Temp_DataBuffer configures the corresponding test serial port according to the serial port number, message type and data in the data.

[0119] The system has a cycle of 100ms, scans the test serial port sending counter, correctly receives the count in the receiving register, and fills the Trans_Temp_DataBuffer according to the protocol package to send data to the corresponding area of ​​the touch screen.

[0120] 5. The FPGA chip 2 sends commands and test data to the corresponding test channel. The test module 10 and the module under test 8 are respectively connected to low-pass filters. At the same time, an attenuator 9 is connected between the test module 10 and the module under test 8 to perform an aging test on the module under test 8.

[0121] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of ordinary technicians in this field without departing from the purpose of the present invention.

[0122] Many other changes and modifications can be made without departing from the concept and scope of the utility model. It should be understood that the utility model is not limited to a specific embodiment, and the scope of the utility model is defined by the appended claims.

Claims

1. A PLC communication module aging test device, characterized in that: The invention comprises a touch screen (1), an FPGA chip (2), a first detection unit (3), a second detection unit (4), a power supply module (5) and a plurality of groups of test channels (6), wherein the test channels (6) comprise a first detection channel (6-1), a second detection channel (6-2), ..., and an nth detection channel (6-n), and the first detection channel (6-1), the second detection channel (6-2), ..., and the nth detection channel (6-n) all comprise a first low-pass filter (7), a module under test (8), an attenuator (9), a test module (10) and a second low-pass filter (11) which are electrically connected in sequence, and a plurality of the modules under test are The modules (8) are respectively electrically connected to the first detection unit (3) and the FPGA chip (2); the plurality of test modules (10) are respectively electrically connected to the second detection unit (4) and the FPGA chip (2); the FPGA chip (2) is electrically connected to the touch screen (1); the power module (5) is respectively electrically connected to the touch screen (1), the FPGA chip (2), the first low-pass filter (7), the module under test (8), the test module (10) and the second low-pass filter (11); the module under test (8) is a module that needs to be subjected to an aging test; and the test module (10) is a standard module used for comparison with the module under test (8).

2. A PLC communication module aging test device according to claim 1, characterized in that: The range of n in the nth detection channel is 1-10.

3. A PLC communication module aging test device according to claim 1, characterized in that: The touch screen (1) is connected to the FPGA chip (2) via an RS232 interface, and the touch screen (1) sends commands and test data to corresponding registers inside the FPGA chip (2) via the RS232 interface.

4. A PLC communication module aging test device according to claim 3, characterized in that: The FPGA chip (2) comprises a test serial port transceiver and a communication serial port transceiver, the test serial port transceiver comprises a test serial port Dx and a tested serial port Tx, the range of x is 1-10, the test serial port Dx is electrically connected to the corresponding test module (10), the tested serial port Tx is electrically connected to the corresponding tested module (8), and the communication serial port transceiver is electrically connected to the RS232 interface of the touch screen (1).

5. The PLC communication module aging test equipment according to claim 1, characterized in that: The first low-pass filter (7) and the second low-pass filter (11) are both third-order π-type LC filters, with a cut-off frequency of 20 kHz and an input impedance of 50 .

6. A PLC communication module aging test device according to claim 4, characterized in that: The attenuator (9) is a π-type fixed amplitude attenuator with an attenuation value of 50 dB; the first detection unit (3) and the second detection unit (4) both comprise a 74LVC4245A chip; the first detection unit (3) is respectively connected to a plurality of tested serial ports Tx and a tested module (8); and the second detection unit (4) is respectively connected to a plurality of test serial ports Dx and a test module (10).

7. The PLC communication module aging test equipment according to claim 1, characterized in that: The power supply module (5) comprises AC220V, VHH, 5V and 3.3V voltages, the AC220V being electrically connected to the first low-pass filter (7) and the second low-pass filter (11) of each test channel (6), the VHH being electrically connected to the VHH pins of the tested module (8) and the test module (10), the VHH being 18-24V, the 5V being electrically connected to the VCC pins of the tested module (8) and the test module (10), and the 3.3V being electrically connected to the touch screen (1) and the FPGA chip (2).

8. The PLC communication module aging test equipment according to claim 1, characterized in that: The PLC communication module aging test device further comprises an upper cover (12), a circuit board (13), an O-type sealing ring (14) and a housing (15); the touch screen (1) is embedded in the upper cover (12); the upper cover (12) and the housing (15) are sealed and connected via the O-type sealing ring (14); the circuit board (13) is installed in a sealed space formed by the upper cover (12) and the housing (15); the FPGA chip (2), the first detection unit (3), the second detection unit (4), the power supply module (5) and a plurality of groups of test channels (6) of the first low-pass filter (7), the attenuator (9) and the second low-pass filter (11) are installed on a PCB board of the circuit board (13); and a plurality of groups of the tested modules (8) and the test modules (10) are installed on the upper cover (12).

9. A PLC communication module aging test device according to claim 8, characterized in that: The upper cover (12) is provided with a plurality of groups of locking seats (12-1), and a plurality of groups of tested modules (8) and testing modules (10) are respectively locked and mounted on the upper cover (12) via the plurality of groups of locking seats (12-1).

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