Quantum key distribution system and gating detector dead time defense circuit thereof

Abstract

The utility model discloses a gate control detector dead time defense circuit and a QKD system. The circuit comprises a clock signal generation module, an FPGA unit and a multi-channel gating detector, the clock signal generation module provides homologous clock signals for the FPGA unit and the multi-channel gating detector, the FPGA unit provides dead time control signals for the multi-channel gating detector when monitoring detection pulse signals output by the multi-channel gating detector, and the detection pulse signals output by the multi-channel gating detector are output by the FPGA unit. And the multi-channel gating detector enters a dead time state when receiving the dead time control signal. By means of the circuit, all detection channels in the multichannel gating detector can enter / exit the dead time state at the same time by means of response of hardware and input optical signals, and defense against dead time attack behaviors is achieved.

Description

Technical Field

[0001] The utility model relates to the field of quantum technology, and more specifically to a gated detector dead time defense circuit for a QKD system and a correspondingly implemented quantum key distribution system. Background Art

[0002] The quantum key distribution (QKD) system consists of multiple components, and the single-photon detector is a very important component. Its manufacturing principle makes it vulnerable to attacks. Figure 1 Taking a typical receiving-end decoding and detection module structure of a polarization-coded QKD system based on the decoyed state BB84 protocol as an example, the transmitting end prepares an optical pulse signal containing four polarization states H, V, P, and N, which is transmitted through the optical fiber channel to the receiving end. The random basis vector selection is completed through the beam splitter in the decoding and detection module, and then the signal reaches the H, V, P, and N four-channel single-photon detectors through the polarization controller and the polarization beam splitter.

[0003] According to the BB84 protocol, when the transmitter and receiver use polarization controllers to complete the calibration of the polarization state detection link at both ends, the probability of the optical pulse signal with a polarization state of |H> reaching the receiver through the beam splitter and polarization beam splitter to reach the H, V, P, and N four-channel single-photon detectors will be close to 50%, 0%, 25%, and 25%, respectively. The same is true for the other three polarization states.

[0004] There are many types of detectors used to achieve single-photon detection. Most practical QKD systems use single-photon avalanche photodiodes (APDs) to achieve single-photon detection. In order to successfully detect the extremely weak single-photon signals received, the APD must work in Geiger mode to obtain a sufficiently high gain. In Geiger mode, when a photon incident is detected, an avalanche current will be generated in the APD and continue spontaneously. Being in an avalanche state for a long time will affect the service life and stability of the APD. Therefore, after triggering an avalanche, the reverse bias of the APD needs to be reduced to below the avalanche voltage by active or passive means to exit the Geiger mode and quench the avalanche current. In addition, the carriers generated during the APD avalanche process are delayed in release after being captured due to defects and impurities in the multiplication layer, resulting in a small amount of additional avalanche signals (i.e., the after-pulse effect), which will lead to error counts and reduce the security key generation rate of the QKD system. To this end, after each successful detection of a light pulse, the APD reverse bias needs to be reduced to below the avalanche voltage and maintained for a period of time, forcing the APD to exit the Geiger mode and enter the linear mode. At this time, single photon incidence will not be able to trigger an effective detection signal. This period of time is called dead time, and the time length is generally tens of nanoseconds to tens of microseconds.

[0005] Dead time attack is to use the dead time effect of the above single photon detector. The attacker injects a fixed polarization strong pulse light (for example, |H> polarized light) into the optical fiber channel before the real optical pulse signal, causing the other three channels of the four detectors H, V, P, and N to trigger detection with a high probability and be in dead time and blinded, leaving only the target detector in normal response mode. The attacker can control the response of the detector at the receiving end. If a detection event occurs at the receiving end at this time, the attacker can judge the detection result of the receiving end with high accuracy. Since the key data mapped by each detector is fixed, the attacker can successfully steal the key data.

[0006] In the QKD system, the anti-dead time attack requires that all channel detectors "enter the dead time at the same time and exit the dead time at the same time" to close the dead time attack vulnerability. Figure 2 As shown, in an existing defense scheme against dead time attacks, a software dead time synchronization scheme is adopted, which first sets a software dead time length at the receiving end, and uses the cycle of the detection event. If it is within the defined software dead time area, it is called invalid detection time, and if it is outside the defined software dead time area, it is called valid detection time. The valid detection time and the invalid detection time are distinguished in time. The detection events in the valid detection time are retained, and whether to extend the dead time of the detector is determined according to the detection events in the invalid detection time. It is a software-based dynamic dead time scheme based on the judgment of detection events.

[0007] This software-based attack defense solution does not take into account the dead time control mechanism of different types of detectors. During the dead time judgment period, the detector working mode is not switched to linear mode, and the detector can still perform single photon detection. During the actual dead time period, multi-channel detectors can continue to respond to single photon detection. During the multi-channel dead time synchronization process, the duration of the detector's dead time will not be fixed, but will be continuously and dynamically extended, which will reduce the effective count of the detector, thereby reducing the code rate of the QKD system. Utility Model Content

[0008] In view of the above-mentioned defects of the prior art, the gated detector dead time defense circuit of the utility model can respond to the detection pulse signal generated by any detection channel in the multi-channel gated detector, and the FPGA unit simultaneously controls the dual-path delay unit of the multi-channel detector to be disabled, so that the gated signal is no longer generated, thereby making all the detection channels of the multi-channel detector enter the dead time state at the same time; and when the dead time ends, the FPGA unit simultaneously controls the dual-path delay unit of the multi-channel detector to be enabled, so that the gated signal is generated again, thereby making all the detection channels of the multi-channel detector exit the dead time state at the same time, thereby providing defense capabilities against dead time attack behaviors. With the help of the circuit of the utility model, the multi-channel detector can be turned off to the linear mode at the same time, and restored to the Geiger mode from the linear mode at the same time, and the dead time length is fixed. The dead time length does not change with the communication distance of the QKD system, the detector count size, etc., which can improve the effective count rate of the detector and improve the performance of the QKD system.

[0009] Specifically, a first aspect of the utility model relates to a gated detector dead time defense circuit for a QKD system, which includes a clock signal generation module, an FPGA unit, and a multi-channel gated detector;

[0010] The multi-channel gated detector is configured to output a detection pulse signal in response to an input optical signal;

[0011] Features:

[0012] The clock signal generation module is configured to provide a homologous clock signal to the FPGA unit and the multi-channel gated detector;

[0013] The FPGA unit is configured to provide a dead time control signal to the multi-channel gated detector when detecting a detection pulse signal output by the multi-channel gated detector;

[0014] The multi-channel gated detector is configured to enter a dead time state upon receiving a dead time control signal.

[0015] Further, the multi-channel gated detector includes N single-photon avalanche photodiodes, N dual-channel delay units, N AND gate logic units and N avalanche signal extraction units, where N is a positive integer greater than 1;

[0016] The dual-path delay unit is configured to output two-path signals to the AND gate logic unit based on an input clock signal;

[0017] The AND gate logic unit is configured to send a gate signal to the single photon avalanche photodiode based on an AND operation of two signals;

[0018] The avalanche signal extraction unit is configured to generate a detection pulse signal according to the avalanche signal output by the single-photon avalanche photodiode;

[0019] The FPGA unit is configured to provide a dead time control signal to the dual-path delay unit based on the received detection pulse signal.

[0020] Optionally, the dead time control signal is a low level signal.

[0021] Furthermore, the dual-path delay unit is configured to be disabled upon receiving a dead time control signal.

[0022] Furthermore, the clock signal generation module includes a phase-locked loop, N single-channel delay units and N dual-channel buffer distribution units;

[0023] The phase-locked loop is configured to output N+1 working clock signals based on an input clock signal through phase-locked frequency multiplication, wherein the frequency of the working clock signal is the same as the working frequency of the multi-channel gated detector;

[0024] The FPGA unit is configured to receive one of the N+1 working clock signals, which is used as a dead time timing working clock;

[0025] The single-channel delay unit is configured to delay one channel of the N+1 working clock signals;

[0026] The dual-path buffer distribution unit is configured to output two identical clock signals to the dual-path delay unit based on the working clock signal output by the single-path delay unit.

[0027] Furthermore, the dual-path delay unit is configured to provide different delays for two paths of the same clock signal, so as to output two paths of signals to the AND gate logic unit.

[0028] Optionally, the dual-path delay unit is configured to provide a delay difference of 1 ns for two homologous clock signals.

[0029] Optionally, the gating signal is a narrow pulse.

[0030] The second aspect of the utility model relates to a quantum key distribution system, which is characterized in that the above-mentioned gated detector dead time defense circuit is arranged at the detection end. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A typical receiving-end decoding and detection module structure of a polarization-coded QKD system based on the decoyed BB84 protocol in the prior art is schematically shown;

[0032] Figure 2The dead time attack defense solution based on software implementation in the prior art is schematically shown;

[0033] Figure 3 An example principle diagram of a gated detector dead time defense circuit according to the utility model is schematically shown. DETAILED DESCRIPTION

[0034] In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example in order to fully convey the spirit of the present invention to those skilled in the art to which the present invention belongs. Therefore, the present invention is not limited to the embodiments disclosed herein.

[0035] Figure 3 An example schematic diagram of a gated detector dead time defense circuit according to the present utility model is shown.

[0036] like Figure 3 As shown, the defense circuit may include a clock signal generation module, a multi-channel gated detector and an FPGA unit, wherein the multi-channel gated detector has N detection channels, and N is a positive integer greater than 1.

[0037] In the defense circuit, the clock signal generation module can provide the same clock signal for the FPGA unit and the multi-channel gated detector.

[0038] Specifically, the clock signal generation module may include a phase-locked loop, N single-path delay units, and N dual-path buffer distribution units. Figure 3 In the example, N is 4.

[0039] The phase-locked loop is used to use the input clock signal (for example, 100KHz) to output N+1 working clock signals through phase-locked frequency multiplication. The frequencies of these working clock signals are adapted to the working frequency of the gated detector (for example, 40MHz). Among them, one of the N+1 working clock signals output by the phase-locked loop will be provided to the FPGA unit as a dead time timing working clock (for example, 40MHz_DeadTime_clk, used for dead time timing); the other N working clock signals are delayed by the corresponding single-channel delay unit and then enter the corresponding dual-channel buffer distribution unit, which outputs two identical clock signals to the corresponding detection channel as the clock signal of the gate control signal of the detection channel.

[0040] The multi-channel gated detector is used to detect the input optical signal to generate a detection pulse signal, and each detection channel thereof may include a corresponding APD, a multi-channel dual-channel delay unit, an AND gate logic unit and an avalanche signal extraction unit.

[0041] The APD is used to generate an avalanche signal in response to an input optical signal.

[0042] The avalanche signal extraction unit is used to generate a detection pulse signal according to the avalanche signal output by the APD, so as to allow the FPGA unit to recognize it.

[0043] The dual-path delay unit is used to output two signals to the AND gate logic unit based on two input clock signals of the same source. As an example, the dual-path delay unit can set different delays for each output signal, for example, controlling the delay difference between the two signals to be 1ns.

[0044] In the present invention, the dual-path delay unit can be in an enabled or disabled state and output / not output a signal based on the control of an enable signal.

[0045] For example, Figure 3 In the example, the DeadTime_EN_X signal is an enable signal for the dual-path delay unit for detecting channel X, wherein: when the DeadTime_EN_X signal is at a low level, the dual-path delay unit is not enabled, and the dual-path delay unit has no output; when the DeadTime_EN_X signal is at a high level, the dual-path delay unit is enabled, and the dual-path delay unit outputs two signals.

[0046] The AND gate logic unit is used to perform an AND operation on the two signals provided by the dual-path delay unit to output a gate control signal (for example, in the form of a narrow pulse) and load it to the corresponding APD. As an example, the AND gate logic unit can be implemented by means of a high-speed AND gate circuit.

[0047] The FPGA unit is used to provide a dead time control signal to the multi-channel gated detector (dual-path delay unit) when it detects that any detection channel i in the multi-channel gated detector generates an avalanche signal (for example, receives a detection pulse signal corresponding to the detection channel i), thereby controlling all detection channels of the multi-channel gated detector to enter the dead time state at the same time.

[0048] For example, Figure 3 In the example of , the dead time control signal can be generated by setting the enable signal DeadTime_EN_X to a low level, thereby disabling the dual-path delay unit when receiving the dead time control signal, that is, having no output.

[0049] In order to better understand the configuration of each module component in the above-mentioned gated detector dead time defense circuit, the working process of the defense circuit will be described in detail below.

[0050] In the normal detection state, when the FPGA unit receives the detection pulse signal output by any detection channel i in the multi-channel gated detector, it generates a dead time control signal according to the dead time length preset internally, and outputs it to all dual-path delay units in the multi-channel gated detector to disable them.

[0051] For example, the FPGA unit sets the enable signal DeadTime_EN_X for the dual-path delay unit to a low level within the preset dead time length, so that all dual-path delay units are disabled and have no output within the dead time length, and then all AND gate logic units no longer generate (narrow pulse) gating signals, so that the reverse voltage across all APDs is lower than the avalanche voltage, the APD enters the linear mode and no longer responds to single-photon signals, and the multi-channel gated detector enters the dead time state.

[0052] Subsequently, the FPGA unit starts timing the dead time state based on the dead time timing working clock. When the preset dead time length timing ends, the FPGA unit can set the enable signal DeadTime_EN_X to a high level and stop providing the dead time control signal to the dual-channel delay unit, that is, the dead time control signal ends. At this time, all dual-channel delay units in the multi-channel gated detector are enabled to output two-channel delay signals, and then all AND gate logic units generate (narrow pulse) gating signals, so that the reverse voltage across all APDs is higher than the avalanche voltage, and the APD enters the Geiger mode and can respond normally to single-photon signals. All detection channels of the multi-channel gated detector simultaneously exit the dead time state and enter the normal detection state.

[0053] It can be seen that, with the circuit configuration of the utility model, all detection channels in the multi-channel gated detector can be synchronously entered into the dead time state based on the hardware response to the input optical signal (i.e., generating an avalanche signal / detection pulse signal); when the dead time state ends based on the timing of the clock signal, all detection channels in the multi-channel gated detector can be synchronously exited from the dead time state. Those skilled in the art can understand that under this circuit configuration, dead time attacks on multi-channel gated detectors can be defended in the form of hardware.

[0054] In addition, the utility model also correspondingly proposes a quantum key distribution system having the above-mentioned gated detector dead time defense circuit arranged at its detection end.

[0055] In summary, in the gated detector dead time defense circuit of the utility model, in response to the detection pulse signal generated by any detection channel in the multi-channel gated detector, the FPGA unit can simultaneously control the dual-path delay unit of the multi-channel detector to be disabled, so that the gated signal is no longer generated, thereby making all the detection channels of the multi-channel detector enter the dead time state at the same time; and when the dead time ends, the FPGA unit simultaneously controls the dual-path delay unit of the multi-channel detector to be enabled, so that the gated signal is generated again, thereby making all the detection channels of the multi-channel detector exit the dead time state at the same time, thereby providing defense capabilities against dead time attack behaviors. With the help of the circuit of the utility model, the multi-channel detector can be turned off to the linear mode at the same time, and restored to the Geiger mode from the linear mode at the same time, and the dead time length is fixed. The dead time length does not change with the communication distance of the QKD system, the detector count size, etc., which can improve the effective count rate of the detector and improve the performance of the QKD system.

[0056] Although the present invention has been described above through specific embodiments in conjunction with the accompanying drawings, those skilled in the art will easily recognize that the above embodiments are merely exemplary and are used to illustrate the principles of the present invention, and do not limit the scope of the present invention. Those skilled in the art can make various combinations, modifications and equivalent substitutions to the above embodiments without departing from the spirit and scope of the present invention.

Claims

1. A gated detector dead time defense circuit for a QKD system, comprising a clock signal generation module, an FPGA unit and a multi-channel gated detector; The multi-channel gated detector is configured to output a detection pulse signal in response to an input optical signal; Features: The clock signal generation module is configured to provide a homologous clock signal to the FPGA unit and the multi-channel gated detector; The FPGA unit is configured to provide a dead time control signal to the multi-channel gated detector when detecting a detection pulse signal output by the multi-channel gated detector; The multi-channel gated detector is configured to enter a dead time state upon receiving a dead time control signal.

2. The gated detector dead time protection circuit according to claim 1, characterized in that: The multi-channel gated detector comprises N single-photon avalanche photodiodes, N dual-channel delay units, N AND gate logic units and N avalanche signal extraction units, where N is a positive integer greater than 1; The dual-path delay unit is configured to output two-path signals to the AND gate logic unit based on an input clock signal; The AND gate logic unit is configured to send a gate signal to the single photon avalanche photodiode based on an AND operation of two signals; The avalanche signal extraction unit is configured to generate a detection pulse signal according to the avalanche signal output by the single-photon avalanche photodiode; The FPGA unit is configured to provide a dead time control signal to the dual-path delay unit based on the received detection pulse signal.

3. The gated detector dead time protection circuit as claimed in claim 2, characterized in that: The dead time control signal is a low level signal.

4. The gated detector dead time protection circuit as claimed in claim 2, characterized in that: The dual-path delay unit is configured to be disabled upon receiving a dead time control signal.

5. The gated detector dead time protection circuit as claimed in claim 2, characterized in that: The clock signal generation module includes a phase-locked loop, N single-channel delay units and N dual-channel buffer distribution units; The phase-locked loop is configured to output N+1 working clock signals based on an input clock signal through phase-locked frequency multiplication, wherein the frequency of the working clock signal is the same as the working frequency of the multi-channel gated detector; The FPGA unit is configured to receive one of the N+1 working clock signals, which is used as a dead time timing working clock; The single-channel delay unit is configured to delay one channel of the N+1 working clock signals; The dual-path buffer distribution unit is configured to output two identical clock signals to the dual-path delay unit based on the working clock signal output by the single-path delay unit.

6. The gated detector dead time protection circuit as claimed in claim 5, characterized in that: The dual-path delay unit is configured to provide different delays for two paths of the same clock signal, so as to output two paths of signals to the AND gate logic unit.

7. The gated detector dead time protection circuit according to claim 6, characterized in that: The dual-path delay unit is configured to provide a 1 ns delay difference for two paths of the same source clock signals.

8. The gated detector dead time protection circuit as claimed in claim 2, characterized in that: The gate control signal is a narrow pulse.

9. A quantum key distribution system, characterized in that: A gated detector dead time protection circuit as described in any one of claims 1 to 8 is arranged at the detection end.

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