Logic calculation board card for memristor array test

Abstract

The utility model relates to a logic calculation board card used for memristor array testing, after the logic calculation board card is built, in actual use, a memristor array to be tested is installed on a base and then is powered on, firstly, the weight of the memristor array to be tested is subjected to reading and writing testing through a weight reading circuit and a weight writing circuit, and then the memristor array to be tested is tested through the weight reading circuit and the weight writing circuit; the logic calculation excitation signal generation circuit generates pulse signals needed by logic calculation, the calculation result measurement circuit measures the result of logic calculation, the bias circuit provides bias voltage for the memristor array to be measured through the gating switch module, and the clock circuit provides the calculation result measurement circuit and the logic calculation excitation signal generation circuit. The weight reading circuit and the weight writing circuit provide clock signals; compared with the prior art, manual operation links are greatly reduced, complex test algorithm development is avoided, the test of the memristor array to be tested is efficiently completed by completely utilizing the existing hardware components through an ingenious circuit connection relation, and finally the test efficiency is effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of memristor testing, and in particular to a logic computing board for testing a memristor array. Background Art

[0002] Memristor array, also known as RRAM (Resistive Random Access Memory) array, is a cross array composed of non-volatile memristors and switch devices. It can store and calculate at the same time, and is expected to break the bottleneck of "storage wall". Because memristor array has the advantages of non-volatility, small area and compatibility with CMOS process, it can realize multiplication and accumulation operations at high speed and low power consumption, so it is widely used in accelerated applications of neural network reasoning calculation. However, due to the structural characteristics of memristor array itself, the functional testing of memristor array is a high-intensity task. The traditional functional testing method of memristor array is to build a dedicated test mold specifically for the function to be tested, such as the logic calculation function. This testing method is inefficient and costly. There is an urgent need for an efficient testing method to solve the technical problem of low efficiency of logic calculation testing of memristor array. Summary of the invention

[0003] Based on this, it is necessary to provide a logic computing board for memristor array testing in order to solve the above technical problems.

[0004] A logic computing board for testing a memristor array comprises: a gating switch module, an FPGA module, a calculation result measurement circuit, a logic computing excitation signal generation circuit, a read weight circuit, a write weight circuit, a bias circuit, a clock circuit, a power supply module and a memristor array base; the memristor array base is used for installing a memristor array to be tested.

[0005] The control ends of the selection switch module, the calculation result measurement circuit, the logic calculation excitation signal generation circuit, the read weight circuit and the write weight circuit are all connected to the FPGA module.

[0006] The gating switch module is connected to the memristor array base, and the FPGA module, the input end of the calculation result measurement circuit, the output end of the logic calculation excitation signal generation circuit, the input end of the read weight circuit, the output end of the write weight circuit and the output end of the bias circuit are all connected to the memristor array base through the gating switch module.

[0007] The clock circuit is used to provide clock to the calculation result measurement circuit, the logic calculation excitation signal generation circuit, the read weight circuit and the write weight circuit.

[0008] The power supply module is used to provide power to the selection switch module, FPGA module, calculation result measurement circuit, logic calculation excitation signal generation circuit, read weight circuit, write weight circuit, bias circuit and clock circuit.

[0009] In one embodiment, the read weight circuit includes: a current-to-voltage operational amplifier module and an ADC module.

[0010] The input end of the current-to-voltage operational amplifier module is connected to the output end of the selection switch module, the output end of the current-to-voltage operational amplifier module is connected to the input end of the ADC module, and the control end and output end of the ADC module and the control end of the current-to-voltage operational amplifier module are all connected to the FPGA module.

[0011] In one embodiment, the write weight circuit includes: a first DAC module and a high power operational amplifier module.

[0012] The control end and data input end of the first DAC module are connected to the FPGA module, the analog output end of the first DAC module is connected to the input end of the high-power operational amplifier module, and the output end of the high-power operational amplifier module is connected to the memristor array base through the selection switch module.

[0013] In one embodiment, the first DAC module is a digital-to-analog converter DAC5682Z, and the high-power operational amplifier module is a high-power operational amplifier THS3491.

[0014] In one embodiment, the logic calculation excitation signal generation circuit includes: a second DAC module and an enhanced driving module.

[0015] The data input terminal and the control terminal of the second DAC module are both connected to the FPGA module, the analog output terminal of the second DAC module is connected to the input terminal of the enhanced driving module, and the output terminal of the enhanced driving module is connected to the memristor array base through the selection switch module.

[0016] In one embodiment, the second DAC module is a digital-to-analog converter AD5532, and the enhanced driving module is an operational amplifier OPA4228.

[0017] In one embodiment, the calculation result measurement circuit includes: a current-to-voltage operational amplifier module, an ADC driver, and a multi-channel ADC module.

[0018] The control end of the multi-channel ADC module is connected to the FPGA module; the input end of the current-to-voltage operational amplifier module is connected to the memristor array base through the gate switch module; the output end of the current-to-voltage operational amplifier module is connected to the input end of the ADC driver, the input end of the multi-channel ADC module is connected to the output end of the ADC driver, and the output end of the multi-channel ADC module is connected to the FPGA module.

[0019] In one embodiment, the ADC driver is an ADA4350 module; the multi-channel ADC module is an AD9249 module; and the output end of the ADA4350 module is connected to the input end of the AD9249 module.

[0020] In one embodiment, the gate switch module includes a row gate switch module and a column gate switch module; both the row gate switch module and the column gate switch module use a cross switch AD75019 module.

[0021] In one of the embodiments, the logic computing board also includes a communication interface module, and the communication interface module includes USB3.0 and UART communication interfaces; the logic computing board is connected to the host computer via the communication interface module.

[0022] The above-mentioned logic calculation board for testing memristor arrays, after the logic calculation board is built, in actual use, the memristor array to be tested is installed on the base and then powered on, firstly, the weights of the memristor array to be tested are read and written through the read weight circuit and the write weight circuit, the pulse signal required for the logic calculation is generated through the logic calculation excitation signal generation circuit, the result of the logic calculation is measured through the calculation result measurement circuit, the bias circuit provides a bias voltage to the memristor array to be tested through the gate switch module, and the clock circuit provides a clock signal to the calculation result measurement circuit, the logic calculation excitation signal generation circuit, the read weight circuit, and the write weight circuit; the manual operation links are greatly reduced, and the complex test algorithm development is avoided, and the existing hardware components are fully utilized with clever circuit connection relationships to efficiently complete the test of the memristor array to be tested, and finally the test efficiency is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A structural diagram of a logic computing board for testing a memristor array in one embodiment;

[0024] Figure 2 A hardware structure diagram of a logic computing board for memristor array testing in another embodiment;

[0025] Figure 3 FIG. 2 is another embodiment of the ADA4350 current-to-voltage conversion principle. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] In one embodiment, Figure 1As shown, a logic computing board for testing a memristor array is provided, and the logic computing board includes: a gate switch module 10, an FPGA module 20, a calculation result measurement circuit 30, a logic calculation excitation signal generation circuit 40, a read weight circuit 50, a write weight circuit 60, a bias circuit 70, a clock circuit 80, a power module 90, and a memristor array base 100; the memristor array base 100 is used to install the memristor array to be tested. Preferably, the memristor array base 100 of the board uses a 32×32 memristor array base, which can support the operation of a maximum of 32×32 memristor arrays.

[0028] The control ends of the selection switch module 10 , the calculation result measurement circuit 30 , the logic calculation excitation signal generation circuit 40 , the read weight circuit 50 , and the write weight circuit 60 are all connected to the FPGA module 20 .

[0029] The gating switch module 10 is connected to the memristor array base 100, and the FPGA module 10, the input end of the calculation result measurement circuit 30, the output end of the logic calculation excitation signal generation circuit 40, the input end of the read weight circuit 50, the output end of the write weight circuit 60 and the output end of the bias circuit 70 are all connected to the memristor array base 100 through the gating switch module 10.

[0030] The clock circuit 80 is used to provide clocks to the calculation result measurement circuit 30 , the logic calculation excitation signal generation circuit 40 , the read weight value circuit 50 , and the write weight value circuit 60 .

[0031] The power supply module 90 is used to provide power to the selection switch module 10, the FPGA module 20, the calculation result measurement circuit 30, the logic calculation excitation signal generation circuit 40, the read weight circuit 50, the write weight circuit 60, the bias circuit 70 and the clock circuit 80.

[0032] Specifically, the memristor array to be tested is controlled by a gate switch module 10 (bidirectional cross-dot switch array) to access various operation signals. Through the row (column) gate switch, 4 excitation signals (AD5532) can be simultaneously accessed to any row (column) of the memristor array, and the output current signals on any 4 rows (columns) can be input into the calculation result measurement circuit (AD9249) through the row (column) gate switch.

[0033] The gate switch module 10 is used to select an area for logic calculation, such as selecting a 4x4 area in the 1K array area for logic operation. Any device in the 1K array can also be gated to perform read and write operations on it.

[0034] The FPGA module 20 serves as a main chip, which may be, but is not limited to, a Kintex7 FPGA. The Kintex7 FPGA controls all circuits to work in coordination.

[0035] The calculation result measurement circuit 30 is used to measure the result of the logic calculation and is also used for the read operation of a single device.

[0036] The logic calculation excitation signal generating circuit 40 is used to generate a pulse signal required for logic calculation.

[0037] The weight reading circuit 50 is used to read the weight of a memristor in the array.

[0038] The write weight circuit 60 is used to change the weight of a memristor in the memristor array.

[0039] The bias circuit 70 is used to generate a variety of different pulse voltages required for memristor logic calculations and provide bias voltages for memristor array testing.

[0040] The write weight circuit 60 can also send a write weight signal to any device in the memristor array to be tested through the row and column switching switches. In addition, the bias circuit 70 can also provide a bias voltage to the memristor array to be tested through the row and column switching switches.

[0041] The onboard selection switch module 10, the logic calculation excitation signal generation circuit 40, the calculation result measurement circuit 30, the write weight circuit 60 and the read weight circuit 50 are all controlled by the FPGA module 20. In order to enable the board to communicate with the host computer, the board is equipped with USB3.0 and UART communication interfaces. The clocks of the onboard logic calculation excitation signal generation circuit 40, the calculation result measurement circuit 30, the write weight circuit 60 and the read weight circuit 50 are provided by the clock circuit 80.

[0042] The hardware structure diagram of the logic computing board used for memristor array testing is shown in the figure. Figure 2 As shown. The board has 32 rows and columns equipped with switch matrices. By controlling the switch array, the switching of various working modes can be realized. The scale of all cross switches (AD75019) is 16×16, and the signal can be transmitted bidirectionally inside. The selection switch module 10 is composed of 4 cross switches AD75019. Two AD75019s can form a 32×32 row selection switch. Similarly, two AD75019s can also form a 32×32 column selection switch. The hardware connection relationship of the whole system is shown as follows Figure 2 As shown in the figure, by using four bidirectional selection switches (AD75019), four excitation signals (AD5532) can be simultaneously input to any row and any column of the memristor array, and the measurement circuit can simultaneously measure (AD9249) the output current signals in any row and any column of the four channels.

[0043] The logic calculation board contains multiple ADC / DACs. One 32-channel low-speed DAC (AD5532HS) is used to generate input pulse signals for logic calculation (amplitude, pulse width, and pulse number are adjustable), with a pulse rate of about 10kHz. One 16-channel (65MSPS) ADC (AD9249) is used to calculate the results of logic calculations in the array. One high-speed DAC (DAC5682Z) is used to implement the write operation of the memristor array weights.

[0044] The logic computing board has a 32×32 memristor array base, which can support the operation of a maximum of 32×32 memristor arrays. The array is controlled by a gating switch (bidirectional cross-dot switch array) to access various operation signals. Through the row (column) gating switch, 4 excitation signals (AD5532) can be simultaneously accessed to any row (column) of the memristor array, and the output current signal on any 4 rows (columns) can be input into the calculation result measurement circuit (AD9249) through the row (column) gating switch. At the same time, the write weight circuit can also send a write weight signal to any device in the memristor array through the row and column gating switches.

[0045] The working process of the logic computing board used for memristor array testing is:

[0046] First, the existing control level (signal) output of the FPGA chip itself is triggered to control the AD75019 cross switch to switch the rows and columns of the memristor array to the corresponding positions (such as in a write operation, the selected row is connected to the set resistance DAC, the unselected row is floating, the selected column is grounded, and the unselected column is floating). Then, the FPGA controls the set resistance DAC, the bias DAC, and the DAC AD5532 used for calculation to send the corresponding pulse waveform. At the same time, it controls the AD9249 to collect the current signal flowing through the memristor array and returns the result to the host computer through USB3.0.

[0047] In the above-mentioned logic calculation board for testing memristor arrays, after the logic calculation board is built, in actual use, the memristor array to be tested is installed on the base and then powered on. First, the weights of the memristor array to be tested are read and written through the read weight circuit and the write weight circuit, the pulse signal required for the logic calculation is generated through the logic calculation excitation signal generation circuit, the result of the logic calculation is measured through the calculation result measurement circuit, the bias circuit provides a bias voltage to the memristor array to be tested through the gate switch module, and the clock circuit provides a clock signal to the calculation result measurement circuit, the logic calculation excitation signal generation circuit, the read weight circuit, and the write weight circuit; the manual operation links are greatly reduced, and the complex test algorithm development is avoided, so that the existing hardware components are fully utilized with ingenious circuit connection relationships to efficiently complete the test of the memristor array to be tested, and finally the test efficiency is effectively improved.

[0048] In one embodiment, the read weight circuit includes: a current-to-voltage operational amplifier module and an ADC module; the input end of the current-to-voltage operational amplifier module is connected to the output end of the selection switch module, the output end of the current-to-voltage operational amplifier module is connected to the input end of the ADC module, and the control end and output end of the ADC module and the control end of the current-to-voltage operational amplifier module are all connected to the FPGA module.

[0049] Specifically, the signal that needs to be obtained during the weight reading process is a current signal. The current signal can be converted into a voltage signal through a current-to-voltage operational amplifier module (the reverse amplification circuit of the operational amplifier), and then collected through an ADC module (the analog-to-digital converter AD9249 is selected as the preferred ADC module) and transmitted to the FPGA module for processing. The specific signal flow is: the current signal to be measured of the memristor array to be measured is transmitted to the current-to-voltage operational amplifier ADA4350 through the selected cross switch AD75019. The single-ended voltage signal converted by ADA4350 is converted into a differential voltage signal through ADA4938, and drives the switched capacitor ADC module (i.e., the analog-to-digital converter AD9249). The current signal to be measured collected by the analog-to-digital converter AD9249 is input into the FPGA module (the Kintex7 FPGA is selected as the preferred FPGA module) to complete the reading of the weight.

[0050] Considering that the resistance value of the memristor varies from 1kΩ to 1MΩ, with a span of 10e3, in order to read the resistance value range of 10e3 and maximize the bandwidth of the operational amplifier, the operational amplifier ADA4350 is selected as the current-to-voltage operational amplifier module in the preferred weight reading circuit.

[0051] The gain bandwidth product of ADA4350 is 175MHz. It has 6 internal feedback paths and can be controlled by FPGA. Therefore, with the help of its internal controllable feedback path, we can programmatically change the feedback resistance value of the current-to-voltage circuit and achieve the measurement of resistance values ​​in the range of 1kΩ to 1MΩ.

[0052] The principle of ADA4350 current-to-voltage conversion is as follows Figure 3 As shown. The internal switch resistance does not affect the conversion accuracy during the conversion process. The converted voltage value is only linearly related to the feedback resistance. Through the internal programmable feedback path, the feedback gears to be set are 100R, 1K, 10K, 100K, 500K, and 1M. When the measurement gear used is appropriate (equivalent to the resistance of the memristor), the amplification factor of the op amp is relatively small, and the gain-bandwidth product of 175MHz meets the requirements.

[0053] After the signal is converted from current to voltage, it needs to be converted into a differential signal before it can be collected by the analog-to-digital converter AD9249. The single-ended to differential chip is the ADA4930 (AD9249 front end) officially recommended by ADI. ADA4930 is the front-end driver circuit officially recommended by ADI to drive AD9249. Considering that the operating voltage of the memristor is ±0.5V, in order to prevent the input of AD9249 from exceeding the full scale, the amplification factor of ADA4930 is set to 1V / V. Since the input signal frequency is low, the signal to be measured is input in the form of DC coupling. ADA4930 is a single-power supply amplifier, so it cannot amplify negative voltage signals. In order to amplify negative voltage signals, a certain voltage bias voltage signal needs to be added to the input end of ADA4930 so that negative voltage signals can also be amplified.

[0054] In one embodiment, the write weight circuit includes: a first DAC module and a high-power operational amplifier module; the control end and the data input end of the first DAC module are both connected to the FPGA module, the analog output end of the first DAC module is connected to the input end of the high-power operational amplifier module, and the output end of the high-power operational amplifier module is connected to the memristor array base through the selection switch module.

[0055] In one embodiment, the first DAC module is a digital-to-analog converter DAC5682Z, and the high-power operational amplifier module is a high-power operational amplifier THS3491.

[0056] Specifically, the write weight circuit requires a voltage output of at least ±10V. The digital-to-analog converter DAC5682Z is ​​an output current type DAC. In order to obtain an output voltage of ±10V, the output current signal of the digital-to-analog converter DAC5682Z is ​​amplified by a high-power operational amplifier THS3491 and applied to any row or column of the memristor array to be tested through a gated cross switch array (AD75019). During the write weight operation, the FPGA module (Kintex 7FPGA is selected as the preferred FPGA module) controls the output of the digital-to-analog converter DAC5682Z and the gate of the AD75019.

[0057] The DAC outputting the pulse signal used in the write weight circuit is the digital-to-analog converter DAC5682Z. The digital-to-analog converter DAC5682Z is ​​a 16-bit 1.0GSPS 2x-4x interpolation dual-channel digital-to-analog converter (DAC). The chip has the same package and configuration as the 5681Z. Its clock circuit is driven by the AD9518.

[0058] DAC5682Z is ​​a current output DAC, so the circuit output needs to be converted into a voltage output. The output current value is amplified by the high-power op amp THS3491 to output the required positive and negative voltage values. The output positive and negative pulses pass through the cross switch array (AD75019) to write the weights of the corresponding memristor to be tested. The high-power op amp THS3491 is a current feedback amplifier, and its output voltage swing (±12V power supply) can reach ±10V.

[0059] In one embodiment, the logic calculation excitation signal generating circuit includes: a second DAC module and an enhanced driving module; the data input terminal and the control terminal of the second DAC module are both connected to the FPGA module, the analog output terminal of the second DAC module is connected to the input terminal of the enhanced driving module, and the output terminal of the enhanced driving module is connected to the memristor array base through the selection switch module.

[0060] In one embodiment, the second DAC module is a digital-to-analog converter AD5532, and the enhanced driving module is an operational amplifier OPA4228.

[0061] Specifically, the logic calculation is mainly realized by the 32×32 memristor array to be tested. During the logic calculation process, the second DAC module (digital-to-analog converter AD5532) of the single chip with 32 channels generates 8 excitation signals (8 for each row and column), and the 8 excitation signals first pass through the operational amplifier OPA4228 emitter-follower circuit to enhance the driving capability. Then the enhanced excitation signal is input into the 32×32 memristor array through the cross switch (AD75019). After the multiplication and accumulation operation, the logic operation result of the memristor array (up to 8 current signals) first flows through the cross switch (AD75019), and then passes through the current-to-voltage operational amplifier circuit (Ada4350) to be converted into a voltage signal. The single-ended voltage signal converted by Ada4350 is converted into a differential voltage signal by ADA4930, and drives the 16-channel (8 channels for each row and column) switched capacitor analog-to-digital converter AD9249. The logic calculation results collected by the analog-to-digital converter AD9249 are input into the FPGA module (Kintex7 FPGA) to complete the logic operation process. In addition to controlling the AD5532 to output 16 excitation signals (8 for each row and column), the Kintex7 FPGA chip also controls the AD9249 to collect 16 (8 for each row and column) logic operation results. In addition, the Kintex7 FPGA also controls the selection of the cross switch AD75019.

[0062] The current-to-voltage op amp is OPA228, which has very low noise performance. 3 n V√H z, and the common mode rejection (CMRR) ratio reaches 138dB. The input bias current and input offset voltage are only 10nA and 75uV. Considering that the input signal to be converted is at the KHz level, and the resistance range of the memristor is 1kΩ~1MΩ. Therefore, under the condition of the feedback resistance of 1kΩ, the amplification factor of the input signal will not exceed 1, and the gain bandwidth product of the OPA228 op amp is 33MHz, which meets the amplification bandwidth requirements of the input signal. There is an offset voltage compensation circuit inside the OPA228, so no balancing resistor is required at its positive input.

[0063] The logic calculation excitation signal generation circuit uses a low-speed 32-channel digital-to-analog converter AD5532HS. The resolution of the digital-to-analog converter AD5532HS is 14 bits, and the channel update rate is 100KSPS. The output voltage range is ±2.5V. This DAC is an SPI serial control DAC and does not require an external clock signal.

[0064] The acquisition of the logic operation results is planned to use AD9249 (14bit, 16 channels) with a sampling rate of 65MSPS, serial LVDS communication, 1.8V power supply, analog input range of 2Vpp, and analog signal bandwidth of 650MHz.

[0065] In one embodiment, the calculation result measurement circuit includes: a current-to-voltage operational amplifier module, an ADC driver and a multi-channel ADC module; the control end of the multi-channel ADC module is connected to the FPGA module; the input end of the current-to-voltage operational amplifier module is connected to the memristor array base through a gate switch module; the output end of the current-to-voltage operational amplifier module is connected to the input end of the ADC driver, the input end of the multi-channel ADC module is connected to the output end of the ADC driver, and the output end of the multi-channel ADC module is connected to the FPGA module.

[0066] In one embodiment, the ADC driver is an ADA4350 module; the multi-channel ADC module is an AD9249 module; and the output end of the ADA4350 module is connected to the input end of the AD9249 module.

[0067] In one embodiment, the gate switch module includes a row gate switch module and a column gate switch module; both the row gate switch module and the column gate switch module use a cross switch AD75019 module.

[0068] In one of the embodiments, the logic computing board also includes a communication interface module, and the communication interface module includes USB3.0 and UART communication interfaces; the logic computing board is connected to the host computer via the communication interface module.

[0069] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A logic computing board for memristor array testing, characterized in that: The logic computing board includes: a gating switch module, an FPGA module, a calculation result measurement circuit, a logic computing excitation signal generation circuit, a read weight circuit, a write weight circuit, a bias circuit, a clock circuit, a power supply module and a memristor array base; the memristor array base is used to install the memristor array to be tested; The control ends of the gating switch module, the calculation result measurement circuit, the logic calculation excitation signal generation circuit, the read weight circuit, and the write weight circuit are all connected to the FPGA module; The gating switch module is connected to the memristor array base, and the FPGA module, the input end of the calculation result measurement circuit, the output end of the logic calculation excitation signal generation circuit, the input end of the read weight circuit, the output end of the write weight circuit, and the output end of the bias circuit are all connected to the memristor array base through the gating switch module; The clock circuit is used to provide a clock to the calculation result measurement circuit, the logic calculation excitation signal generation circuit, the read weight circuit and the write weight circuit; The power supply module is used to provide power to the selection switch module, the FPGA module, the calculation result measurement circuit, the logic calculation excitation signal generation circuit, the read weight circuit, the write weight circuit, the bias circuit and the clock circuit.

2. The logic computing board according to claim 1, characterized in that: The read weight value circuit includes: an operational amplifier module for converting current to voltage and an ADC module; The input end of the current-to-voltage operational amplifier module is connected to the output end of the selection switch module, the output end of the current-to-voltage operational amplifier module is connected to the input end of the ADC module, and the control end and output end of the ADC module and the control end of the current-to-voltage operational amplifier module are all connected to the FPGA module.

3. The logic computing board according to claim 1, characterized in that: The write weight circuit comprises: a first DAC module and a high power operational amplifier module; The control end and data input end of the first DAC module are both connected to the FPGA module, the analog output end of the first DAC module is connected to the input end of the high-power operational amplifier module, and the output end of the high-power operational amplifier module is connected to the memristor array base through the selection switch module.

4. The logic computing board according to claim 3, characterized in that: The first DAC module is a digital-to-analog converter DAC5682Z, and the high-power operational amplifier module is a high-power operational amplifier THS3491.

5. The logic computing board according to claim 1, characterized in that: The logic calculation excitation signal generating circuit comprises: a second DAC module and an enhanced driving module; The data input terminal and the control terminal of the second DAC module are both connected to the FPGA module, the analog output terminal of the second DAC module is connected to the input terminal of the enhanced driving module, and the output terminal of the enhanced driving module is connected to the memristor array base through the selection switch module.

6. The logic computing board according to claim 5, characterized in that: The second DAC module is a digital-to-analog converter AD5532, and the enhanced driving module is an operational amplifier OPA4228.

7. The logic computing board according to claim 1, characterized in that: The calculation result measurement circuit includes: a current-to-voltage operational amplifier module, an ADC driver, and a multi-channel ADC module; The control end of the multi-channel ADC module is connected to the FPGA module; the input end of the current-to-voltage operational amplifier module is connected to the memristor array base through the selection switch module; the output end of the current-to-voltage operational amplifier module is connected to the input end of the ADC driver, the input end of the multi-channel ADC module is connected to the output end of the ADC driver, and the output end of the multi-channel ADC module is connected to the FPGA module.

8. The logic computing board according to claim 7, characterized in that: The ADC driver is an ADA4350 module; the multi-channel ADC module is an AD9249 module; the output end of the ADA4350 module is connected to the input end of the AD9249 module.

9. The logic computing board according to claim 1, characterized in that: The strobe switch module comprises a row strobe switch module and a column strobe switch module; both the row strobe switch module and the column strobe switch module adopt a cross switch AD75019 module.

10. The logic computing board according to claim 1, characterized in that: The logic computing board also includes a communication interface module, which includes USB3.0 and UART communication interfaces; the logic computing board is connected to a host computer via the communication interface module.

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