Light emitting diode chip with high light emitting area
By opening through holes and setting electrodes in the epitaxial layer of the light emitting diode chip, the problem of reducing the light emitting area caused by the etching gap is solved, and a higher light emitting area and brightness is achieved.
Patent Information
- Application Number
- CN202420867350.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-24
- Publication Date
- 2025-01-14
- Estimated Expiration
- 2034-04-24
AI Technical Summary
The existing light emitting diode chips etch notches on the P-type and N-type layers to accommodate the electrodes, resulting in a decrease in the luminous area and a decrease in the luminous brightness.
By opening a first through hole and a second through hole in the epitaxial layer, the insulating layer and the transparent conductive layer to the first and second semiconductor layers, respectively, and first and second electrodes are provided in the through holes to achieve electrical connection. Avoid etching of notches on the epitaxial layer, thereby improving the luminous area and brightness.
It effectively avoids the reduction of the epitaxial layer area, improves the luminous area and brightness of the light emitting diode chip, and increases the luminous brightness.
Smart Images
Figure CN222356868U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the field of semiconductor devices, and in particular relates to a light emitting diode chip with a large light emitting area. Background Art
[0002] Light emitting diodes are a common functional electronic device that are widely used in various fields.
[0003] In the related art, the light-emitting diode chip is an important component of the light-emitting diode, which mainly includes an epitaxial layer and an N-electrode and a P-electrode arranged on the epitaxial layer. The N-electrode is electrically connected to the N-type layer of the epitaxial layer, and the P-electrode is electrically connected to the P-type layer of the epitaxial layer. Since the P-type layer is spaced between the N-type layer and the N-electrode, it is necessary to etch a gap in the P-type layer and the N-type layer to accommodate the N-electrode (see Figure 1 ).
[0004] However, the notches etched on the P-type layer and the N-type layer will reduce the area of the N-type layer and the P-type layer, resulting in a reduction in the light emitting area of the light emitting diode chip and a reduction in the light emitting brightness. Utility Model Content
[0005] The embodiment of the present disclosure provides a light-emitting diode chip with a large light-emitting area, which can increase the light-emitting area of the light-emitting diode chip. The technical solution is as follows:
[0006] The embodiment of the present disclosure provides a light-emitting diode chip, comprising: an epitaxial layer, a transparent conductive layer and an insulating layer stacked in sequence;
[0007] The light-emitting diode chip further includes a first through hole and a second through hole, wherein the first through hole sequentially penetrates the insulating layer and the transparent conductive layer to the first semiconductor layer of the epitaxial layer, and the second through hole sequentially penetrates the insulating layer, the transparent conductive layer, the first semiconductor layer of the epitaxial layer to the second semiconductor layer of the epitaxial layer;
[0008] The first through hole has a first electrode in it, the size of the first through hole matches the size of the first through hole, and the first electrode is electrically connected to the first semiconductor layer. The second through hole has a second electrode in it, the size of the second through hole matches the size of the second through hole, and the second electrode is electrically connected to the second semiconductor layer.
[0009] In an implementation of the present disclosure, an orthographic projection of the outer contour of the first through hole on the plane where the epitaxial layer is located is located within the first semiconductor layer;
[0010] An orthographic projection of an outer contour of the second through hole on a plane where the epitaxial layer is located is located in the second semiconductor layer.
[0011] In an implementation of the present disclosure, the orthographic projection of the outer contour of the second through hole on the plane where the epitaxial layer is located is a circle.
[0012] In an implementation of the present disclosure, a minimum distance between an outer contour of an orthographic projection of the second through hole on the plane where the epitaxial layer is located and an outer contour of an orthographic projection of the second electrode on the plane where the epitaxial layer is located is 5 to 9 μm.
[0013] In an implementation of the present disclosure, an orthographic projection of an outer contour of the second through hole on the plane where the epitaxial layer is located matches an orthographic projection of the second electrode on the plane where the epitaxial layer is located.
[0014] In an implementation of the present disclosure, a minimum distance between an outer contour of an orthographic projection of the second through hole on the plane where the epitaxial layer is located and an outer contour of an orthographic projection of the second electrode on the plane where the epitaxial layer is located is 1-3 μm.
[0015] In an implementation of the present disclosure, the inner sidewall of the second through hole is covered with the insulating layer to isolate the second electrode from the first semiconductor layer and the transparent conductive layer.
[0016] In an implementation of the present disclosure, a distance between the bottom of the second through hole and a surface of the first semiconductor layer facing the second semiconductor layer is 3-7 μm.
[0017] In an implementation of the present disclosure, the outer side surface of the epitaxial layer has a groove, and the groove extends from the first semiconductor layer to the second semiconductor layer;
[0018] At least a portion of the insulating layer is located in the groove.
[0019] In an implementation of the present disclosure, the epitaxial layer further includes a buffer layer, and the buffer layer is located on a side of the second semiconductor layer facing away from the first semiconductor layer.
[0020] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0021] The light-emitting diode chip provided in the embodiment of the present disclosure is provided with a first through hole and a second through hole. The first through hole extends from the insulating layer to the first semiconductor layer, and the first electrode is arranged in the first through hole, so as to realize the electrical connection between the first electrode and the first semiconductor layer. The second through hole extends from the insulating layer to the second semiconductor layer, and the second electrode is arranged in the second through hole, so as to realize the electrical connection between the second electrode and the second semiconductor layer. Since the first electrode and the second electrode realize respective electrical connection through the first through hole and the second through hole, there is no need to etch a notch on the epitaxial layer, which effectively avoids the notch from reducing the area of the epitaxial layer, thereby increasing the light-emitting area of the light-emitting diode chip and increasing the light-emitting brightness.
[0022] That is to say, by providing the first through hole and the second through hole of reasonable size to accommodate the first electrode and the second electrode, it is possible to avoid a large reduction in the area of the epitaxial layer due to directly providing a gap, thereby increasing the light emitting area of the light emitting diode chip and the light emitting brightness. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0024] Figure 1 It is a projection schematic diagram of a light emitting diode chip provided by the related technology;
[0025] Figure 2 is a schematic structural diagram of a light-emitting diode chip provided by an embodiment of the present disclosure;
[0026] Figure 3 is a projection schematic diagram of a light emitting diode chip provided by an embodiment of the present disclosure;
[0027] Figure 4 It is a projection schematic diagram of the light emitting diode chip provided in the embodiment of the present disclosure.
[0028] The symbols in the figure mean the following:
[0029] 10. Epitaxial layer;
[0030] 110, first semiconductor layer; 120, second semiconductor layer; 130, groove; 140, buffer layer;
[0031] 20. Transparent conductive layer;
[0032] 30. Insulation layer;
[0033] 40. a first through hole;
[0034] 50. a second through hole;
[0035] 60. a first electrode;
[0036] 70. a second electrode;
[0037] 80. Substrate. DETAILED DESCRIPTION
[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0039] The embodiment of the present disclosure provides a light emitting diode chip, Figure 2 is a schematic diagram of the structure of the light emitting diode chip, see Figure 2 In this embodiment, the light emitting diode chip includes an epitaxial layer 10, a transparent conductive layer 20 and an insulating layer 30 which are stacked in sequence.
[0040] The light-emitting diode chip further includes a first through hole 40 and a second through hole 50. The first through hole 40 sequentially penetrates the insulating layer 30 and the transparent conductive layer 20 to the first semiconductor layer 110 of the epitaxial layer 10. The second through hole 50 sequentially penetrates the insulating layer 30, the transparent conductive layer 20, the first semiconductor layer 110 of the epitaxial layer 10 to the second semiconductor layer 120 of the epitaxial layer 10. A first electrode 60 is provided in the first through hole 40. The size of the first electrode 60 matches the size of the first through hole 40. The first electrode 60 is electrically connected to the first semiconductor layer 110. A second electrode 70 is provided in the second through hole 50. The size of the second electrode 70 matches the size of the second through hole 50. The second electrode 70 is electrically connected to the second semiconductor layer 120.
[0041] The light-emitting diode chip provided in the embodiment of the present disclosure is provided with a first through hole 40 and a second through hole 50. The first through hole 40 extends from the insulating layer 30 to the first semiconductor layer 110, and the first electrode 60 is disposed in the first through hole 40, so as to realize the electrical connection between the first electrode 60 and the first semiconductor layer 110. The second through hole 50 extends from the insulating layer 30 to the second semiconductor layer 120, and the second electrode 70 is disposed in the second through hole 50, so as to realize the electrical connection between the second electrode 70 and the second semiconductor layer 120. Since the first electrode 60 and the second electrode 70 realize respective electrical connection through the first through hole 40 and the second through hole 50, there is no need to etch a notch on the epitaxial layer 10, which effectively avoids the notch from reducing the area of the epitaxial layer 10, thereby increasing the light-emitting area of the light-emitting diode chip and increasing the light-emitting brightness.
[0042] That is, by providing the first through hole 40 and the second through hole 50 of reasonable size to accommodate the first electrode 60 and the second electrode 70, it is possible to avoid a large reduction in the area of the epitaxial layer 10 due to directly providing a gap. In this way, the light emitting area of the light emitting diode chip is increased, and the light emitting brightness is increased.
[0043] It is worth noting that, although the first through hole 40 and the second through hole 50 are provided, the area of the epitaxial layer 10 is reduced, but since the size of the first through hole 40 corresponds to the first electrode 60, and the size of the second through hole 50 corresponds to the second electrode 70, the loss of the area of the epitaxial layer 10 can be minimized. Therefore, the light-emitting diode chip provided in the embodiment of the present disclosure increases the light-emitting area of the light-emitting diode chip and increases the light-emitting brightness compared to the light-emitting diode chip in the related art.
[0044] In this embodiment, the first semiconductor layer 110 is a P-type layer, and the second semiconductor layer 120 is an N-type layer to form a PN junction, thereby realizing the light emission of the light emitting diode chip.
[0045] Figure 3 is a projection diagram of a light-emitting diode chip. Figure 3 In FIG. 1 , the solid line is the contour line of the second semiconductor layer 120 , the inner contour line of the second semiconductor layer 120 may be equivalent to the contour line of the second through hole 50 , the dashed line is the contour line of the insulating layer 30 , and the dotted line is the contour line of the first electrode 60 and the second electrode 70 . Figure 3 In this embodiment, the orthographic projection of the outer contour of the first through hole 40 on the plane where the epitaxial layer 10 is located is located in the first semiconductor layer 110 , and the orthographic projection of the outer contour of the second through hole 50 on the plane where the epitaxial layer 10 is located is located in the second semiconductor layer 120 .
[0046] In the above implementation, through the above projection relationship, it can be ensured that the first through hole 40 and the second through hole 50 are both opened inside the epitaxial layer 10, rather than opened at the outer edge of the epitaxial layer 10. In this way, the size of the first through hole 40 and the second through hole 50 can be easily controlled, and the size of the first through hole 40 and the second through hole 50 is avoided to be too large.
[0047] In this embodiment, two ways of opening the second through hole 50 are provided, and these two ways of opening are respectively introduced below.
[0048] The first way to start is to see Figure 3 In this embodiment, the orthographic projection of the outer contour of the second through hole 50 on the plane where the epitaxial layer 10 is located is a circle.
[0049] In the above implementation, the area of the orthographic projection of the outer contour of the second through hole 50 on the plane where the epitaxial layer 10 is located is the area of the epitaxial layer 10 occupied by the second through hole 50. Designing the orthographic projection of the outer contour of the second through hole 50 in this way can effectively improve its space utilization and indirectly reduce the area occupied by it.
[0050] Exemplarily, the minimum distance d1 between the outer contour of the orthographic projection of the outer contour of the second through hole 50 on the plane where the epitaxial layer 10 is located and the outer contour of the orthographic projection of the second electrode 70 on the plane where the epitaxial layer 10 is located is 5-9 μm.
[0051] In the above implementation, since the orthographic projection size of the second electrode 70 is certain, the orthographic projection of the outer contour of the second through hole 50 and the minimum spacing therebetween are designed, which can effectively control the size of the orthographic projection of the outer contour of the second through hole 50, thereby ensuring that the second through hole 50 does not occupy too much area of the epitaxial layer 10, thereby increasing the light-emitting area of the light-emitting diode chip and increasing the light-emitting brightness.
[0052] Exemplarily, the outer contour diameter of the orthographic projection of the outer contour of the second through hole 50 on the plane where the epitaxial layer 10 is located is 18-22 μm.
[0053] Such a design of the diameter can ensure that the second through hole 50 does not occupy too much area of the epitaxial layer 10, thereby increasing the light emitting area of the light emitting diode chip and enhancing the light emitting brightness.
[0054] For the second way to start, see Figure 4 , Figure 4 is a projection diagram of a light-emitting diode chip. Figure 4 , the solid lines are the contours of the first through hole 40 and the second through hole 50, the dashed lines are the contours of the insulating layer 30, and the dashed lines are the contours of the first electrode 60 and the second electrode 70. In this embodiment, the orthographic projection of the outer contour of the second through hole 50 on the plane where the epitaxial layer 10 is located matches the orthographic projection of the second electrode 70 on the plane where the epitaxial layer 10 is located.
[0055] In the above implementation, the orthographic projection of the second through hole 50 matches the orthographic projection of the second electrode 70, that is, the outer contours of the two are the same, and they differ only in size. In this way, the orthographic projection area of the second through hole 50 can be increased, thereby increasing the size of the second electrode 70, so that the second electrode 70 can have a higher stress resistance, and the reliability of the second electrode 70 is improved.
[0056] Exemplarily, the minimum distance between the outer contour of the orthographic projection of the outer contour of the second through hole 50 on the plane where the epitaxial layer 10 is located and the outer contour of the orthographic projection of the second electrode 70 on the plane where the epitaxial layer 10 is located is 1-3 μm.
[0057] In the above implementation, since the orthographic projection size of the second electrode 70 is certain, the orthographic projection of the outer contour of the second through hole 50 and the minimum spacing therebetween are designed, which can effectively control the orthographic projection size of the outer contour of the second through hole 50. The smaller the minimum spacing therebetween, the larger the size of the second electrode 70, and the higher the stress resistance of the second electrode 70, thereby improving the reliability of the second electrode 70.
[0058] See again Figure 2 In this embodiment, the inner sidewall of the second through hole 50 is covered with an insulating layer 30 to isolate the second electrode 70 from the first semiconductor layer 110 and the transparent conductive layer 20 .
[0059] In the above implementation, the insulating layer 30 can effectively achieve insulation isolation between the second electrode 70 and the first semiconductor layer 110, and insulation isolation between the second electrode 70 and the transparent conductive layer 20, so that the second electrode 70 is only electrically connected to the second semiconductor layer 120. In this way, the reliability of the light-emitting diode chip is effectively improved.
[0060] Exemplarily, the distance between the bottom of the second through hole 50 and the surface of the first semiconductor layer 110 facing the second semiconductor layer 120 is 3-7 μm.
[0061] The second through hole 50 penetrates deep into the second semiconductor layer 120 , so that the second electrode 70 can also penetrate deep into the second semiconductor layer 120 , thereby effectively improving the electrical connection reliability between the second electrode 70 and the second semiconductor layer 120 .
[0062] Continue to see Figure 2 Exemplarily, the outer side of the epitaxial layer 10 has a groove 130 , the groove 130 extends from the first semiconductor layer 110 to the second semiconductor layer 120 , and at least a portion of the insulating layer 30 is located in the groove 130 .
[0063] In the above implementation, the insulating layer 30 is disposed in the groove 130 , so that the insulating layer 30 can better protect the epitaxial layer 10 , thereby improving the reliability of the light emitting diode chip.
[0064] In this embodiment, the epitaxial layer 10 further includes a buffer layer 140 . The buffer layer 140 is located on a side of the second semiconductor layer 120 facing away from the first semiconductor layer 110 .
[0065] In the above implementation, the second semiconductor layer 120 is grown on the buffer layer 140 , which can effectively improve the growth quality of the second semiconductor layer 120 .
[0066] In order to facilitate the growth of the epitaxial layer 10 , in this embodiment, the light emitting diode chip further includes a substrate 80 . The substrate 80 provides a growth basis for the epitaxial layer 10 . The epitaxial layer 10 is grown on one side of the substrate 80 .
[0067] Exemplarily, the substrate 80 is a sapphire substrate 80. Of course, in other embodiments, the light emitting diode chip may not have the substrate 80, and the present disclosure does not limit this.
[0068] After the test, the test data as shown in Table 1 were obtained.
[0069]
[0070] In Table 1, Figure 1 This corresponds to the first opening method of the second through hole 50. Figure 2 This corresponds to the second opening method of the second through hole 50. Wd represents wavelength, Iv represents brightness, and Vf represents forward bias. Figure 1 Japanese version Figure 2 The brightness of the corresponding two light-emitting diode chips is effectively improved compared with the light-emitting diode chips in the related art.
[0071] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0072] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A light emitting diode chip, characterized in that: include: An epitaxial layer (10), a transparent conductive layer (20) and an insulating layer (30) stacked in sequence; The light-emitting diode chip further comprises a first through hole (40) and a second through hole (50), wherein the first through hole (40) sequentially penetrates the insulating layer (30), the transparent conductive layer (20), and reaches the first semiconductor layer (110) of the epitaxial layer (10), and the second through hole (50) sequentially penetrates the insulating layer (30), the transparent conductive layer (20), the first semiconductor layer (110) of the epitaxial layer (10), and reaches the second semiconductor layer (120) of the epitaxial layer (10); The first through hole (40) has a first electrode (60) therein, the size of the first electrode (60) matches the size of the first through hole (40), and the first electrode (60) is electrically connected to the first semiconductor layer (110); the second through hole (50) has a second electrode (70) therein, the size of the second electrode (70) matches the size of the second through hole (50), and the second electrode (70) is electrically connected to the second semiconductor layer (120).
2. The light emitting diode chip according to claim 1, characterized in that: The orthographic projection of the outer contour of the first through hole (40) on the plane where the epitaxial layer (10) is located is located within the first semiconductor layer (110); The orthographic projection of the outer contour of the second through hole (50) on the plane where the epitaxial layer (10) is located is located within the second semiconductor layer (120).
3. The light emitting diode chip according to claim 1, characterized in that: The orthographic projection of the outer contour of the second through hole (50) on the plane where the epitaxial layer (10) is located is a circle.
4. The light emitting diode chip according to claim 3, characterized in that: The minimum distance between the outer contour of the orthographic projection of the outer contour of the second through hole (50) on the plane where the epitaxial layer (10) is located and the outer contour of the orthographic projection of the second electrode (70) on the plane where the epitaxial layer (10) is located is 5 to 9 μm.
5. The light emitting diode chip according to claim 1, characterized in that: The orthographic projection of the outer contour of the second through hole (50) on the plane where the epitaxial layer (10) is located matches the orthographic projection of the second electrode (70) on the plane where the epitaxial layer (10) is located.
6. The light emitting diode chip according to claim 5, characterized in that: The minimum distance between the outer contour of the orthographic projection of the outer contour of the second through hole (50) on the plane where the epitaxial layer (10) is located and the outer contour of the orthographic projection of the second electrode (70) on the plane where the epitaxial layer (10) is located is 1 to 3 μm.
7. The light emitting diode chip according to any one of claims 1 to 6, characterized in that: The inner side wall of the second through hole (50) is covered with the insulating layer (30) to isolate the second electrode (70) from the first semiconductor layer (110) and the transparent conductive layer (20).
8. The light emitting diode chip according to any one of claims 1 to 6, characterized in that: The distance between the bottom of the second through hole (50) and the surface of the first semiconductor layer (110) facing the second semiconductor layer (120) is 3 to 7 μm.
9. The light emitting diode chip according to any one of claims 1 to 6, characterized in that: The outer side surface of the epitaxial layer (10) has a groove (130), and the groove (130) extends from the first semiconductor layer (110) to the second semiconductor layer (120); At least a portion of the insulating layer (30) is located in the groove (130).
10. The light emitting diode chip according to any one of claims 1 to 6, characterized in that: The epitaxial layer (10) further comprises a buffer layer (140), wherein the buffer layer (140) is located on a side of the second semiconductor layer (120) facing away from the first semiconductor layer (110).